Slide 1

2011 Altera Corporation - Public Backplane Design and Optimization Using 28nm FPGAs Technology Roadshow 2011

Slide 2

2011 Altera Corporation - Public Agenda Backplane Challenges 28-nm Transceiver Architecture & Signal Integrity Features Simulation Tools, Models and Flows 10GBASE-KR Backplane Design Example Backplane Solutions Summary 2

Slide 3

2011 Altera Corporation - Public 10+ Gbps Backplane Design Challenges 3

Slide 4

2011 Altera Corporation - Public Backplane Applications Enterprise switching Line card and switch fabric Core switch Aggregation Cross-bar applications Shared memory architecture Access boxes DSLAM, PON T1, E1, cable Proprietary backplanes/midplanes Time-slot interchange (TSI) Transport Next-generation Ethernet switching Types of transport ROADM OTN WDM MSPP Broadcast switching Serial digital interface (SDI) aggregation 4

Slide 5

2011 Altera Corporation - Public 10GBASE-KR Backplane Electrical TX Eye mask Channel Channel description Insertion loss Return loss RX Jitter Tolerance Return loss System BER =< 1E-12 5

Slide 6

2011 Altera Corporation - Public 28-nm Transceiver Architecture & Signal Integrity Features 6

Slide 7

2011 Altera Corporation - Public Stratix V Transceiver Block Architecture Up to 66 full-duplex transceivers at 14.1 Gbps Scalability and flexibility with continuous bank of transceivers with complete PMA and PCS per channel Multiple transmitter (TX) PLL sources More LC oscillators Programmable LC tuning range Multipurpose fractional PLLs (fPLLs) for additional TX clock source Analog PLL-based CDR per receive channel Advanced TX and receiver (RX) equalization for 14.1-Gbps backplane support Including 10GBASE-KR Optimized PCS / Hard IP for multiple protocol support Additional 28G transceivers 7.... Hard PCS Transceiver PMA.... Embedded HardCopy Block) Fractional PLLs (fPLL) LC Transmit PLLs Clock networks Transceiver PMA

Slide 8

2011 Altera Corporation - Public Dedicated Circuitry for Advanced Signal Conditioning LC PLL for sub-ps transmit jitter Analog-PLL CDR for improved jitter tolerance 4-tap pre-emphasis and linear equalization for 14.1-Gbps backplane applications Advanced signal conditioning including 5-tap DFE and ADCE Mitigate backplane losses and crosstalk Targeted 10GBASE-KR and CEI-11G electricals 8 Backplane Channel: Including 10GBASE-KR Pre- Emphasis EQCDR Analog CDR TX RX LC TX PLL

Slide 9

2011 Altera Corporation - Public 9 Arria V FPGAs Offer Up to 36 Full-Duplex Transceiver Channels with PCS and PMA Scalability and flexibility through a continuous bank of transceivers Complete physical medium attachment (PMA)+ physical coding sublayer (PCS) per channel Unused channels can be utilized as clock multiplier unit (CMU) PLLs Flexible transmit clock sources enable up to 24 independent data rates in a single device Transmit Clock SourceMaximum NumberData Range (Gbps) CMU PLL120.6 6.375 fPLL120.6 3.75 CMU PLL60.6 10.3125........ Clock Networks Hard PCS Transceiver PMA........ Arria V Transceiver Architecture

Slide 10

2011 Altera Corporation - Public 10 Altera 28nm Transceiver Summary Transceiver SI FeatureArria VStratix V Transmit Equalization (pre-emphasis) Main tapMain tap, 2 post tap, 1 pre-tap Receive Equalization (Continuous Time Linear Equalization) 1 stage (4 dB) around 6.25 Gbps 4 stage (20dB) Programmable bandwidth up to 12.5 Gbps Adaptive Dispersion Compensation Engine (ADCE) N/A Up to 12.5 Gbps Decision Feedback Equalization (DFE) N/A5-tap with auto adaption Backplane SupportUp to 30 at 6.375 GbpsUp to 40 at 14.1 Gbps Optical Module Support SFP+ Short Reach (SR) Long Reach (LR) requires external EDC chip Full compliance (SR, LR and LRM) for SFP+ EyeQN/A Vertical & horizontal eye (12.5 Gbps) Serial bit checker for unknown data pattern On-Die Instrumentation Jitter Injection / Stress N/A Jitter modulation of transmitter & receiver

Slide 11

2011 Altera Corporation - Public Simulation Tools, Models and Flows 11

Slide 12

2011 Altera Corporation - Public Transceiver Simulation Models Alteras suite of transceiver design tools Evaluate performance in custom application Run What if simulations for early analysis Create design constraints in layout and design Run in-system verification for board bring-up and live debug 12 HSPICE full circuit models IBIS-AMI behavioral models Fast simulation Analog and algorithmic description of all major transceiver components Analysis of millions of bits

Slide 13

2011 Altera Corporation - Public PELE Pre-emphasis/Equal Link Estimator Optimize the equalization coefficients for the transceiver Early estimate of link performance Inputs: Channel / settings 13 Backplane TX model RX model Customer provided S-parameters PELE Coefficients

Slide 14

2011 Altera Corporation - Public Simulation Model Comparison HSPICEIBIS-AMIPELE AccuracyHighHigh/mediumMedium Time consumptionHours to daysMinutes to hoursMinutes Corner model availabilityFull TT/NormV/85C Flexible data inputsYes PRBS-7/10 Link to other devicesYes No EDA tool requirementSynopsys HSPICEYes, independentNA Simulation platform requirement 64-bit Linux, 8 GB memory EDA-tool dependent 32-bit system, 1 GB memory 14

Slide 15

2011 Altera Corporation - Public HST Jitter and BER Estimator Custom characterization Quickly and accurately estimate system link reliability (BER) Utilize customer-specific channel (S-Parameter) Run statistical analysis using characterization data Margin analysis TX RX Channel Reduction of system cost Cost-effective alternatives for the same system performance 15 Currently Available for Stratix IV and V FPGAs

Slide 16

2011 Altera Corporation - Public Link Simulation Flow Early Stage Use generic S-parameter file From backplane model provider, EDA simulation tool extraction or VNA measurement Use PELE/JBE to see if the selected device compensates channel losses using pre- emphasis or equalization, or both Check to see if the eye opening meets the protocol requirements or device requirements Proceed to device selection 16 Device Selection (TX and RX) Generic S-Parameters (model provider/fab) PELE/HST JBE Eye Mask Requirements Yes No

Slide 17

2011 Altera Corporation - Public Link Simulation Flow Design Phase Device selection Channel design Further analysis Pre-emphasis and/or equalization settings selection Fine tune/validate settings HSPICE IBIS-AMI behavioral models Use JBE to include the statistical data Use the transceiver toolkit to verify and debug 17 Channel Design Extract Backplane S-Parameters PELE EDA Simulations (Fine-tune/Validate Settings) Include Statistical Data (RJ)? Eye Mask Requirements Board Design Use Transceiver Toolkit Debug/Verification HST JBE Yes No Yes

Slide 18

2011 Altera Corporation - Public 10GBASE-KR Backplane Design Example 18

Slide 19

2011 Altera Corporation - Public PELE Configuration Optimization Method TX Pre-emphasis RX CTLE 1ManualAuto 2 3 Manual 4 19 Standalone mathematical tool Requires MATLAB run-time library Inputs Data rate V OD Backplane TX pre-emphasis setting RX equalization setting AC gain (CTLE) DC gain DFE Outputs Deterministic eye opening at TX, RX, and post equalization Optimal pre-emphasis and equalization setting Optimization MethodDFE 1Disable 2Auto 3Manual Stratix V GX PELE Tool Auto/Manual Mode Backplane (*.s4p) Data Rate VOD Pre-emphasis Equalization Eye Opening

Slide 20

2011 Altera Corporation - Public PELE Configuration Optimization Method TX Pre-emphasis RX CTLE 1ManualAuto 2 3 Manual 4 20 Standalone mathematical tool Requires MATLAB run-time library Inputs Data rate: 10.3125 Gbps V OD : 1000 mV Backplane: 30inches_2connectors_backplane.s4p TX pre-emphasis setting: Auto RX equalization setting AC gain (CTLE) : Auto DC gain: 4 (0-8 dB) DFE: Auto Outputs Deterministic eye opening at TX, RX, and post equalization Optimal pre-emphasis and equalization setting Optimization MethodDFE 1Disable 2Auto 3Manual Stratix V GX PELE Tool Auto/Manual Mode Backplane (*.s4p) Data Rate VOD Pre-emphasis Equalization Eye Opening

Slide 21

2011 Altera Corporation - Public PELE Simulation (30 link @10.3125G) 21 TX

Slide 22

2011 Altera Corporation - Public PELE Simulation Output Refer to Stratix V user guide on PELE instructions PELE output results: 22 0.75 UI = deterministic eye opening 1- 0.75 UI = 0.25 UI = non compensated jitter Starting point for optional simulation analysis

Slide 23

2011 Altera Corporation - Public 10GBASE KR Requirements 1. TX Jitter Characteristics RJ < 0.15 UI, DJ < 0.15, DCD < 0.035 Overall TJ TX < 0.28 UI = 27ps @ 10.3125 Gbps 2. Channel Characteristics Insertion loss < 25dB @ 5.15625 GHz 3. Altera RX Requirements Post EQ Eye width > 0.6 UI Eye height > 100mV 4. RX Jitter Tolerance Requirements SJ > 0.115, RJ > 0.13, DCD > 0.130 5. System Performance BER = 1E-12 23 10GBASE-KR channel TX RX EQCDR 1 2 3 4 5

Slide 24

2011 Altera Corporation - Public Transmitter 10GBASE-KR transmit jitter requirements RJ < 0.15 UI, DJ < 0.15, DCD < 0.035 Overall TJ TX < 0.28 UI = 27ps @ 10.3125 Gbps PELE Eye opening @ TX output TX TJ = 1- Eye opening at TX output = 1-0.92313 = 0.07687 UI < 0.185 UI (DJ + DCD) 24 TX RX

Slide 25

2011 Altera Corporation - Public Backplane Channel Channel: Length: 30 Connectors: 2 Loss @ 5.15 GHz: Approx -20dB 25 10GBASE-KR Insertion loss spec: < 25dB @ 5.15625 GHz TX RX

Slide 26

2011 Altera Corporation - Public Receiver RX Jitter Tolerance Requirements o SJ > 0.115, RJ > 0.13, DCD > 0.130 o Altera data sheet and characterization report Altera RX Requirements at 10.3125Gbps o Deterministic eye opening 26 CTLE Eye HeightCTLE Eye WidthDFE Eye HeightDFE Eye Width Requirement100 mV0.60 UI100 mV0.70 UI Actual326 mV0.74 UI352 mV0.75 UI TX RX

Slide 27

2011 Altera Corporation - Public System Performance PELE analysis is a deterministic simulator Jitter and BER Estimator (JBE) incorporates random jitter components of transmitter and receiver through characterized data Early version (EAP) of Stratix V JBE is based on Stratix IV data Final version will incorporate actual silicon measurement JBE will determine Bit Error Ratio performance of link 27 TX RX TX

Slide 28

2011 Altera Corporation - Public Jitter and BER Estimator Tool 28

Slide 29

2011 Altera Corporation - Public JBE Configuration Steps 1. Setup global parameters Target BER Data Rate (Gbps) Test Pattern 2. Link configuration Analysis mode selection/eye mask setup Options: Full Link, TX, RX 29 Step1 Step 2

Slide 30

2011 Altera Corporation - Public JBE Configuration Steps 3. Configure TX settings 4. Configure RX settings 5. Input the non- equalized channel DJ from PELE simulation output 1 Eye opening post equalization May add margin to this number to account for cross-talk 30 Step 3 Step 4 Step 5

Slide 31

2011 Altera Corporation - Public Link Analysis: Full Link Mode Full link simulation shows that the link meets the BER target of 10 -15 Margin analysis 31

Slide 32

2011 Altera Corporation - Public Backplane Solutions 32

Slide 33

2011 Altera Corporation - Public 10GBASE-KR Backplane PCS Auto-negotiation Link Training Forward Error Correction MoreThanIP offers a complete PCS solution for 10GBASE-KR applications for Stratix V 33

Slide 34

2011 Altera Corporation - Public Connectors Major component of link reliability Evaluation of link includes Insertion Loss Return Loss Crosstalk Advanced EDA simulation tools Hardware analysis 34

Slide 35

2011 Altera Corporation - Public Stratix V 5-Tap Decision Feedback Equalizer Improves signal-noise-ratio (SNR) With CTLE, addresses pre-cursor and post-cursor ISI Mitigates the effects of crosstalk Automatically adapts to PVT conditions 35 Z -1 C1 C2 C3 C4 C5 _ From linear equalizer To CDR

Slide 36

2011 Altera Corporation - Public Stratix V FPGA EyeQ Eye Viewer 36 View receiver signal margin with Alteras EyeQ eye viewer Complete vertical and horizontal reconstruction of eye opening Uninterrupted data path for live debug capability Minimize board bring up / debug time with Dynamic reconfiguration and EyeQ Tx Rx Lossy medium Pre- Emphasis EQCDR EyeQ

Slide 37

2011 Altera Corporation - Public Summary Link simulation flow enabled through Altera simulation tools and models 10GBASE-KR backplane system performance achieved Altera offers complete solution for 10+ Gbps backplane analysis and design 37 Stratix V FPGAs offer the optimum platform for 10Gbps+ backplane systems

Slide 38

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the United States and are trademarks or registered trademarks in other countries. 2011 Altera Corporation - Public Thank You Backplane Design and Optimization Using 28-nm FPGAs