28nm fd-soi technology catalog

28nm FD-SOI Technology Catalog

Content

FD-SOI Technology .................................................................. 3The body-bias (bb) advantage ...................................................... 4Standard-cells ................................................................................ 5IO ................................................................................................... 6Memories ....................................................................................... 8Phase locked-loop (PLL) ................................................................. 9Oscillators .................................................................................... 10Analog-to-digital convertors (ADC) .............................................. 11Digital-to-analog convertors (DAC) .............................................. 12Embedded power-management IPs ............................................ 13One-time-programmable (OTP) IP: fuSE ....................................... 13Process-monitoring box (PMb) ...................................................... 14Voltage & thermal sensors ............................................................ 14Linear regulators .......................................................................... 15High-speed serial links .................................................................. 15

Consumer Multimedia

• OptimizedSoCintegration(Mixed-signal&RF)• Energy-efficientSoCunderallthermalconditions• Optimizedleakageinidlemode

3

Theuniqueadvantagesof28nmFD-SOItechnology,allowSoC/ASICdesignerstogainfullbenefitofbest-in-classPerformance,Power,andArea(PPA)inasingleprocess-technologyflavorwithouthavingtochoosemultipletechnologyvariants.

FD-SOI Technology

APPLICATION BENEFITS BY MARKET SEGMENT

A few of the advantages of 28nm FD-SOI technology:• At28nm,FD-SOIrequiresfewermaskstepsbecauseitisasimplerprocess.• InUTBBFD-SOItechnology,thechannelisquitethin,soitcanbeeffectivelycontrolledbytheGate,whichresultsinlowerleakagepower(instatic/stand-bypower).Fordesignoptimizationandflexibility,multiple Threshold Voltage (VT) flavorsofthetransistorareavailable,including:• RVTdeviceforregular-V

Torstandard-V

Tcircuits,

• LVTdeviceforlow-VThigh-speedcircuits.

• Body-BiasingisaneffectivefeatureinFD-SOItocontroltheVTofthetransistortoleveragedeviceelectrostaticsforspeedandleakage

optimization.• Wide operating voltage range,fordifferentapplicationswithcompetitivePPAadvantages:

• VerylowVDDforultra-lowpowerapplications,

• ReducedVDDforcompetitivespeedatreasonablepowerconsumption,

• NominalVDDforhigh-performanceapplications.

• Excellent device electrostatics,(a)lowleakage,leveragingUltra-ThinBodyandBox(UTBB)technology,(b)fasteroperation,duetothefullydepletedchannel,and(c)remarkablereliability

Networking Infrastructure

• Energy-efficientmulticore• Adaptperformance&powertoworkloadviaFBB• Excellentperformanceinmemories

Internet of Things, Wearable

• Ultra-low-voltageoperation• FBBoptimizespower/performance• EfficientRFandanalogintegration

Automotive

• Well-managedleakageinhigh-temperatureenvironments• Highreliabilitythankstohighly-efficientmemories

Baseline

RF

Ultra lowpower

Road

map

Prod

uctio

n

Power and energy efficiencyUltralowleakage,wideBody-Bias&operatingvoltagerangeAnalog performanceformixedsignal&RFdesignRobustnessformissioncriticalapplicationsCost effective platform

4

THE BODY-BIAS (BB) ADVANTAGEEffective lever to optimize between higher performance and lower leakage

BODY-BIASING: AN EXTREMELY POWERFUL AND FLEXIBLE CONCEPT IN FD-SOIBody-biasing,alsooftenreferredtoasbackbiasing,controlsthethresholdvoltage(V

T)

ofatransistortooptimize:• Drivecurrent(forhigherperformance)attheexpenseofincreasedleakagecurrent(ForwardBackBias,FBB)

• Or,leakagecurrent,withsomewhatlowerperformance(ReverseBackBias,RBB)

0 - 1.1 V

Body-biasing facilitates a wide Dynamic Voltage Frequency Scaling (DVFS) range (0.7 V – 1.1 V)• Performanceboostwhereverneeded• Reducepowerconsumptionatagivenperformancerequirement• Processcompensationreducingthemarginstobetakenatdesign• SeamlessinclusionintheEDAflow

FOUNDATION IP/LIBRARIES PORTFOLIO

Standard-Cells

• MultipleArchitectures• MultipleChannel-length(Poly-Biasing)options• Multiple-V

Toptions

• Richportfolioofcells

Memories

• LowVmin

• LowPoweroptions• Mono&Dualrailcompilers• Soft-ErrorRate(SER)robustness

Data Convertors (ADC & DAC)

• MultipleArchitectures• WideResolutionrange(upto24bits)• High-Speed(upto64Gsps)• Best-in-ClassPerformance,Power,Area

IO

• Wideportfolioforvariousapplications• OptimizedforCore/PadLimitedchipconfigurations• DifferentiatingsolutionsforLowPowerandAreaEfficiency• Programmabilityforvariedboard/packageandloadingenvironment

Clock Generators

• Wide-Portfolio• VariousPatentedArchitectures• Best-in-ClassPerformance,Power,Area

Specific IPs

• Body-BiasGenerator• OTPSecurityIP(Fuse)• ProcessMonitoringBlock(PMB),ThermalandVoltageSensors• Regulators• PowerManagementIPs

5

TheMainstreamlibraryandLow-PowerlibraryareavailablewithbothRVTandLVTthreshold-voltagesupportin12-Track(12T)and8-Track(8T)architectures.TheHigh-Performancelibraryhasboth12T&8TarchitecturesandLVTthreshold-voltageoptions.

Low Power

• Isolation• Level-Shifter• Retention/Always-ON

Mainstream

• GeneralPurposeCORE• Multi-BitFlip-Flop• Clock• ECO&PR

High.Performance

• High-PerformanceCORE• SkewedSequentialCells

STANDARD-CELLSSTMicroelectronicsoffersabroadportfolioofstandard-celllibrariesin28nmFD-SOItechnology.Thestandard-cellsdesignedin28nmFD-SOIofferuniqueadvantagestovariousSoC/ASICapplications.Themainstreamstandard-celllibraryisaugmentedbyspecializedlibrariesforlow-powerandhigh-performanceapplications.

....ClassificationbasedonapplicationMultiple tracks and architectures (12T/8T)Multi-threshold voltage (VT) support (LVT/RVT)Multi-channel length variants (Poly-Bias P0/P4/P10/P16)

Library8 Track 12 Track

LVT RVT LVT RVT

Low-Power

CORI (Core Isolation Library) • • • •

CORR (Core Retention Register Library) • • • •

SHIFT (Level Shifter Library) • • • •

CORBF (Core Multi-Bit Flip-Flop Library) • • - -

SYNC (Synchronizer Library) • • • -

CDMPR (Place & Route Library with CDM Protection) - - • •

CDMSHIFT (Level Shifter Library with CDM Protection) - - • •

Mainstream

CORE (Core Library) • • • •

CLK (Clock Library) • • • •

PR (Place & Route Library) • • • •

ECO (Engineering Change Order Library) • • • •

High-Performance

CORHP (High-Performance Core Library) • - • -

CORXT (Library with High-Speed Flip-Flops) • - • -

*OtherelectricalparameterswillbedisclosedunderNDA

6

TheIOsolutionsconsistsofversatilecellswithmultiplefeatures:• Widerangeoffunctionalities:interface functionalities,dedicatedIOfunctionalitiestoserveanalog IP blocks,power-supplyprovisioningtoanSoC,orprovisionofreliable ESD protection

• Multiple Metal Stacks options,Multiple Supply Voltages,and Chip-Layout Configurations(Core-Limited,Pad-Limited,andPad-in-Core)

• Differentiating solutions:Nointermediatesupplyrequiredin3.3VIO,significantlyfewersupplypadsusingcompensationstrategy,multiplepatentsinIOdesign

• IOoffersupports a variety of industry standardslikeI2C,USB,GPIO,MIPISlimbus,SDMMC,HSPROG,EMMCandotherspecifichigh-speedIOinterfaces

• AdvancedESDprotectioncomplianttoIEC 61000-4-2areavailableonrequest

IO28nmFD-SOIIOlibraryenablesflexible,effectiveandreliableinterfacinginSoCdesignwithstate-of-the-artfeaturesandPPAadvantages.Specialapproaches,suchasthecompensationstrategy,flexibilitybetweencompensatedanduncompensatedIO,andESDsolutions,providedifferentiationinSoC/ASICdesignswithapplicationsrangingfromlow-powerhand-helddevicestohigh-performancecomputing.

Inte

rfac

e vo

ltage

Interface speed (Mbps)

1.2 V

1.5 V

1.8 V

2.5 V

CF+/LED/PATA(12 Mbps) 5V Tolerant

(50 Mbps)

SD/MMC 3V3(104 Mbps)

SD/MMC 3V3(104 Mbps)

SD 1V8(240 Mbps)

SD 1V5(240 Mbps)

SD 1V2(240 Mbps)

HSIC(480 Mbps)

EMMC Failsafe(480 Mbps)

HSPROG3V3(150 Mbps)

HSPROG2V5(150 Mbps)

GPIO 3V3(60 Mbps)

GPIO 2V5(60 Mbps)

MIPI SLIMBUS(57.6 Mbps)

MIPI SLIMBUS(57.6 Mbps)

I2C 3V3 FS(6.8 Mbps)



IC_USB(12 Mbps)

3.3 V

5.0 V

10 10050 250 500

USIM(12 Mbps)

USIM(12 Mbps)

USIM(12 Mbps)

Multi-supply

7

Interface/Application Library name IO standard IO supply Features/Specification

General Purpose UART, JTAG

GPIO 1V8 1.8 V Programmable IO, Non-PVT Compensated

JESD76/JESD8-7 1.8 V•8-Level-DriveProgrammability•1V8FailsafeandNon-Failsafe•Support1V5and1V2operation

GPIO 3V33.3 V Programmable IO, Non-PVT Compensated

JESD76/JESD8-B 3.3 V•4-Level-DriveProgrammability•3.3VFailsafeandNon-Failsafe

GPIO 1V8_3V31.8 V & 3.3 V Programmable IO, Non-PVT Compensated

JESD76/JESD8-7JESD8-B

1.8 V3.3 V

•3.3VFailsafecell•Two-leveldrive/slewoptions

2V5_3V32.5V&3.3VProgrammableIO,Non-PVTCompensated

JESD80/JESD8-5JESD76/JESD8-B

2.5V3.3 V

•4-Level-Speedprogrammability

TESTMUX 1V81.8 V High-Performance IO, PVT Compensated

JESD76/JESD8-7 1.8 V•2-Level-Driveprogrammability•Cellswith2/4/6/8mAdrives•Support1.5Vand1.2Voperation

PROG 1V81.8 V High-Performance IO, PVT Compensated

JESD76/JESD8-7 1.8 V

•Isolation&Retentionfeature•2-Level-Driveprogrammability•Non-FailsafeandFailsafecells•Support1V5and1V2operation

PVT Compensation Block

COMPENSATION1V8PVTCompensated - 1.8 V •LibraryforPVTcompensationat1.8V

REFCOMPENSATION1V83V3PVTCompensated -1.8 V3.3 V

•LibraryforPVTcompensationat1.8V&3.3V

Printer/LED SRC 3V3Large transmission length slew rate controlled 3.3 V IO

JESD76/JESD8-B 3.3 V•SupportcriticalSignalIntegrityrequirements•Support6”to24”tracelength

SPI/SD/MMC/EMMC/Flash

SDMMC 1V8_3V31.8 V & 3.3 V SDMMC IO

SD3.01/JESD84A441.8 V3.3 V

•SupportTypeA(33Ω)andTypeB(50Ω)driver

EMMC 1V8 1.8 V EMMC Failsafe IO

JESD84B50 1.8 V

•SupporteMMCTYPE0(50),TYPE1(33), TYPE2(66),andTYPE3(100)•SupportseMMCHS200modeandeMMC HS400mode•SupportSDRandDDR

Digital Audio/MultiDrop

SLIMBUS 1V8 1.8 V Slimbus IO

MIPI Slimbus 1.1 1.8 V•IsolationandRetentionfeature•20cmtracelengthsupport

Interchip USBHSIC1V21.2VHSICIO

High Speed Interchip USB 1.0

1.2V•SlewrateandImpedancecontrol•10cmtransmissionlinesupport•Jitterlessthan365ps

HDMI/PMBus/ANDBus/Addressing/ SMBus/IPMI/LCD Drivers/RTC

I2C 1V8 1.8 V I2C Failsafe Open Drain IO

NXPUM10204

1.8 V•SupportStandardMode(100KHz), FastMode(400KHz),FastPlusMode(1MHz)•Programmablebuilt-inbuspull-upresistor

I2C 1V8 3V3TTFS 1.8 V I2C IO with 3.3 V tolerant and failsafe

1.8 V•SupportStandardMode(100KHz), FastMode(400KHz),FastPlusMode(1MHz)

I2C 3V33.3 V I2C Failsafe Open Drain IO

1.8 V•SupportI2C and SM Bus Mode•SupportI2C Standard Mode (100 KHz) and FastMode(400KHz)

I2C3V35VFSFT3.3 V I2CIOwith5VFailsafeandtolerantOpenDrainfeature

3.3 V•SupportI2C Standard Mode (100 KHz) andFastMode(400KHz)

PMBus/ANDBus/Reset/SMBus/LCD Drivers

OD 3V3Open Drain failsafe 3.3 V IO

JESD76/JESD8-B 3.3 V•Bidirectionalcell(200KHz), Outputcell(850KHz)•4mA/8mAoutputdrivecell

Video5VFSFT5VFailsafeTolerant3.3VIO

JESD36 3.3 V•4mAdrivepush-pullIO•40MHz

Analog Library

ANAF_ANA1.0 V1.8 V3.3 V

•AnalogIOcellswithminimizedparasitic capacitance•Includesbasiccellsenablinganoptimized analog IO ring construction

ANAF_ANA6V1.0 V1.8 V3.3 V

•AnalogFail-Safepadwith6Vsignal protection•RestrictedtoUSB2OTGapplicationonly

ANAF_3V3FS1.0 V1.8 V3.3 V

•Fail-safeANApadwith3.3V and5.0Vsignalprotection

ANAF_ANA_1V8FS 1.8 V •1.8VFail-SafeANApad

ESD, & Supplies Library

BASIC1.8 V3.3 V

•IncludesBasiccellsenablingtheIOring construction in Core-Limited, Pad-Limited or Pad in Core configurations

CORESUPPLY1.0 V1.8 V3.3 V

•DedicatedCoreSupplycells and ESD Core-Clamp

CDMKIT1.1 V1.8 V

•OptimizedCDMprotections

Packaging Library BUMP NA•AvailablewiththreeclassesofBUMPcells•ProvidesFlip-Chipstrategytoan IO library for high pin count


8

• Body-biasingfeaturesupportforprocesscompensationandperformanceboost

• Low-powerfeaturesusinginputgating,standby,peripheryshutdownandarrayretention,andEmbeddedswitches

• Multiple power railfeatureforoperating-voltagereduction

• Multiple bank optionsofferinginterestingtiming-power-density-leakage trade-offs

• Embedded Test featuresincludingBISTmux,scanchains,andsynchronousbypasstoreducetesttimeandimprovetestcoverage

• Neutron Soft Error Rate (SER)lessthan10FIT/MbandImmunitytoAlphaSER

• Patented well structurestoenableUltra-Low-VoltageOperation.

• Multiple mux optionstoselectormodifytheaspectratio

• Speed modeselectiontoadjustthemarginsdependingonthevoltageofoperation

• Margin controlforself-timeandresetoperation

• Redundancytoimprovetheyieldattheproductionlevel

• Bit maskstopreservethecontent

Thecompilersarefurthercomplementedbyarichvarietyoffeatures,including:

MEMORIES28nmFD-SOIembeddedmemoryoffersversatilitytodesignersbyallowingthemtochoosefromawideportfolioofcompilers,withitsadvantageofhighperformanceandenergyefficiency,alongwithhighreliabilityandrobustness.FD-SOImemoriesprovidebest-in-classPPAandfiguresofmerit.TheofferincludesHigh-Performance,Low-Leakage,andLow-VoltageSRAMsandROMs,alongwithspecialmemories.

Single PortHigh Density

Single PortRegister

Read OnlyMemory

Low Leakage (LoLeak)


Single PortRegister

Dual PortHigh Density

Dual PortRegister

High Performance (HiPerf)

High DensityDual PortRegister

Special Memories


Single PortRegister

Dual PortHigh Density

Dual PortRegister

Body Bias Options

Compiler Name Description

Low leakage memory

SPHD_LOLEAK Single-port high-density compiler with best density, leakage trade-off

SPREG_LOLEAK Single-port register file optimized for leakage, speed, and density

ROM_LOLEAK Static ROM mainstream compiler

High performance memory

DPHD_HIPERF Dual-port compiler targeted for high-performance, density, and low-power applications

SPHD_HIPERF Single-port high-density compiler with best density and speed trade-off

DPREG_HIPERF Dual-port dual-rail register file with high-performance bitcell

SPREG_HIPERF Single-portregisterfilewithhighperformanceforCacheRAMapplications

BODYBIAS Memory

SPHD_BODYBIAS Single-port high-density compiler supporting forward body bias

SPREG_BODYBIAS Single-port register file supporting forward body bias for high-performance applications

DPHD_BODYBIAS Dual-port compiler targeted for high-performance, density, and low-power applications

DPREG_BODYBIAS Dual-port dual-rail register file with high-performance bitcell

Special Memory PRF2HD_BODYBIAS Area-optimised,dual-portregisterfileusingsingle-portbitcell


9

The28nmFD-SOIPLLofferhasvariousfeatures:• On-the-fly switching(onrequest)• No dependence on supply

sequence(Inabsenceofanalogordigitalsupply,thePLLisautomaticallyinpower-downmode)

• Multiple operating modes:Normal,power-down,VCOstand-alone,Bypass

• Automatic Bandwidth tracking

• Compatibility with all metal stacks(usesonly5thinmetals)

• Clock de-skewingbyactingasanegativedelayelementtocompensatedclock-treedelay

PHASE LOCKED-LOOP (PLL)PhaseLocked-Loop(PLLs)areclockgeneratorsforfrequencysynthesis.Thestandardoffer(highlycustomizable)issupplementedwithhigh-performance,spread-spectrumandfractional-PLLoffers.

Fractional PLL

• Generatesoutput,whichisafractionalmultipleofinputfrequency

Standard PLL

• Generatesmultiplesofinputfrequency(FrequencySynthesis)• Highlycustomizable

Spread Spectrum PLL

• Spreadsenergyofoutputtoabandaroundit• ReducesElectromagneticInterference(EMI)

High Performance PLL

• Lowjitter,lowpower,lowareaPLLs• LCVCObasedPLLs

NameInput Frequency Output Frequency (MHz) VCO Frequency (MHz)

Min Max Min Max Min Max

PLL_FF_308MHZ 32.768KHz 32.768KHz 26 307.2 307.2 312.01

PLL_PF_960MHZ_B 1.92MHz 93 MHz 480.960 480.960 960 960

PLL_PF_960MHZ_32K 32.768KHz 32.768KHz 153.6 319.98 921.26 959.98

PLL_PF_1066MHZ 195MHz 1066 MHz 195 1066 780 1066

PLL_PF_1200MHZ 9.6 MHz 350MHz 9.52 1248 600 1248

PLL_PF_2132MHZ_7P 19.2MHz 52MHz 754(7phase) 2132(7phase) 754 2132

PLL_PF_3000MHZ_FR 24MHz 40MHz 31.25 3000 1500 3000

PLL_PF_3401MHZ 10 MHz 340MHz 106.25 3400 1700 3400

PLL_PF_4600MHZ_SSCG_FR 4.0MHz 350MHz 19.05 3000 2400 6000

PLL_PF_3200MHZ_SSCG_FR 4.0MHz 350MHz 12.7 1600 1600 3200

PLL_PF_5000MHZ_SSCG_FR 24MHz 40MHz 39.06 2500 2500 5000

PLL_PF_480MHZ_6P (for USB2.0) 2MHz 93 MHz 480(6phase) 480(6phase) 480 480

PLL_PF_6400MHZ 6 MHz 210MHz 50 3200 3200 6400

PLL_PF_4000MHZ 2MHz 372MHz 31.25 2000 2000 4000

PLL_PF_2920MHZ_8P 9.6 MHz 403MHz 1152(8phase) 2920(8phase) 1152 2920

*Area&PowerwillbedisclosedunderNDA

10

ON-CHIP CRYSTAL (XTAL) OSCILLATOR FEATURES:• FrequencyRange:32KHz,24MHz-30MHz• CompatiblewithMultiple-Metallization• ModesSupported:OscillationMode,IDDQMode,ForcethroughMode,StartupTestMode,BypassMode

ON-CHIP RC OSCILLATOR FEATURES:• FrequencyRange:30MHz,45MHz,90MHz

• MetalStack:7or8• ModesSupported:RawFrequencyMode,CalibrationMode,TrackingMode,IDDQMode,BypassMode

OSCILLATORSIn28nmFD-SOITechnology,acomprehensiveportfolioofoscillatorsisavailableenablingareacompetitiveness,multiplemetal-stackcompatibilityandwidefrequencyranges.Theoscillatorssupportvariousmodesofoperation.

Oscillators* FrequencyXTAL parameters

Max Rm Max CO CA/CB

32 KHz XTAL Oscillator

C28SOI_OSC_XO_32K_ULP_LLR_EG 32.768KHz 50KΩ 3.0 pF 18 pF ±20%

C28SOI_OSC_XO_32K_LR_EG 32.768KHz 50KΩ 3.5pF 28pF-32pF

24 MHz to 30 MHz XTAL Oscillator

C28SOI_OSC_XOA_24M_LR_EG 24-30MHz 50Ω 5pF 18 pF ±20%

C28SOI_OSC_XOA_30M_LR_EG 24-30MHz 50Ω

5pF 17 pF ±10%

7 pF 26pF±10%

9 pF 30 pF ±10%

RC Oscillator (FLL based)

C28SOI_RCOSCI_30M_32K_TRAC_LR_EG30 MHz45MHz90 MHz

- - -


11

Reso

lutio

n (b

its)

Speed

6

8

10

12

14

16

18

20

24

∑∆

∑∆

SAR

Pipelined, Time Interleaved SAR

Flash ADC

Industrial control

AudioADC

Low speeddata acquisitionAutomotive,Battery Mgmt,Touch Screen,Microcontroller

GHz Data acquisitionRF application

High speed Data acquisitionLow Power Mobile, Cable Front End,Medical equipment, Wifi, WiMax, Set Top Box, WLAN

Low Speed/DC Audio Band 100 k - 5 Msps 5 - 250 Msps 250 - 500 Msps Gsps

ANALOG-TO-DIGITAL CONVERTORS (ADC)In28nmFD-SOITechnology,abroadportfolioofADCsisavailable,supportingmultipleresolutionsandspeedspecifications.

ADC No of bits Main features Type

AD12PP160MIQ_10 12Bits,ENOB10Bits 160Msps Pipelined

AD12PP500M_10 12Bits,ENOB10Bits 500Msps Pipelined

AD10PP160MIQ_10 10 Bits, ENOB 9 Bits 160Msps Pipelined

AD12PP5G_18 12Bits,ENOB10Bits 5Gsps Pipelined

AD12SA1MLA_18 12Bits,ENOB10Bits 1Msps SAR

AD9SA6G_18 9Bits,ENOB7.5Bits 6Gsps SAR

AD8SA64G_10 8Bits,ENOB6.5Bits 64Gsps SAR

AD14SA250K_18 14Bits,ENOB13Bits 250Ksps SAR


Audio ADC No of bits Main features Type

AD18ASDSE_18 18 Bits SNR 98dB Sigma Delta


• Best-in-classPPA• Multiplearchitecturesavailable

• Availableforvariousapplicationandcustomizableonrequest

• Highspeed(upto64Gsps)• HighResolution(upto24bits)

Thefollowingfeaturesaresupportedin28nmFD-SOIADCs:

12

DIGITAL-TO-ANALOG CONVERTORS (DAC)ST’sDACportfoliofor28nmFD-SOITechnology,offersvariousresolutionsandspeedspecificationsformultipleapplications.

DAC No of bits Main features Type

DACI10HD3x1_1V8 10 Bits Outputcurrent=3.25mASFDR=54dBc@6MHz

Current Steering

DA10HD6X4_18_C28SOI8M 10 BitsOutputcurrent=6mASFDR=54dBc@6MHz

Fs = 160 MHzCurrent Steering

DAI10HD9X4CBLDET_1V8_EG8M 10 Bits

Outputcurrent=8.7mASFDR=54dBc@6MHz

Fs = 160 MHzwith cable detection

Current Steering

DACI10HF1DA3_1V8 10 BitsOutputcurrent=1.25mASFDR=60dBc@Nyquist

Q-switching Current Steering

DACI10HD17TO34X3_1V8_LLR_EG8M 10 BitsOutputcurrent=17mAto34mA

SFDR=54dBc@6MHzFs = 160 MHz

Current Steering

DACI10HF1OPC3_1V8_LLR_EG8M 10 BitsOutputcurrent=1.25mASFDR=60dBc@40MHz

Fs=640MHzCurrent Steering

DACI14HF3TO20DA4CAL_1V8_EG8M 14BitsOutputcurrent=3mAto20mASFDR=70dBc@210MHz

Fs=750MHzCurrent Steering


Audio DAC No of bits Main features Type

DA24VASDLA_18 24Bits SNR 98 db Sigma Delta


• Best-in-classPPA• Multiplearchitecturesavailable

• Availableforvariousapplicationandcustomizableonrequest

• Highspeed(upto10Gsps)• HighResolution(upto24bits)

Thefollowingfeaturesaresupportedin28nmFD-SOIDACs:Re

solu

tion

(bits

)

Speed

6

8

10

12

14

16

18

20

24∑∆

R-String

R-String

AudioADC

Instrumentation DACMedical/Scientific instrumentation

Transmission DACMulti-carrier,Multi-mode baseband/wideband applicationVideo DAC

Compliant to All VideoStandard specification

Servo DACCD/DVD player

Low Speed/DC Audio Band 100 k - 5 Msps 5 - 250 Msps 250 - 500 Msps

Static DACDC motor control,DC gain & bias control

Gsps

Current Steering

13

ONE-TIME-PROGRAMMABLE (OTP) IP: FUSEOTPIPisaone-timeprogrammablememorybasedonananti-fusecellwithsynchronousinterfaceanddual-supplyvoltage.Itisanon-volatilememory,withembeddedprogrammingcapabilityandaspecificprogrammingsequence.In28nmFD-SOItechnology,memorycellssupportdatastorageusingdielectricbreakdownphenomena.Alllibrariesembedahigh-voltagechargepumpanddonotrequireanHVpad.

Library Name Key Features/Specification

FU_OTP_LLR_EG OTPanti-fuselibraryisdesignedin28nmFD-SOItechnology


• Dual supply:1.1V&1.8V(includesaninternalpowerswitch)

• IPsinmultiple-metal stackarerespectivelyfullyblocked

• Storage capacityof1Kbit,2Kbit,4Kbit,8Kbit,and16Kbit.

• Maximum clock frequency(functional)is120MHz

• Wordsize:• Standard with ECC correction:32usefuldatabyword(Defaultmodenotincrementalprogramming)

• No ECC, correction is done by redundancy:16usefuldatabyword(onlyforwordrequiringincrementaldataprogramming)

• Maximum clock frequency(scantest)is100MHz

• Mean programming timeislessthan10us/bit

• Programming lockword-by-word.• Static16bitsdatawordavailableatpowerON

TheOTPIPprovidesthefollowingfeaturesinits28nmFD-SOItechnologyvariant:

EMBEDDED POWER-MANAGEMENT IPsEmbeddedpower-managementIPsenablepoweroptimizationinSoCandASICdesignsthroughBody-Biasing,PowerSwitches,andEmbeddedMetrologycells.

Power Management IPs Description

Body-Biasing IPs

BBGEN_LLR_EG Embedded Body Bias Generator with low power, low Vt and regular Vt process options

BBMUX21_LLR_EG Embedded Body Bias Multiplexer with low power, low Vt and regular Vt process options

Power Switches

EPOD_PLMEG_LLR_EG Peripheral Embedded Power Distribution IP with Power Line Multiplexing feature and switch device EG

EPOD_PSWFBMP_LLR_EG Peripheral Embedded Power Distribution IP with a switch device having Feedback and Modular Pre-charge features

Embedded Metrology Cells

EMET_BE Front-End embedded metrology structure

EMET_FE Back-End embedded metrology structure


14

Sensor Features/Specification

Low Area Temperature Sensor

•Measureson-chiptemperature•Accuracy:±4ºC•Senserange:-40ºCto125ºC•SuitableforsmallSOCs,safetyfeatures

High-Performance Distributed Voltage & Temperature Sensor

•RemoteV&Tsensingwithcentralizedprocessing•Temperatureaccuracy:±1ºCover-40ºCto125ºC•Voltageaccuracy:±5mVover0.6V-1.25V•Temperature-independentvoltage-basedcalibration


VOLTAGE & THERMAL SENSORSVoltageSensorlibraryallowstoembedvoltage-measurementfeatureinSoC,andThermalSensorprovidesdigitalmeasurementofthejunctiontemperature.

Theadvantagesofusingthesesensorsin28nmFD-SOItechnologyare:• DynamicFrequencyScaling(DFVS)forhighperformance

• ThermalandVoltageprofiling,security,thermal(fan)control

• IR-DropAnalysis,Smartpowermanagement

PROCESS-MONITORING BOX (PMB)Process-MonitoringSensorstracktheon-chipprocessfluctuationsfromfab-to-fab,wafer-to-wafer,andwithin-waferusingauniquedieprocessIDtoensurethechipiswithinthepre-definedprocesslimits(temperaturemonitoring,compensationanddebug,andfailureanalysis).

Library Name Description

Sensors

GO2_LR_OD_18 MonitorstheprocessofGO2OD18devicesGO1_LL Measures the SoC performance & helps to debug the failure analysis of chip, based on Low-Power & Low-Vt process optionGO1_LR Measures the SoC performance & helps to debug the failure analysis of chip, based on Low-Power & Regular-Vt process optionCPR8T_LL Contains 8-Track Critical-Path Replica (CPR) cells used for process compensation and voltage scaling

CPR_LLContains12-TrackCritical-PathReplica(CPR)cellsusedforprocesscompensationandvoltagescaling,with three dedicated sensors, based on Low-Power & Low-Vt process option

CPR_LRContains12-TrackCritical-PathReplica(CPR)cellsusedforprocesscompensationandvoltagescaling,with three dedicated sensors, based on Low-Power & Regular-Vt process option

RCM5_COUP_LL Monitors back-end process

Controllers

CONTROL8T_LL 8-Track Process-Monitoring Controller for on-chip compensation to save power, based on Low-Power & Low-Vt process optionCONTROL_LL 12-TrackProcess-MonitoringControllerforon-chipcompensationtosavepower,basedonLow-Power&Low-Vtprocessoption

CONTROL_LR12-TrackProcess-MonitoringControllerforon-chipcompensationtosavepower,based on Low-Power & Regular-Vt process option

CONTROL8T_LL_ASYNC 8-Track Process-Monitoring asynchronous controller with soft CPR, based on Low-Power & Low-Vt process optionCONTROL8T_LR_ASYNC 8-Track Process-Monitoring asynchronous controller with soft CPR, based on Low-Power & Regular-Vt process optionCONTROL_LR_ASYNC 12-TrackProcess-MonitoringasynchronouscontrollerwithsoftCPR,basedonLow-Power&Regular-VtprocessoptionWRAPPER_LL Contains controller logic for sensors used in process monitoring and on-chip compensation to save power


15Interfaces PHYs Description

MIPIDPHY_MCNN_4MFAA_1500MBP_LR_EG MIPIDPHYMaster4DataLane

MIPIDPHY_SCNN_1SFAA_1500MBP_LR_EG MIPI DPHY Slave 1 DataLane

MIPIDPHY_SCNN_2SFAA_1500MBPS_LR_EG MIPIDPHYSlave2DataLane

USB2_1PHY PhysicallayerofUSB2Host&Deviceports



USB2PHY_S PhysicallayerofUSB2Host&Deviceports

OTG2 AddshostfunctionalitytoUSBperipherals

HDMITX_3G4_1V8_LL_EG Electrical layer of the HDMI Transmitter

HDMITX_6G0_1V8_LLR_EG Electrical layer of the HDMI Transmitter

MIPIDIGRF4GPHY_1TX2RX ElectricallayeroftheDIGRF4GPHYtransmitterandreceiver

LVDS1V8_EG Low Voltage Differential Signaling 1.8V IO in standard frame

DPTX_4L_IM5G4_1V8_LLR_EG AnalogphysicallayerofDisplayPorttransmitter

HDMIDPRX_5G4_3V3_LLR_EG DP/HDMI/DVI Combo Receiver


Regulator Key Features/Specification

DC_LN_1V8TO1V0_PHY_EG•Generates1.0Voutputfrom3.3Vand1.8VinputsforvariousPHYIPs•Maininputsupplyisfrom3.3V±10%and1.8V±150mV•Regulatedoutputsupplyis1.0V±100mV

DC_LN_1V8TO1V0_USB_EG•Supportsmain/inputsupplyof1.65V-1.95Vanddigitalregulatedoutputsupply:1.0V±100mV•Nooff-chipcapacitorrequiredforregulatorstability

DC_LN_1V81V0_STBY_LR_EG•Generatesmultipleoutputs(1.8V,1.0V)from3.3Vand1.35Vinputs.•Theregulatedoutputsupplyis1.0V±100mV,whichcanbeprogrammeddownto0.6V,1.8V±150mV

DC_LN_2V51V81V0_LR_EG•Generatesmultipleoutputs(2.5V,1.8V,1.0V)from3.3Vand1.35Vinputs.•Main/inputsupply1:3.0V-3.6VandDDR4supply(1.2V-5%to1.8V+10%)•Regulatedoutputsupplyis1.0V±100mV,whichcanbeprogrammeddown


HIGH-SPEED SERIAL LINKSAdedicatedportfolioofHigh-SpeedSerialLinksissupportedin28nmFD-SOItechnology.

LINEAR REGULATORS28nmFD-SOILinearRegulatorsofferflexibilitytodesignersintermsofgeneratedoutputsfromtherequiredinputsthusdeliveringcustomizedsolutions,withotherexcitingfeatures.

Regulatorfeaturesin28nmFD-SOItechnologyare:• Customizedsolutionforinput&outputvoltages

• Configurableloadcurrent• Lowdrop-out,<200mV

• Noexternalcapacitancerequired• Fast-transientresponse,HighPSR• Voltage-handlingcapacityhigherthandevicebreakdown

• Low-powermodeforStandby• SafetyFeatures:Power-on-Reset,Supplymonitoring,Over-currentprotection,SafeStartup

For more information on ST products and solutions, visit www.st.comOrder code: BRFDSOI0616

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28nm fd-soi technology catalog

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