hacking the backplane: optimizing backplane …©eric bogatin 2006 slide -1 hacking the backplane:...

© Eric Bogatin 2006

Slide -1

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Hacking the Backplane:Optimizing Backplane Performance with

Measurement Based Models Using Agilent ADS

Dr. Eric BogatinSignal Integrity Evangelist

Bogatin Enterprises

Fall 2006

[email protected]


Slide -2

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Hacker (from: www.iwriteiam.nl/HackerDef.html)

hacker:hacker: [originally, someone who makes furniture with an axe] n. …6. An expert or enthusiast of any kind. One might be an astronomy hacker, for example. 7. One who enjoys the intellectual challenge of creatively overcoming or circumventing limitations.


Slide -3

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Hacking the Backplane: The Process

• Goal “improving backplane performance”(applies to any backplane)

• Perform 4 port VNA/TDR measurements• Synthesize the circuit model• Optimize parameter values• Validate the model• Identify the weak links• Optimize the design for enhanced performance• Evaluate enhanced performance


Slide -4

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For More Information

www.BeTheSignal.comFeature articles and columnsSignal integrity public classesOnline lecturesResources Special offer: use coupon code ADS651 to view for free OLL-651 from the www.BeTheSignal.com web site

Published by Prentice Hall, 2004


Slide -5

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Example Backplane:Tyco HM-Zd Legacy Backplane with

XAUI Test Cards

~ 16 inch backplane traces

~ 2

inch

dau

ghte

r ca

rd tr

aces

Total length ~ 20 inches

~ 2

inch

dau

ghte

r ca

rd tr

aces


Slide -6

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Differential mode

Common mode

A Secret to Minimize Confusion About Differential S-Parameters

Think:Think:Differential signalsDifferential signalsCommon signalsCommon signals


Slide -7

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Transparent Translation Between the 4-Port Matrices with PLTS and ADS

Single ended S-parameters Differential S-parameters

Differential T-parametersSingle ended T-parameters

TDR

TermTerm3

Z=50 OhmNum=3

TermTerm1

Z=50 OhmNum=1

TeTe

Z=Nu

TeTe

Z=NuML2CTL_V

CLin1

W [1]=W _1 milLength=Len inSubst="Subst1"

ADS

VNA

Frequency Domain

Time Domain


Slide -8

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TDD11Differential Reflected Signal

Reflected signalConverted to 1st order Impedance Profile

Displayed with Agilent’s PLTS


Slide -9

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Simulating Eye Diagrams from TDD21

PRBS, 5 Gbps, 211 – 1 bits

Convolution integral

=Overlay each bit, synchronous with the clock

+Displayed with Agilent’s PLTS

Impulse Response


Slide -10

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De-constructing Performance Path

• ProsRelate physical features with performanceCan extract design information and material propertiesSimulates very fastDon’t need a lot of geometry information or vendor information

• ConsMay be difficult to find optimum topologyMay be tricky to optimize the parametersNo unique topology – no assurance you have the right one

Fit parameterized models to measured response

Circuit topology model

2 4 6 8 10 120 14

-80

-60

-40

-20

-100

0

freq, GHz

dB(S

21_m

eas)

dB(S

21_s

im)


Slide -11

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Measured Performance of the Backplane in ADS

S_ParamSP1

CalcGroupDelay=yesCalcS=yesStep=10 MHzStop=14 GHzStart=10 MHzSweepVar="freq"

S-PARAMETERS

TranTran1

MaxTimeStep=10 psecStopTime=10 nsecStartTime=0 nsec

TRANSIENT

S4PSNP1

4

1 2

3 RefTermTerm2

Z=50 OhmNum=2

TermTerm1

Z=50 OhmNum=1

TermTerm3

Z=50 OhmNum=3

TermTerm4

Z=50 OhmNum=4

V3_meas

S4PSNP2

4

1 2

3 RefVtPulseSRC2

Period=100 nsecWidth=100 nsecFall=(2.25*RT) nsecRise=(2.25*RT) nsecEdge=erfDelay=0 nsecVhigh=1 VVlow=0 V

t

RR5R=50 Ohm

RR2R=50 Ohm

RR1R=50 Ohm

RR4R=50 Ohm

Converting frequency domain data into time domain simulation


Slide -12

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Starting Place: Measured S-Parameters

2 4 6 8 10 120 14

-80

-60

-40

-20

-100

0

freq, GHz

dB(S

dd21

_mea

s)

2 4 6 8 10 120 14

-100

0

100

-200

200

freq, GHz

phas

e(Sd

d21_

mea

s)

2 4 6 8 10 120 14

-50

-40

-30

-20

-10

-60

0

freq, GHz

dB(S

dd11

_mea

s)

2 4 6 8 10 120 14

-100

0

100

-200

200

freq, GHz

phas

e(Sd

d11_

mea

s)

MeasEqnMeas5

Sdd11_meas=0.5*(S11+S33-S13-S31)Sdd21_meas=0.5*(S21+S43-S32-S41)

EqnMeas


Slide -13

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Transformed by ADS into Time Domain Single Ended

2 4 6 80 10

450

500

550

400

600

time, nsec

V1_

mea

s, m

V

2 4 6 80 10

-0

100

200

300

400

-100

500

time, nsecV

2_m

eas,

mV

2 4 6 80 10

0

20

40

-20

60

time, nsec

V3_

mea

s, m

V

2 4 6 80 10

-15

-10

-5

0

5

-20

10

time, nsec

V4_

mea

s, m

V

1 2

3 4

TDR into chan 1

NEXT FEXT

TDR TDT


Slide -14

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Eye Diagram Simulated from Frequency Domain Measured Data

(PLTS measured Eye Diagram)ADS simulation from the measured S-Parameter data


Slide -15

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Physical Features of Backplane

SMA Launch

Daughter card traces

Daughter card via

Backplane via

connector Backplane traces

SMA Launch


Daughter card via

Backplane viaconnector

Impe

danc

e, in

Ohm

s


Slide -16

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Simplifications to the Model

1. Symmetry between one line in the pair and the other –no mode conversion

2. Symmetry from one end to the other – back half same as front half

3. Negligible via stubs4. Same via model in

daughter card and backplane – different lengths

5. Same dielectric constant and dissipation factor in daughter card and backplane

TDD11 TDD22 Losses smear out far end

1 nsec/div

2 GHz/div


Slide -17

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Circuit Model Topology

V4_sim

V2_sim

Daughter Card via

Backplane viaDaughter Card via

Daughter CardSMA launch

Backplane

ConnectorConnector

TLINTL36

F=(1/TD_SMA) GHzE=360Z=Z_SMA Ohm

ML2CTL_VCLin6

ReuseRLGC=noRLGC_File=Layer[2]=2Layer[1]=2W[2]=W2_DC_1 milS [1]=S_DC_1 milW[1]=W1_DC_1 milLength=Len_DC_1 inSubst="Subst1"

TLINTL37

F=(1/TD_launch) GHzE=360Z=Z_launch Ohm

TLINTL38


CLINPTL40

Ao=0Ae=0Ko=Dk1_DC_1Ke=Dk1_DC_1L=Len_DCvia milZo=(Z11_DCvia-Z12_DCvia) OhmZe=(Z11_DCvia+Z12_DCvia) Ohm

ML2CTL_VCLin7

ReuseRLGC=noRLGC_File=Layer[2]=2Layer[1]=2W[2]=W2_CON_1 milS [1]=S_CON_1 milW[1]=W1_CON_1 milLength=Len_CON_1 inSubst="Subst2"

ML2CTL_VCLin8

ReuseRLGC=noRLGC_File=Layer[2]=2Layer[1]=2W[2]=W2_BP_1 milS [1]=S_BP_1 milW[1]=W1_BP_1 milLength=Len_BP_1 inSubst="Subst3"

CLINPTL44

Ao=0Ae=0Ko=Dk1_BP_1Ke=Dk1_BP_1L=Len_BPvia milZo=(Z11_BPvia-Z12_BPvia) OhmZe=(Z11_BPvia+Z12_BPvia) Ohm

ML2CTL_VCLin9

ReuseRLGC=noRLGC_File=Layer[2]=2Layer[1]=2W[2]=W2_CON_1 milS [1]=S_CON_1 milW[1]=W1_CON_1 milLength=Len_CON_1 inSubst="Subst2"

CLINPTL45

Ao=0Ae=0Ko=Dk1_DC_1Ke=Dk1_DC_1L=Len_DCvia milZo=(Z11_DCvia-Z12_DCvia) OhmZe=(Z11_DCvia+Z12_DCvia) Ohm

ML2CTL_VCLin10

ReuseRLGC=noRLGC_File=Layer[2]=2Layer[1]=2W[2]=W2_DC_1 milS [1]=S_DC_1 milW[1]=W1_DC_1 milLength=Len_DC_1 inSubst="Subst1"

TLINTL47


TLINTL48


TLINTL49


TLINTL50


RR41R=50 Ohm

RR42R=50 Ohm

TLINTL35


RR40R=50 Ohm

RR16R=50 Ohm

CC4C=C_DCvia pF

CC26C=C_DCvia pF

CC5C=C_DCvia pF

CC27C=C_DCvia pF

CC7C=C_BPvia pF

CC28C=C_BPvia pF

CC6C=C_BPvia pF

CC29C=C_BPvia pF

CLINPTL42

Ao=0Ae=0Ko=Dk1_BP_1Ke=Dk1_BP_1L=Len_BPvia milZo=(Z11_BPvia-Z12_BPvia) OhmZe=(Z11_BPvia+Z12_BPvia) Ohm

VtPulseSRC3

Period=100 nsecWidth=100 nsecFall=(2.25* RT) nsecRise=(2.25*RT) nsecEdge=erfDelay=0 nsecVhigh=1 VV low=0 V

t

SMA Launch


Daughter card via

Backplane via

connector Backplane traces

SMA Launch


Daughter card via

Backplane viaconnector

SMA LaunchDaughter card traces

Daughter card via

Backplane via

connector

Backplane traces

SMA LaunchDaughter card traces

Daughter card viaBackplane

via

connector


Slide -18

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Very Simple Differential Via Model

Ze = Z11 + Z12Zo = Z11 – Z12Dke = Dko = DkLen = 90 mils (daughter card)

Len = 190 mils (backplane)

Len

uniform ideal differential pair model

Negligible stub

Cvia

Ideal, lossless differential pair


Slide -19

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Optimizing Circuit Model Parameters

• Outputs:T11 (TDR) (sensitive to single ended impedance profile)T21 (TDT) (sensitive to len, dielectric constant)T31 (NEXT) (sensitive to line to line coupling)T41 (FEXT) (should be 0, sensitive to via structure)TDD11 (DTDR) (sensitive to diff impedance profile)SDD21 (sensitive to impedance profile and losses)

• Strategy:Start at the beginning of the modelOptimize parameter values- try for TDD11 best fit


Slide -20

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0.5 1.0 1.5 2.00.0 2.5

450

500

550

400

600

time, nsec

V1_

mea

s, m

VV

1_si

m, m

V

0 .5 1.0 1.5 2.00.0 2.5

0.9

1.0

1.1

0.8

1.2

time, nsec

Vdd

11__

mea

sV

dd11

__si

m

54 6

-15

-10

-5

0

5

-20

10

time, nsec

V4_

mea

s, m

VV

4_si

m, m

V

0 .5 1.0 1.5 2.00.0 2.5

0

20

40

60

-20

80

time, nsec

V3_

mea

s, m

VV

3_si

m, m

V

Sculpting the Daughter Card Parameters – dielectric thickness

ParamSweepSweep1

Step=1Stop=11Start=7SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="Tran1"SweepVar="H1_DC_1"

PARAMETER SWEEP

Sweeping H1_DC: 7 to 11 mils, step 1 milImpacts V11, V31, Vdd11Optimized value of H1_DC ~ 9.2 mils

NEXT FEXT

TDR DTDR


Slide -21

www.BeTheSignal.com

0.5 1.0 1.5 2.00.0 2.5

450

500

550

400

600

time, nsec

V1_

mea

s, m

VV

1_si

m, m

V

0 .5 1.0 1.5 2.00.0 2.5

0.9

1.0

1.1

0.8

1.2

time, nsec

Vdd

11__

mea

sV

dd11

__si

m

0 .5 1.0 1.5 2.00.0 2.5

0

20

40

60

-20

80

time, nsec

V3_

mea

s, m

VV

3_si

m, m

V

54 6

-15

-10

-5

0

5

-20

10

time, nsec

V4_

mea

s, m

VV

4_si

m, m

V

Sculpting the Daughter Card Parameters – separation

Sweeping S1_DC: 10 to 20 mils, step 2 milsImpacts V31, Vdd11Optimized value of S1_DC ~ 15 mils

NEXT FEXT

TDR DTDR


Slide -22

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Sculpting the Backplane Parameters – line width

2 4 6 80 10

0.9

1.0

1.1

0.8

1.2

time, nsecV

dd11

__m

eas

Vdd

11__

sim

2 4 6 80 10

450

500

550

400

600

time, nsec

V1_

mea

s, m

VV

1_si

m, m

V

W1_BP = 8 mils to 16 mils, step 2

Optimized value ~ 11.6

TDR

DTDR

VARVAR14

S_BP_1=16W2_BP_1=W1_BP_1W1_BP_1=11.6Len_BP_1=16.7

EqnVar

VARVAR16

T2_BP_1=1Df2_BP_1=Df1_BP_1Df1_BP_1=Df1_DC_1Dk2_BP_1=Dk1_BP_1Dk1_BP_1=4H2_BP_1=H1_BP_1H1_BP_1=16

EqnVar


Slide -23

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Optimizing Daughter Card/Backplane Via Parameters

Ze = Z11 + Z12Zo = Z11 – Z12Dke = Dko = Dk

Cvia

0.5 1.0 1.5 2.00.0 2.5

0.9

1.0

1.1

0.8

1.2

time, nsec

Vdd

11__

mea

sV

dd11

__si

m

0 .5 1.0 1.5 2.00.0 2.5

450

500

550

400

600

time, nsec

V1_

mea

s, m

VV

1_si

m, m

V

0 .5 1.0 1.5 2.00.0 2.5

0

20

40

60

80

-20

100

time, nsec

V3_

mea

s, m

VV

3_si

m, m

V

54 6

-20

-10

0

10

20

-30

30

time, nsec

V4_

mea

s, m

VV

4_si

m, m

V

Sweeping Z11: 50 to 70 ohms, step 5

Z11 = 50 Ohms

Z11 ~ 65 Ohms

NEXT FEXT

TDR DTDR


Slide -24

www.BeTheSignal.com

0.5 1.0 1.5 2.00.0 2.5

0.9

1.0

1.1

0.8

1.2

time, nsec

Vdd

11__

mea

sV

dd11

__si

m

0 .5 1.0 1.5 2.00.0 2.5

450

500

550

400

600

time, nsec

V1_

mea

s, m

VV

1_si

m, m

V

0 .5 1.0 1.5 2.00.0 2.5

0

20

40

60

80

100

120

-20

140

time, nsec

V3_

mea

s, m

VV

3_si

m, m

V

54 6

0

20

40

-20

60

time, nsec

V4_

mea

s, m

VV

4_si

m, m

V



Cvia

Sweeping Z12: 10 to 50 ohms, step 10

Z12 = 50 OhmsZ11 ~ 65 ohmsZ12 ~ 30 Ohms

NEXT FEXT

TDR DTDR


Slide -25

www.BeTheSignal.com

0.5 1.0 1.5 2.00.0 2.5

0.9

1.0

1.1

0.8

1.2

time, nsec

Vdd

11__

mea

sV

dd11

__si

m

0 .5 1.0 1.5 2.00.0 2.5

0

20

40

60

-20

80

time, nsec

V3_

mea

s, m

VV

3_si

m, m

V

54 6

-15

-10

-5

0

5

-20

10

time, nsec

V4_

mea

s, m

VV

4_si

m, m

V

0 .5 1.0 1.5 2.00.0 2.5

450

500

550

400

600

time, nsec

V1_

mea

s, m

VV

1_si

m, m

V



Cvia

Sweeping C_DCvia: 0.2 to 0.6 pF, step 0.1 pF

C_DCvia = 0.6 pFZ11 ~ 65 ohmsZ12 ~ 30 ohmsC_DCvia ~ 0.4 pF

NEXT FEXT

TDR DTDR


Slide -26

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Via Analysis

VARVAR13

C_DCvia=0.4 {o}Len_DCviaStub=100-Len_DCviaLen_DCvia=90 {o}Z12_DCvia=30 {o}Z11_DCvia=65 {o}

EqnVar


Cvia

Zodd = 65 – 30 = 35 ohmsZdiff = 2 x Zodd = 70 Ohms


Slide -27

www.BeTheSignal.com

Optimized Parameters

0.5 1.0 1.5 2.00.0 2.5

0.9

1.0

1.1

0.8

1.2

time, nsec

Vdd

11__

mea

sV

dd11

__si

m

0 .5 1.0 1.5 2.00.0 2.5

450

500

550

400

600

time, nsec

V1_

mea

s, m

VV

1_si

m, m

V

0 .5 1.0 1.5 2.00.0 2.5

0

20

40

60

-20

80

time, nsec

V3_

mea

s, m

VV

3_si

m, m

V

54 6

-15

-10

-5

0

5

-20

10

time, nsec

V4_

mea

s, m

VV

4_si

m, m

V

Good, but not perfect.

Is it good enough?

NEXT FEXT

TDR DTDR


Slide -28

www.BeTheSignal.com

Overall Time Domain Performance

2 4 6 80 10

0.9

1.0

1.1

0.8

1.2

time, nsec

Vdd

11__

mea

sV

dd11

__si

m

2 4 6 80 10

450

500

550

400

600

time, nsec

V1_

mea

s, m

VV

1_si

m, m

V

2 4 6 80 10

0

20

40

60

-20

80

time, nsec

V3_

mea

s, m

VV

3_si

m, m

V

2 4 6 80 10

-15

-10

-5

0

5

-20

10

time, nsec

V4_

mea

s, m

VV

4_si

m, m

V

Very good time domain performance

NEXT FEXT

TDR DTDR


Slide -29

www.BeTheSignal.com

Frequency DomainSweeping Df

2 4 6 8 10 120 14

-50

-40

-30

-20

-10

-60

0

freq, GHz

dB(S

dd11

_mea

s)dB

(Sdd

11_s

im)

2 4 6 8 10 120 14

-100

0

100

-200

200

freq, GHz

phas

e(Sd

d11_

mea

s)ph

ase(

Sdd1

1_si

m)

2 4 6 8 10 120 14

-80

-60

-40

-20

-100

0

freq, GHz

dB(S

dd21

_mea

s)dB

(Sdd

21_s

im)

2 4 6 8 10 120 14

-100

0

100

-200

200

freq, GHz

phas

e(Sd

d21_

mea

s)ph

ase(

Sdd2

1_si

m)

Df from 0.015 to 0.035 step 0.005

Df ~ 0.025

SDD11 SDD21


Slide -30

www.BeTheSignal.com

Final Frequency Domain Response

2 4 6 8 10 120 14

-50

-40

-30

-20

-10

-60

0

freq, GHz

dB(S

dd11

_mea

s)dB

(Sdd

11_s

im)

2 4 6 8 10 120 14

-100

0

100

-200

200

freq, GHz

phas

e(Sd

d11_

mea

s)ph

ase(

Sdd

11_s

im)

2 4 6 8 10 120 14

-80

-60

-40

-20

-100

0

freq, GHz

dB(S

dd21

_mea

s)dB

(Sdd

21_s

im)

2 4 6 8 10 120 14

-100

0

100

-200

200

freq, GHz

phas

e(S

dd21

_mea

s)ph

ase(

Sdd

21_s

im)

BW of the model ~ 10 GHz

2 4 6 8 10 120 14

1E-9

2E-9

3E-9

4E-9

0

5E-9

freq, GHz

dela

y(2,

1)de

lay(

6,5)

delay

SDD11 SDD21

Very little dispersion


Slide -31

www.BeTheSignal.com

21 22 23 24 25 26 27 28 2920 30

0.00

0.05

0.10

0.15

0.20

-0.05

0.25

time, nsec

Vdd

21_p

rbs_

mea

sV

dd21

_prb

s_si

m

PRBS Results: 5 Gbps, BW = 10 GHz

21 22 23 24 25 26 27 28 2920 30

0

50

100

150

200

-50

250

time, nsec

V_pr

bs_f

ilter

ed, m

V

Bit stream going into the interconnect VDD21 signal out

measured

simulated with model


Slide -32

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Measured and Simulated Eye Diagram: 5 Gbps PRBS

measured simulated


Slide -33

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Hacking the Backplane

• Laminate dissipation factor: From Df = 0.025 0.01

• Via designFrom Zdiff = 2 x (65-30) = 70 Ohms 100 ohmsFrom C = 0.4 pF and 0.3 pF 0.1 pF

• Signal TracesFrom Zdiff = 106 ohms 100 Ohms


Slide -34

www.BeTheSignal.com

Df from 0.025 0.01

2 4 6 8 10 120 14

-80

-60

-40

-20

-100

0

freq, GHz

dB(S

dd21

_mea

s)dB

(Sdd

21_s

im)

21 22 23 24 25 26 27 28 2920 30

0.00

0.05

0.10

0.15

0.20

-0.05

0.25

time, nsec

Vdd

21_p

rbs_

mea

sV

dd21

_prb

s_si

m

measured

simulated

measured

simulated

Measured response Simulated response


Slide -35

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Optimized Via Design

From 70 Ohm to 100 Ohm diff Impedance

Removal of NFPs, excess capacitance reduced to 0.1 pF

2 4 6 80 10

0.9

1.0

1.1

0.8

1.2

time, nsec

Vdd1

1__m

eas

Vdd1

1__s

im



Slide -36

www.BeTheSignal.com

2 4 6 80 10

0.9

1.0

1.1

0.8

1.2

time, nsec

Vdd1

1__m

eas

Vdd1

1__s

im

Daughter Card and Back Plane Differential Impedance: 106 ohms 100 Ohms


Decreasing H to decrease diff impedance


Slide -37

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Hacking: Pushing All the Knobs

• Optimized performanceLower loss laminate (could be compensated with TX, RX equalization)Transparent viasImpedance matched traces

Original response Optimized response

5 Gbps


Slide -38

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Optimized Design Enables 10 Gbps Performance

Original response Optimized response

5 Gbps

10 Gbps


Slide -39

www.BeTheSignal.com

Summary

• PLTS enables complete characterization of backplane differential channel

• ADS can be used to build simple, topology based circuit modelsIntegrate measured data

Multiple display modes: emulate TDR, DTDR, VNA, Differential VNA, PRBS, eye diagram

Multiple differential pair elements

Parameterized values for all circuit elements

Integrated 2D field solver

Quick, fast, interactive parameter optimization

Simple comparison of measured and simulated response

• Biggest impact on performance is from:Dielectric loss

Via design

Matched trace impedances

• This optimized backplane can operate at over 10 Gbps


Slide -40

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Published by Prentice Hall, 2004

hacking the backplane: optimizing backplane …©eric bogatin 2006 slide -1 hacking the backplane:...

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