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JasperGold for Targeted ROI

• JasperGold solutions portfolio delivers competitive advantage across the spectrum of SoC design applications:– Architectural analysis– RTL design and debug– Verification, including regression test and low power analysis– Chip integration and software programmers’ model– Silicon debug

• JasperGold is for:– Architects– RTL designers– Verification engineers and formal experts– Silicon teams

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JasperGold Targeted ROI and Applications Summary

Jasper Application Area

Resource Impact

Risk Impact TTM Impact ROI

Architectural verification

High High High

RTL design and debug High High High

Proofs of critical functionality•Verification •Regression test •Low-power modes

High High High High

SoC Integration High High High

Post-silicon debug High High Varies

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Architectural and RTL Design and Debug

"JasperGold's user interactive Design Tunneling enable the tool to solve previously intractable block-level proofs by directing the engines to consider only the logic which is relevant to the problem."  

Prosenjit Chatterjee, NVIDIA Corporation

Jasper Application Area

Examples ROI

Architectural verification

•Communications and bus architecture•Cache coherency•Multi processor protocol•Deadlocks, livelocks•Reference modeling / executable spec

High

RTL design and debug

•RTL development and designer sandbox •X-propagation detection•Initialization connections•Logic optimization•Register verification

High

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Proofs of Critical Functionality / Verification

"Jasper has significantly improved the scalability of formal model checking. JasperGold Verification System's interactive use-model allows formal model checking to run on larger, more complex designs."  

Shrenik Mehta, Sun Microsystems

Jasper Application Area

Examples ROI

Proofs of critical functionality

•Packet integrity•Multi-processor coherence•Flow control•Error correction•Protocol certification•Token leakage•Regression test•Mixed signal and asynchronous design support•DFT

High

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Low Power Verification

“On the wireless side, the big focus is low power. That introduces the complexity of having to deal with low-power techniques. There are many power domains and many voltage domains…All of that needs to be not only designed, but verified. Making sure that none of the power modes are incompatible with each other is one of the big challenges.”

Philippe Magarshack , ST Microelectronics

Jasper Application Area

Examples ROI

Verification of low-power modes

•Power architecture•Clock gating•Power shutoff isolation cells

Varies

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SoC Integration

"After using several competing products, Qualcomm selected Jasper as our formal verification provider of choice because of their superior technology and solutions-oriented applications support. We are now deploying JasperGold across design and verification teams worldwide to deliver higher quality in the industry’s most highly integrated wireless devices.“

J. Scott Runner, Qualcomm

Jasper Application Area

Examples ROI

SoC Integration •Chip-level connectivity , automated programming • Automated pad ring verification• Automated clock verification

•Connectivity debug automation, connectivity matrix • Chip-level verification• Automation of problem formulation, analysis,

debugging• Multi-cycle path verification

•Firmware development• Programming sequence generation and automation

High

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Silicon Debug

“In post-silicon debug, a set of observed events or conditions describes a failure scenario... Modern formal verification methods are especially adept at finding counterexamples to properties, and can often do so efficiently in large state spaces. “

C. Richard Ho, D. E. Shaw Research

Jasper Application Area

Examples ROI

Post-silicon debug

•Root cause bugs•Validate fixes

Varies

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JasperGold Leads Industry Deployment

JasperGold Technology Deployment• Methodology• Capacity• Visibility

• Supported by Jasper Services

• Patented formal technology– 12 patents, more pending

Methodology

Capacity

FormalTechnolog

y

Visibility

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Jasper Portfolio of Solutions