young, chadwin delin - ncsu
TRANSCRIPT
ABSTRACT
YOUNG, CHADWIN DELIN. Charge Trapping Characterization Methodology for the Evaluation of Hafnium-based Gate Dielectric Film Systems. (Under the direction of Dr. Richard T. Kuehn and Dr. Veena Misra) Scaling of advanced CMOS device dimensions, as set forth for future technology nodes by
the International Technology Roadmap for Semiconductors (ITRS), will require reduction of
the equivalent oxide thickness (EOT) of gate dielectrics below a point that can be physically
realized using silicon dioxide. In order to continue EOT scaling below ~1.5 nm and reduce
gate leakage current, higher dielectric constant materials will be needed to replace SiO2.
Hafnium-based dielectrics are being widely investigated as potential candidates for the gate
dielectric application. Their charge trapping characteristics were identified as a primary
issue preventing the introduction of Hf-based materials into CMOS technology, potentially
causing threshold voltage instability and mobility degradation.
Several measurement techniques can be used to study and quantify charge trapping:
Capacitance-Voltage (C-V) hysteresis, alternating stress and sense Vfb/Vt instability, charge
pumping, and fast transient Id-Vg measurement. While each of these techniques can provide
information on specific aspects of the charge trapping phenomenon, some measurements are
more convenient (e.g., less time consuming), and some may be more sensitive for resolving
subtle differences between the experimental samples. In particular, C-V hysteresis
measurements can be used to monitor ∆Vfb shifts for evaluation of hysteresis. A more
quantifiable technique that uses a constant voltage gate dielectric stress (CVS) with
interspersed limited-voltage-range C-V measurements around flatband can be used.
Although systematic, this technique results in the de-trapping of some of the charge between
the stress and sense sequence. A more useful approach is the charge pumping (CP) technique.
Fixed-amplitude charge pumping (FA CP) measures interface state densities, whereas
variable-amplitude (VA CP) measures trap densities in the high-κ bulk. However,
interpretation of the data can be complicated due to the gate and source/drain leakage.
Another powerful technique is the fast transient Id-Vg measurement in the microsecond
regime. The shift of the Id-Vg curves generated by the up and down swing of a trapezoid
pulse (i.e., ∆Vt) corresponds to the amount of the trapped charge. Our data indicates that the
fast transient and charge pumping results on the charge trapping correlate rather well (though
there are differences in values) while the “stress and sense” approach seems to be less
adequate. Charge pumping and fast transient measurements were conducted on HfSixOy
(20% SiO2) and “hybrid stack” (HfO2/ HfSixOy) gate dielectrics to investigate the effects of
trapped charge on device performance (i.e., mobility). The HfSixOy films were deposited at 2
Torr and 4 Torr and were subjected to various post deposition anneal (PDA) ambients and
temperatures. 4 Torr silicates exhibit a higher mobility (peak and high field) than 2 Torr
silicates that were subjected to the same post deposition processes. The impact of interfacial
and bulk high-κ properties on charge trapping issues was investigated using hybrid gate
dielectric stacks of varying physical thickness with polysilicon electrodes. FA CP gives low
interface state densities for all depositions indicating good interface passivation, whereas VA
CP and fast transient shows large trap densities in the bulk of the high-κ layer. Results
demonstrate that the bulk trapping in the high-κ film contributes to the degradation of device
performance. Using fast transient measurements and analysis, trapped charge and free-carrier
mobility can be extracted allowing characterization of the “trap free” mobility, which is quite
close to the universal electron mobility curve in the high field regime for process conditions
of interest.
CTU,NCg TNAPPING CHAna CTERI Z ATToN MBTHoDoL o GY FoRTHE EVIT,UATION OF HITNIUM-BASED G.q.rn DTBT,nCTRIC Frrvr
SySTBMS
byCnaown DnltN YouNc
A dissertation submitted to the Graduate Faculty ofNorth Carolina State University
in partial fulfillment of therequirements for the Degree of
Doctor of Philosophy
Er,rcrnrcAr, AND Corupurnn ENcTNEERTNG
Raleigh, NC
November 2003
APPROVED BY:
Dr. Richard T. KuehnChair of Advisorv Committee
Dr. Veena MisraCo-Chair of Advisory Committee
Dr. Dennis M. Mhher
To my family, Qiana, and all those who have paved a way for me to complete this research
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BIOGRAPHY Chadwin Delin Young was born to Clark and Carlotta Young on Wednesday, May 17, 1972
in Rochester, MN. From elementary school until the 7th grade, Chad attended St. Pius X
school where was in special education until the 6th grade. Through encouragement from his
parents and perseverance, Chad was able to be a part of regular classroom instruction in all
subjects by the time he reached the 7th grade. During this time, Chad participated in many
activities and sports such as Boy Scouts, hockey, basketball, soccer, football, and baseball.
In 1984, Chad’s father was transferred to the IBM facilities in Austin, TX. Upon
moving to Georgetown (suburb town of Austin), Chad was enrolled at Georgetown Junior
High School. His academics continued to improved where he was an A student and
participated in several school activities and played basketball, hockey, and soccer. Each year
Chad received several awards of which one was Co-Student of the Year in the 8th grade.
In 1986, Chad entered Georgetown High School. During his 4 years of high school,
Chad continued to excel academically; played basketball, hockey, and soccer; participated in
the Texas Alliance for Minority Engineers (TAME); and began to take on leadership
responsibilities as a Vice President in TAME and the senior class. While being involved
with TAME and having relatives in the engineering field, Chad chose to major in Electrical
Engineering. At the culmination of his high school tenure, Chad was awarded the honor of
Mr. GHS, and he received the Texas Achievement Award scholarship and admission from
the University of Texas at Austin.
While attending the University of Texas (UT), Chad continued in many leadership
roles in campus organizations such as Alpha Phi Alpha Fraternity, Inc., and the National
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Society of Black Engineers (NSBE) where he served on the chapter, regional, and national
level. In addition, Chad began to get involved in undergraduate research activities in
microelectronics/device fabrication. His most worthwhile experience was during the summer
of 1995 as a participant in the North Carolina State University Research Experience for
Undergraduates. This opportunity helped Chad confirm that pursing a Ph. D. in this area was
a good idea. As Chad’s undergraduate years came to a close, he continued to receive
numerous academic and leadership awards. Chad was inducted into the Friar Society which
is UT’s most prestigious honor society based on contributions to the University. As a senior,
he received the Ex-Students Association’s Presidential Leadership Awards given to only 2
students per classification, and he received several “best all-round” type awards from
different entities on campus. In his graduating spring semester, Chad was named National
Member of the Year in NSBE, and he received a Graduate Engineering Education Fellowship
and admission from the North Carolina State University.
While attending NC State University (NCSU), Chad joined the Center for Advanced
Electronic Materials Processes where he completed a MS degree in Electrical Engineering.
Chad continued to be involved in NSBE on the national level and he was the president of the
NCSU Graduate Student Association. Chad received the NCSU Chancellor’s African-
American Leadership Award for his involvement with the NCSU community. He continued
on for his Ph. D., where that research was completed at International SEMATECH in Austin,
TX, as part of the collaboration in the Research Center for Front End Processes.
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ACKNOWLEDGEMENTS
First, I would like to thank God and His blessing me with all those mentioned herein or
otherwise unmentioned that have been instrumental in helping me during my Ph. D. studies.
To George Brown, Richard Kuehn, and Dennis Maher: Thank you for your patience
as I hit a couple of roadblocks on the way to this point. In addition, thank you for your
sacrifice, discussion, and instruction. Dennis, thanks for all the Saturday mornings! Your
insight and support are truly appreciated. Dick, thanks for keeping me focused and for
working to allow me to finish this dissertation work at International SEMATECH (ISMT).
George, you certainly filled the role of advisor in every way when I transferred my research
to ISMT. Thank you for the direction and support.
To Ken Matthews: Thank you for joining the test group! You really don’t know how
much you made my life easier. If it wasn’t for you and your hard work with streamlining and
automating bench measurements and data collection, I would not have been able to do the
things I needed to do to complete my degree – like go to IMEC.
To Andreas Kerber, Gennadi Bersuker, Eduard Cartier, Guido Groeseneken, and
Robin Degraeve: Thank you for the discussion opportunities and measurement support.
Andi and Ed, I sincerely thank you for taking the time to show me so much more than just
how to make a measurement during my stay in Leuven. Gennadi, thanks for all the guidance,
evening discussions and ideas regarding my data. Guido and Robin, thanks for your
assistance in analyzing some of my data and for providing the accommodations I stayed in
while in Leuven.
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To the FEP Technical Team: Thanks for the samples I used in my measurements, for
the support, and the “gentle” feedback I received on “dry run” presentations .
To Dr. John R. Hauser and Dr. Veena Misra: Thank you for the discussions and
support during my Ph. D. studies.
To Mom, Dad, Cerissa, my “lovely wife-to-be” Qiana, and family: Thanks for all the
support and words of encouragement. Qiana: your support and encouragement have been
unparalleled! You have been my source of inspiration when times would get rough. I also
appreciate the fact that you have had to take on some added responsibilities for us as this
chapter in our lives comes to a close. Mom and Dad, thanks for always being there in every
way imaginable. Cerissa, thanks for being such an awesome little sister and so supportive
and helpful in the final stages of my Ph. D. studies. Rest of the family, thank you for always
being supportive and asking how this Ph. D. process was going.
To Daphine McKinney, Andy Oberhofer, Trey Phillips, Oliver Myers, Dedra Eatmon
Kirklen Henson, Jarvis Davis, Dexter Hodge, Shweta Shah, Chad Weintraub, Swarnal
Borthakur, Jang Sim, and other fellow students at some point during my studies: Thanks for
the friendship, moments shared “in the struggle,” discussion, and collaboration.
To AEMP staff (administrative and technical, past and present), Equal Opportunity in
Engineering Office (at NCSU and U. of Texas – Austin), and the National Society of Black
Engineers: Thank you for all the support, training, and preparation as I have progressed
through my studies.
To anyone not listed: understand that you are not forgotten and thank you for
whatever part you have played in helping me reach this point in my life.
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TABLE OF CONTENTS
LIST OF FIGURES ..................................................................................................................... x LIST OF TABLES ...................................................................................................................xvii 1 INTRODUCTION ............................................................................................................... 1
1.1 Gate Dielectric Scaling .......................................................................................... 1 1.2 High-κ Gate Dielectrics ......................................................................................... 3 1.3 Overview of the Dissertation ................................................................................. 4 1.4 References.............................................................................................................. 5
2 DIAGNOSTIC METHODS FOR GATE DIELECTRIC EVALUATION ..................................... 9 2.1 Introduction............................................................................................................ 9 2.2 Metal-Insulator-Semiconductor Structures.......................................................... 10
2.2.1 Ideal MIS Structure With Doped Poly-Silicon as the Gate....................... 11 2.2.2 Qualitative Description ............................................................................. 12 2.2.3 Accumulation ............................................................................................ 12 2.2.4 Flatband..................................................................................................... 14 2.2.5 Depletion................................................................................................... 14 2.2.6 Inversion.................................................................................................... 15
2.3 Non-Ideal Characteristics of the MIS Structure................................................... 17 2.3.1 Effect of Insulator Charges of the Flatband Voltage ................................ 17 2.3.2 Flatband Voltage ....................................................................................... 19 2.3.3 Effects of Poly-Depletion.......................................................................... 20
2.4 Conditions for p+ Poly-Silicon and n-Type Substrate.......................................... 21 2.5 Current-Voltage Characteristics........................................................................... 22
2.5.1 Gate Current Versus Gate Voltage............................................................ 22 2.5.2 Drain Current Versus Drain Voltage......................................................... 26
2.6 Mobility Extraction.............................................................................................. 28 2.7 Summary .............................................................................................................. 30 2.8 References............................................................................................................ 30
3 ELECTRICAL CHARACTERIZATION CONCERNS FOR SUB-2NM EOT GATE DIELECTRICS ON SILICON............................................................................................. 31 3.1 Introduction.......................................................................................................... 31 3.2 Capacitance- Voltage Measurement .................................................................... 32 3.3 MIS Parameter Extraction.................................................................................... 40
3.3.1 C-V Measurement Issues .......................................................................... 41 3.3.2 Parameter Extraction Methodology .......................................................... 42
3.4 Drain Current- Gate Voltage Measurements ....................................................... 49 3.4.1 Id-Vg Leakage Current Correction............................................................. 51 3.4.2 Mobility Extraction ................................................................................... 52
3.5 Summary .............................................................................................................. 54 3.6 References............................................................................................................ 55
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4 TEST STRUCTURE DESIGN ............................................................................................ 57 4.1 Introduction.......................................................................................................... 57 4.2 Starting Material .................................................................................................. 57 4.3 Test Structure Design........................................................................................... 58 4.4 Process Flow ........................................................................................................ 63
4.4.1 Alternative Gate Dielectric Processing Techniques.................................. 65 4.5 Summary .............................................................................................................. 67 4.6 References............................................................................................................ 68
5 CHARGE TRAPPING MEASUREMENTS AND THEIR APPLICATION TO HIGH-κ GATE STACK EVALUATION............................................................................................ 69 5.1 Introduction.......................................................................................................... 69 5.2 Capacitance – Voltage Hysteresis........................................................................ 70
5.2.1 Application of Capacitance – Voltage Hysteresis Measurements ............ 73 5.3 Stress and Sense Methodologies.......................................................................... 83
5.3.1 Stress/C-V Measurement .......................................................................... 84 5.3.2 Stress/I-V Measurement............................................................................ 86 5.3.3 Application of the Stress/C-V Measurement ............................................ 87
5.4 Charge Pumping................................................................................................... 90 5.5 Fast Transient Charge Trapping Technique......................................................... 95 5.6 Comparison of Charge Trapping Measurement Techniques ............................... 98 5.7 Fast Transient Mobility Extraction .................................................................... 102 5.8 Summary ............................................................................................................ 104 5.9 References.......................................................................................................... 105
6 CHARGE TRAPPING AND MOBILITY DEGRADATION IN MOCVD HAFNIUM SILICATE GATE DIELECTRIC STACK STRUCTURES.................................................... 107 6.1 Introduction........................................................................................................ 107 6.2 Process Flow and Experiment............................................................................ 108 6.3 Experimental Results ......................................................................................... 108
6.3.1 SIMS Analysis ........................................................................................ 108 6.3.2 DC Measurements................................................................................... 109 6.3.3 Charge Pumping...................................................................................... 112 6.3.4 Fast Transient .......................................................................................... 114 6.3.5 Pulsed Id-Vg Mobility Extraction........................................................... 116
6.4 Summary ............................................................................................................ 119 6.5 References.......................................................................................................... 120
7 CHARGE TRAPPING MODEL FOR MOCVD HAFNIUM-BASED GATE DIELECTRIC STACK STRUCTURES AND ITS IMPACT ON DEVICE PERFORMANCE ..... 121 7.1 Introduction........................................................................................................ 121 7.2 Process Flow and Experiment............................................................................ 122 7.3 Results and Discussion ...................................................................................... 123
7.3.1 Physical Analysis .................................................................................... 124 7.3.2 Electrical Analysis .................................................................................. 125 7.3.3 High-κ Bulk Trapping............................................................................. 134 7.3.4 Pulsed Id-Vg Mobility Extraction ............................................................ 141
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7.4 Summary ............................................................................................................ 143 7.5 References.......................................................................................................... 143
8 CONCLUSIONS ............................................................................................................. 145 APPENDIX: PRESENTATIONS AND PUBLICATIONS.............................................................. 148
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LIST OF FIGURES
Figure 2.1. A MIS capacitor where the darkly shaded portion represents the metal electrode, the “hatched” portion represents the insulating dielectric, and the unshaded portion represents the silicon substrate. This forms a parallel plate capacitor...................................................................................... 10
Figure 2.2. a) The band structure of an ideal (no oxide charges, perfect insulator, and uniformly doped substrate) MIS structure. b) The same ideal band structure with the exception of a highly doped polysilicon electrode replacing the metal that is assumed in the ideal case. ...................................... 11
Figure 2.3. a) The accumulation condition in an n+/p MIS capacitor. A negative bias applied to the gate creates the accumulation of holes (+) at the SiO2-Si interface. b) As the negative bias is applied, the degenerately doped poly-silicon becomes accumulated, and thus can be considered as a metal electrode. ................................................................................................ 13
Figure 2.4. a) The depletion condition in an n+/p MIS capacitor. As the voltage applied to the gate increases from a negative bias, holes (+) leave the SiO2-Si interface creating a depletion region shown in the lightly shaded region below the dielectric. b) The band bending resulting from the applied gate bias. .............................................................................................. 15
Figure 2.5. a) The inversion condition in an n+/p MIS capacitor. As the bias applied to the gate becomes more positive, holes leave the SiO2-Si interface creating a depletion region shown in the lightly shaded region below the dielectric until a maximum depth is reached. Then, electrons (-) move to the substrate surface to create an inversion layer. b) The band bending resulting from a negative applied gate bias where band bending in the poly represents poly depletion................................................................ 16
Figure 2.6. Polysilicon depletion effect. The depleted gate electrode at the poly-Si interface adds a capacitance in series with the oxide capacitance and substrate capacitance. ....................................................................................... 21
Figure 2.7. Energy band diagram description of Fowler-Nordheim injection. ..................... 25Figure 2.8. Energy band diagram description of direct tunneling through a
trapezoidal barrier............................................................................................. 25 Figure 2.9. Schematic of MISFET device............................................................................ 26 Figure 2.10. Universal mobility characteristic versus the effective field at the silicon
surface showing the effects of coulomb, phonon, and surface roughness scattering at different effective field strengths. ................................................ 29
Figure 3.1. A circuit representation of the capacitance contributions from the various charges found in an MIS capacitor assuming that the only oxide charge present is interface trapped charge. .................................................................. 35
x
Figure 3.2. The equivalent circuit representation when an accumulation bias or inversion (low frequency) bias is applied to the gate electrode. The accumulation charge is large. Thus, the accumulation capacitance is large. Circuit theory states that as capacitance becomes large it acts like a short. Therefore, only Cox is present............................................................. 36
Figure 3.3. The equivalent circuit representation when a depletion bias is applied to the gate electrode. The depletion capacitance (Cb) is dominant, and the interface capacitance (Cit) cannot be neglected. Also, weak inversion begins to appear, which adds another capacitance contribution (Cn). .............. 37
Figure 3.4. The equivalent circuit representation when a strong inversion high frequency bias is applied to the gate electrode. The inversion charge cannot form. Thus, the depletion contribution is included in the circuit model. ............................................................................................................... 38
Figure 3.5. The ideal C-V quasi-static and high frequency characteristics of an n /p MIS structure. In an nMISFET, the impact of polysilicon depletion on C-V characteristics for an n /p structure can be seen.
+
+ ...................................... 39Figure 3.6. The ideal C-V quasi-static and high frequency characteristics of an p /n
MIS structure. In an pMISFET, the impact of polysilicon depletion on C-V characteristics for an p /n structure can be seen.
+
+ ...................................... 40Figure 3.7. Plot of the C-V characteristics for 3 frequencies with meter corrections
either on or off for a nominal 2.4 nm thick oxide. ........................................... 44 Figure 3.8. Plot of the C-V characteristics for 3 frequencies with meter corrections
either on or off for a nominal 1.5 nm thick oxide. ........................................... 44 Figure 3.9. a) The three-element equivalent circuit for a MIS Capacitor, and b) The
equivalent parallel mode circuit for the impedance analyzer. .......................... 45 Figure 3.10. Plot of the C-V characteristics for the dual-frequency technique to
extract the true capacitance, Co, in which the Co model diverges because important required measurement parameter values from Nara, et al., are no longer met. The Hauser model is fit to the Co data which shows good agreement with the 250 kHz curve................................................................... 49
Figure 3.11. Typical current components measured during an Id – Vg sweep...................... 50 Figure 3.12. Typical Id-Vd characteristic for 2 nm SiO2 nMISFET ..................................... 50 Figure 3.13. Transistor current components showing the impact of gate leakage (I )
on the measured drain current (the ‘droop’ in I ), and its removal in the corrected drain current (I ).
g
Dmeas
d,ch ..................................................................... 53Figure 3.14. Schematic of a transistor showing the current components in an I – V
measurement.d g
.................................................................................................... 53Figure 3.15. Gate leakage impact on the extracted mobility where the ‘drooping’ I –
V produces a distorted mobility curve while the I corrected for gate leakage mobility characteristic is more robust.
d
g d................................................ 54
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Figure 4.1. Plot of the C-V characteristics for a more heavily doped substrate and a less heavily doped substrate where the highly doped substrate exhibits a “stretched-out” behavior in the depletion regime allowing better resolution of the flat band voltage and midgap interface state density. ........... 58
Figure 4.2. Plot of the C-V characteristics for multiple area n+/p MIS Capacitors showing the effect of area size and no pad capacitance correction. For large areas, the gate leakage and series resistance affect the accumulated capacitance while the two smaller areas show the impact of not correcting for the pad capacitance since open and closed circles are not in as good agreement as subsequently seen in Figure 3. .................................. 60
Figure 4.3. Plot of the C-V characteristics for multiple area n+/p MIS Capacitors showing the effect of area size and the pad capacitance correction where the two smaller areas are in agreement when corrected for pad capacitance which establishes the validity of this data. The large area device data must be ignored. ............................................................................ 61
Figure 4.4. Three capacitor structures: a) true nested capacitor, b) nested gated capacitor, and c) overlap capacitor................................................................... 63
Figure 4.5. Schematic of a typical self-aligned MISFET..................................................... 64 Figure 4.6. CrosSectional TEM image of an ALD HfO2 transistor structure. ..................... 66 Figure 4.7. CrosSectional TEM image of an MOCVD Hf-based transistor structure. ........ 67Figure 5.1. Voltage “inversion to accumulation” and “accumulation to inversion”
sweep methodology that demonstrates larger ∆Vfb when voltage sweep widens: b) shows a larger ∆Vfb value compared to a) due to wider voltage sweep (larger electric field strength). .................................................. 72
Figure 5.2. Voltage “inversion to accumulation” and “accumulation to inversion” sweep methodology showing no ∆Vfb up to a –2.3 V accumulation bias. ....... 75
Figure 5.3. Voltage “inversion to accumulation” and “accumulation to inversion” sweep methodology showing noticeable ∆Vfb when a “critical accumulation bias of –2.4 V is reached............................................................ 75
Figure 5.4. Gate injected electron trapping shown: sweep in both directions after initial bi-directional C – V sweep shows no hysteresis and lies on the gate injected “accumulation to inversion” curve of the initial C – V. ............. 76
Figure 5.5. Gate injected electron trapping: “Fresh” site measurement starting in accumulation shows no hysteresis and lies on the “accumulation to inversion” curve of the initial C – V................................................................. 76
Figure 5.6. Attempts to remove trapped electrons using high temperature to determine activation energies. The electrons remained trapped after a) 100ºC, b) 150ºC, and c) 200ºC following an initial C – V measurement at room temperature to trap the electrons......................................................... 78
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Figure 5.7. Bi-directional C – V sweeps illustrating full charge recovery when a C – V accumulation bias of –1 V (identical up-sweeps) is used and increasing substrate injected electron trapping as C – V bias into inversion is increased. ...................................................................................... 79
Figure 5.8. Conventional bi-directional sweep with a subsequent forward and back sweep in accumulation shows similar results to the capacitor. ........................ 80
Figure 5.9. Conventional bi-directional sweep with a subsequent “accumulation to inversion” sweep further into inversion (i.e., Vg = 1 V) and back shows similar results to the capacitor. ......................................................................... 81
Figure 5.10. Conventional bi-directional sweep with a subsequent “accumulation to inversion” sweep further into inversion (i.e., Vg = 1.5 V) and back shows a critical voltage has been reach where electrons trap and de-trap. ...... 81
Figure 5.11. Conventional bi-directional sweep with a subsequent “accumulation to inversion” sweep and back shows quite similar characteristics where electrons trap from the gate and substrate, but de-trap as the sweeps move through depletion and weak inversion.................................................... 82
Figure 5.12. Waveform of the applied voltage versus time for a “stress and sense” measurement..................................................................................................... 87
Figure 5.13. Interspersed C-V measurements (inversion to accumulation to inversion) taken around the Vfb value after each Vstress cycle for ALD HfO2. Positive flatband shift is evident suggesting negative trapped charge from the substrate as well as a widening hysteresis effect after stresses. Inset: the region in theC-V curve where the data was measured........................................................................................................... 88
Figure 5.14. Trapped charge, ∆Nt, vs. Qinj, calculated from Vfb shift, ∆Vfb, with respect to the initial value. The first point corresponds to ∆Nt after the first stress and so on. The noise here suggests an unstable extraction of based on the C – V up-sweeps being so close together. ................................... 89
Figure 5.15. Interspersed C-V measurements (inversion to accumulation to inversion) taken around the Vfb value after each Vstress cycle for MOCVD Hf silicate. Positive flatband shift is evident suggesting negative trapped charge from the substrate as well as a widening hysteresis effect after stresses. Notice the larger Vfb shift compared to the ALD HfO2 (Figure 5.13) ............................................................................ 89
Figure 5.16. Trapped charge, ∆Nt, vs. Qinj, calculated from Vfb shift, ∆Vfb, with respect to the initial value. The first point corresponds to ∆Nt after the first stress and so on. Notice the larger quantity of trapped charge due to more pronounced Vfb shift as compared to ALD HfO2. ................................... 90
Figure 5.17. Schematic of the charge pumping measurement where (a) shows the measurement conFiguration and (b) shows the measurement and resulting Icp for FA CP (left) and VA CP (right). .............................................. 92
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Figure 5.18. Examples of fixed and variable amplitude charge pumping to assess interface and bulk trapping, respectively. SiO2 sample is shown for comparison. ...................................................................................................... 94
Figure 5.19. An example of using variable amplitude charge pumping as a process monitor for experimental split designs illustrating the effect of an increased temperature for an N2O PDA has reduced the amount of measured Nt. ..................................................................................................... 95
Figure 5.20. The transistor is used in an inverter circuit with the gate receiving a single pulse from the pulse generator. The voltage is measured at the transistor drain and converted to drain current because the load resistance value is known. ................................................................................ 97
Figure 5.21. Example data of the pulsed Id – Vg where ∆Vt is measured at 50% of the maximum Id on a W/L = 10/1 µm transistor..................................................... 97
Figure 5.22. Example data of the pulsed Id versus time on a W/L = 10/1 µm transistor where the ‘droop’ at the top is associated with the drop of pulsed Id – Vg at Vg = 2.5 V. ............................................................................. 98
Figure 5.23. EOT versus nominal physical thickness for verification of scaling and extraction of κ ~ 12 and 0.9 nm interfacial oxide for Hafnium silicate (20% SiO2) gate stacks. .................................................................................... 99
Figure 5.24. Comparison results showing that fast transient measurement extracts the largest trapped charge density followed by variable amplitude charge pumping and then the “stress and sense” approach has the least which is expected due to bias relaxation and Vfb extraction done near the discharge condition......................................................................................... 101
Figure 5.25. Bi-directional C – V sweeps illustrating full charge recovery when a C – V accumulation bias of –1 V (identical up-sweeps) is used and increasing substrate injected electron trapping as C – V bias into inversion is increased. .................................................................................... 102
Figure 5.26. Comparison of electron mobility from pulsed/CP methodology and conventional split C-V for a MOCVD hybrid stack. Inset: comparison of pulsed Id-Vg to DC Id-Vg for the mobility shown. ..................................... 104
Figure 6.1. SIMS shows position differences in the Si and O signals indicating the N2O 800°C film is thicker than the NH3 film. Higher nitrogen incorporation in the NH3 PDA is also evident when compared to the N2O PDA........................................................................................................ 109
Figure 6.2. Example of conventional electron mobility extraction (Split CV and NCSU Mob2d). Inset shows CV, split CV, and DC ramp Id-Vg used............ 111
Figure 6.3. Comparison of 2 Torr v 4 Torr silicate peak and high field (1.3 MV/cm) electron mobilities with various PDAs (where 4 Torr deposited material mobilities are higher). .................................................................................... 111
Figure 6.4. Examples of fixed and variable amplitude charge pumping to assess interface and bulk trapping, respectively........................................................ 113
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Figure 6.5. Comparison of 2 Torr v 4 Torr interface (1 MHz) and bulk traps (10 kHz at a stress field 6 MV/cm) where 2 Torr 700°C PDAs trap the most and 2 Torr, 4 Torr N2O 800°C traps the least for the conditions illustrated. ......... 113
Figure 6.6. Duty cycle study: A higher trap density is achieved with longer discharge times suggesting more time is required to de-trap than to trap (10 kHz 5% is higher than 100 kHz 50%). .................................................... 114
Figure 6.7. Examples of pulsed Id-Vg characteristics showing increased charge trapping with increasing inversion bias for 100 µs rise, fall, and pulse width times. DC Id-Vg is shown for comparison. .......................................... 115
Figure 6.8. Comparison of ∆Vt at different charging times for various PDAs using pulsed Id-Vg (Figure 9) to determine ∆Vt at 50% of the maximum Id for a) Vg = 2 V and b) Vg = 1.5 V......................................................................... 116
Figure 6.9. "Trap free" inversion charge compared with split CV where trapped charge is not removed..................................................................................... 117
Figure 6.10. Comparison of electron mobility from pulsed/CP methodology and DC ramp (see Figures 2 and 3) measurements for NH3 700°C PDA. Inset: comparison of pulsed Id-Vg to DC Id-Vg for the mobility shown................... 118
Figure 6.11. Comparison of electron mobility from pulsed/CP methodolgy and DC ramp (see Figures 2 and 3) measurements for N2 800°C PDA. Inset: comparison of pulsed Id-Vg to DC Id-Vg for the mobility shown................... 118
Figure 7.1. Schematic representation of the gate stacks in Table I. ................................... 122 Figure 7.2. HRTEM images of the 30/15 (left) and 15/15 (right) hybrid stacks. Note
that the interfacial oxide layer as about 1 nm in both samples. ..................... 124 Figure 7.3. SIMS profiles of hybrid films following wet etch removal of the poly
electrode where the 20/15 and 15/15 hybrid stacks are quite similar............. 125 Figure 7.4. Conventional split C-V data showing a small decrease in CET as the
physical thickness of the high-κ is reduced.inv
................................................... 127Figure 7.5. DC Id-Vg data showing an increase in drive current as the physical
thickness of the high-κ is reduced.................................................................. 127 Figure 7.6. Electron mobility extracted with the split C-V methodology. Thinner
high-κ stacks resulted in higher mobility. ...................................................... 128 Figure 7.7. DC Id-Vg data showing a ∆Vt shift when sweeping the gate voltage –1 V
→ 2 V → –1 V. De-trapping as the down trace goes returns to –1 V can be seen. ........................................................................................................... 128
Figure 7.8. Interface (Nit) and bulk (Nt) trapping data for the different hybrid stacks obtained with FA CP and VA CP, respectively. .............................................. 130
Figure 7.9. In the accumulation (ACC) state, gate leakage current adds to the I at the low amplitudes of the VA CP measurement (Insets: “ACC” and inner log plot). In the inversion (INV) state, DC leakage current flows from S/D to the gate that indirectly enhances I due to enhanced injection into the high-κ film.
cp
cp
....................................................................................... 131
xv
Figure 7.10. Pulsed Id-Vg characteristics for a) 30/15, b) 20/15, and c) 15/15 hybrid stacks with different inversion bias pulses with 100 µs rise, fall, and pulse width times. DC Id-Vg is shown for comparison in each case. ............ 133
Figure 7.11. ∆Vt values (measured as in Figure 7.10) for different gate biases and charging times vs. gate stack physical thickness. Horizontal dashed lines connect data point of similar ∆Vt obtained with different charging times/physical thickness values...................................................................... 134
Figure 7.12. Band diagram example for a Hf-based gate dielectric on a SiO interfacial oxide illustrating voltage drops across the two portions of the gate stack where V is based on the assumed uniform dielectric constant.
2
2 .... 136Figure 7.13. Band diagram for a plausible bulk-trapping model as a function of
physical thickness where the possibility of electron trapping from substrate injection increases with increasing physical thickness. .................. 139
Figure 7.14. ∆Vt values for different gate biases and charging times vs. gate stack physical thickness for Hf silicate (20% SiO2). Horizontal dashed lines connect data point of similar ∆Vt obtained with different charging times/physical thickness values...................................................................... 140
Figure 7.15. Comparison of electron mobility from pulsed/CP method and DC ramp for: a) 20/15 and b) 15/15 hybrid stacks. Insets: comparison of pulsed Id-Vg to DC Id-Vg for the mobilities shown.................................................... 142
xvi
LIST OF TABLES
Table 4.1. Results of the test structure design case study with pictorial representation of the device structures..................................................................................... 63
Table 4.2. Synopsis of an nMIS transistor process flow ...................................................... 64 Table 6.1. 20% SiO2 Hf silicate gate stacks under evaluation with parameters
extracted from NCSU CVC [6] and DC measurements................................. 110 Table 7.1. Parameters extracted from NCSU CVC and DC measurements for
MOCVD hybrid gate stacks [9]. .................................................................... 123 Table 6.2. Expected charge at the high-κ/SiO2 interface are an order of magnitude
different while ∆Vt’s are similar..................................................................... 138
xvii
1 INTRODUCTION
As discussed in [1], Moore’s law [2-6] is the guiding principal for the integrated
circuit (IC) industry. In order to follow Moore’s Law (≈ 16% compound annual growth
rate), device scaling is the key attribute for planar MOSFET circuitry based on work done by
B. Dennard [7-9]. Device scaling is ultimately the reduction in device dimensions. As
lengths and width are reduced, so must thickness be reduced in order scale proportionately.
One of the critical research issues is the scaling of the gate dielectric. The International
Technology Roadmap for Semiconductors has established a “timeline” for these scaling
demands in effort to meet the performance requirements of given technology nodes [10].
1.1 Gate Dielectric Scaling
After J. Kilby’s demonstration of the concept of IC’s (1959) [11] in conjunction with
the fabrication of the first MOSFET by D. Kahng and M.M. Attala (1960) [12] and planar
silicon devices [13, 14], process control was of serious concern. One area of concern was the
gate dielectric in the MOS structure. Silicon dioxide has been the ideal gate dielectric
because of its amorphous structure, insolubility in water, a huge band gap of ~ 9eV, ability to
be patterned and/or used as a blocking layer, ability to serve as a separator between metal
conducting layers and silicon substrates, and its compatibility with silicon low interface state
densities [1]. The latter was not always the case however. This SiO2 gate dielectric was
quite susceptible to process control in the early stages. Controlling the SiO2 growth
1
uniformly across the wafer, mobile charges, fixed charge, and interface trapped charge was
instrumental in the development of MOS technologies in subsequent years.
Post Deposition Anneals (PDA’s) and Post Metallization Anneals (PMA’s)
introduced in the 1960’s significantly reduced fixed and interface charge [15]. HCI was
introduced as part of the oxidizing ambient to “getter” mobile charge resulting in a
significant reduction in metal contamination (lifetime killers) and mobile ions [16]. In
addition, as gate oxides begin to scale (reduction in physical thickness) to the ultra thin oxide
regime, the aboved mentioned charges are greatly reduced compared to interface trapped
charge.
While scaling the oxide has been the norm of the IC industry, moderate
concentrations of nitrogen have been introduced to stop boron penetration from p+ poly gates,
but direct tunneling leakage current is rendering ultra-thin oxides below ~1.5 nm almost
useless because the leakage currents are too high. The direct tunneling current increases as
the SiO2 thickness is reduced [17]. Another set of issues with the reduction of dielectric
thickness is quantum mechanical effects and polysilicon depletion effects, which are
amplified as the SiO2 thickness is reduced. These two effects result in an increase in the
effective dielectric thickness because the quantum confinement of the substrate and the
depletion region in the poly add capacitances in series with the oxide capacitance creating
what is interpreted as a thicker oxide [18, 19]. To accommodate these issues, IC design
architecture must be skillfully done to innovate new ways to limit power consumption as
much as possible, and the need for finding an alternative gate dielectric is required.
2
1.2 High-κ Gate Dielectrics
Because of the limitations of SiO2, the search for an alternative gate dielectric has begun.
The requirements of this new dielectric include [1]: an increase in the dielectric constant (κ),
a large band gap for high barrier heights to both electrons and holes [20], and compatibility
with conventional planar CMOS processing. The increase in the κ value allows a thicker
dielectric to be implemented at the same capacitance value required for device drive in a
given technology node. The thicker dielectric reduces the tunneling leakage current with the
hope of maintaining the performance of SiO2.
There are many potential candidates for high-κ gate dielectrics with the κ values
ranging from 7 – 80. These candidates include: Si3N4, Al2O3, Y2O3, La2O3, Ta2O5, TiO2,
ZrO2, and HfO2 [21]. However, TiO2 and Ta2O5 have low thermal stability which makes
them incompatible with conventional CMOS processing [21]. Al2O3 alone, which has a κ
value of 9, may not be sufficient to achieve sub 1 nm equivalent oxide thickness (EOT)
values. However, when incorporated into HfO2 as an Hf-Aluminate, the film enhances
scalability toward sub nm EOT applications [22]. Although scaling is possible, other device
parameters such as transconductance are degraded when comparing Hf-Aluminates to
conventional HfO2 [23]. La2O3 and Y2O3 have higher κ values of 30 and 15, respectively,
but lose their κ values in conventional processing due to silicate formation [24]. La2O3 could
still be a possible candidate with continued process optimization. Recently, significant effort
has been put into ZrO2 and more particularly, HfO2 [22, 25-34]. The two metal oxides and
3
their silicates have improved thermal stability. Although phase separation often occurs in the
Hf silicates [35-37], they survive the thermal budget of conventional planar CMOS
processing to achieve integration in devices. However, a definite choice has not been made
because there are still significant strides to be made to “plug and play” high-κ for SiO2. In
particular, Hf-based gate stacks suffer from Vt instability and charge trapping [38].
1.3 Overview of the Dissertation
The research presented herein is focused on electrical characterization and analysis of
hafnium-based gate dielectric stack structures. Chapter 2 provides theory and background
including definitions and understanding of device characteristics that are evaluated in
subsequent chapters. Chapter 3 provides measurement methodologies for measuring device
properties in the presence of significant gate leakage while chapter 4 discusses the
importance of test structure design as well as outlining the typical process flow to fabricate
capacitors and transistor structures used in this work. Chapter 5 addresses charge trapping
measurements and their application to high-κ gate stack evaluation. The promising
techniques outlined in chapter 5 are then employed in chapters 6 and 7 to investigate process
conditions and bulk trapping, respectively. Chapter 8 summarizes the findings and points to
an area for future work.
4
1.4 References
[1] H. R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G. A. Brown, C. D. Young, P. M. Zeitzoff, J. Gutt, P. Lysaght, M. I. Gardner, and R. W. Murto, "High-κ gate stacks for planar, scaled CMOS integrated circuits," Microelectronic Engineering, vol. 69, pp. 152-167, 2003.
[2] G. E. Moore, "MOS Transistor as an Individual Device and in Integrated Arrays," IEEE Spectrum, vol. 2, pp. 49-&, 1965.
[3] G. E. Moore, "Microprocessors and Integrated Electronic Technology," Proceedings of the IEEE, vol. 64, pp. 837-841, 1976.
[4] G. E. Moore, "The role of Fairchild in silicon technology in the early days of "silicon valley"," Proceedings of the IEEE, vol. 86, pp. 53-62, 1998.
[5] G. E. Moore, "Cramming more components onto integrated circuits (Reprinted from Electronics, pg 114-117, April 19, 1965)," Proceedings of the IEEE, vol. 86, pp. 82-85, 1998.
[6] R. Goodall, D. Fendel, A. Allan, P. Landler, and H. R. Huff, "Long-term Productivity Mechanisms of the Semiconductor Industry," presented at ECS, 2002.
[7] R. H. Dennard, "U.S. Patent No. 3,387,286." USA, June 4, 1968.
[8] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. Leblanc, "Design of ion-implanted MOSFET's with very small physical dimensions (Reprinted from IEEE Journal of Solid-State Circuits, vol 9, pg 256-268, 1974)," Proceedings of the IEEE, vol. 87, pp. 668-678, 1999.
[9] R. H. Dennard, "Evolution of the MOSFET Dynamic Ram - a Personal View," IEEE Transactions on Electron Devices, vol. 31, pp. 1549-1555, 1984.
[10] International Technology Roadmap for Semiconductors, "http://public.itrs.net," 2001.
[11] J. S. Kilby, "Invention of Integrated-Circuit," IEEE Transactions on Electron Devices, vol. 23, pp. 648-654, 1976.
[12] M. M. Atalla, E. Tannenbaum, and E. J. Scheibner, "Stabilization of Silicon Surfaces by Thermally Grown Oxides," Bell Syst. Tech. J., vol. 38, pp. 749-783, 1959.
[13] J. A. Hoerni, "Planar Silicon Devices and Transistors," IEEE Transactions on Electron Devices, vol. 8, pp. 178, 1961.
[14] J. A. Hoerni, "Planar Silicon Transistors and Diodes," presented at IRE Electron Dev. Mtg., Washington, D.C., Oct. 1960.
5
[15] D. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed. New York: John Wesley & Sons, 1998.
[16] R. A. Colclaser, Microelectronics Processing and Device Design. New York: John Wiley & Sons, 1980.
[17] S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's," IEEE Electron Device Letters, vol. 18, pp. 209-211, 1997.
[18] W. K. Henson, K. Z. Ahmed, E. M. Vogel, J. R. Hauser, J. J. Wortman, R. D. Venables, M. Xu, and D. Venables, "Estimating Oxide Thickness of Tunnel Oxides Down to 1.4 nm Using Conventional Capacitance-Voltage Measurements on MOS Capacitors," IEEE Electron Device Letters, vol. 20, pp. 179-181, 1999.
[19] C. A. Richter, A. R. Hefner, and E. M. Vogel, "A Comparison of Quantum-Mechanical Capacitance-Voltage Simulators," IEEE Electron Device Letters, vol. 22, pp. 35-37, 2001.
[20] J. Robertson, "Band offsets of high dielectric constant gate oxides on silicon," Journal of Non-Crystalline Solids, vol. 303, pp. 94-100, 2002.
[21] G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-κ gate dielectrics: Current status and materials properties considerations," Journal of Applied Physics, vol. 89, pp. 5243-5275, 2001.
[22] T. H. Hou, J. Gutt, C. Lim, S. Marcus, C. Pomarede, E. Shero, H. de Waard, C. Werkhoven, M. Gardner, R. W. Murto, and H. R. Huff, "Improved Scalability of High-k Gate Dielectrics by Using Hf-Aluminates," presented at 1st International Symposium on High Dielectric Constant Materials: Materials Science, Processing, Manufacturing, and Reliability Issues at the Fall Meeting of the Electrochemical Society, Salt Lake City, Utah, 2002.
[23] J. H. Lee, Y. S. Kim, H. S. Jung, J. H. Lee, N. I. Lee, H. K. Kang, J. H. Ku, H. S. Kang, Y. K. Kim, K. H. Cho, and K. P. Suh, presented at Symp.on VLSI Technology Digest, 2002.
[24] A. Chin, Y. H. Wu, S. B. Chen, C. C. Liao, and W. J. Chen, "High Quality La2O3 and Al2O3 Gate Dielectrics with Equivalent Oxide Thickness 5-10 Å," presented at Symp. on VLSI Technology Digest, 2000.
[25] J. Barnett, D. Riley, T. C. Messina, P. Lysaght, and R. Carpio, "Wet etch enhancement of HfO2 films by implant processing," Diffusion and Defect Data Part B Solid State Phenomena, vol. 92, pp. 11-14, 2003.
[26] H. Dedong, K. Jinfeng, L. Changhai, and H. Ruqi, "Reliability characteristics of high-K gate dielectrics HfO2 in metal-oxide semiconductor capacitors," Microelectronic Engineering, vol. 66, pp. 643-7, 2003.
[27] X. Garros, C. Leroux, D. Blin, J. F. Damlencourt, A. M. Papon, and G. Reimbold, "Investigation of HfO2 dielectric stacks deposited by ALD with a mercury probe,"
6
presented at 32nd European Solid State Device Research Conference. 24-26 Sept. 2002, Firenze, Italy, 2002.
[28] M. Gutowski, J. E. Jaffe, L. Chun Li, M. Stoker, R. I. Hegde, R. S. Rai, and P. J. Tobin, "Thermodynamic stability of high-k dielectric metal oxides ZrO/sub 2/ and HfO2 in contact with Si and SiO2," presented at Silicon Materials Processing, Characterization and Reliability. Symposium. 1-5 April 2002, San Francisco, CA, USA, 2002.
[29] D. Han De, F. Kang Jin, H. Lin Chang, and Q. Han Ru, "Annealing characteristics of ultra-thin high-K HfO2 gate dielectrics," Chinese Physics, vol. 12, pp. 325-7, 2003.
[30] H. Hang, Z. Chunxiang, Y. F. Lu, Y. H. Wu, T. Liew, M. F. Li, B. J. Cho, W. K. Choi, and N. Yakovlev, "Physical and electrical characterization of HfO2 metal-insulator-metal capacitors for Si analog circuit applications," Journal of Applied Physics, vol. 94, pp. 551-7, 2003.
[31] Y. Kim, C. Lim, C. D. Young, K. Matthews, J. Barnett, B. Foran, A. Agarwal, G. A. Brown, G. Bersuker, P. Zeitzoff, M. Gardner, R. W. Murto, L. Larson, C. Metzner, S. Kher, and H. R. Huff, "Conventional Poly-Si Gate MOS-transistors With a Novel, Ultra-Thin Hf-oxide Layer," presented at VLSI Technology Symposium, Kyoto, Japan, 2003.
[32] S. J. Lee, C. H. Choi, A. Kamath, R. Clark, and D. L. Kwong, "Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO2-SiO2) prepared by in situ RTCVD process for system-on-chip applications," IEEE Electron Device Letters, vol. 24, pp. 105-7, 2003.
[33] P. F. Lee, J. Y. Dai, K. H. Wong, H. L. W. Chan, and C. L. Choy, "Growth and characterization of Hf-aluminate high-k gate dielectric ultrathin films with equivalent oxide thickness less than 10 Å," Journal of Applied Physics, vol. 93, pp. 3665-7, 2003.
[34] C. Lim, Y. Kim, A. Hou, J. Gutt, S. Marcus, C. Pomarede, E. Shero, H. Waard, C. Werkhoven, L. Chen, J. Tamim, N. Chaudhary, G. Bersuker, J. Barnett, C. D. Young, P. Zeitzoff, G. A. Brown, M. Gardner, R. W. Murto, and H. R. Huff, "Effect of Deposition Sequence and Plasma Treatment on ALCVD(TM) HfO2 n-MOSFET Properties," presented at 1st International Symposium on High Dielectric Constant Materials: Materials Science, Processing, Manufacturing, and Reliability Issues at the Fall Meeting of the Electrochemical Society, Salt Lake City, Utah, 2002.
[35] P. S. Lysaght, P. J. Chen, R. Bergmann, T. Messina, R. W. Murto, and H. R. Huff, "Experimental observations of the thermal stability of high-k gate dielectric materials on silicon," Journal of Non-Crystalline Solids, vol. 303, pp. 54-63, 2002.
[36] P. Lysaght, B. Foran, S. Stemmer, G. Bersuker, J. Bennett, R. Tichy, L. Larson, and H. R. Huff, "Thermal response of MOCVD hafnium silicate," Microelectronic Engineering, vol. 69, pp. 182-189, 2003.
7
[37] P. S. Lysaght, B. Foran, G. Bersuker, P. J. J. Chen, R. W. Murto, and H. R. Huff, "Physicochemical properties of HfO2 in response to rapid thermal anneal," Applied Physics Letters, vol. 82, pp. 1266-1268, 2003.
[38] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics," IEEE Electron Device Letters, vol. 24, pp. 87-89, 2003.
8
2 DIAGNOSTIC METHODS FOR GATE DIELECTRIC EVALUATION
2.1 Introduction
As the semiconductor industry strives for smaller and faster devices, many issues need to be
addressed in order to reach targeted objectives. One major issue is the scaling of device
dimensions. As lengths and widths reduce, film heights (thickness) must also reduce. One of
these areas is the gate dielectric in a Metal-Insulator-Semiconductor (MIS) structure. The
gate dielectric thickness is the smallest fabricated dimension in MIS transistors today.
Electrical characterization of the MIS test structures is crucial in the development of future
MIS devices and circuitry.
The Metal-Insulator-Semiconductor (MIS) structure plays a significant role in MIS
Field Effect Transistors (MISFETs) which are prevalent in the integrated circuit technology
of today. The MIS capacitor is the metal-insulator-semiconductor structure that creates the
conductive channel in a MISFET. With the use of semiconductor processing equipment,
these structures can be fabricated together to form a parallel plate capacitor as shown in
Figure 2.1 where the metal gate and the silicon substrate form the metal plates and the
insulator forms the dielectric between the two plates. These structures are used extensively
in research as a process control that addresses the need for characterization of ultra-thin
oxides and alternative gate dielectrics.
9
2.2 Metal-Insulator-Semiconductor Structures
To do this research, a fundamental understanding of MIS materials is vital. One useful tool
is the semiconductor band structure of these materials. Figure 2.2a shows the ideal case of
the MIS structure. In the ideal case, several assumptions have been made according to
Pierret [1]: i) there are no charges present in the dielectric film; ii) the dielectric is a perfect
insulator where no current can pass through under different biasing conditions; iii) the
semiconductor thickness must be large enough to contain a field free region in the bulk of the
substrate despite the applied gate potential; iv) the semiconductor is a uniformly doped
substrate; and v) the backside semiconductor-metal contact must be ohmic.
MetalInsulator
Semiconductor
Figure 2.1. A MIS capacitor where the darkly shaded portion represents the metal electrode, the “hatched” portion represents the insulating dielectric, and the unshaded portion represents the silicon substrate. This forms a parallel plate capacitor.
10
a) b)
n+poly I p-type
Si
Vacuum Level
mΦ sΦ
M I S
Vacuum Level
mΦ sΦ
FmEvE
cE
FsEcE
vEFsEFmE
Figure 2.2. a) The band structure of an ideal (no oxide charges, perfect insulator, and uniformly doped substrate) MIS structure. b) The same ideal band structure with the exception of a highly doped polysilicon electrode replacing the metal that is assumed in the ideal case.
2.2.1 Ideal MIS Structure With Doped Poly-Silicon as the Gate
Now that the assumptions have been given, static biasing issues can be addressed for
degenerately doped poly-silicon serving as the gate electrode of the MIS capacitor. The four
static biasing conditions that will be addressed are: accumulation, flatband, depletion (in the
substrate), and inversion (in the substrate). The MIS conFiguration under consideration is n+
poly-silicon on an p-type substrate.
11
2.2.2 Qualitative Description
In the scenario presented, the substrate is at ground and the bias is applied to the poly-silicon
gate. In this situation, the semiconductor Fermi level, EFs, is at ground potential, and the
poly-silicon Fermi level, EFm, can be considered as a "handle" that moves up for negative
applied bias and down for a positive applied bias. Another important parameter to discuss is
the metal (degenerately doped poly-silicon) - semiconductor work function, Φms. The work
function is in units of electron volts (eV) and is defined as the distance from the Fermi level
to the vacuum level for a given material (Figure 2.2b). The metal-semiconductor work
function is the difference of the metal work function from that of the semiconductor. Thus,
smms Φ−Φ=Φ (2.1)
Assuming that no oxide charge or interface charge is present, the ideal flatband voltage, Vfb,
is the value of Φms. Flatband voltage and its importance are addressed later in Section 2.3.1.
2.2.3 Accumulation
For an n+/p structure, accumulation occurs when a negative bias is applied to the gate. The
negative charges on the gate attract holes to the SiO2-Si interface to form an accumulation
layer (see Figure 2.3a).
12
The band structure also undergoes a change from a previous static bias condition to
Figure 2.3b for an p-type substrate. When the negative bias is applied to the gate, the Fermi
level moves up relative to the grounded Fermi level in the substrate creating the band
bending shown. In Figure 2.3b, the degenerately doped poly-silicon becomes accumulated,
and thus can be considered as a metal electrode.
- - -- - - -
- -V ++++++++++
a) b)
Figure 2.3. a) The accumulation condition in an n+/p MIS capacitor. A negative bias applied to the gate creates the accumulation of holes (+) at the SiO2-Si interface. b) As the negative bias is applied, the degenerately doped poly-silicon becomes accumulated, and thus can be considered as a metal electrode.
13
2.2.4 Flatband
The flatband voltage is the voltage required to make the bands horizontal (i.e., with no band
bending) as shown in Figure 2.2b. Using the assumption that no charges are present in the
oxide, the flatband voltage can be positive or negative depending on the value of Φm relative
to Φs, as demonstrated in (2.1). In the case of an n+/p structure, the flatband voltage is
negative because the work function for the degenerately doped polysilicon is less than that of
semiconductor relative to the vacuum level.
2.2.5 Depletion
As the bias increases from a negative accumulation bias, holes begin to leave the SiO2-Si
interface until the flatband condition is reached. Continuing to increase the bias begins to
deplete holes at the interface as well as a certain distance into the p-type substrate forming a
depletion region shown in Figure 2.4a.
The band structure also undergoes a change from a previous static bias condition to
Figure 2.4b for a p-type substrate. When the increasing bias is applied to the gate, the Fermi
level moves downward relative to the grounded Fermi level in the substrate creating the band
bending shown. In addition, Figure 2.4b shows the beginning of depletion in the polysilicon.
14
b)a)
- V +V
- - - -+++
Figure 2.4. a) The depletion condition in an n+/p MIS capacitor. As the voltage applied to the gate increases from a negative bias, holes (+) leave the SiO2-Si interface creating a depletion region shown in the lightly shaded region below the dielectric. b) The band bending resulting from the applied gate bias.
2.2.6 Inversion
As the bias continues to increase from a depletion bias, assuming sufficient inversion charge
is established (which could take some time), a maximum depletion width is established, and
then, electrons begin to move towards the SiO2-Si interface to form an inversion layer as
shown in Figure 2.5a.
The band structure also undergoes a change from a previous static bias condition to
Figure 2.5b for an n-type substrate. When the increasing bias is applied to the gate, the Fermi
level continues to move downward relative to the grounded Fermi level in the substrate
15
creating the band bending shown. In addition, Figure 5b shows the depletion that occurs in
the polysilicon.
b)a)
+ +V
+++++- - - -
Figure 2.5. a) The inversion condition in an n+/p MIS capacitor. As the bias applied to the gate becomes more positive, holes leave the SiO2-Si interface creating a depletion region shown in the lightly shaded region below the dielectric until a maximum depth is reached. Then, electrons (-) move to the substrate surface to create an inversion layer. b) The band bending resulting from a negative applied gate bias where band bending in the poly represents poly depletion.
16
2.3 Non-Ideal Characteristics of the MIS Structure
The MIS structure can stray from the ideal scenario presented above in two important areas.
One area is the presence of charges in the insulating film that affects its electrical properties.
Another area of interest is the replacement of a metal gate with degenerately doped
polysilicon. A phenomenon known as poly-depletion creates problems in electrical
characterization of dielectric films as insulator layers become thinner.
2.3.1 Effect of Insulator Charges of the Flatband Voltage
Process control was a serious concern at the beginning of integrated circuit fabrication. One
area of concern was the growth of the SiO2 gate dielectric on silicon substrates. Issues
included: SiO2 growth control, charges in the oxide, and interface trap sites [2]. Gate
dielectric films potentially have four types of charges present. These charges are fixed
insulator charge, mobile insulator charge, insulator trapped charge, and interface trapped
charge. These charges can alter the flatband voltage of MIS field effect transistors.
2.3.1.1 Mobile Ionic Charge
Mobile ionic charges (Qm) are ionic impurities present in the film. These impurities include
Na+, Li+, K+, and possibly H+ which can readily move under bias. However, the processing
17
technologies of today have greatly limited the existence of these ionic impurities due to a
process called “gettering” [3]. The introduction of HCl in the oxidizing ambient would
“getter” mobile charge greatly reducing metal contamination (lifetime killers) and mobile
ions.
2.3.1.2 Insulator Trapped Charge and Fixed Insulator Charge
Insulator Trapped Charge (Qot) can take the form of trapped holes (positive) or trapped
electrons (negative) in the film. Fixed insulator charge (Qf) is a positive charge that comes
from structural defects in the dielectric. For SiO2 films, these charges are located less than 2
nm from the SiO2-Si interface. The amount of fixed charge found in films is due to the
oxidation process. For instance, the process temperature, “oxidation” ambient, post –
processing, and substrate orientation are oxidation process issues. Determining this
particular type of charge is difficult to establish in the presence of moderate densities of
interface trapped charge. The amount of oxide fixed charge is more readily distinguished
after the interface trapped charge is removed with a low-temperature (~450 ºC) hydrogen or
forming gas anneal [3].
In the ultra-thin oxide regime, the above mentioned charge types are minimal relative
to interface trapped charge for SiO2 [3], but could be significant for high dielectric constant
(high-κ) gate dielectrics.
18
2.3.1.3 Interface Trapped Charge
Interface trapped charge (Qit) is located at the SiO2-Si interface. According to Schroder [3],
interface trapped charges can be negative or positive. Although usually positive, these
polarities are determined by the structural and oxidation-induced defects [3]. Also, interface
charge is determined by defects caused over time such as radiation, and hot electron
injection. The important issue here is that the interface trapped charge electrically
communicates with the silicon substrate. These traps can be charged or discharged based on
the surface potential.
2.3.2 Flatband Voltage
The impact of these charges is demonstrated in the equation for the flatband voltage (Vfb) [3].
( )ox
s
ox
ot
ox
m
ox
fmsfb C
QitCQ
CQ
CQ
V φγγφ −−−−= 21 (2.2)
The flatband voltage is the amount of bias necessary to create a “flatband” condition (Figure
2.2) in the poly-silicon gate, insulator, and silicon substrate. For Eq. 2.2, it is assumed that
both fixed charge and interface charge are at the SiO2-Si interface. Mobile and insulator
trapped charge can be located throughout the insulator. The effect of these charges depends
on their placement within the oxide. If these charges are located close to the SiO2-Si
19
interface, the effect on the flatband is greatest due to the fact that the charge is “imaged” on
the semiconductor. If the mobile and/or insulator trapped charge are located at the gate
electrode/dielectric interface, the effect on the flatband voltage is negligible due to “imaging”
all the charge on the gate. So, the γ factor of Eq. 2.3 represents the location of the mobile
and insulator trapped charges in the dielectric film. The γ factor is defined as [3]
( )
( )∫
∫ ⎟⎟⎠
⎞⎜⎜⎝
⎛
=ox
ox
t
t
ox
dxx
dxxtx
0
0
ρ
ργ (2.3)
where ρ(x) = mobile or insulator trapped charge per unit volume. Eq. 2.2 also shows how the
interface trapped charge contribution is dependent upon the surface potential.
2.3.3 Effects of Poly-Depletion
A space-charge region that forms in a polysilicon gate causes the effect known as poly-
depletion. Figure 2.6 shows this phenomenon, which adds a capacitance contribution in
series to the oxide capacitance and substrate capacitance.
20
+++++- - - - -
C
C
C
dp
ox
b
Figure 2.6. Polysilicon depletion effect. The depleted gate electrode at the poly-Si interface adds a capacitance in series with the oxide capacitance and substrate capacitance.
2.4 Conditions for p+ Poly-Silicon and n-Type Substrate
For completeness, a brief description of p-channel FETs is described here. When the
electrode type and substrate type are interchanged (i.e., p+ poly-silicon and n-type substrate),
the explanation given in Section 2.2 would be reversed. Accumulation for this structure is a
positive voltage on the gate, and instead of holes, electrons accumulate at the silicon
substrate interface with the gate dielectric. As the bias decreases from a positive voltage,
electrons begin to leave the SiO2-Si interface until the flatband condition is reached. As the
voltage continues to decrease, electrons are depleted forming the depletion space charge
region. Decreasing the bias further into the inversion regime, the maximum depletion width
is established and holes move to the SiO2-Si interface to form an inversion layer. Thus, the
21
Figures presented throughout Sections 2.2.1 –2.2.2 would be opposite of what is shown.
Poly depletion would occur under negative bias conditions for a p+ poly-silicon gate
electrode.
2.5 Current-Voltage Characteristics
In order to assess off-state leakage current (i.e, power consumption) and device performance,
current-voltage (I-V) measurements are usually done. Typical measurements include: gate
current versus gate voltage (Ig-Vg), drain current versus gate voltage (Id-Vg), and drain
current versus drain bais (Id-Vd).
2.5.1 Gate Current Versus Gate Voltage
Reducing gate leakage current, Ig, while improving device performance (i.e., device drive) of
particular interest in low-power consuming applications today. This is typically monitored
by measuring the current density, Jg, (Jg=Ig/area(cm2)) of MIS structures in accumulation at a
measurement condition of VVV fbg 1+= . In addition, understanding the conduction
mechanisms aides in understanding the leakage current process that helps the industry
determine limits of operation for a given MIS structure at a particular technology node. The
current transport models use quantum mechanic approaches to demonstrate that as gate
22
dielectric thickness is reduced to increase device drive, the gate leakage increases. The SiO2
gate dielectric will reach its physical limits and need to be replaced by a higher dielectric
constant material (κox) that allows for a physically thicker film (tox) while retaining a high Cox
value required for improved device performance. Referring to Eq. 2.4, if κox increases, then
the tox value can increase, for the same Cox of a lower κox value and thinner tox.
ox
oxoox t
AC κε= (2.4)
where A is the area typically in cm2.
The two dielectric current transport models widely used today are direct tunneling
(DT) and Fowler-Nordheim tunneling (FNT). The primary difference between the two
models is the tunnel barrier shape. The two barrier shapes of interest are: triangular for FNT
(Figure 2.7) and trapezoidal for DT (Figure 2.8). Current density under the FNT condition
can be mathematically explained by [4]:
⎟⎟⎠
⎞⎜⎜⎝
⎛−=
oxoxFNT E
BAEJ exp2 (2.5)
where the Eox is the electric field strength in dielectric, A and B are constants dependent upon
the barrier height, ΦΒ, and the effective mass, m* as given below:
23
B
qAΦ
=h2
3
16π (2.6)
( ) 232
1*234
BqmB Φ=h
(2.7)
where q is the electron charge, and is Plack’s constant. A simplified expression often used
for direct tunneling is [5]:
h
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛−Φ−=
22
2exp 1*
2Vqm
ttAJ Boxox
DTh
(2.8)
where A is a constant, tox is the physical thickness of the SiO2 interface, m* is the effective
mass of an electron in SiO2, q is the fundamental electronic charge, ħ is Plank’s constant, ΦB
is the barrier height of SiO2 to Si substrate, and V1 is the voltage drop across the SiO2 portion
(Vox in Figure 2.8). Modeling tunneling currents through stacked dielectrics is discussed in
[6].
24
M I Stox
n+ poly
ΦBVoxJFNT
Figure 2.7. Energy band diagram description of Fowler-Nordheim injection.
SItox
VoxΦB
M
n+ poly
JDT
Figure 2.8. Energy band diagram description of direct tunneling through a trapezoidal barrier.
25
2.5.2 Drain Current Versus Drain Voltage
In MISFET devices (Figure 2.9), Id-Vd and Id-Vg measurements are of significant interest
because they provide vital information about how the device performs. Id-Vd can be used to
investigate the operational device performance. This measurement is done by measuring the
drain current as the drain voltage is swept typically from 0 V to an inversion operating bias
(VDD). This yields the saturation current, Idsat, which provides the drain current value under
typical operating conditions. This saturation characteristic is due to the channel region being
“pinched off” at the drain end of the MISFET when ( )tgD VVV −≥ . The current saturates
because electrons must be swept from the edge of the “pinch off” region to the drain due to
the transverse electric field that has been established by the drain relative to substrate
voltage.
Gate
Source Drain
Substrate
L
Dielectric
Vg
Vd
Ig
Id
Gate
Source Drain
Substrate
L
Dielectric
Vg
Vd
Ig
Id
Gate
Source Drain
Substrate
L
Dielectric
Vg
Vd
Ig
Id
Figure 2.9. Schematic of MISFET device
The Id-Vg characteristic can be used to explain two regimes of operation: the linear
regime and saturation regime as described above. In the linear region, the MISFET channel
region functions like a resistance and the drain current is then proportional to the drain
26
voltage. This channel resistance is controlled by the applied gate bias. As mentioned above,
once the drain bias is greater then Vg-Vt, the drain current saturates. Two mathematical
expressions can be used to explain each region of operation:
( ) Dtgoxeff VVVCL
WId −≅ µ for the linear regime (2.9)
and
( )2tgoxeff VVC
LWId −≅ µ for the saturation regime (2.10)
The threshold voltage, Vt is defined as:
ox
BASiBfbt C
NqVV
φεφ
2++= (2.11)
and
⎟⎟⎠
⎞⎜⎜⎝
⎛⋅≅
i
AB n
Nq
kT ln2φ (2.12)
27
where NA is the ionized impurity acceptors, and ni is the intrinsic carrier concentration. As
shown in Eq. 2.11, Vt can be affected by changes in the flatband voltage caused by charges
(see Sections 2.3.1 – 2.3.2).
2.6 Mobility Extraction
Another important use of the Id-Vg characteristic in the linear regime is extracting the
effective mobility when used in conjunction with the inversion capacitance characteristic in
the split CV technique [7] or NCSU Mob2d [8]. The effective carrier mobility, µeff, is
defined as:
inv
D
QL
Wgeff⎟⎠⎞
⎜⎝⎛
=µ (2.13)
where gD = Id/Vd, Qinv is the inversion charge, W is the channel width, and L is the channel
length. Effective mobility is typically plotted versus effective field Eeff which is defined as:
Sio
invb QQEeffκεη+
= (2.14)
28
where Qb is the depletion charge, η is 1/2 for electrons and 1/3 for holes [8]; κSi is the
dielectric constant of silicon; and εo is the permittivity of free space. Different scattering
mechanisms impact, µeff, as a function of the effective field is illustrated in Figure 2.10 [9].
As can be seen, µeff is affected by coulomb scattering µcoul at the low field regime, while at
high fields surface roughness scattering, µrough, dominates. In the moderate effective field
regime, µeff is subject to the affect of phonon scattering, µphonon. The Matthiessan rule allows
these scattering mechanisms to be included in the calculation of effective mobility:
roughphononcouleff µµµµ1111
++= (2.15)
µphonon
µroughµcoul
Effective mobility (µeff)
Phononscattering
Surfaceroughnessscattering
Effe
ctiv
e M
obili
ty, µ
eff [
cm2 /V
*sec
]
Effective Field, Eeff [MV/cm]
Coulombscattering
Figure 2.10. Universal mobility characteristic versus the effective field at the silicon surface showing the effects of coulomb, phonon, and surface roughness scattering at different effective field strengths.
29
2.7 Summary
Theory and definitions of terms and techniques have been discussed here to prepare the
reader for the work presented in this dissertation.
2.8 References
[1] R. F. Pierret, Field Effect Devices, vol. IV, 2nd ed. New York: Addison-Wesley Publishing Company, Inc., 1990.
[2] R. A. Colclaser, Microelectronics Processing and Device Design. New York: John Wiley & Sons, 1980.
[3] D. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed. New York: John Wesley & Sons, 1998.
[4] M. Depas, B. Vermeire, and P. W. Mertens, "Determination of Tunneling Parameters in Ultra-thin Oxide Layer Poly-Si/SiO2/Si Structures," Solid State Electronics, vol. 38, pp. 1465-1471, 1995.
[5] S. M. Sze, Physics of Semiconductor Devices, 2nd ed: John Wiley & Sons, Inc., 1981.
[6] Y. Ando and T. Itoh, "Calculation of transmission tunneling Current Across Arbitrary Potential Barriers," Journal of Applied Physics, vol. 61, pp. 1497-1502, 1987.
[7] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, "Charge accumulation and mobility in thin dielectric MOS transistors," Solid State Electronics, vol. 25, pp. 833-41, 1982.
[8] J. R. Hauser, "Extraction of experimental mobility data for MOS devices," IEEE Transactions on Electron Devices, vol. 43, pp. 1981-1988, 1996.
[9] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the Universality of Inversion Layer Mobility in Si MOSFETs: Part I - Effects of Substrate Impurity Concentration," IEEE Transactions on Electron Devices, vol. 41, pp. 2357-2362, 1994.
30
3 ELECTRICAL CHARACTERIZATION CONCERNS FOR SUB-2nm EOT GATE DIELECTRICS ON SILICON
3.1 Introduction
As all critical dimensions are scaled down to achieve device goals set by the ITRS Roadmap,
improved metrology precision becomes of utmost importance. For instance, as the EOT
approaches 1 nm, even one angstrom becomes a 10% variation of this targeted value, which
is too large to realize device operation tolerances. Measurement precision must approach 0.1
angstrom. Precision is seen as a more important goal than accuracy for this parameter, since
accurately measuring EOT is difficult for non-crystalline materials because of the inherent
uncertainty of interface delineation from HRTEM studies. It is thus suggested that precision
will be the guiding principle, which will depend on standardization of process, device,
measurement, and data analysis.
To establish this high-precision methodology, an evaluation of process, device,
measurement, and data analysis issues is needed, leading to an optimized procedure that can
be utilized as a standard. Standardization of the capacitance measurement is necessary
through the use of industry standard test equipment, proper measurement mode (series or
parallel circuit), measurement frequency, and voltage range. In addition, an equivalent
circuit model with a suitable industry-accepted model is necessary. Then, capacitor and
transistor test structure design and fabrication should be optimized, including small devices
31
with various areas and low electrode and substrate resistance. This begins with the proper
choice of resistivity for the starting material. Finally, data analysis needs to be considered.
Because several different models can predict different extracted values for the same data set
(e.g., EOT and Vfb) [1], only one model should be chosen for use within a given set of data,
and the model used must be clearly identified in every case.
3.2 Capacitance- Voltage Measurement
In order to assess the impact of charges in a dielectric film or obtain its electrical thickness,
the capacitance-voltage (C-V) measurement can be done on a MIS capacitor. Capacitance
can be expressed as:
dVdQC = (3.1)
Here, capacitance, C, is defined as the change in the charge amount, dQ, due to a change in
the voltage, dV. This method is known as differential capacitance. This change in voltage is
typically a small-signal ac voltage imposed on a dc sweep bias that is applied to the MIS
device. There are two types of measurements known as high frequency and low frequency
measurements where low-frequency is often accomplished using a quasi-static technique.
32
Both techniques have similar attributes, but differ in the inversion regime. These similarities
and differences will be explained later in this Section.
To begin to understand the capacitance value at a given bias, we look at the MIS
capacitor from a fundamental standpoint. The gate voltage, using Kirchhoff’s Voltage Law,
can be defined as
soxfbG VVV ψ++= (3.2)
where Vfb is the flatband voltage, Vox is the voltage drop across the oxide, and ψs is the
surface potential. Since insulator charges are not as prevalent in today’s ultra-thin silicon
dioxide technology (as previously stated in 2.3.1), their effects can be neglected. Thus, only
the charge on the gate, Qg; substrate, Qs; and interface, Qit, need be addressed [2]. Because
of charge neutrality, the sum of the charges must be zero. So,
0=++ itsg QQQ . (3.3)
Therefore, the semiconductor and interface charges must offset the charge on the gate.
( )itsg QQQ +−= (3.4)
33
So, looking from the gate voltage perspective, the capacitance, C, is defined as
g
g
dVdQ
C = (3.5)
Now, substitute eq 3.3 and eq 3.4 into eq 3.5 to obtain
its
s
its
oxsox
its
dQdQd
dQdQdVddV
dQdQC
++
+
−=++
−=φφ
1 (3.6)
where Qs is defined as
bnps QQQQ ++= (3.7)
with Qs comprised of the hole charge, Qp; the electron charge, Qn; and the space-charge
region bulk charge, Qb.
Substituting Eq. 3.7 into Eq. 3.6 yields
34
itbnpoxitbnp
s
its
ox
CCCCCdQdQdQdQd
dQdQdV
C
++++
+=
++++
+
−=11
11φ
(3.8)
The sign in Eq. 3.8 becomes positive because the minus sign cancels in either of these two
cases: i) the negative oxide and gate bias for a p-type substrate; ii) the negative
semiconductor charges due to a positive gate bias [2]. Figure 3.1 shows an equivalent circuit
that represents Eq. 3.8.
Cox
Cn CbCp Cit
Figure 3.1. A circuit representation of the capacitance contributions from the various charges found in an MIS capacitor assuming that the only oxide charge present is interface trapped charge.
Now, consider a MIS capacitor in which the substrate is p-type. As a gate bias is swept
from the accumulation condition to the inversion condition, the equivalent circuit
capacitances will change due to a transition in the amount of charge on the circuit elements.
So, for accumulation, a negative bias is applied to the gate. Holes in the substrate will then
35
accumulate at the SiO2-Si interface. As the ac signal oscillates (∆V) on the dc bias, a small
amount of charge (∆Q) is added or subtracted on both sides of the oxide. The accumulation
charge build up creates a large capacitance, Cp, relative to the other capacitances. From
circuit theory, as capacitance becomes large, a capacitor approaches a short circuit. Thus,
Figure 3.1 will become Figure 3.2 for both the quasi-static and high frequency
measurements.
Cox
Figure 3.2. The equivalent circuit representation when a large accumulation bias or inversion (low frequency) bias is applied to the gate electrode. The accumulation charge is large. Thus, the accumulation capacitance is large. Circuit theory states that as capacitance becomes large it acts like a short. Therefore, only Cox is present.
As the gate voltage is increased, the accumulation layer decreases, and a depletion
region is formed. In the depletion region, the bulk charge, Qs, is dominant, and it is
described by
36
WqNQ Db = (3.9)
where ND is the ionized donor concentration, and W is the depletion width. The contribution
of the interface trapped charge may not be neglected in this regime. Also, a small amount of
inversion charge becomes involved as weak inversion begins to appear. So, Figure 3.1 will
be approximately Figure 3.3 in the depletion regime for both high-frequency and quasi-static
measurements.
Cox
Cb CitCn
Figure 3.3. The equivalent circuit representation when a depletion bias is applied to the gate electrode. The depletion capacitance (Cb) is dominant, and the interface capacitance (Cit) cannot be neglected. Also, weak inversion begins to appear, which adds another capacitance contribution (Cn).
As the bias continues to increase and strong inversion is reached, electrons build up at
the SiO2-Si interface, and a maximum depletion width is established. Since minority carriers
37
are in abundance in strong inversion, it is important to note that the charge response to the ac
signal is not as fast as it is for majority carriers (holes). If the ac signal is slow enough to
simulate a string of dc bias states, minority carriers can be generated or recombined from
electron-hole pairs in response to the slowly varying ac signal. In this case, Cn will dominate
because Qn is high. Thus, we have the same circuit as in accumulation (Figure 3.2).
If the ac sweep is not slow enough, the generation and recombination processes
cannot respond to the ac sweep. So, the electrons will not move to the SiO2-Si interface and
the depletion width will continue to grow in order to compensate for the applied charge.
Now, Figure 3.1 becomes Figure 3.4 due to the capacitance contribution from the depletion
region, and the phenomenon known as deep depletion occurs.
Cox
Cb
Figure 3.4. The equivalent circuit representation when a strong inversion high frequency bias is applied to the gate electrode. The inversion charge cannot form. Thus, the depletion contribution is included in the circuit model.
Figure 3.5 illustrates the ideal C-V characteristics generated by [3] for an n+/p MIS
structure, and the impact of polysilicon depletion on C-V characteristics for an n+/p structure.
38
Figure 3.6 shows the ideal C-V characteristics of a p+/n MIS structure, and the impact of
polysilicon depletion on C-V characteristics for a p+/n structure.
-3 -2 -1 0 1 20.00.20.40.60.81.01.21.41.61.8
InversionDepletion
Spec
ific
Cap
acita
nce
[µF/
cm2 ]
Voltage [V]
High Frequency Quasi-Static
Ideal nMOS C-V Characteristic w/ poly depletionPoly depletion effect
Accumulation
Figure 3.5. The ideal C-V quasi-static and high frequency characteristics of an n+/p MIS structure. In an nMISFET, the impact of polysilicon depletion on C-V characteristics for an n+/p structure can be seen.
39
-2 -1 0 1 2 30.00.20.40.60.81.01.21.41.61.8
AccumulationDepletionInversion
Ideal pMOS C-V Characteristic w/ poly depletion
Spec
ific
Cap
acita
nce
[µF/
cm2 ]
Voltage [V]
High Frequency Quasi-Static
Poly depletion effect
Figure 3.6. The ideal C-V quasi-static and high frequency characteristics of an p+/n MIS structure. In an pMISFET, the impact of polysilicon depletion on C-V characteristics for an p+/n structure can be seen.
3.3 MIS Parameter Extraction
As insulator thickness is reduced, there are more challenges to extract the thickness value
from capacitance – voltage (C-V) measurements. For instance, problems occur when trying
to extract oxide capacitance, Cox, from the accumulation capacitance.
40
3.3.1 C-V Measurement Issues
The traditional method for extracting oxide thickness begins with taking the measured
capacitance in accumulation. Then, this capacitance value is substituted into Eq. 3.10 and
solved for tox.
ox
oxoox t
AC κε= (3.10)
where εo is the permittivity of free space (8.85 E-14 F/cm), κox is the dielectric constant of
silcon dioxide (3.9), A is the area (cm2), and tox is the oxide thickness (cm).
However, the accumulation capacitance can be impacted by quantum mechanical
effects [4-6], gate leakage current, and series resistance [7]. When the C-V curve begins to
decrease in accumulation, the cause is the tunneling current and the series resistance
according to Henson, et al [8]. The Henson, et al solution was to use the NCSU-CVC model
which fits the experimental C-V data to create a full C-V theoretical model using a non-linear
least squares method that accounts for the quantum mechanical and poly depletion effects to
estimate the oxide thickness [9].
Another problem in ultra-thin oxides is that the C-V curve does not saturate in
accumulation. This is due to the fact that the accumulation capacitance, Cp, is now a factor
since the oxide capacitance is high for ultra-thin oxides (Eq. 3.11).
poxeq CCC111
+= (3.11)
41
This non-saturation effect creates a problem because Cox is different at different bias
values, which ultimately yield different tox values when using Eq. 3.10.
3.3.2 Parameter Extraction Methodology
Since there are many issues to address when dealing with accumulation capacitance, many
models have been developed. However, each model’s accuracy has an impact on a final
result such as tox, for example. This rationale also holds true in the determination of the
substrate capacitance, Cs, contribution [10] in an effort to obtain an accurate value for Cs,
which in turn allows for an accurate value of Cox in
)()(
)(VCCVCC
VCsox
sox
+⋅
= (3.12)
3.3.2.1 Measurement Considerations
Before a standard measurement technique and/or procedure can be established, an
understanding of the limitations of the probe station set-up configuration is necessary. Probe
station resonance can affect higher frequency measurements if not taken into account. A
quantitative procedure outlined in [11] can be used to identify and characterize this source of
42
error, improving the precision of the measured data. This approach determined that
resonance effects limited precise measurements for frequencies above 250 kHz on the probe
station used in this work.
Once the possible measurement frequency range is determined, the additional
parasitic impedances characteristic to the system set-up (i.e., cables, probes, and device under
test) must be taken into account. This is done through the open and short correction on the
Agilent 4284A Impedance Analyzer. The open correction accounts for any stray
capacitance, and the short correction accounts for the stray inductance and resistance. As
previously stated, the open correction at International SEMATECH (ISMT) is done on an
isolated bond pad to remove the pad capacitance contribution. Above the sub-2 nm regime,
meter corrections may not be a factor. Figure 3.7 shows the C-V characteristics taken at 3
frequencies (i.e., 10 kHz, 100 kHz, 250 kHz) of a nominal 2.4 nm thick oxide with meter
corrections on and off. It can be seen that with or without the meter corrections the C-V
curves are in excellent agreement. However, when characterizing thinner oxides (~1.6 nm),
meter corrections cannot be neglected. Figure 3.8 shows C-V characteristics taken at 3
frequencies (i.e., 10 kHz, 100 kHz, and 250 kHz) of a nominal 1.5 nm thick oxide with the
meter corrections
43
-3 -2 -1 0 10
10
20
30
40
50
60
70
80
Cap
acita
nce
[pF]
Voltage [V]
10 kHz, Corrected 100 kHz, Corrected 250 kHz, Corrected 10 kHz, Uncorrected 100 kHz, Uncorrected 250 kHz, Uncorrected
Figure 3.7. Plot of the C-V characteristics for 3 frequencies with meter corrections either on or off for a nominal 2.4 nm thick oxide.
-3 -2 -1 0 1
0
20
40
60
80
100
120
Cap
acita
nce
[pF]
Voltage [V]
10 kHz, Corrected 100 kHz, Corrected 250 kHz, Corrected 10 kHz, Uncorrected 100 kHz, Uncorrected 250 kHz, Uncorrected
Figure 3.8. Plot of the C-V characteristics for 3 frequencies with meter corrections either on or off for a nominal 1.5 nm thick oxide.
44
either on or off. For this case, the uncorrected curves have degraded (roll-over) in strong
accumulation. Since the series resistance, Rs, contribution from the probe station set-up is
not accounted for, the value of Rs increases.
In an effort to explain this, Figure 3.9a shows the widely accepted equivalent circuit
for a MIS capacitor, and Figure 3.9b shows the equivalent circuit that the impedance meter
uses [12]. The expression that converts what the meter measures into the equivalent circuit
model using impedance transformations is [8]:
[ ][ ] 2222
22
)()()(
ccTsT
cTcm
CCGRGCGCC
ωωω
+++
+= (3.13)
a) b)
Cox GT
Rs Gs1=
Cm Gm
Figure 3.9. a) The three-element equivalent circuit for a MIS Capacitor, and b) The equivalent parallel mode circuit for the impedance analyzer.
45
where Cc contains all of the relevant capacitances (i.e., Cox, Cpoly, and Csub), GT is the
tunneling conductance, Rs is the series resistance, and fπω 2= . Henson, et al., show that the
product of Rs and GT in (1) causes the degradation in the measured capacitance [8].
Using the same equivalent circuit but dealing with admittances rather than
impedances, a somewhat simpler expression for equation (3.13) is obtained, as shown below.
( ) ( )[ ] ( ) cTs
s
cTs
csm C
GGG
CGGCGC ×
+≈
++= 2
2
22
2
ω (3.14)
For many cases of practical interest, the second term of the denominator of equation (3.14) is
negligible, showing that the reduction of the measured capacitance, the so-called rollover
effect, can be thought of as a sort of ‘conductance divider’, reducing the measured
capacitance when the conductances associated with the gate insulator and series resistance
become comparable.
3.3.2.2 Dual Frequency Technique
The first step in the analysis of the measured data is to extract capacitance values
representative of the insulator/interface regions of the device, not those of the complex
structure represented by the equivalent circuit of Figure 3.9a. This relationship is given in
equations (3.13) and (3.14), but these include unknown parameters that cannot be determined
46
from a single capacitance measurement. Yang and Hu [13] suggested that parallel
capacitance and dissipation factor measurements at two frequencies would provide enough
information to extract the desired parameters. Their dual-frequency technique uses Equation
3 to return the frequency-independent capacitance, Co, based on taking capacitance data at 2
frequencies
( ) ( )2
22
1
222
22
211
21 11
ffDCfDCfCo −
+−+= (3.15)
where fi is the measurement frequency (I = 1, 2), Ci and Di are the measured capacitance and
dissipation factor, respectively, at the measurement frequency, fi.
This dual-frequency approach has several limitations, however, including the
relevance of the simple equivalent circuit and the possible frequency dependence of the
circuit elements. Nara, et al. [14] propose guidelines for selection of the two frequencies
using two underlying assumptions: I) measured capacitance does not vary greatly over the
measurement frequency range and ii) the dissipation factor × frequency product is constant.
If these two criteria are met, and the dissipation factor, D1, is less than 1.1 for frequency, f1,
then f2 must be chosen significantly smaller than f1. It should then be possible to achieve a
reasonable precision of less than 4% in the parameter values.
If a C-V characteristic reasonably representative of the sample can be obtained by
these techniques, it is still necessary to extract the desired electrical parameters, taking into
47
account the relevant physical phenomena in the device, including quantum confinement
effects and polysilicon depletion in the gate electrode. There are several algorithms available
for this purpose [1], but the CVC model of Hauser [9] is used here. This model-based
parameter extraction algorithm uses the actual measured capacitance data and applies a least-
squares non-linear fit to the data set. From this fit, MIS parameters are extracted based on
theoretical models that account for polysilicon depletion and quantum-mechanical
confinement effects in the substrate. As a standardized process, all extracted parameters
from the collected data presented in this paper have been modeled by the Hauser, et al,
methodology.
Figure 3.10 shows the results of applying the Yang methodology with the Nara
guidelines to C-V curves taken at 10 kHz and 250 kHz. In strong accumulation, the
frequency-independent capacitance diverges because some of the assumptions for Nara
analysis are no longer met. The Hauser model was subsequently used to determine a non-
linear least-squares fit to the Co capacitance curve before the divergence. The Hauser model
fit of Co is actually in good agreement with the 250 kHz curve, indicating that at this
frequency, the parallel equivalent circuit provides a reasonable approximation of the sample
(Figure 4a).
48
-2 -1 0 1
0
10
20
30
40
50
60
Cap
acita
nce
[pF]
Voltage [V]
f = 250 kHz f = 10 kHz Co
Hauser model fit
Figure 3.10. Plot of the C-V characteristics for the dual-frequency technique to extract the true capacitance, Co, in which the Co model diverges because important required measurement parameter values from Nara, et al., are no longer met. The Hauser model is fit to the Co data which shows good agreement with the 250 kHz curve.
3.4 Drain Current- Gate Voltage Measurements
As stated in Section 2.5, current-voltage (I-V) measurements are usually done to assess off-
state leakage current (i.e, power consumption) and device performance of MISFETs. Typical
measurements include: gate current versus gate voltage (Ig-Vg), drain current versus gate
voltage (Id-Vg), and drain current versus drain bais (Id-Vd).Figure 3.11 and 3.12 show
characteristics of Id-Vg and Id-Vd, respectively.
49
-1.0 -0.5 0.0 0.5 1.0 1.5 2.010-12
10-10
10-8
10-6
10-4
10-2
Ig
Isub
nFET W/L = 10/1 µm
Cur
rent
[A]
Vg [V]
Open symbol: VD=0.1VSolid symbol: VD=1.5V
Id
Figure 3.11. Typical current components measured during an Id – Vg sweep.
0.0 0.5 1.0 1.5 2.00.0
0.5
1.0
1.5
2.0
2.5
3.0
Saturation region
Vg = 0.5VVg = 0.75V
Vg = 1V
Vg = 1.5V
I d [m
A]
Vd [V]
Vg = 2V
Linear region
nFET W/L = 10/1 µm
Figure 3.12. Typical Id-Vd characteristic for 2 nm SiO2 nMISFET
50
3.4.1 Id-Vg Leakage Current Correction
Leakage parasitics can affect the Id – Vg characteristic which is a significant component to
effective mobility extraction. As previously stated, the gate leakage component becomes
more significant as the gate dielectric physical thickness reduces. A physical based approach
on correcting the Id – Vg curve in the presence of appreciable gate leakage current was
presented in [15]. The model presented here assumes that the substrate current is negligible
which is a good approximation since the substrate current is typically small in an Id – Vg
measurement at typical operating regimes. In addition, the gate leakage current density is
assumed to be constant and equal over the channel region. The ‘droop’ of the Id – Vg curve
in strong inversion illustrated in Figure 3.13 demonstrates the effect of gate leakage. As the
gate leakage current increases, electrons that are supposed to participate in the drain current
across the channel are now being lost to the gate leakage current. This current loss to the
gate implies non-constant channel current that results in the ‘droop’ seen. Using the
assumptions presented above with the physically based model and Figure 3.14, another
simplistic model is possible. Since the assumption of negligible substrate current is used, the
Figure illustrates that the gate leakage comes from the source and drain. Due to the constant
current assumption and a symmetric device, the gate leakage current is equal from the source
(Is,g) and the drain (Id,g). In addition, the source and drain each provide one-half of the gate
leakage:
gdgsg III ,, += (3.16)
51
and
2,,g
gdgsIII == (3.17)
The measured channel drain current (IDmeas) can be expressed as:
2,g
chdmeasDIII −= (3.18)
So, the leakage corrected channel drain current (Id,ch) is:
2,g
measDchdIII += (3.19)
3.4.2 Mobility Extraction
This corrected channel drain current, where no ‘droop’ is evident, is illustrated in Figure
3.13. Figure 3.15 demonstrates the effect gate leakage has on the extracted mobility using
the NCSU Mob2d model [16]. Since the extraction algorithm uses non-linear least squares
fitting to experimental data, a distorted Id – Vg will result in a poor model fit which leads to
52
inaccuracies in the determination of the effective mobility. The IDmeas mobility result is
severely distorted compared to the corrected Id,ch mobility.
0.0 0.5 1.0 1.5 2.00
5
10
15
20
2 nm SiO2 gate oxidenFET W/L = 20/20 µm
Vd = 40mV
Gate Leakage (Ig = Is,g + Id,g) Measured ID (IDmeas) Corrected ID (Id,ch = IDmeas + Ig/2)
Cur
rent
[µA
]
Gate Voltage [V]
'Droop'
Figure 3.13. Transistor current components showing the impact of gate leakage (Ig) on the measured drain current (the ‘droop’ in IDmeas), and its removal in the corrected drain current (Id,ch).
Is,g
Is,g Id,g
Id,g
Id,chIs,ch
Is,g
Is,g Id,g
Id,g
Id,chIs,ch
Figure 3.14. Schematic of a transistor showing the current components in an Id – Vg measurement.
53
0.2 0.4 0.6 0.8 1.0 1.2 1.4100
150
200
250
300
350
400
450
500
2 nm SiO2 gate oxidenFET W/L = 20/20 µm
Effe
ctiv
e M
obili
ty [c
m2 /V
*sec
]
Effective Field [MV/cm]
Uncorrected mobility (IDmeas) Corrected Mobility (Id,ch) Universal
Figure 3.15. Gate leakage impact on the extracted mobility where the ‘drooping’ Id – Vg produces a distorted mobility curve while the Id corrected for gate leakage mobility characteristic is more robust.
3.5 Summary
Concerns have been addressed for sub-2 nm regime gate dielectric characterization, leading
to a proposed standardized methodology for electrical characterization of these structures.
This standardized procedure calls for the use of highly doped substrates; measurements on
multiple devices areas and, of course, multiple measurements on a given area for
reproducibility; and a measurement protocol that includes meter corrections and data analysis
54
techniques to provide robust parameter and mobility extractions important for the
characterization of gate dielectric materials for the sub-2 nm EOT era.
3.6 References
[1] C. A. Richter, A. R. Hefner, and E. M. Vogel, "A Comparison of Quantum-Mechanical Capacitance-Voltage Simulators," IEEE Electron Device Letters, vol. 22, pp. 35-37, 2001.
[2] D. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed. New York: John Wesley & Sons, 1998.
[3] E. M. Vogel, C. A. Richter, and B. G. Rennex, "A capacitance-voltage model for polysilicon-gated MOS devices including substrate quantization effects based on modification of the total semiconductor charge," Solid-State Electronics, vol. 47, pp. 1589-1596, 2003.
[4] F. Stern and W. E. Howard, "Properties of Semiconductor Surface Inversion Layers in the Electric Quantum Limit," Physical Review B, vol. 163, pp. 816, 1967.
[5] E. D. Castro and P. Olivo, "Quantum Effects in Accumulation Layers of Si-SiO2 interfaces in the WKB Effective Mass Approximation," Phys. Stat. Sol., vol. 132, pp. 153, 1985.
[6] K. S. Krisch, J. D. Bude, and L. Manchanda, "Gate Capacitance Attenuation in MOS Devices with Thin Gate Oxides," IEEE Electron Device Letters, vol. 17, pp. 512, 1996.
[7] S. Kar and W. E. Dahlke, "Interface state in MOS Structures with 20-40 Å thick SiO2 films on Nondegenerate Si," Solid State Electronics, vol. 15, pp. 221, 1972.
[8] W. K. Henson, K. Z. Ahmed, E. M. Vogel, J. R. Hauser, J. J. Wortman, R. D. Venables, M. Xu, and D. Venables, "Estimating Oxide Thickness of Tunnel Oxides Down to 1.4 nm Using Conventional Capacitance-Voltage Measurements on MOS Capacitors," IEEE Electron Device Letters, vol. 20, pp. 179-181, 1999.
[9] J. R. Hauser and K. Ahmed, "Characterization of Ultrathin Oxides Using Electrical C-V and I-V Measurements," presented at Characterization and Metrology for ULSI Technology: 1998 International Conference, 1998.
[10] B. Ricco, P. Olivo, T. N. Nguyen, T.-S. Kuah, and G. Ferriani, "Oxide-Thickness Determination in Thin-Insulator MOS Structures," IEEE Transactions on Electron Devices, vol. 35, pp. 423-438, 1988.
55
[11] I. Polishchuk, G. A. Brown, and H. R. Huff, "Sources of Resonance-Related Errors in Capacitance Versus Voltage Measurement Systems," Review of Scientific Instruments, vol. 71, pp. 3962-3963, 2000.
[12] E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology: John Wiley & Sons, 1982.
[13] K. J. Yang and C. Hu, "MOS Capacitance Measurements for High-Leakage Thin Dielectrics," IEEE Transactions on Electron Devices, vol. 46, pp. 1500-1501, 1999.
[14] A. Nara, N. Yasuda, H. Satake, and A. Toriumi, "Limitations of the Two-frequency Capacitance Measurement Technique Applied to Ultra-Thin SiO2 Gate Oxides," presented at IEEE 2001 International Conference on Microelectronic Test Structures, 2001.
[15] P. M. Zeitzoff, C. D. Young, G. A. Brown, and K. Yudong, "Correcting Effective Mobility Measurements for the Presence of Significant Gate Leakage Current," IEEE Electron Device Letters, vol. 24, pp. 275-7, 2003.
[16] J. R. Hauser, "Extraction of experimental mobility data for MOS devices," IEEE Transactions on Electron Devices, vol. 43, pp. 1981-1988, 1996.
56
4 TEST STRUCTURE DESIGN
4.1 Introduction
As the gate dielectric thickness diminishes below 2 nm in MIS devices, extreme care must be
taken when conducting electrical measurements and eventual parameter extraction. The
electrical measurement, and the subsequent data analysis that need to be considered were
discussed in Chapter 3. Attentiveness to test structure design is just as important in
standardizing a methodology to characterize sub-2 nm dielectrics in order to extract robust
and precise parameters such as equivalent oxide thickness (EOT) and flatband voltage (Vfb).
In order to evaluate the electrical characterization methodologies mentioned, quality device
structures must be designed and fabricated.
4.2 Starting Material
In an effort to assess starting material, C-V measurements were made on highly doped
substrates with a similar 2.0 nm In-Situ Steam Generated (ISSG) oxide growth. C-V
characteristics are shown in Figure 4.1. It can be seen that the more heavily doped substrate
57
C-V curve is “stretched-out” in the depletion regime. This allows better resolution of the flat
band voltage and midgap interface state density for precise characterization.
-3 -2 -1 0 1
0
20
40
60
80
100
120
Cap
acita
nce
[pF]
Voltage [V]
Lightly Doped Wafer Highly Doped Wafer
Figure 4.1. Plot of the C-V characteristics for a more heavily doped substrate and a less heavily doped substrate where the highly doped substrate exhibits a “stretched-out” behavior in the depletion regime allowing better resolution of the flat band voltage and midgap interface state density.
4.3 Test Structure Design
To assess the need for multiple area testing and pad capacitance contribution, C-V
measurements were made on multiple area n+/p MIS capacitors. Figure 4.2 shows the C-V
characteristics for three areas without the pad capacitance correction. It can be seen that for
58
the large gate area, gate leakage and series resistance affect the accumulated capacitance
while the two smaller areas show the impact of not correcting for the pad capacitance
contribution since the area independent C-V curves do not lie on each other. Figure 4.3
demonstrates the C-V characteristics for multiple areas with the pad capacitance correction.
This plot shows that with the pad capacitance correction, the two smaller area C-V curves
come into agreement, which established the validity of this data. Accounting for pad
capacitance can be done in one of two ways. First, in an electrical measurement, contacting
the probe on an isolated bond pad (i.e., no device) during the open circuit meter correction
will account for the pad capacitance contribution. Assuming that the pad area is constant for
all device sizes, another approach is to plot Cox at a given bias versus gate area [1]. Once this
is completed, linear regression analysis on this data should be done. Extrapolating the linear
regression to the y-intercept (i.e., as the device area goes to zero) yields the value of the pad
capacitance contribution to the total measured capacitance.
59
-3 -2 -1 0 1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Spec
ific
Cap
acita
nce
(C-C
pad)
/A [µ
F/cm
2 ]
Voltage [V]
A = 1.96E-5 cm2
A = 7.85E-5 cm2
A = 1.93E-3 cm2
A = 1.93E-3 cm2
Cpad = 0 pF
Figure 4.2. Plot of the C-V characteristics for multiple area n+/p MIS Capacitors showing the effect of area size and no pad capacitance correction. For large areas, the gate leakage and series resistance affect the accumulated capacitance while the two smaller areas show the impact of not correcting for the pad capacitance since open and closed circles are not in as good agreement as subsequently seen in Figure 3.
60
-3 -2 -1 0 1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Cpad = 1.1 pF
Spec
ific
Cap
acita
nce
(C-C
pad)
/A [µ
F/cm
2 ]
Voltage [V]
A = 1.96E-5 cm2
A = 7.85E-5 cm2
A = 1.93E-3 cm2
A = 1.93E-3 cm2
Figure 4.3. Plot of the C-V characteristics for multiple area n+/p MIS Capacitors showing the effect of area size and the pad capacitance correction where the two smaller areas are in agreement when corrected for pad capacitance which establishes the validity of this data. The large area device data must be ignored.
To assess the impact of the test structure design on electrical measurements, a case
study was performed on three different capacitor structures as shown Figure 4.4 as part of
Table 4.1. The true nested capacitor (a) is a structure where the gate polysilicon electrode
pad does not overlap onto the field oxide. In this conFiguration, there is no pad capacitance
contribution. The nested gated capacitor (b) has a highly doped region surrounding the
nested capacitor to provide a source of carriers for simulated low-frequency measurements.
This particular device has two probe contacts for the highly doped region and the capacitor
61
gate, respectively. The capacitor gate has a long pad structure, which will be shown to
provide a significant amount of pad capacitance relative to the total measured capacitance.
The simple overlap capacitor (c) is a typical structure currently in use. Table 4.1 summarizes
the case study results. Here, the pad capacitance was simply calculated by subtracting the
nested structure capacitance from the overlap structure capacitance, since no isolated bond
pad was available. This value was verified by comparison with that computed from the
known pad area and isolation oxide thickness. This overlap contribution is then subtracted
from the overlap capacitor to leave only the gate oxide capacitance contribution. Table 4.1
shows that these extracted parameters are in excellent agreement. However, for the nested
gated capacitor, subtracting the same amount of overlap capacitance is not enough to yield
the same agreement of the true nested and overlap capacitors because the long, narrow pad
has a larger geometry. This geometry has apparently affected both the C-V curve shape and
extracted EOT values. It should be noted that this larger geometry is also contributing more
series resistance.
62
Table 4.1. Results of the test structure design case study with pictorial representation of the device structures
Parameter original data 100 kHz data Dual Freq. data
EOT [A] 17.1 17.2 17.0Nsurf [/cc] 3.3E+15 3.0E+15 2.4E+15Nbulk [/cc] 1.6E+15 1.7E+15 1.5E+15Vfb [V] -0.937 -0.935 -0.929Rs(-2V) [ohm] 35.2RMS data fit error - 0.7% 1.1%
100 kHz data Dual Freq. data Dual Freq. data(no pad correction) (no pad correction) (pad correction)
EOT [A] 16.7 16.3 16.5Nsurf [/cc] 8.4E+15 7.3E+15 4.3E+15Nbulk [/cc] 1.8E+16 1.7E+16 7.2E+15Vfb [V] -0.958 -0.957 -0.944Rs(-2V) [ohm] 80.7 81.6RMS data fit error 0.4% 1.2%
100 kHz data 100 kHz data Dual Freq. data(no pad correction) (pad correction) (pad correction)
EOT [A] 17.0 17.2 17.0Nsurf [/cc] 5.1E+15 3.30E+15 2.45E+15Nbulk [/cc] 5.4E+15 1.90E+15 1.70E+15Vfb [V] -0.947 -0.936 -0.929Rs(-2V) [ohm] 27.8RMS data fit error 0.7% 0.9% 1.2%
Overlap Capacitor (single pad)
True Nested Capacitor (no pad)
Nested Gated Capacitor (2-pad)
(a)
(b)
(c)
Figure 4.4. Three capacitor structures: a) true nested capacitor, b) nested gated capacitor, and c) overlap capacitor
4.4 Process Flow
Figure 4.5 illustrates a planar transistor that was fabricated using a typical self-aligned
MISFET process flow that is listed in Table 4.2. This device structure is used in the
63
evaluation of alternative gate dielectrics in an effort to find a replacement for the SiO2 gate
dielectric.
Gate
Source Drain
Substrate
L
Dielectric
P-type Si
n+n+
n+ poly-Si
Gate
Source Drain
Substrate
L
Dielectric
P-type Si
n+n+
n+ poly-Si
Figure 4.5. Schematic of a typical self-aligned MISFET
Table 4.2. Synopsis of an nMIS transistor process flow
Major Process Steps
Process Description
1 200 mm, (100), p/p+ epitaxial wafer or homogeneous moderately heavily doped 2 Poly buffered LOCOS + well formation/channel-implants 3 HF-dip + O3 wet clean 4 Dielectric growth or deposition 5 Amorphous Si deposition + Phosphorus ion implant (for nMIS) 6 Gate patterning 7 LDD implant + Spacer deposition 8 Spacer etch to remove high-k dielectric from source/drain regions 9 S/D implant + Rapid Thermal Anneal (1000C/10 sec) 10 Ti-salicide formation 11 ILD deposition + CMP planarization 12 Contact W-plug formation 13 Metal deposition and patterning 14 Forming gas anneal
64
4.4.1 Alternative Gate Dielectric Processing Techniques
Two attractive deposition techniques used to fabricate Hf-based gate dielectrics in major
process step #4 is Atomic Layer Deposition (ALD) and Metal Organic Chemical Vapor
Deposition (MOCVD).
4.4.1.1 ALD
This approach provides precise thickness control and deposition uniformity across the wafer,
and good reproducibility due to a self-limiting growth process that requires alternating cycles
of reaction gases injected into a reaction chamber. The growth kinetics of the self-limitations
is governed by the surface reaction during each reaction cycle followed by a purge and the
subsequent introduction of the alternate reaction cycle. Typical precursors used include
metal chlorides like HfCl4 and water. The two precursors are introduced separately, one in
each reaction cycle [3]. The ALD samples used in this work were deposited using the
precursors mentioned followed by a post deposition anneal (PDA) in N2 at 6000C for 60
seconds [4], unless otherwise noted.
65
substrate silicon
Spacer
Poly
Ti-salici
deSpacer Poly
Ti-salicide
10 nm
ALD HfO2
Bottom Interface ~1 nm
a-Si
substrate silicon
Spacer
Poly
Ti-salici
deSpacer Poly
Ti-salicide
substrate silicon
Spacer
Poly
Ti-salici
deSpacer Poly
substrate silicon
Spacer
Poly
Ti-salici
deSpacer Poly
Ti-salicide
10 nm
ALD HfO2
Bottom Interface ~1 nm
a-Si
Figure 4.6. CrosSectional TEM image of an ALD HfO2 transistor structure.
4.4.1.2 MOCVD
This approach more readily allows the deposition of meal alloys. The two primary
precursors used in the CVD process are: TDEAH (Hf-(N-(CH2-CH3)2)4 and tetrakis-
dimethylamide-silicon, TDMAS, Si-N-(CH3)2)4. Using both of these precursors allows the
creation of HfO2 or HfSixOy films that can be varied in their composition [5]. The MOCVD
samples used in this work were deposited at 485ºC using the precursors above to form HfO2
or Hf Silicate (20% SiO2) followed by a PDA typically in NH3 at 700ºC for 60 seconds,
unless otherwise noted.
66
100 nm
Poly
Ti-Salicide
5 n m
MOCVD HfSixOy
Bottom Interface ~1 nm
100 nm
Poly
Ti-Salicide
100 nm
Poly
Ti-Salicide
5 n m
MOCVD HfSixOy
Bottom Interface ~1 nm
5 n m
MOCVD HfSixOy
Bottom Interface ~1 nm
Figure 4.7. CrosSectional TEM image of an MOCVD Hf-based transistor structure.
4.5 Summary
The starting material for MIS electrical characterization should be moderately highly doped
substrates to maximize parameter extraction. The impact of device design on the extraction
of electrical parameters such as equivalent oxide thickness has been demonstrated in the case
study presented. Finally, a process flow for typical MISFETs used in the subsequent charge
trapping studies has been outlined.
67
4.6 References
[1] C. Young, B. Barnes, S. Castro, E. Condon, K. Koh, M. Scrader, S. Shah, K. Williamson, M. Xu, R. Kuehn, D. Maher, D. Venables, A. Oberhofer, G. Wang, and J. Chen, "University and Small Firm Collaboration for Process Development of Advanced Gate Dielectrics," presented at 13th Biennial University/Government/Industry Microelectronics Symposium, Minneapolis, MN, 1999.
[2] C. Lim, Y. Kim, A. Hou, J. Gutt, S. Marcus, C. Pomarede, E. Shero, H. Waard, C. Werkhoven, L. Chen, J. Tamim, N. Chaudhary, G. Bersuker, J. Barnett, C. D. Young, P. Zeitzoff, G. A. Brown, M. Gardner, R. W. Murto, and H. R. Huff, "Effect of Deposition Sequence and Plasma Treatment on ALCVD(TM) HfO2 n-MOSFET Properties," presented at 1st International Symposium on High Dielectric Constant Materials: Materials Science, Processing, Manufacturing, and Reliability Issues at the Fall Meeting of the Electrochemical Society, Salt Lake City, Utah, 2002.
[3] D. Riihela, M. Ritala, R. Matero, and M. Leskela, "Introducing atomic layer epitaxy for the deposition of optical thin films," Thin Solid Films, vol. 289, pp. 250-255, 1996.
[4] K. Yudong, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, L. JaeEun, B. Foran, F. Shaapur, A. Agarwal, P. Lysaght, G. A. Brown, C. Young, S. Borthakur, L. Hong Jyh, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. W. Murto, A. Hou, H. R. Huff, E. Shero, C. Pomarede, M. Givens, M. Mazanez, and C. Werkhoven, "Conventional n-channel MOSFET devices using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode," International Electron Devices Meeting. Technical Digest Cat. No.01CH37224., vol. 20, pp. 1-4, 2001.
[5] Y. Kim, C. Lim, C. D. Young, K. Matthews, J. Barnett, B. Foran, A. Agarwal, G. A. Brown, G. Bersuker, P. Zeitzoff, M. Gardner, R. W. Murto, L. Larson, C. Metzner, S. Kher, and H. R. Huff, "Conventional Poly-Si Gate MOS-transistors With a Novel, Ultra-Thin Hf-oxide Layer," presented at VLSI Technology Symposium, Kyoto, Japan, 2003.
68
5 CHARGE TRAPPING MEASUREMENTS AND THEIR APPLICATION TO HIGH-κ GATE STACK EVALUATION
5.1 Introduction
The charge trapping process has been identified as one of the significant issues for Hf-based
materials introduction into the CMOS technology, potentially causing threshold voltage
instability and mobility degradation. Several measurement techniques can be used to study
and quantify charge trapping: Capacitance-Voltage (C-V) hysteresis, alternating stress and
sense Vfb/Vt instability, charge pumping, and fast transient Id-Vg measurement. While each
of these techniques can provide information on specific aspects of the charge trapping
phenomenon, some measurements are more convenient (e.g., less time consuming), and some
may be more sensitive for resolving subtle differences between the experimental samples. In
particular, C-V hysteresis measurements can be used to monitor ∆Vfb shifts. However, this
technique as a sole measurement of ∆Vfb has some drawbacks since the results strongly
depend on the test conditions, that is the voltage sweep amplitude and ramp rate. To address
this issue, a more quantifiable technique that uses a constant voltage gate dielectric stress
(CVS) with interspersed limited-voltage-range C-V measurements around flatband can be
used [1]. Although systematic, this technique results in the de- trapping of some of the
charge between the stress and sense sequence. A useful alternative approach to investigation
of the charge trapping is provided by two versions of the charge pumping (CP) technique [2].
69
Fixed-amplitude (FA) variable base CP under different frequencies conditions can be used to
evaluate the silicon substrate/gate dielectric interface. Variable-amplitude (VA) fixed base
CP can provide some insight about trap sites located in the bulk of the gate dielectric.
However, interpretation of the data can be complicated due to the gate, as well as
source/drain leakage. Finally, another technique is the fast transient Id-Vg measurement,
where the drain current is measured during the microseconds of the gate pulse, reflects the
effect of charge trapping [3]. The shift of the Id-Vg curves generated by the up and down
swing of the pulse (i.e., ∆Vg) corresponds to the amount of the trapped charge. Examples of
these measurements and analysis to explain the findings above are presented herein.
5.2 Capacitance – Voltage Hysteresis
Capacitance-Voltage (C-V) measurements can provide vital device parameters such as
equivalent oxide thickness, EOT, flatband voltage, Vfb, and substrate doping, Nsub, when
properly done as stated in Chapter 3. In addition, a forward and back sweep of the C-V
measurement known as a hysteresis measurement can be used to monitor trapped charge by
obtaining the difference in the flatband voltage (Figure 5.1). The flatband voltage expression
given in Section 2.3.2 can be used to determine the amount of trapped charge, and is restated
here for convenience:
70
ox
omsfb C
QV −Φ= (5.1)
where Qo is comprised of the charges mentioned in Sections 2.3.1.1 – 2.3.1.3. Since Vfb is
also in the threshold voltage expression, the difference in a forward and back C-V sweep can
be seen in the inversion regime of a transistor or quasi-static measurement as well.
The measured trapped charge is often subject to the injection field strength, Estress,
across the dielectric stack, which can be described as:
EOTV
E gstress = (5.2)
where Vg is the gate bias and EOT is typically in cm. Since different EOT’s can exist within
a sample set that is under investigation, one should match the field strength for the given
sweep condition. Figure 5.1 illustrates a different ∆Vfb for different bias sweep conditions on
the same sample showing the impact of field strength. In addition the sweep condition (i.e.,
step voltage, frequency, integration time) should be the same when comparing samples.
71
-3 -2 -1 0 1 20
20
40
60
80
100
Vinv = 0.8 V
Vaccum = -2.2 V
∆Vfb = 105 mV
Cap
acita
nce
[pF]
Voltage [V]
Inv to Accum Accum to Inv
Freq = 100 kHz4 nm ALD HfO2
a)
-3 -2 -1 0 1 20
20
40
60
80
100
b) Vinv = 1.3 V
Vaccum = -2.6 V Freq = 100 kHz4 nm ALD HfO2
Cap
acita
nce
[pF]
Voltage [V]
Inv to Accum Accum to Inv
∆Vfb = 191 mV
Figure 5.1. Voltage “inversion to accumulation” and “accumulation to inversion” sweep methodology that demonstrates larger ∆Vfb when voltage sweep widens: b) shows a larger ∆Vfb value compared to a) due to wider voltage sweep (larger electric field strength).
72
Capacitance-Voltage hysteresis measurements also serve as a qualitative approach to
understand trapping phenomena in MIS structures. Using C-V hysteresis as a quantitative
approach may be challenging without solid understanding of the trapping that is occurring.
5.2.1 Application of Capacitance – Voltage Hysteresis Measurements
One application in particular is the MOCVD Hybrid Stack which will be evaluated here.
Two trapping modes are seen in this particular gate stack with one mode coming from gate
injection and the other from substrate injection. The hybrid stack was formed by two
consecutive depositions on a chemical oxide under vacuum conditions where an HfO2 layer
of 4.0 nm nominal thickness was followed by a 1.0 nm 20% SiO2 Hf silicate layer such that
the stack was defined as:
Chemical Oxide / 40Å HfO2 / 10Å HfSixOy / Poly electrode
5.2.1.1 Capacitance Results
Capacitance – Voltage measurements with a forward and back sweep were collected on
capacitor and transistor test structures. For the capacitor, a series of measurements were
taken such that the Estress increased in magnitude. The C – V measurements taken below
–2.3 V has no obvious Vfb shift (Figure 5.2), but if the measurement is done again out to
–2.4 V, a noticeable Vfb shift can be seen (Figure 5.3). At this time, it is important to note
that the Vfb shift is positive suggesting a “critical” voltage is required to achieve the gate
73
injected electron trapping demonstrated. To further investigate this, C – V measurements
were done with sweep voltage ranges 1 to –2.52 to 1 V. After the initial C – V sweep was
conducted to achieve gate injected electron trapping, a subsequent C – V sweep was repeated
on the same device. The result is shown in Figure 5.4 where charge retention can be seen.
The subsequent C – V sweep in both directions after an initial bi-directional sweep shows no
hysteresis and lies on the backsweep curve of the initial C – V. The measurement was
repeated again on an unmeasured site, but the measurement was started at the injection
condition of –2.52 V, swept to 1 V and then back to –2.52 V. The result is shown in Figure
5.5. Charge retention is achieved again because starting the measurement in accumulation
demonstrates no hysteresis and lies on the backsweep curve of the original C – V curve
measured on another site.
74
-3 -2 -1 0 102468
101214161820
1E-5 cm2 CapFreq = 50 kHz
Cap
acita
nce
[pF]
Voltage [V]
Inv to Accum Accum to Inv
Vaccum = -2.3 V
Figure 5.2. Voltage “inversion to accumulation” and “accumulation to inversion” sweep methodology showing no ∆Vfb up to a –2.3 V accumulation bias.
-3 -2 -1 0 102468
101214161820 Vaccum = -2.4 V
Cap
acita
nce
[pF]
Voltage [V]
Inv to Accum Accum to Inv
1E-5 cm2 CapFreq = 50 kHz
Figure 5.3. Voltage “inversion to accumulation” and “accumulation to inversion” sweep methodology showing noticeable ∆Vfb when a “critical accumulation bias of –2.4 V is reached.
75
-2 -1 0 102468
101214161820
1E-5 cm2 CapFreq = 100 kHz
Cap
acita
nce
[pF]
Voltage [V]
Initial C-V Inv to Accum Accum to Inv
After Initial C-V Inv to Accum Accum to Inv
Figure 5.4. Gate injected electron trapping shown: sweep in both directions after initial bi-directional C – V sweep shows no hysteresis and lies on the gate injected “accumulation to inversion” curve of the initial C – V.
-2 -1 0 102468
101214161820
1E-5 cm2 CapFreq = 100 kHz
Cap
acita
nce
[pF]
Voltage [V]
Initial C-V Inv to Accum Accum to Inv
"Fresh" C-V Accum to Inv Inv to Accum
Figure 5.5. Gate injected electron trapping: “Fresh” site measurement starting in accumulation shows no hysteresis and lies on the “accumulation to inversion” curve of the initial C – V.
76
Elevated temperatures were used in an attempt to release the trapped electrons and
estimate the activation energy. An initial C – V measurement was taken to trap the electrons.
The wafer was placed on a hot chuck for one minute, removed, and re-measured. Figure 5.6
illustrates that electron release did not occur at: a) 100oC, b) 150oC, or c) 200oC.
-2 -1 0 102468
101214161820
a)
1E-5 cm2 CapFreq = 100 kHz
Cap
acita
nce
[pF]
Voltage [V]
Initial C-V Inv to Accum Accum to Inv
After 100oC for 1 min Inv to Accum Accum to Inv
-2 -1 0 102468
101214161820
b)1E-5 cm2 CapFreq = 100 kHz
Cap
acita
nce
[pF]
Voltage [V]
Initial C-V Inv to Accum Accum to Inv
After 150oC for 1 min Inv to Accum Accum to Inv
77
-2 -1 0 102468
101214161820
1E-5 cm2 CapFreq = 100 kHz
Cap
acita
nce
[pF]
Voltage [V]
Initial C-V Inv to Accum Accum to Inv
After 200oC for 1 min Inv to Accum Accum to Inv
c)
Figure 5.6. Attempts to remove trapped electrons using high temperature to determine activation energies. The electrons remained trapped after a) 100ºC, b) 150ºC, and c) 200ºC following an initial C – V measurement at room temperature to trap the electrons.
5.2.1.2 Transistor Results
Capacitance – Voltage measurements were made on nMISFET devices of dimensions W/L =
20/20 µm. All transistors were measured at 100 kHz with a 40 mV step.
78
0.0 0.5 1.0 1.5 2.00
1
2
3
4
5
6W/L = 20/20 µm TransistorFreq = 100 kHz
C-V Sweep
Cap
acita
nce
[pF]
Voltage [V]
-1 to 1.5 V 1.5 to -1 V -1 to 2 V 2 to -1 V -1 to 2.4 V 2.4 to -1 V
Figure 5.7. Bi-directional C – V sweeps illustrating full charge recovery when a C – V accumulation bias of –1 V (identical up-sweeps) is used and increasing substrate injected electron trapping as C – V bias into inversion is increased.
C – V data was collected in the inversion regime starting at different inversion
voltages and finishing at –1 V. Figure 5.7 shows the output of this approach with the C – V
“turn on” regime shifting towards the right as the C – V measurement is started further in
inversion (i.e., starting the C – V measurement at 2.4 V shifts further to the right than starting
at 1.5 V, etc.) This shows electron trapping from substrate injection. The identical C – V up-
sweeps shows the least amount of electron trapping from the substrate because the
measurement came from the discharge accumulation condition. This demonstrates a trapping
phenomenon similar to that proposed by Kerber, et al. [2].
79
-2 -1 0 1 20
1
2
3
4
5
6
7
Freq = 100 kHzW/L = 20/20 µm Transistor
Cap
acita
nce
[pF]
Voltage [V]
Inv to Accum Accum to Inv Accum to Inv Inv to Accum
Figure 5.8. Conventional bi-directional sweep with a subsequent forward and back sweep in accumulation shows similar results to the capacitor.
After an initial bi-directional C – V sweep, C – V data was collected in the
accumulation regime starting at – 2 V and sweeping into the depletion (0.52 V) and inversion
(1 V) regimes and back to – 2 V in Figures 5.8 and 5.9, respectively. Figure 5.8 illustrates
that gate injection is present, reminiscent of the capacitor data previously shown. The gate-
injected trapped electrons stay trapped even out to 1 V since the accumulation C – V forward
and back sweeps lie on the back sweep of the conventional C – V sweep starting in inversion
to accumulation and back to inversion. Somewhere between 1 V and 1.5 V, the gate-injected
trapped electrons begin to de-trap as shown in Figure 5.10.
80
-2 -1 0 1 20
1
2
3
4
5
6
7
Freq = 100 kHzW/L = 20/20 µm Transistor
Cap
acita
nce
[pF]
Voltage [V]
Inv to Accum Accum to Inv Accum to Inv Inv to Accum
Figure 5.9. Conventional bi-directional sweep with a subsequent “accumulation to inversion” sweep further into inversion (i.e., Vg = 1 V) and back shows similar results to the capacitor.
-2 -1 0 10
1
2
3
4
5
6
7
Freq = 100 kHzW/L = 20/20 µm Transistor
Cap
acita
nce
[pF]
Voltage [V]
Accum to Inv Inv to Accum
Figure 5.10. Conventional bi-directional sweep with a subsequent “accumulation to inversion” sweep further into inversion (i.e., Vg = 1.5 V) and back shows a critical voltage has been reach where electrons trap and de-trap.
81
-2 -1 0 1 20
1
2
3
4
5
6
7
Qs
Qg
23
4
Freq = 100 kHzW/L = 20/20 µm Transistor
Cap
acita
nce
[pF]
Voltage [V]
Inv to Accum Accum to Inv Accum to Inv Inv to Accum
1
Figure 5.11. Conventional bi-directional sweep with a subsequent “accumulation to inversion” sweep and back shows quite similar characteristics where electrons trap from the gate and substrate, but de-trap as the sweeps move through depletion and weak inversion.
Now, lets bring this learning to the situation in Figure 5.11. It can be seen in Figure
5.11 that C – V sweeps, reproduce similar C – V curves whether inversion to accumulation
and back to inversion or accumulation to inversion and back to accumulation. Taking a
closer look, let Qg represent the gate-injected electron trapping charge seen in the capacitor
and accumulation-only transistor C – V measurements (Figures 5.8-5.9). Also, let Qs
represent the substrate-injected electron trapping seen in the inversion only transistor C – V
measurement (Figure 5.7). If the C – V measurement starts in inversion, Qs is large due to
substrate injection. This shifts the C – V curve to the right (#1 in Figure 5.11). As the C – V
sweeps moves out of inversion and into accumulation (#2 in Figure 5.11), the Qs charge is
82
de-trapped. Once the “critical” voltage is reached in accumulation, Qg charge is trapped (#3
in Figure 5.11), and remains trapped as the sweep moves from accumulation to inversion
until some critical point beyond “turn-on” where it is de-trapped. This is the case because
Figure 5.10 shows this phenomenon.
5.3 Stress and Sense Methodologies
As demonstrated in Section 5.2, a typical measurement for charge trapping is the C-V
hysteresis measurement to determine the flatband voltage shift, ∆Vfb. However, this
technique as a sole measurement of ∆Vfb has some drawbacks in that it is a function of the
voltage sweep amplitude and ramp rate. To address this issue, a more systematic, quantifiable
technique that uses a constant voltage gate dielectric stress with interspersed limited-voltage-
range C-V measurements to determine ∆Vfb was used [1]. Flat band voltage as a function of
stress time or injected charge provides information on how much charge is trapped in the
gate stack structure.
First, 100 kHz C-V data was collected on NMOS capacitors and transistors. The
NCSU CVC model [4] was envoked to extract Vfb, capacitance at Vfb (Cfb), EOT and
effective electric field across the oxide (Eox). These parameters were user inputs into the
charge-trapping application developed for the Keithley 4200 Semiconductor Characterization
System, which controlled a Keithley 708A Switch Matrix and 590 C-V Analyzer. The
application and system components enable a constant voltage stress with interspersed
83
limited-voltage-range C-V measurements of a few tenths of a volt around Vfb to minimize
any additional stress. This C – V sweep could also be bi-directional to see any hysteresis
related to the measurement itself. The ∆Vfb is then referenced from the initial limited-voltage
range C-V measurement taken before stressing. This technique was applied to various
hafnium-based gate dielectrics in an effort to evaluate the charge-trapping nature of the
respective films.
When the device under test (DUT) experiences the voltage stress condition, leakage
current is measured in an effort to quantify the amount of charge injected into the gate, which
is expressed as:
∫= dtIQ Leakageinj (5.3)
Between voltage stresses, three types of measurements can be done in sequence: C-V,
I-V and charge-pumping [5]. From these measurements, important device parameters can be
extracted and plotted as a function of time to show the degradation caused by the stresses.
5.3.1 Stress/C-V Measurement
For instance, in stress and C-V measurements [1], the DUT usually is a MIS capacitor or
transistor. A C-V sweep is performed on the DUT before and after voltage stress. The C-V
sweep can be a full sweep from inversion to accumulation, so that a flat band voltage can be
calculated by quantum mechanical modeling.
However, a faster and easier way is to do the voltage sweep in a relatively small
voltage range around an estimated or pre-determined flatband capacitance. The flatband
84
voltage is then extracted from the C-V data. For definiteness we assume that the change in
the flatband voltage shift is due to interface trapped charge located at the gate stack/substrate
interface. The trapped charge, ∆Nt, was calculated using:
fbox
t Vq
CN ∆−=∆ (5.4)
based on measured ∆Vfb, and Cox is the gate stack capacitance. ∆Nt was then plotted versus
time or injected charge, Qinj.
Trapped charge calculated from the change in flat band voltage is an approximation
of the charge located in the insulator structure. However, since charge can be generated in
places other than at the silicon-insulator interface, stress and C-V measurements only give a
rough estimate of how much is trapped due to injected charge.
This measurement technique has the advantage of being simple and direct. It
measures the effect of trapped charges from the C-V curve shift along the voltage axis as a
function of injected charges. The stress was done with a positive polarity at different voltages
(calculated by the NCSU CVC model) in order to keep the electric field strength constant at 6
MV/cm in all samples. Substrate injection was done on W/L = 20/20 µm (4E-6 cm2)
transistors with source/drain connected to the substrate. However, it is essential to avoid
relaxation of trapped charges during the stress cycle. If trapped charges de-trap too fast, some
of the trapped charges may be lost during switching between the stress and C-V
measurements. Minimizing the switching time is the key to success in this measurement.
Another drawback with C-V is that it measures the combination of traps initially in the film
85
in addition to those created later by the stress.
5.3.2 Stress/I-V Measurement
Stress/I-V measurement is similar to stress/C-V measurement except that an MOS transistor is used
as the DUT. During stress, the source, drain, and substrate terminals of the MOSFET are grounded;
stress is only applied on the gate dielectric. After stress, an Id-Vg test is performed, and the key
parameters, such as threshold voltage (Vt) and channel transconductance can be extracted. Plotting
the shift of those parameters as a function of injected charge makes it possible to obtain the trapped
charge density also. The advantage of this method is that it requires only I-V measurements without
the need for a switching matrix. This would avoid or significantly reduce charge relaxation effects.
This is particularly true if stress is done under operating polarity, eliminating the need for stress
polarity reversal, a major source of de-trapping. However, modeling work is required to interpret the
data.
Figure 5.12 is an example of voltage waveforms applied to an MIS capacitor in one
stress cycle that includes stress, C – V, and I – V measurements. A forward and backward C
– V sweep (center waveform in Figure 5.12) might be used to uncover any hysteresis effect
in the high-κ dielectric film.
86
switch matrix connectionV
Time
stress CV with
forward & backward voltage sweep
Optional IV
switch matrix connection
switch matrix connection
stress CV with
forward & backward voltage sweep
Optional IV
switch matrix connection
stress CV with
forward & backward voltage sweep
Optional IV
connectionswitch matrix
connectionV
Time Figure 5.12. Waveform of the applied voltage versus time for a “stress and sense” measurement.
5.3.3 Application of the Stress/C-V Measurement
Figure 5.13 illustrates results the interspersed C – V measurements around the flatband
voltage where the bi-directional sweep shows an overall shift to the right demonstrating
negative trapped charge and a hysteresis effect that widens as the stress duration increases on
a 3 nm physically thick ALD HfO2 film. The inset illustrates the location where the C – V
measurements were taken on the transistor. The noise seen in Figure 5.14 suggests an
unstable extraction of ∆Vfb based on C – V traces being so close together. The
instrumentation must be switched from stress to C – V measurement, so a voltage
discontinuity appears at the DUT terminals during the switching time. This voltage
discontinuity results in relaxation of trapped charges from trapping centers. If so, the C – V
measurement afterwards would indicate a smaller flat-band voltage shift due to fewer trapped
charges. Therefore, the switching time between instruments must be minimized. Another
87
example of this methodology is demonstrated in Figures 5.15 and 5.16. In this instance, a
3.5 nm physically thick MOCVD hafnium silicate (20% SiO2) was subjected to similar stress
measurement conditions. The Vfb again shifts to the right suggesting substrate injected
electron trapping (Figure 5.15). Notice the larger ∆Vfb shifts demonstrating a larger ∆Nt
quantity compared to the ALD HfO2 film (Figure 5.16). The trapped charge seems to be
retained longer in this MOCVD gate stack. Another important issue to include here is that
the interspersed C – V measurements are collected around the flatband condition which is
close to the discharge voltage of –1 V previously identified in Section 5.2.1.2.
ALD HfO2ALD HfO2
Voltage [V]-1.00 -0.95 -0.90 -0.85 -0.80 -0.75 -0.70 -0.65
Cap
acita
nce
[F]
3e-12
4e-12
4e-12
5e-12
5e-12
5e-12
6e-12Initial CV CV After Stress1 After Stress9 CV After Stress18
Voltage [V]-2 -1 0 1 2
Cap
acita
nce
[F]
0.0
1.0e-12
2.0e-12
3.0e-12
4.0e-12
5.0e-12
6.0e-12
7.0e-12
Positive Vstress
Initial Data for NCSU CVC
ALD HfO2
ALD HfO2ALD HfO2
Voltage [V]-1.00 -0.95 -0.90 -0.85 -0.80 -0.75 -0.70 -0.65
Cap
acita
nce
[F]
3e-12
4e-12
4e-12
5e-12
5e-12
5e-12
6e-12Initial CV CV After Stress1 After Stress9 CV After Stress18
Voltage [V]-2 -1 0 1 2
Cap
acita
nce
[F]
0.0
1.0e-12
2.0e-12
3.0e-12
4.0e-12
5.0e-12
6.0e-12
7.0e-12
Positive Vstress
Initial Data for NCSU CVC
ALD HfO2
ALD HfO2ALD HfO2
Voltage [V]-1.00 -0.95 -0.90 -0.85 -0.80 -0.75 -0.70 -0.65
Cap
acita
nce
[F]
3e-12
4e-12
4e-12
5e-12
5e-12
5e-12
6e-12Initial CV CV After Stress1 After Stress9 CV After Stress18
Voltage [V]-2 -1 0 1 2
Cap
acita
nce
[F]
0.0
1.0e-12
2.0e-12
3.0e-12
4.0e-12
5.0e-12
6.0e-12
7.0e-12
Positive Vstress
Initial Data for NCSU CVC
ALD HfO2
Figure 5.13. Interspersed C-V measurements (inversion to accumulation to inversion) taken around the Vfb value after each Vstress cycle for ALD HfO2. Positive flatband shift is evident suggesting negative trapped charge from the substrate as well as a widening hysteresis effect after stresses. Inset: the region in theC-V curve where the data was measured.
88
Injected Charge, Qinj [-C/cm2]
0.001 0.01 0.1 1 10∆Tr
appe
d C
harg
e D
ensi
ty, ∆
Nt [
#/cm
2 ]
-1.2e+11
-1.0e+11
-8.0e+10
-6.0e+10
-4.0e+10
-2.0e+10
0.0
O3/ALD HfO2 "thin"/N2 SI
Figure 5.14. Trapped charge, ∆Nt, vs. Qinj, calculated from Vfb shift, ∆Vfb, with respect to the initial value. The first point corresponds to ∆Nt after the first stress and so on. The noise here suggests an unstable extraction of based on the C – V up-sweeps being so close together.
-0.95 -0.90 -0.85 -0.80 -0.75 -0.70
4.20E-012
4.40E-012
4.60E-012
4.80E-012
5.00E-012
5.20E-012
5.40E-012
5.60E-012
5.80E-012
6.00E-012
6.20E-012
Cap
acita
nce
[F]
Voltage [V]
Initial CV CV after stress1 CV after stress5 CV after stress12 CV after stress19
(+) Vstress
Substrate InjectionMOCVD Hf Silicate
Figure 5.15. Interspersed C-V measurements (inversion to accumulation to inversion) taken around the Vfb value after each Vstress cycle for MOCVD Hf silicate. Positive flatband shift is evident suggesting negative trapped charge from the substrate as well as a widening hysteresis effect after stresses. Notice the larger Vfb shift compared to the ALD HfO2 (Figure 5.13)
89
0.1 1 10 100-9.00E+011
-8.00E+011
-7.00E+011
-6.00E+011
-5.00E+011
-4.00E+011
-3.00E+011
-2.00E+011
∆Tr
appe
d C
harg
e D
ensi
ty, ∆
Nt [
#/cm
2 ]
Injected Charge, Qinj [-C/cm2]
Substrate Injection MOCVD Hf Silicate
Figure 5.16. Trapped charge, ∆Nt, vs. Qinj, calculated from Vfb shift, ∆Vfb, with respect to the initial value. The first point corresponds to ∆Nt after the first stress and so on. Notice the larger quantity of trapped charge due to more pronounced Vfb shift as compared to ALD HfO2.
5.4 Charge Pumping
Since charge trapping in the high-κ results in degraded mobility, charge trapping
measurements were taken. Charge-pumping (CP) measurements are widely used to
characterize interface state densities in MOSFET devices [6]. This type of measurement is
very effective because accurate assessment and correction for the gate leakage is possible for
thin gate materials that have relatively large gate leakage [7, 8]. The mean interface trap
density within an energy range ( itD ) is calculated by:
90
EqAfI
D cpit ∆
= (5.5)
or
qAfI
N cpit = (5.6)
where Icp is the measured charge-pumping current, q is the fundamental electronic charge, A
is the area, f is the frequency, and ∆E is the difference between the inversion Fermi level and
the accumulation Fermi level. Nit is the trap density measured without determination of ∆E.
The conventional type of charge-pumping measurement involves the measurement of the
substrate current while applying a string of voltage pulses of fixed amplitude, rise time, fall
time, frequency, and duty cycle to the gate of the transistor. The measured substrate current,
Icp, is actually a recombination current as the voltage pulses swing the device back and forth
91
A
S D
G tr tf
VaVbase
Vtop
(a)
Vfb
Vt
Icp
Vbase
Icp
Vtop(b)
Fixed-Amplitude (FA) CP Variable-Amplitude (VA) CP
A
S D
G tr tf
VaVbase
Vtop
(a)
A
S D
G tr tf
VaVbase
Vtop
A
S D
G tr tf
VaVbase
Vtop
tr tf
VaVbase
Vtop
(a)
Vfb
Vt
Icp
Vbase
Icp
Vtop(b)
Fixed-Amplitude (FA) CP Variable-Amplitude (VA) CP
Vfb
Vt
Icp
Vbase
Icp
Vtop(b)
Fixed-Amplitude (FA) CP Variable-Amplitude (VA) CP
Figure 5.17. Schematic of the charge pumping measurement where (a) shows the measurement conFiguration and (b) shows the measurement and resulting Icp for FA CP (left) and VA CP (right).
between accumulation and inversion. As the transistor goes into inversion, electrons from
the source and drain fill interface traps. As the device goes back into accumulation,
untrapped electrons are released to the source and drain. The trapped electrons recombine
with majority holes to create Icp. Maximum exchange occurs when the device swings
through flatband and the threshold voltage. The source, drain, and body are tied to ground
92
(Figure 5.17a). The gate bias pulse can be done with a fixed-amplitude (FA) variable base
sweep or with a fixed-base variable amplitude (VA) sweep. In the FA CP measurement, the
amplitude and pulse shape are fixed while sweeping the base voltage (Figure 5.17b). At each
base voltage step, substrate recombination current can be measured and plotted against base
voltage (ICP vs. Vbase). The interface trap density ( itD , Nit) as a function of band bending can
then be extracted from the charge-pumping current if the ∆E is known or simply calculated
as Nit. In the VA sweep, the base voltage and pulse shape are fixed with step changes in
voltage amplitude (Figure 5.17b). The information obtained is similar to that extracted from
FA CP; however, ICP vs. Vtop is plotted. These CP measurements can also be performed at
different frequencies, so that a frequency response of the traps can be obtained. For high-κ
gate stack structures, VA CP technique can also quantify the bulk trapped charge (Nt,) as:
qAfI
N cpt = (5.7)
because trapped charge farther into the gate stack can be electrically sensed [2].
Demonstration of FA CP and VA CP can be seen in Figure 5.18. In the case of FA CP,
which examines the substrate interface with the dielectric stack, low interface state densities
are demonstrated at different frequencies, whereas VA CP illustrates the frequency
dependence. As frequency decreases, the ability to access trap sites deeper in the high-κ
stack increases creating a higher trap density compared to higher frequencies. At a lower
frequency, electrons have more time to inject farther into the bulk trapping sites as well as
93
release from those sites to participate in the measured recombination current (Icp). A SiO2
reference is shown for comparison. Because of the attributes of VA CP, it can be used for
process characterization. Figure 5.19 illustrates how this relatively quick measurement can
be used to evaluate a Hf silicate that experienced N2O PDAs at 700ºC and 800ºC where the
800ºC PDA shows flatter Nt – Vtop curves suggesting less trapping for this case. This is
attributed to an increase in the interfacial oxide thereby increasing the tunneling distance to
traps in this Hf silicate gate stack. Details of this are explained in chapter 6.
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0109
1010
1011
1012
Variable Amplitude CPVbase = -1 V
Vtop = -1 to 2 Vtr, tf = 100ns
Chem Ox interface, 3 nm HfO2, N2 600oC PDA
1 MHz 100 kHz 10 kHz
Nit,
Nt [
#/cy
cle*
cm2 ]
Vbase [V] or Vtop [V]
Fixed Amplitude CPVamp = 1.2 V
Vbase = -1.5 to 0 Vtr, tf = 100ns
nFET W/L=10/1µm
SiO2 at 100 kHz
Figure 5.18. Examples of fixed and variable amplitude charge pumping to assess interface and bulk trapping, respectively. SiO2 sample is shown for comparison.
94
-1.0 -0.5 0.0 0.5 1.0 1.5109
1010
1011
1012 Chem Ox interface, 3.5 nm HfSixOy, 700oC/800oC N2O PDA
nFET W/L = 10/1 µm
Vbase = -1.0VNt [
#/cy
cle*
cm2 ]
Vtop [V]
1 MHz N2O 800oC 100 kHz N2O 800oC 10 kHz N2O 800oC 1 MHz N2O 700oC 100 kHz N2O 700oC 10 kHz N2O 700oC
Figure 5.19. An example of using variable amplitude charge pumping as a process monitor for experimental split designs illustrating the effect of an increased temperature for an N2O PDA has reduced the amount of measured Nt.
5.5 Fast Transient Charge Trapping Technique
In order to evaluate charge-trapping phenomena at faster measurement times, the fast
transient pulsed Id-Vg measurement is required. Using a digital oscilloscope, the gate and
drain voltages are simultaneously recorded (5000 data points). The measurement
conFiguration is represented in Figure 5.19 which illustrates the nFET in an inverter circuit
where Id is expressed as
95
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛ −⋅=
L
DDD
D
DDDd R
VVVVVI (5.8)
where VDD is 100 mV, VD is the voltage recorded at the drain of the nFET, and RL is the load
resistance. Measurements were done as outlined in [3] with tr, tf, and the pulse width (PW)
values equally set. For the W/L = 10/1 µm transistor, the load resistance, RL, is 330 Ω. Each
FT single pulse measurement started and ended at –1 V with the top of the pulse taken to 1,
1.5, 2, and 2.2 V. The difference measured between the Id-Vg curves generated by the up and
down swing of Vg reflects the effect of the charge trapping (i.e., ∆Vt). Figure 5.20 illustrates
representative single pulse Id-Vg characteristics for a MOCVD Hf silicate (20% SiO2). The
Vt difference is extracted at 50% of the maximum Id current. Another approach is to plot Id
versus time as demonstrated in Figure 5.21. In a plot such as this, the degradation in drive
current over time can be seen. Note that the vertical drop at Vg = 2.5 V of the Id – Vg curve
(Figure 5.20) is associated with the ‘droop’ at the top of the Id – time current pulse (Figure
5.21).
96
DigitizingO-scope
PulseGenerator
VDD
VD
RL
Vg
DigitizingO-scope
PulseGenerator
VDD
VD
RL
Vg
Figure 5.20. The transistor is used in an inverter circuit with the gate receiving a single pulse from the pulse generator. The voltage is measured at the transistor drain and converted to drain current because the load resistance value is known.
0.0 0.5 1.0 1.5 2.0 2.5 3.00
50
100
150
200
250
300
350 Chem Oxide interface, 4.5 nm HfO2, NH3 700oC PDA
tf
tr
tftr
PW
Dra
in C
urre
nt [µ
A]
Gate Voltage [V]
Vg = -1 to 2.5 VPW = 100 µs
tr, tf = 5µs
PW∆Vt
max Id
Figure 5.21. Example data of the pulsed Id – Vg where ∆Vt is measured at 50% of the maximum Id on a W/L = 10/1 µm transistor.
97
0 50 100 150 200 2500
50
100
150
200
250
300
350 Chem Oxide interface, 4.5 nm HfO2, NH3 700oC PDA
PW = Pulse Width
Vg = -1 to 2.5 VPW = 100 µs
tr, tf = 5µs
Dra
in C
urre
nt [µ
A]
Time [µs]
tftr
PW
tr tf
Figure 5.22. Example data of the pulsed Id versus time on a W/L = 10/1 µm transistor where the ‘droop’ at the top is associated with the drop of pulsed Id – Vg at Vg = 2.5 V.
5.6 Comparison of Charge Trapping Measurement Techniques
The charge trapping measurement approaches presented in Sections 5.3 – 5.5 were compared
and analyzed to address similarities and differences. CVS with interspersed C – V, variable
amplitude charge pumping, and fast transient single pulse measurements were taken on
MOCVD hafnium silicate (20% SiO2) films of various thickness (4.5, 4, 3.5, and 2.5 nm)
deposited on a chemical interfacial oxide of ~1 nm. As verification of the variable physical
thickness of the Hf silicate, a graph of EOT vs high-κ physical thickness illustrates a κ-value
98
of ~12 which is typical for 20% SiO2 incorporated Hf silicate films [9], and an interfacial
oxide of 0.9 nm (Figure 5.22).
0 1 2 3 4 5 60.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
EOT
[nm
]
Nominal Physical Thickness [nm]
HfSixOy (20% SiO2)
dielectric constant (κ) ~ 12IL oxide thickness = .9 nm
Figure 5.23. EOT versus nominal physical thickness for verification of scaling and extraction of κ ~ 12 and 0.9 nm interfacial oxide for Hafnium silicate (20% SiO2) gate stacks.
In an effort to standardize the measurement for a self-consistent comparison of the
measurement techniques, Vstress was chosen to be 2 V (substrate injection condition) on nMIS
transistors. Another standardization for the correlation is that the trapped change is assumed
to be at the silicon substrate interface. This assumption allows the trapped charge, Nt, to be
defined as:
99
Vq
CN oxt ∆= (5.9)
where ∆V is the measured voltage shift, ∆Vfb or ∆Vt.
Constant Voltage Stress with C – V was done where the trap densities were extracted
from the shifted Vfb referenced to the initial after the first stress (~0.16 sec) and after the last
stress (~205 sec). In addition, VA CP pulse shape conditions were set to mimic the single
pulse as close as possible.
The fast single pulse measurement and VA CP conditions were set to imitate each
other as close as possible. In each case, the rise and fall times were set to 100 µs with the
pulse width set to 100 µs. For VA CP, this equates to a measurement frequency of 2.5kHz
with tr, tf = 100 µs and 50% duty cycle. The results of the comparison are shown in Figure
5.23. The fast transient pulse measurements show the largest Nt values compared to the other
approaches. This is attributed to the measurement’s ability to resolve the fast rise, charging,
and fall times under substrate injection conditions. The VA CP Nt values are on the same
order of magnitude as the single pulse measurement, but it is about four times less. This
could be attributed to the fact that charge pumping measures a recombination current of
repetitive pulses that might result in lower Nt values because of an inability to sense all that
has been trapped. So, in essence, the two techniques measure different phenomena;
therefore, yielding different results. The “stress and sense” approach provides significantly
lower Nt values in both cases (.16 sec and 205 sec). As stated earlier, charge relaxation
occurs when switching between instruments and measuring around Vfb which has been
100
shown to be a discharge condition as demonstrated in Figure 5.24. This illustrates an example
of this discharge condition for these Hf silicate stacks, similar to the hybrid stacks illustrated
in Figure 5.7. This approach could obviously be improved by monitoring threshold voltage
shift with CVS and interspersed Id-Vg measurements [10] instead. Here there is no need to
switch to a C – V meter and the measured quantity, Vt, is not near the discharge condition.
4.5 nm 4 n
m3.5
nm2.5
nm
1011
1012
1013
20% SiO2 HfSixOy Nominal Physical Thickness
Vstress = 2V
Nt a
t Si I
nter
face
[#/c
m2 ]
Single Pulse @ tr, tf, PW = 100µs Var Amp CP @ 2.5 kHz w/ tr, tf = 100µs CVS with CV @ 0.16 sec CVS with CV @ 205 sec
TooLeaky
Figure 5.24. Comparison results showing that fast transient measurement extracts the largest trapped charge density followed by variable amplitude charge pumping and then the “stress and sense” approach has the least which is expected due to bias relaxation and Vfb extraction done near the discharge condition.
101
-1.0 -0.5 0.0 0.5 1.0 1.5 2.00
1
2
3
4
5
Cap
acita
nce
[pF]
Gate Voltage [V]
-1 to 1 V 1 to -1 V -1 to 1.5 V 1.5 to -1 V -1 to 2 V 2 to -1 V
C-V Sweep
Hf Silicate (20% SiO2)
Freq = 100 kHz
Figure 5.25. Bi-directional C – V sweeps illustrating full charge recovery when a C – V accumulation bias of –1 V (identical up-sweeps) is used and increasing substrate injected electron trapping as C – V bias into inversion is increased.
5.7 Fast Transient Mobility Extraction
The fast transient mobility extraction algorithm [9] demonstrates the impact of the trapped
charge on the mobility of high-κ gate stacks. The procedure uses charge pumping and pulsed
Id – Vg measurements. CP was used to obtain the inversion charge, Qinv, and the rise time of
the fast transient pulsed Id-Vg values was used to calculate the channel conductance, gd:
d
dd V
Ig = (5.10)
102
where Id is the drain current and Vd is the voltage applied to the drain.
For the calculation of the effective mobility, µeff, one uses:
inv
deff
QL
Wg
⎟⎠⎞
⎜⎝⎛
=µ (5.11)
where W and L are the width and length of the transistor, respectively. Using the pulsed Id-
Vg and inversion charge pumping as outlined in [9] permits estimation of the free-carrier
mobility. The CP measurement involves measuring a long channel device using fast rise and
fall times (e.g., 5 µs) to take advantage of the geometric effect. This measures inversion
charge as well as trapped charge because a long channel device with fast rise and fall times
does not allow the inversion charge to release back to source and drain (geometric effect),
therefore becoming part of the measured Icp. The VA CP technique explained earlier
measures the trapped charge, Nt and subtracting this from the long channel measurement
yields the free inversion carriers, Ninv. Figure 5.25 illustrates the results of this approach for
an MOCVD Hf-based gate stack. The Figure clearly demonstrates an increase in the peak
and high field mobility with the high field mobility being quite close to the universal
mobility when using the mobility extraction approach. Thus one can conclude that, for this
particular gate stack, most of the observed mobility degradation is associated with charge
trapping effects which shift the flatband and threshold voltages of the device.
103
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.60
50100150200250300350400450500
0.0 0.5 1.0 1.5 2.00
20406080
100120140
MOCVD HybridnFET W/L = 10/1µm
Vd = 40mV
Pulsed Id-Vg (100kHz) DC Id-Vg
Dra
in C
urre
nt [µ
A]
Gate Voltage [V]
MOCVD Hybrid Stack
DC Mobility Pulsed Mobility UniversalEf
fect
ive
Mob
ility
[cm
2 /V*s
ec]
Effective Field [MV/cm]
Figure 5.26. Comparison of electron mobility from pulsed/CP methodology and conventional split C-V for a MOCVD hybrid stack. Inset: comparison of pulsed Id-Vg to DC Id-Vg for the mobility shown.
5.8 Summary
In summary, C-V hysteresis is a good approach for qualitative understanding of the charge
trapping that occurs in high-κ dielectrics. The “stress and sense” approach loses trapped
charge in the measurement of ∆Vfb while variable amplitude CP could be an excellent
process-monitoring tool for measuring the trapped charge. Finally, the fast transient
technique is an excellent benchmark in measuring and quantifying trapped charge in high-κ
gate sacks.
104
5.9 References
[1] S. Zafar, A. Callegari, V. Narayanan, and S. Guha, "Impact of moisture on charge trapping and flatband voltage in Al2O3 gate dielectric films," Applied Physics Letters, vol. 81, pp. 2608-2610, 2002.
[2] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics," IEEE Electron Device Letters, vol. 24, pp. 87-89, 2003.
[3] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, "Characterization of the Vt-instability in SiO2/HfO2 Gate Dielectrics," presented at International Reliability Physics Symposium, Dallas, Texas, 2003.
[4] J. R. Hauser and K. Ahmed, "Characterization of Ultrathin Oxides Using Electrical C-V and I-V Measurements," presented at Characterization and Metrology for ULSI Technology: 1998 International Conference, 1998.
[5] Y. Zhao, C. D. Young, and G. A. Brown, "How to Electrically Qualify High-k Gates," in Semiconductor International, vol. 26, 2003, pp. 51-58.
[6] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De-Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Transactions on Electron Devices, vol. ED-31, pp. 42-53, 1984.
[7] P. Masson, J. L. Autran, and J. Brini, "On the tunneling component of charge pumping current in ultrathin gate oxide MOSFETs," IEEE Electron Device Letters, vol. 20, pp. 92-4, 1999.
[8] S. S. Chung, S.-J. Chen, C.-K. Yang, S.-M. Cheng, S.-H. Lin, Y.-C. Sheng, H.-S. Lin, K.-T. Hung, D.-Y. Wu, T.-R. Yew, S.-C. Chien, F.-T. Liou, and F. Wen, "A Novel and Direct Determination of the Interface Traps in Sub-100nm CMOS Devices with Direct Tunneling Regime (12-16A) Gate Oxide," presented at VLSI Technology Symposium, Honolulu, Hawaii, 2002.
[9] G. Lucovsky, B. Rayner, Z. Yu, and J. Whitten, "Experimental determination of band offset energies between Zr silicate alloy dielectrics and crystalline Si substrates by XAS, XPS and AES and ab initio theory: a new approach to the compositional dependence of direct tunneling currents," presented at IEEE International Electron Devices Meeting. 8 11 Dec. 2002 San Francisco, CA, USA, 2002.
[10] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, "Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks," Journal of Applied Physics, vol. 93, pp. 9298-9303, 2003.
105
[11] A. Kerber, E. Cartier, L. A. Ragnarsson, M. Rosmeulen, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, and G. Groeseneken, "Direct Measurement of the Inversion Charge in MOSFETs: Application to Mobility Extraction in Alternative Gate Dielectrics," presented at VLSI Technology Symposium, Kyoto, Japan, 2003.
106
6 CHARGE TRAPPING AND MOBILITY DEGRADATION IN MOCVD HAFNIUM SILICATE GATE DIELECTRIC STACK STRUCTURES
6.1 Introduction
In order to meet the International Technology Roadmap for Semiconductors (ITRS),
requirements for Equivalent Oxide Thickness (EOT) and gate leakage current, the SiO2 gate
dielectric will need to be replaced by a higher dielectric constant material [1]. Hafnium-based
gate dielectrics are being widely investigated as a replacement for SiO2 [2, 3]. In this chapter,
investigations of interfacial and bulk high-κ properties on device performance (i.e., mobility)
have been carried out [4, 5] using 20% SiO2 hafnium silicate gate dielectrics. Samples of this
composition were subjected to various post deposition anneal (PDA) ambients and
temperatures to determine anneal effects on charge trapping and electron mobility
characterized by conventional DC measurements, fixed-amplitude variable base (FA) and
fixed-base variable amplitude (VA) charge pumping (CP), Secondary Ion Mass Spectroscopy
(SIMS), and fast transient (FT) measurements.
107
6.2 Process Flow and Experiment
The process flow used to fabricate planar NMOS transistors was similar to a typical self-
aligned, polysilicon gate process flow with Ti-salicide formation after source/drain activation
(1000°C, 10 sec) as outlined in Chapter 4. Hf silicate gate dielectrics were deposited on
ozone (O3) cleaned substrates [3]. The MOCVD Hf silicate was deposited on the chemical
oxide interfacial layer at two chamber pressures (2 Torr and 4 Torr) such that 20% SiO2 was
incorporated into a 3.5 nm physically thick film. Following the gate dielectric deposition,
PDAs were performed in NH3, N2, or N2O ambients for 60 seconds at 700°C and compared
with N2 and N2O PDAs for 60 seconds at 800°C. Table I shows these process combinations.
Physical and electrical characterization followed device fabrication.
6.3 Experimental Results
6.3.1 SIMS Analysis
SIMS analysis shows differences in the position of the Si substrate signal indicating the N2O
800°C film is thicker than the NH3 film (Figure 6.1). The oxygen profiles are consistent with
this thickness difference. The Si plateau is common for profiles through SiO2 layers and is
seen only in the N2O sample. In addition, Figure 6.1 indicates that the N incorporation in the
NH3 sample is greater than the N2O sample. These results are useful in understanding the
electrical characterization results presented herein.
108
0 5 10 15 20
101
102
103
104
N
O
Si
PDAGray: NH3 700oC
Black: N2O 800oC
Cou
nts
per S
econ
d
Depth [nm]
Figure 6.1. SIMS shows position differences in the Si and O signals indicating the N2O 800°C film is thicker than the NH3 film. Higher nitrogen incorporation in the NH3 PDA is also evident when compared to the N2O PDA.
6.3.2 DC Measurements
Table 6.1 summarizes DC characteristics of the gate stacks evaluated with data extracted
from W/L = 20/20 µm transistors using the Keithley 4200 SCS. Initially, 100 kHz C-V, gate
leakage (Jg), and DC Id-Vg data were collected on nMOS transistors. The NCSU CVC model
[6] was invoked to extract Vfb and EOT from the 100kHz C-V data. As shown in the table,
PDA type and temperature affect the extracted EOT with the NH3 PDA producing the lowest
EOT while N2O PDAs produce the highest EOTs as expected. Next, conventional split C-V
[7] and NCSU Mob2d [8] mobility extractions were carried out for comparison on these
samples. Mobility characteristics obtained by split C-V and Mob2d are in good agreement as
109
shown in the example in Figure 6.2. In addition, the inset shows an example of conventional
C-V, split C-V, and DC Id-Vg. Figure 6.3 illustrates a comparison of peak and high field (1.3
MV/cm) electron mobility for 2 Torr and 4 Torr silicates with various PDAs. As can be seen,
silicates deposited at 4 Torr show significantly higher electron mobilities than 2 Torr
deposited silicates. NH3 700°C and N2 800°C PDAs show improved peak and high field
mobility values while retaining an ~ 1.6 nm EOT when compared to the N2 700°C PDA.
Increased peak and high field mobility values are obtained on N2O PDAs, which is attributed
to an increased interfacial oxide (EOT > 1.8 nm) [4] confirmed by SIMS. However, these
values are lower than the universal electron mobility. This mobility degradation has been
attributed to a number of mechanisms resulting in charge trapping (i.e., inversion charge loss)
in the high-κ [5].
Table 6.1. 20% SiO2 Hf silicate gate stacks under evaluation with parameters extracted from NCSU CVC [6] and DC measurements.
MOCVD HfSiO PDA EOT [nm] Vfb [V]
Jg (Vfb-1)
[-A/cm2]
N2 700°C 1.81 -0.847 2.32E-03
N2O 700°C 1.98 -0.848 7.02E-04 2 Torr 3.5nm
20% SiO2
N2O 800°C 2.29 -0.854 1.12E-04
NH3 700°C 1.62 -0.837 1.41E-02
N2 700°C 1.73 -0.817 1.28E-02
N2O 700°C 1.84 -0.797 5.59E-03
N2 800°C 1.68 -0.814 1.57E-02
4 Torr 3.5nm 20% SiO2
N2O 800°C 2.11 -0.824 6.39E-04
110
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
0
50
100
150
200
250
-2 -1 0 1 20
1
2
3
4
5
6
7 Conventional CV Split CV
Freq = 100kHz Vd = 40mV
nFET W/L = 20/20 µm
Cap
acita
nce
[pF]
Gate Voltage [V]
0
2
4
6
8
10
12
14
Id
Drain C
urrent [µA]
Universal
Split CV
NCSU Mob2d
4T Hf Silicate/NH3 700oC PDA
Effe
ctiv
e M
obili
ty [c
m2 /V
*sec
]
Effective Field [MV/cm] Figure 6.2. Example of conventional electron mobility extraction (Split CV and NCSU Mob2d). Inset shows CV, split CV, and DC ramp Id-Vg used.
1.6 1.8 2.0 2.275
100
125
150
175
200
225
250
275
1.6 1.8 2.0 2.2
High Field Mobilityµeff @ 1.3 MV/cm
Peak Mobilityµeff @ Peak
N2 700oCN2O 700oCN2O 800oC
NH3 700oC N2 800oC
Effe
ctiv
e M
obili
ty [c
m2 /V
*sec
]
EOT [nm]
open symbols: 4T Silicateclosed symbols: 2T Silicate
Figure 6.3. Comparison of 2 Torr v 4 Torr silicate peak and high field (1.3 MV/cm) electron mobilities with various PDAs (where 4 Torr deposited material mobilities are higher).
111
6.3.3 Charge Pumping
Since charge trapping in the high-κ results in degraded mobility, charge trapping
measurements were taken. Fixed-Amplitude CP was done with a FA of 1.2 V, with rise (tr)
and fall (tf) times equal to 100 ns on W/L = 10/1 µm transistors. Variable-Amplitude CP had
the same tr and tf with a fixed base level of –1 V and a variable amplitude stepped at 50 mV
to 2 V. A base voltage of –1 V has been shown to exhibit a discharge condition [9] which
was also the case for the gate stacks measured. Figure 6.4 illustrates examples of FA and VA
CP for the NH3 700°C PDA where low interface state densities are seen at different
frequencies, although an increase in Nt is shown for VA CP as the frequency decreases since
a ‘slower’ pulse allows trap filling deeper into the gate stack. Figure 6.5 shows a CP
comparison of 2 Torr versus 4 Torr for interface (1 MHz) and bulk trapping (10 kHz at a
stress field of 6 MV/cm). The left pane shows Nit values of 1-3E10/cycle·cm2 for all samples.
The right pane illustrates Nt values where 2 Torr silicates are higher than or similar to the 4
Torr samples for the same PDA. This result suggests that the degradation in the extracted
mobility is impacted by the amount of trapped charge since the 2 Torr samples have lower
peak and high field mobility values. The 700°C PDAs exhibit higher Nt values, and the
N2O 800°C anneal have the lowest values. By varying the duty cycle (modulating the pulse
signal width), the charge time can be matched while allowing different discharge times.
Figure 6.6 shows the effect of a longer discharge time (inset) where higher trap densities are
measured, suggesting a longer time to de-trap than to trap (10 kHz 5% is somewhat higher
than 100 kHz 50%).
112
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0109
1010
1011
1012
Variable Amplitude CPVbase = -1 V
Vtop = -1 to 2 Vtr, tf = 100ns
4 Torr with NH3 700oC PDA
1 MHz 100 kHz 10 kHz
Nit,
Nt [
#/cy
cle*
cm2 ]
Vbase [V] or Vtop [V]
Fixed Amplitude CPVamp = 1.2 V
Vbase = -1.5 to 0 Vtr, tf = 100ns
nFET W/L=10/1µm
Figure 6.4. Examples of fixed and variable amplitude charge pumping to assess interface and bulk trapping, respectively.
N2 700
C
N2O 70
0C
NH3 700
C
N2 800
C
N2O 80
0C0
1
2
3
All: 1-3x1010
Freq = 1 MHzFixed Amp. CP"Interface"Peak Nit value
Nit [
1011
/cyc
le*c
m2 ]
2T Silicate 4T Silicate
N2 700
C
N2O 70
0C
NH3 700
C
N2 800
C
N2O 80
0C
Freq = 10 kHz
Var. Amplitude CP "Bulk" Nt @ 6 MV/cm N
t [1011/cycle*cm
2]
Figure 6.5. Comparison of 2 Torr v 4 Torr interface (1 MHz) and bulk traps (10 kHz at a stress field 6 MV/cm) where 2 Torr 700°C PDAs trap the most and 2 Torr, 4 Torr N2O 800°C traps the least for the conditions illustrated.
113
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0109
1010
1011
1012
1013
50%
5%
x 100%Pulse WidthPeriod
Duty Cycle =
Period
Pulse Width
Time
SiO2
Si Substrate
Hi-κ
nFET W/L=10/1µmVbase = -1.0Vtr, tf = 100ns
Nt [
#/cy
cle*
cm2 ]
Vtop [V]
10kHz 50% Duty Cycle 10kHz 5% 100kHz 50% 100kHz 5% 1 MHz 50%
Figure 6.6. Duty cycle study: A higher trap density is achieved with longer discharge times suggesting more time is required to de-trap than to trap (10 kHz 5% is higher than 100 kHz 50%).
6.3.4 Fast Transient
Fast Transient (FT) Id-Vg (demonstrated in Chapter 5) was performed on the same devices to
examine the fast transient charge trapping of the 4 Torr silicate gate stacks [10]. Figure 6.7
illustrates representative single pulse Id-Vg characteristics for: a) NH3 700°C, b) N2 800°C,
and c) N2O 800°C PDAs where increased charge trapping is seen as bias goes further into
inversion. DC Id-Vg is shown for comparison where degradation due to charge trapping from
a slower measurement can be seen. In Figure 6.8a and Figure 6.8b, comparisons of ∆Vt at
different charging times for various PDA conditions using pulsed Id-Vg (Figure 6.7) to
determine ∆Vt at 50% of maximum Id are shown. Fast transient analysis shows the NH3 and
114
N2 800°C PDAs can have significant amount of trapped charge. The N2O 800°C annealed
gate stacks show reduced amounts of trapped charge due to increased interfacial layer
thickness that reduces the tunneling of electrons to the bulk silicate trap sites.
0.0 0.5 1.0 1.5 2.0 2.50
20
40
60
80
100
120
140
160
b)
N 2 8 00oC P DA
Dra
in C
urre
nt [µA
]
Gate Voltage [V]0.0 0.5 1.0 1.5 2.0 2.50
20
40
60
80
100
120
140
160
c)
N 2O 80 0oC PDA
Dra
in C
urre
nt [µA
]
Gate Voltage [V]
0.0 0.5 1.0 1.5 2.0 2.50
20
40
60
80
100
120
140
160
Vg Pulse Height -1 to 1 V -1 to 1 .5 V -1 to 2 V -1 to 2 .2 V
t r, PW, t f = 100µs
DC Id-Vg
NH3 700oC PDAnFET W/L = 10/1 µmVd = 40mV
Drai
n C
urre
nt [µA
]
Gate Voltage [V]
PW
t rt f
PW
tr tf
∆Vt
a)
Figure 6.7. Examples of pulsed Id-Vg characteristics showing increased charge trapping with increasing inversion bias for 100 µs rise, fall, and pulse width times. DC Id-Vg is shown for comparison.
115
10-6 10-5 10-4 10-3
10-3
10-2
10-1
10-3
10-2
10-1
Detection Limit
Vg = 1.5 V
∆
V t [V]
Charging Time [sec]
b)
a)Detection Limit
Vg = 2 V
∆V t [
V] NH3 700oC
N2 700oC
N2O 700oC
N2 800oC
N2O 800oC
Figure 6.8. Comparison of ∆Vt at different charging times for various PDAs using pulsed Id-Vg (Figure 9) to determine ∆Vt at 50% of the maximum Id for a) Vg = 2 V and b) Vg = 1.5 V.
6.3.5 Pulsed Id-Vg Mobility Extraction
The 4 Torr silicates were further studied to determine the impact of the trapped charge on the
mobility using the fast transient mobility extraction technique discussed in Chapter 5 [11].
Figure 6.9 shows “trap free” inversion charge compared with split CV, which includes the
trapped charge as well as the inversion charge. Comparisons of electron mobility from FT/CP
and DC ramp (see Figures 6.2 and 6.3) measurements for NH3 700°C and N2 800°C PDAs
are shown in Figure 6.10 and Figure 6.11. The insets illustrate a comparison of pulsed Id-Vg
116
to DC Id-Vg for the mobility values shown. Since the DC mobility extraction technique
includes trapped charge, Qinv is larger than it should be while the gd is degraded due to the
reduced DC Id (Figures 6.10 and 6.11 insets). Using the above methodology, a “trap-free”
Qinv for the “trap-free” gd produces a higher µeff. So, if transistors in logic circuits were able
to turn on and off at fast rates (i.e., high frequencies), high-κ gate dielectrics would be useful.
Unfortunately, some transistors in circuits could be in the “on” state for a relatively longer
time allowing for charge trapping to occur and, therefore, degrade the effective electron
mobility.
0.0 0.5 1.0 1.5 2.00
5
10
15 4T with NH3 700oC PDA
Nin
v, N
t [10
12/c
ycle
*cm
2 ]
Vgate or Vtop [V]
Split CV with trapped chargeInversion Charge Pumping:
100kHz Trap-Free inversion charge Trapped charge
Figure 6.9. "Trap free" inversion charge compared with split CV where trapped charge is not removed.
117
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80
50100150200250300350400450500
0.0 0.5 1.0 1.5 2.00
20406080
100120140
NH3 700oC PDAnFET W/L = 10/1 µm
Vd = 40mV
Pulsed Id-Vg (100kHz) DC Id-Vg
Dra
in C
urre
nt [µ
A]
Gate Voltage [V]
DC Mobility Pulsed Mobility Universal
Effe
ctiv
e M
obili
ty [c
m2 /V
*sec
]
Effective Field [MV/cm]
Figure 6.10. Comparison of electron mobility from pulsed/CP methodology and DC ramp (see Figures 2 and 3) measurements for NH3 700°C PDA. Inset: comparison of pulsed Id-Vg to DC Id-Vg for the mobility shown.
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80
50100150200250300350400450500
0.0 0.5 1.0 1.5 2.00
20
40
60
80
100
120
140
N2 800oC PDAnFET W/L = 10/1 µm
Vd = 40mV
Pulsed Id-Vg (100kHz) DC Id-Vg
Dra
in C
urre
nt [µ
A]
Gate Voltage [V]
DC Mobility Pulsed Mobility Universal
Effe
ctiv
e M
obili
ty [c
m2 /V
*sec
]
Effective Field [MV/cm]
Figure 6.11. Comparison of electron mobility from pulsed/CP methodolgy and DC ramp (see Figures 2 and 3) measurements for N2 800°C PDA. Inset: comparison of pulsed Id-Vg to DC Id-Vg for the mobility shown.
118
6.4 Summary
MOCVD 20% SiO2 Hf silicate deposited at 4 Torr with a chemical oxide interfacial layer
produces higher mobility values than 2 Torr silicates that were subjected to the same
processing. The N2O PDA increases the thickness of the interfacial oxide, and the NH3 PDA
incorporates more nitrogen according to SIMS. From CP, when the charge time is held
constant and the discharge time is increased by varying the duty cycle, the Nt values are
higher suggesting that more time is required to de-trap than to trap. With a 50% duty cycle of
a given frequency, fixed-amplitude CP and fixed-base variable amplitude CP show quite low
interface state trap densities (1-3E10/cycle·cm2) for a chemical oxide interfacial layer, and
large high-κ bulk trap densities (0.7-3E11/cycle·cm2). Using fast transient measurements and
analysis, NH3 700°C and N2 800°C PDAs exhibit significant amounts of trapped charge, but
DC mobility is higher in the peak and high field regime while retaining an ~1.6 nm EOT as
compared to the N2 700°C PDA. Furthermore, free-carrier mobility extractions for these two
anneals indicate that the “intrinsic” mobility, after correcting for the trapped charge, is quite
close to the universal electron mobility curve in the high field regime.
119
6.5 References
[1] International Technology Roadmap for Semiconductors, http://public.itrs.net, 2001.
[2] R. M. Wallace and G. Wilk, "High- κ gate dielectric materials," MRS Bulletin, vol. 27, pp. 192-7, 2002.
[3] Y. Kim, C. Lim, C. D. Young, K. Matthews, J. Barnett, B. Foran, A. Agarwal, G. A. Brown, G. Bersuker, P. Zeitzoff, M. Gardner, R. W. Murto, L. Larson, C. Metzner, S. Kher, and H. R. Huff, "Conventional Poly-Si Gate MOS-transistors With a Novel, Ultra-Thin Hf-oxide Layer," presented at VLSI Technology Symposium, Kyoto, Japan, 2003.
[4] M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, "Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-κ insulator: The role of remote phonon scattering," Journal of Applied Physics, vol. 90, pp. 4587-4608, 2001.
[5] T. Yamaguchi, R. Iijima, T. Ino, A. Nishiyama, H. Satake, and N. Fukushima, "Additional Scattering Effects for Mobility Degradation in Hf-silicate Gate MISFETs," presented at International Electron Device Meeting, Washington, DC, 2002.
[6] J. R. Hauser and K. Ahmed, "Characterization of Ultrathin Oxides Using Electrical C-V and I-V Measurements," presented at Characterization and Metrology for ULSI Technology: 1998 International Conference, 1998.
[7] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, "Charge accumulation and mobility in thin dielectric MOS transistors," Solid State Electronics, vol. 25, pp. 833-41, 1982.
[8] J. R. Hauser, "Extraction of experimental mobility data for MOS devices," IEEE Transactions on Electron Devices, vol. 43, pp. 1981-1988, 1996.
[9] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics," IEEE Electron Device Letters, vol. 24, pp. 87-89, 2003.
[10] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, "Characterization of the Vt-instability in SiO2/HfO2 Gate Dielectrics," presented at International Reliability Physics Symposium, Dallas, Texas, 2003.
[11] A. Kerber, E. Cartier, L. A. Ragnarsson, M. Rosmeulen, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, and G. Groeseneken, "Direct Measurement of the Inversion Charge in MOSFETs: Application to Mobility Extraction in Alternative Gate Dielectrics," presented at VLSI Technology Symposium, Kyoto, Japan, 2003.
120
7 CHARGE TRAPPING MODEL FOR MOCVD HAFNIUM-BASED GATE DIELECTRIC STACK STRUCTURES AND ITS IMPACT ON DEVICE PERFORMANCE
7.1 Introduction
In order to meet the International Technology Roadmap for Semiconductors (ITRS)
requirements for equivalent oxide thickness (EOT) and gate leakage current, the conventional
SiOxNy gate dielectric will need to be replaced by higher dielectric constant materials [1].
Hafnium-based dielectrics are being widely investigated as potential candidates for the gate
dielectric material [2, 3]. Threshold voltage instability and mobility degradation, however,
have been identified as significant issues for Hf-based materials [4-8]. To continue to address
these issues and those from the previous chapter, we investigated the electrical properties of
samples referred to as hybrid stacks (HfO2/Hf Silicate) of various thickness with respect to
charge trapping. The impact of charge trapping on device performance was characterized by
conventional DC measurements, fixed-amplitude (FA) variable base and fixed-base variable
amplitude (VA) charge pumping (CP) [6], Secondary Ion Mass Spectroscopy (SIMS), high
resolution Transmission Electron Microscopy (HRTEM), and fast transient (FT)
measurements [7, 8].
121
7.2 Process Flow and Experiment
Transistors were fabricated on 200 mm (100) p/p+ epitaxial wafers using a standard NMOS
process flow – self-aligned, a-Si gate and 1000°C, 10 sec source/drain activation. In this
study, MOCVD hybrid stacks were deposited on ozone (O3) cleaned substrates [3]. The
hybrid stack was formed by two consecutive depositions under vacuum conditions where an
HfO2 layer (of 1.5 nm, 2.0 nm, and 3.0 nm nominal thickness) was followed by a 1.5 nm
20% SiO2 Hf silicate layer (top Hf silicate layer improves high-κ/polysilicon interface,
Figure 7.1). All hybrid stacks received an NH3 post deposition anneal (PDA) at 700°C for 60
sec. A brief summary of the electrical results collected on the W/L=20/20 µm
30Å HfO2 20Å HfO2 15Å HfO2
15Å HfSixOy
15Å HfSixOy 15Å HfSixOy
30/15 Hybrid
Si SubstrateSiO2 IL 10Å
20/15 Hybrid 15/15 Hybrid
30Å HfO2 20Å HfO2 15Å HfO2
15Å HfSixOy
15Å HfSixOy 15Å HfSixOy
30/15 Hybrid
Si SubstrateSiO2 IL 10Å
20/15 Hybrid 15/15 Hybrid
Figure 7.1. Schematic representation of the gate stacks in Table I.
122
Table 7.1. Parameters extracted from NCSU CVC and DC measurements for MOCVD hybrid gate stacks [9].
ID 1st High - κ 2nd High - κ EOT [nm] Vfb [V] Jg (Vfb–1)
[-A/cm2]
1 HfO2 30 Å 1.45 -0.853 4.87E-03
2 HfO2 20 Å 1.36 -0.831 1.61E-01
3 HfO2 15 Å
HfSixOy 15 Å
1.39 -0.819 2.05E-01
transistors is presented in Table 7.1. The NCSU CVC model [9] was used to extract Vfb and
EOT from the C-V data. Conventional 100kHz split C-V [10] and NCSU Mob2d [11]
mobility extractions were also carried out on these samples. On short channel transistors
(W/L = 10/1 µm), fixed amplitude (FA) charge pumping (CP) and variable amplitude (VA)
CP were also performed to investigate the gate stack interface (Nit) and bulk (Nt) trapping,
respectively. Pulsed Id-Vg measurements were done on the same devices to examine the fast
transient characteristics of the hybrid stacks.
7.3 Results and Discussion
In an effort to characterize trapped charge in MOCVD hafnium-based gate dielectric stack
structures, the “hybrid” stack was subjected to physical and electrical analysis.
123
7.3.1 Physical Analysis
High Resolution Transmission Electron Micrograph (HRTEM) images were collected on the
hybrid stack samples. Figure 7.2 of the HRTEM images for the 30/15 and 15/15 hybrid
stacks shows a similar thickness of an interfacial oxide of 1 nm adjacent to the silicon
substrate. To investigate the hybrid stack further, Secondary Ion Mass Spectroscopy (SIMS)
was also done (Figure 7.3). The SIMS profiles done after the wet etch removal of the poly
electrode suggests that the 20/15 and 15/15 samples are quite similar.
30/15 Hybrid 15/15 Hybrid30/15 Hybrid 15/15 Hybrid
Figure 7.2. HRTEM images of the 30/15 (left) and 15/15 (right) hybrid stacks. Note that the interfacial oxide layer as about 1 nm in both samples.
124
2 4 6 8 100 2 4 6 8 10
100
101
102
103
104
105
(b)
HfO2 Signal
Depth [nm]
SiO2 Signal
30/15 Hybrid 20/15 Hybrid 15/15 Hybrid
Cou
nts
per S
econ
d
(a)
Figure 7.3. SIMS profiles of hybrid films following wet etch removal of the poly electrode where the 20/15 and 15/15 hybrid stacks are quite similar.
7.3.2 Electrical Analysis
7.3.2.1 DC Measurements
The effect of the high-κ physical thickness was initially investigated with conventional DC
characterization methodologies using the Keithley 4200 SCS. A brief summary of the
electrical results collected on W/L = 20/20 µm transistors is presented in Table 7.1. The
EOT and flatband voltage, Vfb, were extracted using NCSU CVC for CV measurements
taken at 100 kHz. The 30/15 hybrid has a larger EOT while the 20/15 and 15/15 hybrids
have lower and similar EOTs which seem to be supported by the physical analysis. For
125
mobility extraction, split CV and Id-Vg measurements were made. Figure 7.4 shows the
inversion capacitance, Cinv, where the thinner hybrids have a small decrease in the
capacitance equivalent thickness, CETinv, which is defined as:
invinv C
ACET ε= (7.1)
where ε is the dielectric constant of SiO2 (3.9·εo), and A is the area. Figure 7.5 shows Id-Vg
characteristics where it can be seen that the thickest high-κ stack has the lowest drive current.
Although the difference is subtle in the inversion capacitance since EOT values are similar, a
significant difference can be seen in the Id-Vg curves. This is mainly attributed to a lower
mobility (Figure 7.6). The entire 30/15 hybrid mobility curve is significantly lower than the
thinner hybrid stacks. This relative reduction in mobility is interpreted to be caused by the
inversion carrier loss due to electron trapping in the thicker gate stack. To verify this, Id-Vg
sweeps were taken from –1 to 2 V and 2 to –1 V. As shown in Figure 7.7, when sweeping
the gate voltage from 2 to –1 V, a significant Vt shift can be seen for the 30/15 case, and then
de-traps as the measurement sweeps back to an accumulation voltage of –1 V.
126
-0.5 0.0 0.5 1.0 1.5 2.00
123
45
678
9 Split CVnFET W/L = 20/20µm
Freq = 100 kHz
15/15 Hybrid 20/15 Hybrid 30/15 Hybrid
Cap
acita
nce
[pF]
Gate Voltage [V]
Figure 7.4. Conventional split C-V data showing a small decrease in CETinv as the physical thickness of the high-κ is reduced.
0.0 0.5 1.0 1.5 2.00
2
4
6
8
10
12
14
nFET W/L = 20/20µmVd = 40mV
30/15 Hybrid 20/15 Hybrid 15/15 Hybrid
Dra
in C
urre
nt [µ
A]
Gate Voltage [V]
Figure 7.5. DC Id-Vg data showing an increase in drive current as the physical thickness of the high-κ is reduced.
127
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.60
50
100
150
200
250
300
Effe
ctiv
e M
obili
ty [c
m2 /V
*sec
]
Effective Field [MV/cm]
30/15 Hybrid 20/15 Hybrid 15/15 Hybrid Universal
Figure 7.6. Electron mobility extracted with the split C-V methodology. Thinner high-κ stacks resulted in higher mobility.
0.0 0.5 1.0 1.5 2.00
2
4
6
8
10
down
30/15 HybridnFET W/L = 20/20 µm
Vg Sweep Direction -1 to 2 V 2 to -1 V
Dra
in C
urre
nt [µ
A]
Gate Voltage [V]
shifted up-sweep
up
Figure 7.7. DC Id-Vg data showing a ∆Vt shift when sweeping the gate voltage –1 V → 2 V → –1 V. De-trapping as the down trace returns to –1 V can be seen.
128
7.3.2.2 Charge Pumping
Charge-pumping measurements are widely used to characterize interface state densities in
MOSFET devices [12]. These measurements can also be performed at different frequencies,
so that the frequency response of the traps can be obtained as outlined in Chapter 5 [6]. For
high-κ gate stack structures, this CP technique can quantify the bulk trapped charge, Nt. FA
CP was executed at 1 MHz with a fixed amplitude of 1.2 V and tr = tf = 100 ns. The results
in Figure 7.8 show that the three stacks exhibit ~ 3.5E10/cycle·cm2 demonstrating low Nit
values for all stacks evaluated. In the VA CP measurements, tr and tf were also set to 100 ns
while the frequency was 100 kHz with the base level fixed at –1 V and the variable
amplitude stepped by 50 mV up to 2 V (Figure 7.8). According to VA CP data, the 30/15
stack traps are more efficiently filled at lower voltages, below Vtop ~1.25 V, while at higher
voltages the thinner stacks show higher recombination current, Icp. An explanation of this is
shown in Figure 7.9 where the device inversion (INV) and accumulation (ACC) states
influence the measured CP current (Icp). When the device is in the “ACC” state of the pulse
cycle (Vbase = -1), the gate leakage component is added to the measured ICP. However, this
contribution does not have a significant impact on the Nt calculation of VA CP into
inversion. In the “INV” state of the pulse cycle, the scaled hybrids exhibit a higher
source/drain (S/D) leakage from the junctions to the gate, which indirectly enhances Icp due
to enhanced injection into the high-κ film. This explanation is supported by the fact that if
this leakage went through the gate and did not get trapped, there would be a reduction in the
measured Icp as the frequency decreases.
129
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
1010
1011
1012Fixed Amplitude CP
Vamp = 1.2 VVbase = -1.5 to 0 V
Freq = 1 MHztr, tf = 100ns
Variable Amplitude CPVbase = -1 V
Vtop = -1 to 2 VFreq = 100kHz
tr, tf = 100ns
Nit
or N
t [#/
cycl
e*cm
2 ]
Vbase [V] or Vtop [V]
30/15 Hybrid 20/15 Hybrid 15/15 Hybrid
Figure 7.8. Interface (Nit) and bulk (Nt) trapping data for the different hybrid stacks obtained with FA CP and VA CP, respectively.
130
Icp
I(d,g)I(s,g)
Ig
ACC.
Icp
I(d,g)I(s,g)INV.
Icp
I(d,g)I(s,g)
Ig
ACC.
Icp
I(d,g)I(s,g)
Ig
ACC.
Icp
I(d,g)I(s,g)
Ig Icp
I(d,g)I(s,g)
Ig
ACC.
Icp
I(d,g)I(s,g)INV.
Icp
I(d,g)I(s,g)INV.
Icp
I(d,g)I(s,g)Icp
I(d,g)I(s,g)INV.
-1.0 -0.5 0.0 0.5 1.0 1.5 2.00.0
1.0x10-8
2.0x10-8
3.0x10-8
4.0x10-8
5.0x10-8
6.0x10-8
7.0x10-8
8.0x10-8
9.0x10-8
1.0x10-7
-1.0 -0.5 0.0 0.5 1.0 1.5 2.010-1510-1410-1310-1210-1110-1010-910-810-710-6
Variable Amplitude CPVbase = -1 V
Vtop = -1 to 2 VFreq = 100kHz
tr, tf = 100ns
I S/D
or
I cp [A
]
Vtop [V]
1 MHz 100 kHz 10 kHz
closed symbols: S/D Leakageopen symbols: Icp
I S/
D o
r I cp
[A]
Vtop [V]
ON
OFF
20/15 Hybrid
Figure 7.9. In the accumulation (ACC) state, gate leakage current adds to the Icp at the low amplitudes of the VA CP measurement (Insets: “ACC” and inner log plot). In the inversion (INV) state, DC leakage current flows from S/D to the gate that indirectly enhances Icp due to enhanced injection into the high-κ film.
7.3.2.3 Fast Transient
Pulsed Transit Charge Trapping Measurements were done similar to [7]. The measurement
conFiguration in Section 5.5, shows the nFET in an inverter circuit where Id is
131
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛ −⋅=
L
DDD
D
DDDd R
VVVVVI (7.2)
where VDD is 100 mV, VD is the voltage measured at the drain of the nFET, and RL is the
load resistance. Measurements were done with tr, tf, and the pulse width (PW) values equally
set. For the W/L = 10/1 µm transistor, the load resistance, RL, is 330 Ω. Each single pulse
(SP) measurement started and ended at –1 V with the top of the pulse taken to 1, 1.5, 2, and
2.2 V. The difference measured between the Id–Vg curves generated by the up and down
swing of Vg reflects the effect of the charge trapping (i.e., ∆Vt). Pulsed Id – Vg data was
collected on the hybrid stacks, using different charging times and pulse voltages, seen in
Figure 7.10. All the results show that ∆Vt increases as the gate bias pulse increases. A
comparison to the conventional DC Id-Vg shows the reduction in drive current with the
‘slower’ measurement due to charge trapping during the measurement. In addition, the ∆Vt
shifts increased with the increase in the physical thickness of the hybrid stack. Figure 7.11
summarizes the ∆Vt results with respect to charging time, physical thickness, and pulse
heights.
132
0.0 0.5 1.0 1.5 2.0 2.50
20
40
60
80
100
120
Vg Pulse Height -1 to 1 V -1 to 1.5 V -1 to 2 V -1 to 2.2 V
tr, PW, tf = 100µs
DC Id-Vg
30/15 HybridnFET W/L = 10/1 µmVd = 40mV
Dra
in C
urre
nt [µ
A]
Gate Voltage [V]
a)
0.0 0.5 1.0 1.5 2.0 2.50
20
40
60
80
100
120
140
160
b)
Vg Pulse Height -1 to 1 V -1 to 1.5 V -1 to 2 V -1 to 2.2 V
tr, PW, tf = 100µs
DC Id-Vg
20/15 HybridnFET W/L = 10/1 µmVd = 40mV
Dra
in C
urre
nt [µ
A]
Gate Voltage [V]
PW
tr tf
PW
tr tf
∆Vt
0.0 0.5 1.0 1.5 2.0 2.50
20
40
60
80
100
120
140
c)
Vg Pulse Height -1 to 1 V -1 to 1.5 V -1 to 2 V -1 to 2.2 V
tr, PW, tf = 100µs
DC Id-Vg
15/15 HybridnFET W/L = 10/1 µmVd = 40mV
Dra
in C
urre
nt [µ
A]
Gate Voltage [V]
Figure 7.10. Pulsed Id-Vg characteristics for a) 30/15, b) 20/15, and c) 15/15 hybrid stacks with different inversion bias pulses with 100 µs rise, fall, and pulse width times. DC Id-Vg is shown for comparison in each case.
133
7.3.3 High-κ Bulk Trapping
To address a critical issue of the location of the trapped charge – bulk of the high-κ film or the
interface of the high-κ film with the sub-oxide interfacial layer (IL) – we estimated whether
the observed ∆Vt shifts can be explained by the charge trapping exclusively at the
high-κ/oxide interface. If only these interface traps are responsible for the electron
3.0 3.5 4.0 4.5 3.0 3.5 4.0 4.53.0 3.5 4.0 4.50.0
0.1
0.2
0.3
0.4
0.5
0.6 Vg = 2 V
High-κ Physical Thickness [nm]
Q' DT = 2.120E-9
Q'DT = 2.415E-10
Q'DT = 1.397E-10
Q' DT = 2.415E-9
Vg = 2.2 V
Vg = 1.5 V
∆V t [
V]
Charging Time 5µs 10µs 100µs
Figure 7.11. ∆Vt values (measured as in Figure 7.10) for different gate biases and charging times vs. gate stack physical thickness. Horizontal dashed lines connect data point of similar ∆Vt obtained with different charging times/physical thickness values.
trapping, ∆Vt would be proportional to the injected charge determined by the direct tunneling
current (JDT) through the interfacial oxide layer multiplied by the charging time (τ). In this
case, the same ∆Vt values in the samples of different thickness in Figure 7.11 should
134
correspond to the same injected charge since, in all types of stacks, the interfacial oxide
thickness = 1 nm (Figure 7.2). One needs to take into account that the different physical
thickness of the high-κ film will cause a different voltage drop across this interfacial layer.
The voltage drop across the interfacial oxide was determined by using the potential balance
expression
polysoxmsg VVV +++Φ= ψ (7.3)
where Φms is the workfunction difference between the polysilicon gate, Φm, and silicon
substrate Φs, defined as , Vsm Φ−Φ ox is the voltage drop across the gate dielectric stack, ψs is
the surface potential (i.e., band bending), and Vpoly is the voltage drop across the polysilicon
gate. NCSU CVC was used to extract the values of C-V parameters from C-V curves
measured at 100 kHz on W/L = 20/20 µm transistors. The C-V sweep started in the
“discharge” condition (i.e., starting in accumulation) and swept into inversion minimizing
charge trapping. A model C-V curve was generated with [15] to compare the results with
CVC for Φms, Vox, ψs, and Vpoly. Equation 7.3 was solved for Vox, where Φms was assumed to
be ideal. This ideal flatband voltage, Vfb, was compared to the extracted Vfb from CVC. The
difference was subtracted from Vox to account for the voltage shift from ideal (i.e., fixed
charge). A simplifying assumption for the graded dual layer hybrid stack is to model it as a
single layer with a uniform κ-value of 16 (a value between 12 and ~20 for silicates and HfO2,
respectively). The conduction band offset of Hf silicate and Hf oxide are governed by the 5d
135
electron states, therefore expected to be the same offset for pure hafnium oxide or silicate
(20% SiO2) (Figure 7.12) [16, 17]. Taking this into account, one gets:
21 VVVox += (7.4)
where V1 is the voltage drop across the interfacial oxide and V2 is the voltage drop across the
high-k. Since CV 1∝ , ratios can be established as follows:
21 VVVox += SiO2
V2
V1
HfSixOy
HfO2
Figure 7.12. Band diagram example for a Hf-based gate dielectric on a SiO2 interfacial oxide illustrating voltage drops across the two portions of the gate stack where V2 is based on the assumed uniform dielectric constant.
136
1
2
2
1
1
2
1
1
2
2
2
1 V
t
tV
t
tVV
phy
phy
phy
phy
ε
ε
ε
ε
=⇒= (7.5)
where ε1 is 3.9·εo, tphy1 is the interfacial oxide (1 nm) thickness, ε2 is 16·εo, tphy2 is the total
nominal high-κ stack thickness. From these ratios, the voltages can be determined in terms
of the other and subsequently substituted into equation 7.4. This yields
1
2
2
1
1
1 V
t
tVV
phy
phyox ε
ε
+= (7.6)
Since the values are know for Vox , ε1, assumed ε2, tphy1 (from TEM), and tphys2 is the nominal
high-k thickness, V1 can be solved for and substituted back into equation 7.4 to obtain V2.
So, for a given Vg, the voltage drops across the interfacial oxide and high-κ portion
can be determined. Now, a direct tunneling calculation across the interfacial layer can be
made using the MIS Tunnel Diode expression [18]:
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛−Φ−=
22
2exp 1*
2Vqm
ttAJ Boxox
DTh
(7.7)
137
where A is a constant, tox is the physical thickness of the SiO2 interface, m* is the effective
mass of an electron is SiO2, q is the fundamental electronic charge, ħ is Plank’s constant, ΦB
is the barrier height of SiO2 to Si substrate, and Vox is the voltage drop across the SiO2
portion. If the injected electrons trap at the high-κ/SiO2 interface, then:
τ•=∝∆ DTDTt JQV (7.8)
where QDT is the tunneling charge and τ is the charging time. From (7.8), one should
expect that similar ∆Vt values (obtained from different samples and charge times) should
correspond to similar tunneling charge values. Verification was performed for all cases of
similar ∆Vt values (Figure 7.11). For example, Table 6.2 shows Q’DT for two cases
demonstrating very similar ∆Vt’s, the 20/15 (3.5nm) at 100 µs sample and the 30/15 (4.5 nm)
at 10 µs sample with a stress Vg = 2 V. Expected charges at the high-κ/SiO2 interface are an
order of magnitude different while the ∆Vt’s are similar.
Table 6.2. Expected charge at the high-κ/SiO2 interface are an order of magnitude different while ∆Vt’s are similar.
3.5 nm @ 100 µs 4.5 nm @ 10 µs
τ•∝ JQ' DTDT 2.415E-10 2.120E-9
138
Therefore, various ∆Vt values cannot be explained by high-κ/SiO2 interface trap filling only,
leaving the option of bulk trapping in the high-κ to be further investigated. Figure 7.13
provides a plausible bulk-trapping model for the energy band diagram. This model
demonstrates the possible capture of the injected electrons as the high-κ thickness increases.
6 5 4 3 2 1 0-3
-2
-1
0
1
2
3
1.5 nm HfSixOy 3 nm HfO2
1.5 nm HfSixOy 1.5 nm HfO2
V or
Φb [
V]
Gate Stack Physical Thickness [nm]
Vg = 2V 30/15 Hybrid Bands 15/15 Hybrid Bands Hi-κ/SiO2 Traps Bulk Hi-κ Traps Hi-κ/SiO2 Traps Bulk Hi-κ Traps
1 nm SiO
Drawn to scale
Figure 7.13. Band diagram for a plausible bulk-trapping model as a function of physical thickness where the possibility of electron trapping from substrate injection increases with increasing physical thickness.
Since there could be a concern that the reduction in trapping for thinner hybrid stacks
is due to the SiO2 rich layer moving closer to the interfacial oxide layer (see Section 7.3.1)
and a non-uniform κ-value in the high-κ portion of the gate stack that impacts the extracted
voltage drops, this study was repeated for single layer 20% SiO2 HfSixOy films on a chemical
oxide interfacial layer. A value κ=12 was extracted for the single layer 20% SiO2 Hf Silicate
139
(HfSixOy) films of multiple thickness with an interfacial oxide of 0.9 nm (inset Figure 7.14).
Figure 7.14 shows that the increase of ∆Vt values as a function of charging time and physical
thickness similar to the hybrid stacks, as well as greater ∆Vt values than in hybrid stacks of
the same physical thickness. Again, for similar ∆Vt’s, there is an order of magnitude
difference in the Q’DT calculation demonstrating that all the trapped charge cannot be solely
at the high-κ/IL interface.
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.60.150.200.250.300.350.400.450.500.550.600.650.700.75
0 1 2 3 4 5 60.81.01.21.41.6
1.82.0
EOT
[nm
]
Nominal Physical Thickness [nm]
HfSixOy (20% SiO2)
Interfacial oxide thickness = .9 nmdielectric constant (κ) ~ 12
Q'DT = 3.254E-10Q'DT = 8.373E-9
Vg = 2.2V
∆V t [
V]
Physical Thickness [nm]
Charging Time 5µs 10µs 100µs
Figure 7.14. ∆Vt values for different gate biases and charging times vs. gate stack physical thickness for Hf silicate (20% SiO2). Horizontal dashed lines connect data point of similar ∆Vt obtained with different charging times/physical thickness values.
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7.3.4 Pulsed Id-Vg Mobility Extraction
The 20/15 and the 15/15 hybrid stacks were further studied to determine the impact of the
trapped charge on the mobility using the fast transient mobility extraction technique
discussed in Chapter 5 [8]. Figure 7.15a and 7.15b show the results of this approach for
20/15 hybrid and 15/15 hybrid stacks, respectively. The Figures show an increase in the
peak and high field mobility with the high field mobility being quite close to the universal
mobility. Thus one can conclude that, for these particular gate stacks, most of the observed
mobility degradation is associated with charge trapping effects.
141
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80
50100150200250300350400450500
0.0 0.5 1.0 1.5 2.00
20406080
100120140
20/15 HybridnFET W/L = 10/1µm
Vd = 40mV
Pulsed Id-Vg (100kHz) DC Id-Vg
Dra
in C
urre
nt [µA
]
Gate Voltage [V]
20/15 Hybrid Stack
DC 20/15 Pulsed 20/15 UniversalEf
fect
ive
Mob
ility
[cm
2 /V*s
ec]
Effective Field [MV/cm]a)
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80
50100150200250300350400450500
b)
0.0 0.5 1.0 1.5 2.00
20406080
100120140
15/15 HybridnFET W/L = 10/1µm
Vd = 40mV
Pulsed Id-Vg (100kHz) DC Id-Vg
Dra
in C
urre
nt [µ
A]
Gate Voltage [V]
15/15 Hybrid Stack
DC 15/15 Pulsed 15/15 UniversalEf
fect
ive
Mob
ility
[cm
2 /V*s
ec]
Effective Field [MV/cm]
Figure 7.15. Comparison of electron mobility from pulsed/CP method and DC ramp for: a) 20/15 and b) 15/15 hybrid stacks. Insets: comparison of pulsed Id-Vg to DC Id-Vg for the mobilities shown.
142
7.4 Summary
Electron trapping data obtained with the pulsed Id-Vg measurements suggests that the
trapping occurs mostly in the bulk of the high-κ film rather than only at the interface of the
high-κ dielectric and interfacial oxide which leads to less bulk trapping in physically thinner
high-κ gate stacks. Carrier mobility of thinner hybrid stacks corrected for the inversion
charge loss due to electron trapping is found to approach the universal high field electron
mobility.
7.5 References
[1] International Technology Roadmap for Semiconductors, http://public.itrs.net, 2001. [2] R. M. Wallace and G. Wilk, "High- k gate dielectric materials," MRS Bulletin, vol. 27,
pp. 192-7, 2002. [3] Y. Kim, C. Lim, C. D. Young, K. Matthews, J. Barnett, B. Foran, A. Agarwal, G. A.
Brown, G. Bersuker, P. Zeitzoff, M. Gardner, R. W. Murto, L. Larson, C. Metzner, S. Kher, and H. R. Huff, "Conventional Poly-Si Gate MOS-transistors With a Novel, Ultra-Thin Hf-oxide Layer," presented at VLSI Technology Symposium, Kyoto, Japan, 2003.
[4] M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, "Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-κ insulator: The role of remote phonon scattering," Journal of Applied Physics, vol. 90, pp. 4587-4608, 2001.
[5] T. Yamaguchi, R. Iijima, T. Ino, A. Nishiyama, H. Satake, and N. Fukushima, "Additional Scattering Effects for Mobility Degradation in Hf-silicate Gate MISFETs," presented at International Electron Device Meeting, Washington, DC, 2002.
[6] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage
143
instability in SiO2/HfO2 dual layer gate dielectrics," IEEE Electron Device Letters, vol. 24, pp. 87-89, 2003.
[7] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, "Characterization of the Vt-instability in SiO2/HfO2 Gate Dielectrics," presented at International Reliability Physics Symposium, Dallas, Texas, 2003.
[8] A. Kerber, E. Cartier, L. A. Ragnarsson, M. Rosmeulen, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, and G. Groeseneken, "Direct Measurement of the Inversion Charge in MOSFETs: Application to Mobility Extraction in Alternative Gate Dielectrics," presented at VLSI Technology Symposium, Kyoto, Japan, 2003.
[9] J. R. Hauser and K. Ahmed, "Characterization of Ultrathin Oxides Using Electrical C-V and I-V Measurements," presented at Characterization and Metrology for ULSI Technology: 1998 International Conference, 1998.
[10] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, "Charge accumulation and mobility in thin dielectric MOS transistors," Solid State Electronics, vol. 25, pp. 833-41, 1982.
[11] J. R. Hauser, "Extraction of experimental mobility data for MOS devices," IEEE Transactions on Electron Devices, vol. 43, pp. 1981-1988, 1996.
[12] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De-Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Transactions on Electron Devices, vol. ED-31, pp. 42-53, 1984.
[13] S. S. Chung, S.-J. Chen, C.-K. Yang, S.-M. Cheng, S.-H. Lin, Y.-C. Sheng, H.-S. Lin, K.-T. Hung, D.-Y. Wu, T.-R. Yew, S.-C. Chien, F.-T. Liou, and F. Wen, "A Novel and Direct Determination of the Interface Traps in Sub-100nm CMOS Devices with Direct Tunneling Regime (12-16Å) Gate Oxide," presented at VLSI Technology Symposium, Honolulu, Hawaii, 2002.
[14] P. Masson, J. L. Autran, and J. Brini, "On the tunneling component of charge pumping current in ultrathin gate oxide MOSFETs," IEEE Electron Device Letters, vol. 20, pp. 92-4, 1999.
[15] E. M. Vogel, C. A. Richter, and B. G. Rennex, "A capacitance-voltage model for polysilicon-gated MOS devices including substrate quantization effects based on modification of the total semiconductor charge," Solid-State Electronics, vol. 47, pp. 1589-1596, 2003.
[16] P. W. Peacock and J. Robertson, "Band offsets and Schottky barrier heights of high dielectric constant oxides," Journal of Applied Physics, vol. 92, pp. 4712-4721, 2002.
[17] G. Lucovsky, B. Rayner, Z. Yu, and J. Whitten, "Experimental determination of band offset energies between Zr silicate alloy dielectrics and crystalline Si substrates by XAS, XPS and AES and ab initio theory: a new approach to the compositional dependence of direct tunneling currents," presented at IEEE International Electron Devices Meeting. San Francisco, CA, USA, Dec. 2002.
[18] S. M. Sze, Physics of Semiconductor Devices, 2nd ed: John Wiley & Sons, Inc., 1981.
144
8 CONCLUSIONS
In this work, robust characterization techniques were instrumental in evaluating gate
dielectric stack structures in an effort to determine if they meet the rigorous device guidelines
set by the ITRS.
These effective measurements and strategies have established a standardized
methodology for electrical characterization of sub – 2 nm EOT gate dielectrics through the
use of highly doped substrates for “short loop” capacitors; measurements on multiple areas
for precise scaling with area for data validation; and multiple measurements on a given area
for reproducibility. In addition, a case study on device structures showed the impact proper
device structures have on the development of precision parametrics. Gate leakage becomes a
significant issue in sub – 2 nm EOT gate stacks, and algorithms for correcting measured data
were demonstrated through meter corrections in C-V measurements. A gate leakage
correction for Id-Vg measurements was shown for robust mobility extraction when gate
leakage is appreciable.
With the need for a high-κ gate dielectric to replace SiO2, devices were fabricated
with a Hf – based dielectric deposited by ALD or MOCVD on a chemical oxide interfacial
layer. One of the major issues with high-κ integration is charge trapping that produces
threshold voltage shifts and mobility degradation. To investigate charge trapping, several
measurement methodologies were employed. C – V hysteresis measurements were shown to
provide a good qualitative approach to understanding the charge trapping that is occurring.
145
However, C – V hysteresis is subject to the sweep rate and sweep amplitude. As a more
standardized approach, a constant voltage stress with interspersed C – V around the flatband
voltage was demonstrated. While a more systematic approach, this “stress-and-sense”
measurement loses trapped charge in the switching of the measurement equipment (i.e., from
voltage stress to C – V) and because the extraction methodology is near the discharge
condition of –1 V. Due to the fast charging and discharging of trap sites in the high-κ gate
stacks that were evaluated, faster measurements were needed in an attempt to quantify the
trapped charge. Charge pumping (CP) was shown to be an excellent process monitoring tool
for measuring trapped charge where fixed-amplitude (CP) at high frequencies provides
robust characterization of the substrate/dielectric interface and variable-amplitude (CP)
allows characterization of the high-κ bulk trapping properties. The fast transient charge
trapping measurements provided the best methodology to quantify the trapped charge. The
fast transient gate pulse on the MISFET under test in an inverter circuit provided a robust and
systematic way to quantify trapped charge. Since CP and first transient measurements are
better protocols for measuring trapped charge, they were used to evaluate an experiment that
addressed different post deposition anneals (PDA) on the same starting MOCVD Hf silicate
starting film deposited at two chamber pressures (2 Torr and 4 Torr). Out of the PDA’s
administered, all of the 4 Torr silicate stacks produced higher mobilities than any of the 2
Torr stacks for the same PDA. This was attributed to larger amounts of trapped charge in the
2 Torr stacks as measured by charge pumping. The N2O PDA’s increased the interfacial
oxide thickness as shown by SIMS. This leads to improved mobility values for these stacks
because the tunneling distance to high-κ trapping sites was increased as a consequence of the
146
thicker interfacial layer. However, large EOTs occurred for the N2O PDA gate stacks which
obviously does not help the effort to scale gate dielectric stacks. Two promising PDA’s that
require further optimization include NH3 at 700ºC and N2 800ºC. The fast transient
technique paired with variable amplitude change pumping provided a way to extract a “trap
free” mobility. For some of the MOCVD samples presented herein, the “trap free” mobility
was quite close to the universal electron mobility curve in the high field regime. These time-
resolved measurements were also instrumental in the development of the bulk trapping model
that was proposed.
In an effort to explain why the mobility was improved as the high-k physical
thickness decreases, it was demonstrated that all of the trapped charge could not be located
only at the interface of the high-κ/interfacial layer suggesting trapping in the bulk of the
high-κ. This leads to less trapping in physically thinner high-κ gate stacks where it was
shown that mobility improved over a thicker high-κ stack.
Future work should be directed to finding approaches to minimize charge trapping in
high-κ gate dielectrics. This will require work on the deposition techniques themselves to
reduce chlorine and carbon contamination in ALD and MOCVD layers, respectively. In
addition, an optimized post deposition anneal treatment will also be required. Although not
presented here, a metal gate seems to be a requirement to achieve sub-1 nm EOT’s with
high-κ gate stacks and needs to be further studied. The characterization techniques in place
to continue to evaluate and quantify trapped charge and its effects on the performance of
emerging high-κ gate dielectric MIS structures.
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APPENDIX: PRESENTATIONS AND PUBLICATIONS
University and Small Firm Collaboration for Process Development of Advanced Gate Dielectrics C. Young, B. Barnes, S. Castro, E. Condon, K. Koh, M. Schrader, S. Shah, K. Williamson, M. Xu, R. Kuehn, D. Maher, D. Venables, A. Oberhofer, G. Wang, and J. Chen, in the Proceedings of 13th Biennial University/Government/Industry Microelectronics Symposium, (June 2-3, 1999, University of Minnesota, Minneapolis, MN, pp. 64-72)
Process Definition for Obtaining Ultra-thin Silicon Oxides Using Full-wafer Electrical and Optical Measurements A. Oberhofer, J. Chen, K. Koh, M. Schrader, S. Shah, R. Venables, C. Young, M. Xu, R. Kuehn, D. Maher and D. Venables, in the MRS Symposium Proceedings on Ultra-thin SiO2 Materials and High-K Dielectrics, (edited by H. Huff, C. Richter, M. Green, G. Lucovsky and H. Hattori) Volume 567, pp. 573-578 1999.
Characterization of Ultrathin Oxide Interfaces (Tox < 1 nm) in Oxide-Nitride Stack Formed by Remote Plasma Enhanced Chemical Vapor Deposition Zhigang Wang, Dexter W. Hodge, Shengqiang Wang, Wenmei Li, Chad Young, Robert T. Croswell, John R. Hauser, in the 4th International Symposium: Physics and Chemistry of SiO2 and the Si-SiO2 Interface, at the 197th Meeting of the Electrochemical Society, (edited by H. Z. Massoud, I. Baumvol, M. Hirose, E. H. Poindexter), May 14-18, 2000, Toronto, Canada, pp. 209-216.
Revisiting Electrical Characterization Concerns for Sub-2 nm EOT Gate Dielectrics on Silicon Chadwin Young, George A. Brown and Howard R. Huff, at the International Workshop on Device Technology: Alternatives to SiO2 as Gate Dielectrics for Future Si-Based Microelectronics, September 3-5, 2001, Porto Alegre, Brazil, p. 7
Growth of Sub-1 nm EOT Gate Quality ZrO2 and HfO2 Films by MOCVD Using TDEAZ and TDEAH Precursors Avinash K. Agarwal, Chan Lim, Craig Metzner, Shreyas Kher, George A. Brown, Chadwin Young, Robert Murto and Howard Huff at the International Workshop on Device Technology: Alternatives to SiO2 as Gate Dielectrics for Future Si-Based Microelectronics, September 3-5, 2001, Porto Alegre, Brazil, p. 12
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Ultra-thin Gate-thickness In line Monitoring: Correlation of Thickness Values Extracted from Quantox COS and MOS Capacitor Characteristics Kwame N. Eason, Xiafang Zhang, Bao Vu, Michael Schrader,
Chadwin Young, Shweta Shah, Kwangok Koh, Brian Taff, Stephanie
Bogle, Dennis Maher, Alain Diebold, and Clive Hayzelden, in the SEMI Technology Symposium (STS) Critical Technologies Conference, Gate Stack Engineering, at SEMICON Southwest 2001, Oct. 2001, Austin, TX, pp. 69-76.
Integration of High-k Gate Stack Systems into Planar CMOS Process Flows H.R. Huff, A. Agarwal, Y. Kim, L. Perrymore, D. Riley, J. Barnett, C. Sparks, M. Freiler, G. Gebara, B. Bowers, P.J. Chen, P. Lysaght, B. Nguyen, J.E. Lim, S. Lim, G. Bersuker, P. Zeitzoff, G.A. Brown, C. Young, B. Foran, F. Shaapur, A. Hou, C. Lim, H. Alshareef, S. Borthakur, D.J. Derro, R. Bergmann, L.A. Larson, M.I. Gardner, J. Gutt, R.W. Murto, K. Torres and M.D. Jackson at the International Workshop on Gate Insulator Program, November 1-2, 2001, Tokyo, Japan, pp. 1-10.
Conventional n-channel MOSFET Devices Using Single Layer HfO2 and ZrO2 as High-k Gate Dielectrics with Polysilicon Gate Electrode Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, J.E. Lim, B. Foran, F. Shaapur, A. Agarwal, P. Lysaght, G.A. Brown, C.D. Young, S. Borthakur, H. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. Murto, A. Hou, H.R. Huff, E. Shero, C. Pomarede, M. Givens, M. Mazanec, and C. Werkhoven, in the Technical Digest of the International Electron Device Meeting, December 2-5,2001, Washington, D.C., pp. 20.2.1-4.
High-k Gate Stacks for Planar, Scaled CMOS Integrated Circuits H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A. Brown, C.D. Young, P. Zeitzoff, J. Gutt, P. Lysaght, M.I. Gardner, and R.W. Murto at the Nano and Giga Challenges in Microelectronics, September 10-13, 2002, Moscow, submitted for publication in the Conference Proceedings.
Characteristics of ALCVDTM HfO2 grown using a modified Deposition Sequence for High-k Gate Stacks Chan Lim, Yudong Kim, Alex Hou, Jim Gutt, Steven Marcus, Christophe Pomarede, Gennadi Bersurker, Joel Barnett, Chadwin Young, Peter Zeitzoff, George A. Brown, Mark Gardner, Robert W. Murto, and Howard Huff at the ALCVD™ Conference, submitted for publication in the Symposium Proceedings.
149
Effects of Deposition Sequence and Plasma Treatment on ALCVDTM HfO2 n-MOSFET Properties Chan Lim, Yudong Kim, Alex Hou, Jim Gutt, Steven Marcus, Christophe Pomarede, Eric Shero, Henk de Waard, Chris Werkhoven, Lee Chen, Jihane Tamim, Nirmal Chaudhary, Gennadi Bersurker, Joel Barnett, Chadwin Young, Peter Zeitzoff, George A. Brown, Mark Gardner, Robert W. Murto, and Howard Huff, in Physics and Technology of High-k Gate Dielectrics I, ECS PV 2002--28, 83-92 (2002), Metrology Study of Sub 20Å Oxynitride by Corona-Oxide-Silicon (COS) and Conventional C – V Approaches Pui Yee Hung, George A. Brown, Michelle Zhang, Joe Bennett, Husam N. Al-Shareef, Chadwin Young, Chris Oroshiba, and Alain Diebold at the 2002 MRS Spring Meeting, San Francisco, CA, Vol. 716, B2.12, pp. 119-124.
Correcting Effective Mobility Measurements for the Presence of Significant Gate Leakage Current P.M. Zeitzoff, C.D. Young, G.A. Brown, and Y.Kim, IEEE Electron Device Letters, Vol. 24, No. 4, April 2003, pp. 275-277.
Conventional Poly-Si Gate MOS-Transistors With a Novel, Ultra-Thin Hf-Oxide Layer Y. Kim, C. Lim, C.D. Young, K Matthews, J. Barnett, B. Foran, A. Agarwal, G.A. Brown, G. Bersuker, P. Zeitzoff, M. Gardner, R.W. Murto, L. Larson, C. Metzner, S. Kher, and H.R. Huff at the 2003 Symposium on VLSI Technology Digest of Technical Papers, June 10-12, 2003, Kyoto, Japan, Session 12A-5.
High-k Gate Stacks for Planar, Scaled CMOS Intgrated Circuits H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A. Brown, C.D. Young, P.M. Zeitzoff, J. Gutt, P. Lysaght, M. I. Gardner and R.W. Murto, Microelectronic Engineering, 69, numbers 2-4, pp. 152-167 (September 2003)
How to Electrically Qualify High-κ Gates Yuegang Zhao, Chadwin D. Young, and George A. Brown, Semiconductor International, vol. 26, 2003, pp. 51-58.
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Charge Trapping and Mobility Degradation in MOCVD Hafnium Silicate Gate Dielectric Stack Structures C. D. Young, A. Kerber, T. H. Hou, E. Cartier, G. A. Brown, G. Bersuker, Y. Kim, C. Lim, J. Gutt, P. Lysaght, J. Bennett, C. H. Lee, S. Gopalan, M. Gardner, P. Zeitzoff, G. Groeseneken, R. W. Murto, and H. R. Huff, presented at the 203rd Fall Meeting of the Electrochemical Society, Physics and Technology of High-K Gate Dielectrics - II, October 12-16, 2003, Orlando, FL, PV 2003-??, The Electrochemical Society Proceedings Series, Pennington, NJ (2003).
Charge Trapping in MOCVD Hafnium-based Gate Dielectric Stack Structures and the Impact on Device Performance Chadwin D. Young, Gennadi Bersuker, George A. Brown, Chan Lim, Pat Lysaght, Peter Zeitzoff, Robert W. Murto, and Howard R. Huff, presented at the Integrated Reliability Workshop, October 20-23, 2004, Lake Tahoe, CA, proceedings volume in press.
Charge Trapping Measurements and Their Application to High-κ Gate Stack Evaluation Chadwin D. Young, Gennadi Bersuker, and George A. Brown, presented at the Semiconductor Research Corporation’s Topical Research Conference on Reliability, October 27-28, 2003, Austin, TX.
Charge Trapping and Device Performance Degradation in MOCVD Hafnium-based Gate Dielectric Stack Structures Chadwin D. Young, Gennadi Bersuker, George A. Brown, Chan Lim, Pat Lysaght, Peter Zeitzoff, Robert W. Murto, and Howard R. Huff, to be presented at the International Reliability Physics Symposium, April 25-29, 2004, Phoenix, AZ.
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