© Copyright 2011 Xilinx

ML631 GTX Chip to Chip IBERT

October 2011

XTP128

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Revision History

Date Version Description 10/26/11 13.3 Updated for 13.3

07/06/11 13.2 Initial version.

ML631 IBERT Overview

Xilinx ML631 Board Software Requirements Setup for the ML631 IBERT Designs ML631 GTH IBERT Designs

– ML631 GTH Chip to Chip IBERT Design – ML631 GTH P4 – J4 IBERT Design

GTX Clock Setup ML631 GTX IBERT Designs

– ML631 GTX Chip to Chip IBERT Designs – ML631 GTX AirMax Loopback IBERT Designs

ML631 IBERT Design Creation References

Note: This presentation applies to the ML631

ML631 IBERT Overview

Description – The LogiCORE Integrated Bit Error Ratio (IBERT) core is used to create a

pattern generation and verification design to exercise the Virtex-6 GTH and GTX transceivers. A graphical user interface is provided through the IBERT console window of the ChipScope Pro Analyzer

Reference Design IP – LogiCORE IBERT Example Designs – ChipScope Pro Analyzer

• ChipScope Pro Software and Cores User Guide (UG029)

Note: Presentation applies to the ML631

Xilinx ML631 Board

Note: Presentation applies to the ML631

ISE Software Requirements

Xilinx ISE 13.3 software

Note: Presentation applies to the ML631

ChipScope Pro Software Requirement

Xilinx ChipScope Pro 13.3 software

Note: Presentation applies to the ML631

Setup for the ML631 IBERT Designs

Setup for the ML631 IBERT Designs

Unzip the ML631 IBERT Design Files (13.3 C) to your C:\ drive – Available through http://www.xilinx.com/ml631

Note: Presentation applies to the ML631

Setup for the ML631 IBERT Designs

Important: Set the power switch, SW1, to OFF first The ML631 uses two power supplies; connect both power supplies

– Use a power strip to turn on both power supplies simultaneously

Only after the two power supplies are on, turn on the power switch

1

Setup for the ML631 IBERT Designs

When powering down, turn the power switch off, then turn off the power strip – Always follow this sequence when cycling power to the ML631

Leave the power off for now

Setup for the ML631 IBERT Designs

ATX power supplies can be used in lieu of standard power supplies The +12 V on each supply must be capable of supplying 15 A

Setup for the ML631 IBERT Designs

Connect J118 and J120 to pins 2-3 (1) – This selects SMAs J124 and J125 as the clock for the 3 U1 GTH input clocks

Connect J121 and J123 to pins 2-3 (1) – This selects SMAs J126 and J127 as the clock for the 6 U2 GTH input clocks

Note: Presentation applies to the ML631

1 2

Setup for the ML631 IBERT Designs

HTG AirMax Loopback Rev 2.0 boards (3 each) – Part number: HTG-AIRMAX-LOOPBACK – Connect X2 to X1 and X4 to X3

Note: Presentation applies to the ML631

Setup for the ML631 IBERT Designs

Connect a USB Type-A to Mini-B cable to the USB JTAG connector on the ML631 board – Connect this cable to your PC

Note: Presentation applies to the ML631

Setup for the ML631 IBERT Designs

SMA Cables – www.flrst.com – P/N: ASPI-024-ASPI-S402

Note: Presentation applies to the ML631

GTX Clock Setup

GTX Clock Setup

Turn board power off Connect J117 and J14 to pins “U1” (1)

– This selects U1 as the IIC master

Note: Presentation applies to the ML631

1

GTX Clock Setup

Attach AirMax Loopback connectors and SMA GTX Clock – Connect AirMax to P4-J4

Note: Presentation applies to the ML631

GTX Clock Setup

Attach AirMax Loopback connectors and SMA GTX Clock – Connect SMA J134 to J9 – Connect SMA J135 to J10

Note: Presentation applies to the ML631

GTX Clock Setup

Attach AirMax Loopback connectors – Connect AirMax to P1-J1 – Connect AirMax to P2-J2

Note: Presentation applies to the ML631

GTX Clock Setup

Set the power switch, SW1, to OFF (1) Turn on the power strip (with the two ML631 power supplies) Turn on the power switch (1)

1

GTX Clock Setup

Open ChipScope Pro and select JTAG Chain -> USB Cable… (1) Verify 12 MHz operation and click OK (2)

1

2

Note: Presentation applies to the ML631

GTX Clock Setup

Click OK (1)

1

Note: Presentation applies to the ML631

GTX Clock Setup

Select Device → DEV:1 MyDevice1 (XC6VHX565T) → Configure… Select <Design Path>\ready_for_download\u1_clk_test.bit

GTX Clock Setup

Select Device → DEV:2 MyDevice2 (XC6VHX565T) → Configure… Select <Design Path>\ready_for_download\u2_clk_test.bit

Note: Presentation applies to the ML631

GTX Clock Setup

Select File → Open Project… Select <Design Path>\ready_for_download\ml631_clk_test.cpj

Note: Presentation applies to the ML631

GTX Clock Setup

All clocks except the 200 & 50 MHz clocks should be at 156.25 MHz – As seen here, U1_MGTREFCLK0_114 is at 0 MHz

GTX Clock Setup

Press SW6 to reset the clocks – Avoid hitting the “PROG” Switch

Note: Presentation applies to the ML631

GTX Clock Setup

U1_MGTREFCLK0_114 is now at 156.25 – All clocks should appear as seen below

GTX Clock Setup

Select File → New Project

GTX Clock Setup

Press the PROG button on both FPGAs

Note: Presentation applies to the ML631

GTX Clock Setup

Click OK in this dialog box after the two FPGAs are blank ChipScope is now ready to accept a new project

– Repeat this process after each section to clear out the old project

Note: Presentation applies to the ML631

ML631 GTX 112 Chip to Chip IBERT Design

ML631 GTX 112 Chip to Chip IBERT Design

U1 GTX 112 Chip to Chip IBERT Connections

ML631 GTX 112 Chip to Chip IBERT Design

U2 GTX 112 Chip to Chip IBERT Connections

ML631 GTX 112 Chip to Chip IBERT Design

Select Device → DEV:1 MyDevice1 (XC6VHX565T) → Configure… Select <Design Path>\ready_for_download\

example_ml631_gtx_112_ibert.bit

ML631 GTX 112 Chip to Chip IBERT Design

Select Device → DEV:2 MyDevice2 (XC6VHX565T) → Configure… Select <Design Path>\ready_for_download\

example_ml631_gtx_112_ibert.bit

Note: Presentation applies to the ML631

ML631 GTX 112 Chip to Chip IBERT Design

Select File → Open Project… Select <Design Path>\ready_for_download\ml631_gtx_112_c2c.cpj

Note: Presentation applies to the ML631

ML631 GTX AirMax P1J1 12-Lane IBERT Design

Click Yes on this Dialog

Note: Presentation applies to the ML631

ML631 GTX AirMax P1J1 12-Lane IBERT Design

Click Yes on this Dialog

Note: With Chip to Chip IBERT, linking requires correct settings in both FPGAs

ML631 GTX 112 Chip to Chip IBERT Design

The line rate is 6.25 Gbps (1)

Note: U1: Bank 100, 101

1

ML631 GTX 112 Chip to Chip IBERT Design

TX Diff Output Swing = 590 mV TX Pre-Emphasis = 0; TX Post-Emphasis = 0

Note: Best settings may vary from board to board

ML631 GTX 112 Chip to Chip IBERT Design

TX/RX Data Patterns are set to PRBS 31-bit (1) Click BERT Reset buttons (2)

Note: Presentation applies to the ML631

1

2

ML631 GTX 112 Chip to Chip IBERT Design

View the RX Bit Error Count (1)

Note: Presentation applies to the ML631

1

ML631 GTX 112 Chip to Chip IBERT Design

Select the second IBERT window

Note: Presentation applies to the ML631

ML631 GTX 112 Chip to Chip IBERT Design

The line rate is 6.25 Gbps (1)

1

Note: U2: Bank 110, 111

ML631 GTX 112 Chip to Chip IBERT Design

TX Diff Output Swing = 590 mV TX Pre-Emphasis = 0; TX Post-Emphasis = 0

Note: Best settings may vary from board to board

ML631 GTX 112 Chip to Chip IBERT Design

TX/RX Data Patterns are set to PRBS 31-bit (1) Click BERT Reset buttons (2)

1

2

Note: Presentation applies to the ML631

ML631 GTX 112 Chip to Chip IBERT Design

View the RX Bit Error Count (1) Select File → New Project and press PROG on both FPGAs

Note: Presentation applies to the ML631

1

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design U1 GTX 1x31x41x5 Chip to Chip IBERT Connections

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design U2 GTX 1x31x41x5 Chip to Chip IBERT Connections

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design

Select Device → DEV:1 MyDevice1 (XC6VHX565T) → Configure… Select <Design Path>\ready_for_download\

example_ml631_gtx_103_104_105_ibert.bit

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design

Select Device → DEV:2 MyDevice2 (XC6VHX565T) → Configure… Select <Design Path>\ready_for_download\

example_ml631_gtx_113_114_115_ibert.bit

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design Select File → Open Project… Select <Design Path>\ready_for_download\

ml631_gtx_1x31x41x5_c2c.cpj

Note: Presentation applies to the ML631

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design Click Yes on this Dialog

Note: Presentation applies to the ML631

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design Click Yes on this Dialog

Note: With Chip to Chip IBERT, linking requires correct settings in both FPGAs

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design The line rate is 6.25 Gbps (1)

Note: U1: Bank 102, 103

1

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design TX Diff Output Swing = 590 mV TX Pre-Emphasis = 0; TX Post-Emphasis = 0

Note: Best settings may vary from board to board

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design TX/RX Data Patterns are set to PRBS 31-bit (1) Click BERT Reset buttons (2)

Note: Presentation applies to the ML631

1

2

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design View the RX Bit Error Count (1)

Note: Presentation applies to the ML631

2

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design Select the second IBERT window

Note: Presentation applies to the ML631

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design The line rate is 6.25 Gbps (1)

Note: U2: Bank 112, 113

1

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design TX Diff Output Swing = 590 mV TX Pre-Emphasis = 0; TX Post-Emphasis = 0

Note: Best settings may vary from board to board

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design TX/RX Data Patterns are set to PRBS 31-bit (1) Click BERT Reset buttons (2)

Note: Presentation applies to the ML631

1

2

ML631 GTX 1x31x41x5 Chip to Chip IBERT Design View the RX Bit Error Count (1) Select File → New Project and press PROG on both FPGAs

Note: Presentation applies to the ML631

2

References

References

ChipScope Pro – ChipScope Pro Software and Cores User Guide

http://www.xilinx.com/support/documentation/sw_manuals/ xilinx13_3/chipscope_pro_sw_cores_ug029.pdf

Documentation

Documentation

Virtex-6 – Virtex-6 HXT FPGAs

http://www.xilinx.com/products/silicon-devices/fpga/virtex-6/hxt.htm

ML631 Documentation – Virtex-6 HXT FPGA Packet Processing/Traffic Management (PP/TM) Kit

http://www.xilinx.com/products/boards-and-kits/EK-V6-ML631-G.htm – ML631 Hardware User Guide

http://www.xilinx.com/support/documentation/boards_and_kits/ug841.pdf