xtp039: sp601 mig design creation
TRANSCRIPT
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SP601 MIG Design Creation
December 2009
© Copyright 2009 Xilinx XTP039
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Overview
Spartan-6 Memory Controller BlockXilinx SP601 BoardSoftware RequirementsSP601 SetupGenerate MIG CoreModifications to Example DesignCompile Example Design ChipScope Pro SetupRun MIGReferences
Note: This presentation applies to the SP601
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Spartan-6 Memory Controller Block
Dedicated Memory Controller Blocks (MCB) for Simplified DRAM interfaces – Up to 4 MCB cores in a single Spartan-6 device– Embedded controller and physical (PHY) interface– Supports 4-bit, 8-bit, or 16-bit single component memory– Memory densities up to 4 Gbit
Performance up to 667 Mb/s (333 MHz double data rate) Configurable dedicated Multi-port user interface to FPGA logic – 1 to 6 ports per MCB depending on configuration– Internal 32-, 64-, or 128-bit data bus options
Note: Presentation applies to the SP601
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MCB Block Diagram
Simple User Interface abstracts away complexity of memory transactionsMIG / EDK wrapper delivers complete interface solution
– Internal block assembly and signal connectivity is made transparent to the user
Note: Presentation applies to the SP601
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Memory Controller Block Startup
Automatic memory configuration and controller calibration
Note: Presentation applies to the SP601
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Xilinx SP601 Board
Note: Presentation applies to the SP601
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ISE Software Requirement
Xilinx ISE 11.4 software– Install the WebPACK for the Spartan-6 LX16 devices– Run XilinxUpdate and download the WebPACK devices
Note: Presentation applies to the SP601
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ChipScope Pro Software Requirement
Xilinx ChipScope Pro 11.4 software
Note: Presentation applies to the SP601
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Generate MIG Example Design
Open the CORE GeneratorStart → All Programs → Xilinx ISE Design Suite 11 →ISE → Accessories → CORE Generator
Create a new project; select File → New Project
Note: Presentation applies to the SP601
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Generate MIG Example Design
Create a project directory: sp601_mig_designName the project: sp601_mig_design.cgpSet the Part (as shipped on the SP601):– Family: Spartan6– Device: xc6slx16– Package: csg324– Speed Grade: -2
Note: Presentation applies to the SP601
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Generate MIG Example Design
Select GenerationSet the Design Entry to VerilogClick OK
Note: Presentation applies to the SP601
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Generate MIG Example Design
Right click on MIG Version 3.3– Select Customize
Note: Presentation applies to the SP601
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Generate MIG Example Design
Leave this page as is– Click Next
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Generate MIG Example Design
Leave this page as is– Click Next
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Generate MIG Example Design
For the Bank 3 Middle MCB, select Memory Type– DDR2 SDRAM– Click Next
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Generate MIG Example Design
Set the Frequency to 333.33 MHz (3000 ps)Set the Memory part to EDE1116ACBG-8E
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Generate MIG Example Design
Leave this page as is– Click Next
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Generate MIG Example Design
Select– One 128-bit bi-directional
Port
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Generate MIG Example Design
Leave this page as is– Click Next
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Generate MIG Example Design
Select Calibrated Input TerminationSet Debug Signals– Enable– Click Next
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Generate MIG Example Design
Leave this page as is– Click Next
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Generate MIG Example Design
Leave this page as is– Click Next
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Generate MIG Example Design
Leave this page as is– Click Next
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Generate MIG Example Design
Click Generate
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Generate MIG Example Design
After the MIG core finishes generating, click Close on the Datasheet window
Note: Presentation applies to the SP601
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Generate MIG Example Design
MIG design appears in Project IP
Note: Presentation applies to the SP601
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Modifications to Example Design
RDF0005.zip includes– ChipScope Project File, UCF, Verilog Files, and pre-built Example Design
files
Modifications to RTL Files for SP601 Example Design– Added GPIO outputs for visual status indicators with heartbeat clock
• GPIO LED 3 = Calibration done• GPIO LED 2 = PLL locked• GPIO LED 1 = Error• GPIO LED 0 = Heartbeat (blinking)
– Add DIFF_TERM = TRUE on IBUFGDS input buffer for SP601• To terminate 200 MHz LVDS input clock
– Change CLKFBOUT_MULT to generate proper clocks:• MCB block runs at 667 MHz• Traffic Generator runs at 83.75 MHz• Soft calibration clock runs at 83.75 MHz
Note: Presentation applies to the SP601
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Modifications to Example Design
Updates to UCF file specifically required for SP601 board:– Changed LOC of 200MHz differential sys_clk inputs– Changed LOC of sys_rst_n input to SP601 CPU_RESET switch– Added LOC for GPIO LED signals (2.5V bank voltage)– Increase sys_clk_ibufg period constraint from 3ns to 5ns
Note: Presentation applies to the SP601
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Modifications to Example Design
Unzip the rdf0005.zip file to your C:\sp601_mig_design directory– This adds modifications to the example design– A fully pre-built SP601 example design is included in the zip file (2)
• Use the included bitstream to run MIG with ChipScope• Run ise_flow.bat in <design directory>\sp601_prebuilt_example_design\
mig_33\example_design\par to recompile the pre-built example design
Note: Overwrites Core Generator output files with SP601 specific files (1)
1
2
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Compile Example Design
Start a windows command shell and enter these commands:cd sp601_mig_design\mig_33\example_design\parise_flow.bat
Note: Presentation applies to the SP601
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SP601 Setup
Connect a USB Mini-B Cable to the USB JTAG on the SP601 board
– Connect this cable to your PC
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ChipScope Pro Setup
After the design compiles, open ChipScope Pro Analyzer– Click on the Open Cable Button (1)– Click OK (2)
Note: Presentation applies to the SP601
1
2
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ChipScope Pro Setup
Select Device → DEV:0 MyDevice0 (XC6SLX16) → Configure…Select <Design Path>\mig_33\example_design\par\example_top.bit
Note: Presentation applies to the SP601
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ChipScope Pro Setup
Select File → Open Project…Select <Design Path>\mig_33\example_design\par\sp601_ddr2_mig3.3.cpj
Note: Presentation applies to the SP601
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Run MIG Example Design
Click on Trigger Setup to view trigger settingsThe error bit value should be set to 1
Note: Presentation applies to the SP601
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Run MIG Example Design
Click on Waveform; click the Arm Trigger button (1)Detection of an error will cause ChipScope Pro to trigger
Note: Presentation applies to the SP601
1
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Run MIG Example Design
The Example Design should run error free (no trigger on error)To force a trigger, click the T! button (1)
Note: Presentation applies to the SP601
1
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Adjust Data Pattern using VIO Console
Select VIO ConsoleSet TrafficGen_VIO_Enable to 1
Note: Presentation applies to the SP601
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Adjust Data Pattern using VIO Console
Set TrafficGen_DataMode to "011" for HAMMER_DATA_MODE
Note: Presentation applies to the SP601
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Adjust Data Pattern using VIO Console
Press and release the CPU RESET switch, SW9, after each change to TrafficGen_VIO_Enable or TrafficGen_DataMode
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Adjust Data Pattern using VIO Console
Click on Waveform; click the Arm Trigger button (1)Force a trigger by clicking the T! button (2)
Note: Presentation applies to the SP601
1 2
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Adjust Data Pattern using VIO Console
Hammer Data Mode – 16 bit DQ data bus changes all bits on each cycle, “hammering” the bus– Read data compared with ‘expected’ data and error generated on mismatch
Note: Presentation applies to the SP601
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Adjust Data Pattern using VIO Console
Set TrafficGen_DataMode to "101" for WALKING1_DATA_MODEPush CPU Reset, click Arm Trigger button, click T! button
Note: Presentation applies to the SP601
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Adjust Data Pattern using VIO Console
Walking 1s Data Mode
Note: Presentation applies to the SP601
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Adjust Data Pattern using VIO Console
See UG388 for more details on the available data patterns– ADDR_DATA_MODE = 3'b010;
– HAMMER_DATA_MODE = 3'b011;
– NEIGHBOR_DATA_MODE = 3'b100;
– WALKING1_DATA_MODE = 3'b101;
– WALKING0_DATA_MODE = 3'b110;
– PRBS_DATA_MODE = 3'b111;
Note: Presentation applies to the SP601
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References
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References
Spartan-6– Spartan-6 FPGA Memory Controller – UG388
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf– Spartan-6 FPGA Memory Interface Solutions User Guide – UG416
http://www.xilinx.com/support/documentation/user_guides/ug416.pdf
ChipScope Pro– ChipScope Pro Software and Cores User Guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/chipscope_pro_sw_cores_ug029.pdf
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Documentation
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Documentation
Spartan-6– Spartan-6 FPGA Family
http://www.xilinx.com/products/spartan6/index.htm
SP601 Documentation– Spartan-6 FPGA SP601 Evaluation Kit
http://www.xilinx.com/products/devkits/EK-S6-SP601-G.htm– SP601 Getting Started Guide
http://www.xilinx.com/support/documentation/boards_and_kits/ug523.pdf– SP601 Hardware User Guide
http://www.xilinx.com/support/documentation/boards_and_kits/ug518.pdf– SP601 Reference Design User Guide
http://www.xilinx.com/support/documentation/boards_and_kits/ug524.pdf