lab 6 sp601 design platform introduction
DESCRIPTION
Lab 6 SP601 Design Platform Introduction. FPGA Design Platform. Introduction. FPGA SP601 設計板是 Spartan-6 系列中的理想入門用設計平台。 可利用 Spartan-6 FPGA SP601 來設計視聽娛樂、消費性電子以及一些低成本與低功耗的產品。 SP601 設計板功能包含乙太網路、通用 I/O 、 DDR2 memory control 、 Flash memory control 以及 UART 等功能應用。. SP601 的特徵 -1. - PowerPoint PPT PresentationTRANSCRIPT
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Lab 6SP601 Design Platform
Introduction
FPGA Design Platform
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Introduction FPGA SP601 設計板是 Spartan-6系列中的理想入門用設計平台。
可利用 Spartan-6 FPGA SP601來設計視聽娛樂、消費性電子以及一些低成本與低功耗的產品。
SP601設計板功能包含乙太網路、通用 I/O、 DDR2 memory control、 Flash memory control以及 UART等功能應用。
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SP601的特徵 -1
FPGA: XC6SLX16 CS324-2CES Spartan-6
Configuration: Onboard configuration circuitry 8MB Quad SPI Flash 16MB Parallel (BPI) Flash JTAG
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SP601的特徵 -2 Memory:
DDR2 Component Memory 128MB IIC 8Kb IIC EEPROM
Communication: 10/100/1000 Tri-Speed Ethernet PHY Serial (UART) to USB Bridge
Expansion Connectors: FMC-LPC connector (68 single-ended or 34
differential user defined signals) 8 User I/O (Digilent 2x6 Header)
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SP601的特徵 -3 Clocking:
200MHz Oscillator (Differential) Socket (Single-Ended) Populated with 27MHz Osc SMA Connectors (Differential)
Display: 4X LEDs
Control: 4X Push Buttons 4X DIP Switches
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SP601 Development Board
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SP601 Block Diagram
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Power Management
SP601是一個 5V電源供電,透過板子上的滑動開關做電源開啟或關閉,右圖為轉換至板子上之電源供給情形。
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User I/O
SP601提供了以下用戶和通用 I/O能力,作為快速電路及裝置規劃做檢查或是做為基本的 I/O
• User LEDs • User DIP switch • Pushbutton switches • CPU Reset pushbutton switch • GPIO male pin header • FMC-LPC Connecter
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User LEDs
10欲知其 pin腳之詳細定義,請參照 SP601 Hardware User Guide.pdf p30.31
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User DIP switch
11欲知其 FPGA pin腳之詳細定義,請參照 SP601 Hardware User Guide.pdf p31
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Pushbutton switches
12欲知其 FPGA pin腳之詳細定義,請參照 SP601 Hardware User Guide.pdf p32
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GPIO male pin header
13欲知其 FPGA pin腳之詳細定義,請參照 SP601 Hardware User Guide.pdf p33
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JTAG Configuration
透過 USB-TO-JTAG來與電腦溝通。 JTAG配置可以在任何模式下做設置並且在任何模式下都擁有優先權。
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Expansion Connector
欲知其 FPGA pin腳之詳細定義,請參照 SP601 Hardware User Guide.pdf p25.26.41
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Question and Answer
歷史人物中,誰跑最快 ?