Spartan-6 Libraries Guidefor Schematic Designs

UG616 (v 11.4) December 2, 2009

Xilinx Trademarks and Copyright Information

Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to yousolely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce,distribute, republish, download, display, post, or transmit the Documentation in any form or by any meansincluding, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the priorwritten consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation.Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinxassumes no obligation to correct any errors contained in the Documentation, or to advise you of any correctionsor updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may beprovided to you in connection with the Information.

THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NOWARRANTY OF ANY KIND. XILINXMAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDINGTHE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR APARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILLXILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTALDAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THEDOCUMENTATION.

© Copyright 2002-2009 Xilinx Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and otherdesignated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property oftheir respective owners.

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Table of ContentsXilinx Trademarks and Copyright Information......................................................................................... 2

Chapter 1 About this Guide......................................................................................................................... 45About Design Elements ........................................................................................................................ 45

Chapter 2 Functional Categories .................................................................................................................. 47Chapter 3 About Design Elements ............................................................................................................... 65

ACC16 ................................................................................................................................................ 66Introduction.................................................................................................................................. 66Logic Table ................................................................................................................................... 67Design Entry Method .................................................................................................................... 67For More Information .................................................................................................................... 67

ACC4.................................................................................................................................................. 68Introduction.................................................................................................................................. 68Logic Table ................................................................................................................................... 69Design Entry Method .................................................................................................................... 69For More Information .................................................................................................................... 69

ACC8.................................................................................................................................................. 70Introduction.................................................................................................................................. 70Logic Table ................................................................................................................................... 71Design Entry Method .................................................................................................................... 71For More Information .................................................................................................................... 71

ADD16................................................................................................................................................ 72Introduction.................................................................................................................................. 72Logic Table ................................................................................................................................... 72Design Entry Method .................................................................................................................... 72For More Information .................................................................................................................... 72

ADD4 ................................................................................................................................................. 73Introduction.................................................................................................................................. 73Logic Table ................................................................................................................................... 73Design Entry Method .................................................................................................................... 73For More Information .................................................................................................................... 73

ADD8 ................................................................................................................................................. 74Introduction.................................................................................................................................. 74Logic Table ................................................................................................................................... 74Design Entry Method .................................................................................................................... 74For More Information .................................................................................................................... 74

ADSU16 .............................................................................................................................................. 75Introduction.................................................................................................................................. 75Logic Table ................................................................................................................................... 75Design Entry Method .................................................................................................................... 76For More Information .................................................................................................................... 76

ADSU4................................................................................................................................................ 77Introduction.................................................................................................................................. 77Logic Table ................................................................................................................................... 77Design Entry Method .................................................................................................................... 78For More Information .................................................................................................................... 78

ADSU8................................................................................................................................................ 79Introduction.................................................................................................................................. 79Logic Table ................................................................................................................................... 79Design Entry Method .................................................................................................................... 80For More Information .................................................................................................................... 80

AND12................................................................................................................................................ 81Introduction.................................................................................................................................. 81Design Entry Method .................................................................................................................... 81For More Information .................................................................................................................... 81

AND16................................................................................................................................................ 82

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Introduction.................................................................................................................................. 82Design Entry Method .................................................................................................................... 82For More Information .................................................................................................................... 82

AND2 ................................................................................................................................................. 83Introduction.................................................................................................................................. 83Design Entry Method .................................................................................................................... 83For More Information .................................................................................................................... 83

AND2B1.............................................................................................................................................. 84Introduction.................................................................................................................................. 84Design Entry Method .................................................................................................................... 84For More Information .................................................................................................................... 84

AND2B1L ........................................................................................................................................... 85Introduction.................................................................................................................................. 85Logic Table ................................................................................................................................... 85Port Descriptions........................................................................................................................... 85Design Entry Method .................................................................................................................... 85For More Information .................................................................................................................... 85

AND2B2.............................................................................................................................................. 86Introduction.................................................................................................................................. 86Design Entry Method .................................................................................................................... 86For More Information .................................................................................................................... 86

AND3 ................................................................................................................................................. 87Introduction.................................................................................................................................. 87Design Entry Method .................................................................................................................... 87For More Information .................................................................................................................... 87

AND3B1.............................................................................................................................................. 88Introduction.................................................................................................................................. 88Design Entry Method .................................................................................................................... 88For More Information .................................................................................................................... 88

AND3B2.............................................................................................................................................. 89Introduction.................................................................................................................................. 89Design Entry Method .................................................................................................................... 89For More Information .................................................................................................................... 89

AND3B3.............................................................................................................................................. 90Introduction.................................................................................................................................. 90Design Entry Method .................................................................................................................... 90For More Information .................................................................................................................... 90

AND4 ................................................................................................................................................. 91Introduction.................................................................................................................................. 91Design Entry Method .................................................................................................................... 91For More Information .................................................................................................................... 91

AND4B1.............................................................................................................................................. 92Introduction.................................................................................................................................. 92Design Entry Method .................................................................................................................... 92For More Information .................................................................................................................... 92

AND4B2.............................................................................................................................................. 93Introduction.................................................................................................................................. 93Design Entry Method .................................................................................................................... 93For More Information .................................................................................................................... 93

AND4B3.............................................................................................................................................. 94Introduction.................................................................................................................................. 94Design Entry Method .................................................................................................................... 94For More Information .................................................................................................................... 94

AND4B4.............................................................................................................................................. 95Introduction.................................................................................................................................. 95Design Entry Method .................................................................................................................... 95For More Information .................................................................................................................... 95

AND5 ................................................................................................................................................. 96Introduction.................................................................................................................................. 96

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Design Entry Method .................................................................................................................... 96For More Information .................................................................................................................... 96

AND5B1.............................................................................................................................................. 97Introduction.................................................................................................................................. 97Design Entry Method .................................................................................................................... 97For More Information .................................................................................................................... 97

AND5B2.............................................................................................................................................. 98Introduction.................................................................................................................................. 98Design Entry Method .................................................................................................................... 98For More Information .................................................................................................................... 98

AND5B3.............................................................................................................................................. 99Introduction.................................................................................................................................. 99Design Entry Method .................................................................................................................... 99For More Information .................................................................................................................... 99

AND5B4............................................................................................................................................. 100Introduction................................................................................................................................. 100Design Entry Method ................................................................................................................... 100For More Information ................................................................................................................... 100

AND5B5............................................................................................................................................. 101Introduction................................................................................................................................. 101Design Entry Method ................................................................................................................... 101For More Information ................................................................................................................... 101

AND6 ................................................................................................................................................ 102Introduction................................................................................................................................. 102Design Entry Method ................................................................................................................... 102For More Information ................................................................................................................... 102

AND7 ................................................................................................................................................ 103Introduction................................................................................................................................. 103Design Entry Method ................................................................................................................... 103For More Information ................................................................................................................... 103

AND8 ................................................................................................................................................ 104Introduction................................................................................................................................. 104Design Entry Method ................................................................................................................... 104For More Information ................................................................................................................... 104

AND9 ................................................................................................................................................ 105Introduction................................................................................................................................. 105Design Entry Method ................................................................................................................... 105For More Information ................................................................................................................... 105

BRLSHFT4 ......................................................................................................................................... 106Introduction................................................................................................................................. 106Logic Table .................................................................................................................................. 106Design Entry Method ................................................................................................................... 106For More Information ................................................................................................................... 106

BRLSHFT8 ......................................................................................................................................... 107Introduction................................................................................................................................. 107Logic Table .................................................................................................................................. 107Design Entry Method ................................................................................................................... 107For More Information ................................................................................................................... 107

BSCAN_SPARTAN6 ........................................................................................................................... 108Introduction................................................................................................................................. 108Port Descriptions.......................................................................................................................... 109Design Entry Method ................................................................................................................... 109Available Attributes ..................................................................................................................... 109For More Information ................................................................................................................... 109

BUF ................................................................................................................................................... 110Introduction................................................................................................................................. 110Design Entry Method ................................................................................................................... 110For More Information ................................................................................................................... 110

BUFCF ............................................................................................................................................... 111

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Introduction................................................................................................................................. 111Design Entry Method ................................................................................................................... 111For More Information ................................................................................................................... 111

BUFG................................................................................................................................................. 112Introduction................................................................................................................................. 112Port Descriptions.......................................................................................................................... 112Design Entry Method ................................................................................................................... 112For More Information ................................................................................................................... 112

BUFGCE ............................................................................................................................................ 113Introduction................................................................................................................................. 113Logic Table .................................................................................................................................. 113Design Entry Method ................................................................................................................... 113For More Information ................................................................................................................... 113

BUFGCE_1 ......................................................................................................................................... 114Introduction................................................................................................................................. 114Logic Table .................................................................................................................................. 114Design Entry Method ................................................................................................................... 114For More Information ................................................................................................................... 114

BUFGMUX......................................................................................................................................... 115Introduction................................................................................................................................. 115Logic Table .................................................................................................................................. 115Port Descriptions.......................................................................................................................... 115Design Entry Method ................................................................................................................... 115Available Attributes ..................................................................................................................... 115For More Information ................................................................................................................... 116

BUFGMUX_1...................................................................................................................................... 117Introduction................................................................................................................................. 117Logic Table .................................................................................................................................. 117Design Entry Method ................................................................................................................... 117For More Information ................................................................................................................... 117

BUFH................................................................................................................................................. 118Introduction................................................................................................................................. 118Port Descriptions.......................................................................................................................... 118Design Entry Method ................................................................................................................... 118For More Information ................................................................................................................... 118

BUFIO2 .............................................................................................................................................. 119Introduction................................................................................................................................. 119Port Descriptions.......................................................................................................................... 119Design Entry Method ................................................................................................................... 119Available Attributes ..................................................................................................................... 119For More Information ................................................................................................................... 119

BUFIO2_2CLK.................................................................................................................................... 120Introduction................................................................................................................................. 120Design Entry Method ................................................................................................................... 120For More Information ................................................................................................................... 120

BUFIO2FB .......................................................................................................................................... 121Introduction................................................................................................................................. 121Port Descriptions.......................................................................................................................... 121Design Entry Method ................................................................................................................... 121Available Attributes ..................................................................................................................... 121For More Information ................................................................................................................... 121

BUFPLL ............................................................................................................................................. 122Introduction................................................................................................................................. 122Port Descriptions.......................................................................................................................... 122Design Entry Method ................................................................................................................... 122Available Attributes ..................................................................................................................... 122For More Information ................................................................................................................... 122

CARRY4............................................................................................................................................. 123Introduction................................................................................................................................. 123

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Port Descriptions.......................................................................................................................... 123Design Entry Method ................................................................................................................... 123For More Information ................................................................................................................... 123

CB16CE.............................................................................................................................................. 124Introduction................................................................................................................................. 124Logic Table .................................................................................................................................. 124Design Entry Method ................................................................................................................... 124For More Information ................................................................................................................... 124

CB16CLE............................................................................................................................................ 125Introduction................................................................................................................................. 125Logic Table .................................................................................................................................. 126Design Entry Method ................................................................................................................... 126For More Information ................................................................................................................... 126

CB16CLED ......................................................................................................................................... 127Introduction................................................................................................................................. 127Logic Table .................................................................................................................................. 127Design Entry Method ................................................................................................................... 128For More Information ................................................................................................................... 128

CB16RE.............................................................................................................................................. 129Introduction................................................................................................................................. 129Logic Table .................................................................................................................................. 129Design Entry Method ................................................................................................................... 129For More Information ................................................................................................................... 129

CB2CE ............................................................................................................................................... 130Introduction................................................................................................................................. 130Logic Table .................................................................................................................................. 130Design Entry Method ................................................................................................................... 130For More Information ................................................................................................................... 130

CB2CLE ............................................................................................................................................. 131Introduction................................................................................................................................. 131Logic Table .................................................................................................................................. 131Design Entry Method ................................................................................................................... 131For More Information ................................................................................................................... 132

CB2CLED........................................................................................................................................... 133Introduction................................................................................................................................. 133Logic Table .................................................................................................................................. 133Design Entry Method ................................................................................................................... 134For More Information ................................................................................................................... 134

CB2RE................................................................................................................................................ 135Introduction................................................................................................................................. 135Logic Table .................................................................................................................................. 135Design Entry Method ................................................................................................................... 135For More Information ................................................................................................................... 135

CB4CE ............................................................................................................................................... 136Introduction................................................................................................................................. 136Logic Table .................................................................................................................................. 136Design Entry Method ................................................................................................................... 136For More Information ................................................................................................................... 136

CB4CLE ............................................................................................................................................. 137Introduction................................................................................................................................. 137Logic Table .................................................................................................................................. 137Design Entry Method ................................................................................................................... 137For More Information ................................................................................................................... 138

CB4CLED........................................................................................................................................... 139Introduction................................................................................................................................. 139Logic Table .................................................................................................................................. 140Design Entry Method ................................................................................................................... 140For More Information ................................................................................................................... 140

CB4RE................................................................................................................................................ 141

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Introduction................................................................................................................................. 141Logic Table .................................................................................................................................. 141Design Entry Method ................................................................................................................... 141For More Information ................................................................................................................... 141

CB8CE ............................................................................................................................................... 142Introduction................................................................................................................................. 142Logic Table .................................................................................................................................. 142Design Entry Method ................................................................................................................... 142For More Information ................................................................................................................... 142

CB8CLE ............................................................................................................................................. 143Introduction................................................................................................................................. 143Logic Table .................................................................................................................................. 144Design Entry Method ................................................................................................................... 144For More Information ................................................................................................................... 144

CB8CLED........................................................................................................................................... 145Introduction................................................................................................................................. 145Logic Table .................................................................................................................................. 145Design Entry Method ................................................................................................................... 146For More Information ................................................................................................................... 146

CB8RE................................................................................................................................................ 147Introduction................................................................................................................................. 147Logic Table .................................................................................................................................. 147Design Entry Method ................................................................................................................... 147For More Information ................................................................................................................... 147

CC16CE ............................................................................................................................................. 148Introduction................................................................................................................................. 148Logic Table .................................................................................................................................. 148Design Entry Method ................................................................................................................... 148For More Information ................................................................................................................... 148

CC16CLE ........................................................................................................................................... 149Introduction................................................................................................................................. 149Logic Table .................................................................................................................................. 149Design Entry Method ................................................................................................................... 149For More Information ................................................................................................................... 150

CC16CLED......................................................................................................................................... 151Introduction................................................................................................................................. 151Logic Table .................................................................................................................................. 151Design Entry Method ................................................................................................................... 152For More Information ................................................................................................................... 152

CC16RE.............................................................................................................................................. 153Introduction................................................................................................................................. 153Logic Table .................................................................................................................................. 153Design Entry Method ................................................................................................................... 153For More Information ................................................................................................................... 153

CC8CE ............................................................................................................................................... 154Introduction................................................................................................................................. 154Logic Table .................................................................................................................................. 154Design Entry Method ................................................................................................................... 154For More Information ................................................................................................................... 154

CC8CLE ............................................................................................................................................. 155Introduction................................................................................................................................. 155Logic Table .................................................................................................................................. 155Design Entry Method ................................................................................................................... 155For More Information ................................................................................................................... 156

CC8CLED .......................................................................................................................................... 157Introduction................................................................................................................................. 157Logic Table .................................................................................................................................. 157Design Entry Method ................................................................................................................... 158For More Information ................................................................................................................... 158

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CC8RE ............................................................................................................................................... 159Introduction................................................................................................................................. 159Logic Table .................................................................................................................................. 159Design Entry Method ................................................................................................................... 159For More Information ................................................................................................................... 159

CD4CE............................................................................................................................................... 160Introduction................................................................................................................................. 160Logic Table .................................................................................................................................. 161Design Entry Method ................................................................................................................... 161For More Information ................................................................................................................... 161

CD4CLE............................................................................................................................................. 162Introduction................................................................................................................................. 162Logic Table .................................................................................................................................. 163Design Entry Method ................................................................................................................... 163For More Information ................................................................................................................... 163

CD4RE ............................................................................................................................................... 164Introduction................................................................................................................................. 164Logic Table .................................................................................................................................. 165Design Entry Method ................................................................................................................... 165For More Information ................................................................................................................... 165

CD4RLE............................................................................................................................................. 166Introduction................................................................................................................................. 166Logic Table .................................................................................................................................. 167Design Entry Method ................................................................................................................... 167For More Information ................................................................................................................... 167

CFGLUT5........................................................................................................................................... 168Introduction................................................................................................................................. 168Port Descriptions.......................................................................................................................... 168Design Entry Method ................................................................................................................... 168Available Attributes ..................................................................................................................... 169For More Information ................................................................................................................... 169

CJ4CE ................................................................................................................................................ 170Introduction................................................................................................................................. 170Logic Table .................................................................................................................................. 170Design Entry Method ................................................................................................................... 170For More Information ................................................................................................................... 170

CJ4RE ................................................................................................................................................ 171Introduction................................................................................................................................. 171Logic Table .................................................................................................................................. 171Design Entry Method ................................................................................................................... 171For More Information ................................................................................................................... 171

CJ5CE ................................................................................................................................................ 172Introduction................................................................................................................................. 172Logic Table .................................................................................................................................. 172Design Entry Method ................................................................................................................... 172For More Information ................................................................................................................... 172

CJ5RE ................................................................................................................................................ 173Introduction................................................................................................................................. 173Logic Table .................................................................................................................................. 173Design Entry Method ................................................................................................................... 173For More Information ................................................................................................................... 173

CJ8CE ................................................................................................................................................ 174Introduction................................................................................................................................. 174Logic Table .................................................................................................................................. 174Design Entry Method ................................................................................................................... 174For More Information ................................................................................................................... 174

CJ8RE ................................................................................................................................................ 175Introduction................................................................................................................................. 175Logic Table .................................................................................................................................. 175

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Design Entry Method ................................................................................................................... 175For More Information ................................................................................................................... 175

COMP16 ............................................................................................................................................ 176Introduction................................................................................................................................. 176Design Entry Method ................................................................................................................... 176For More Information ................................................................................................................... 176

COMP2 .............................................................................................................................................. 177Introduction................................................................................................................................. 177Design Entry Method ................................................................................................................... 177For More Information ................................................................................................................... 177

COMP4 .............................................................................................................................................. 178Introduction................................................................................................................................. 178Design Entry Method ................................................................................................................... 178For More Information ................................................................................................................... 178

COMP8 .............................................................................................................................................. 179Introduction................................................................................................................................. 179Design Entry Method ................................................................................................................... 179For More Information ................................................................................................................... 179

COMPM16 ......................................................................................................................................... 180Introduction................................................................................................................................. 180Logic Table .................................................................................................................................. 180Design Entry Method ................................................................................................................... 180For More Information ................................................................................................................... 180

COMPM2........................................................................................................................................... 181Introduction................................................................................................................................. 181Logic Table .................................................................................................................................. 181Design Entry Method ................................................................................................................... 181For More Information ................................................................................................................... 181

COMPM4........................................................................................................................................... 182Introduction................................................................................................................................. 182Logic Table .................................................................................................................................. 182Design Entry Method ................................................................................................................... 182For More Information ................................................................................................................... 182

COMPM8........................................................................................................................................... 183Introduction................................................................................................................................. 183Logic Table .................................................................................................................................. 183Design Entry Method ................................................................................................................... 183For More Information ................................................................................................................... 183

COMPMC16....................................................................................................................................... 184Introduction................................................................................................................................. 184Logic Table .................................................................................................................................. 184Design Entry Method ................................................................................................................... 184For More Information ................................................................................................................... 185

COMPMC8 ........................................................................................................................................ 186Introduction................................................................................................................................. 186Logic Table .................................................................................................................................. 186Design Entry Method ................................................................................................................... 186For More Information ................................................................................................................... 187

CR16CE.............................................................................................................................................. 188Introduction................................................................................................................................. 188Logic Table .................................................................................................................................. 188Design Entry Method ................................................................................................................... 188For More Information ................................................................................................................... 188

CR8CE ............................................................................................................................................... 189Introduction................................................................................................................................. 189Logic Table .................................................................................................................................. 189Design Entry Method ................................................................................................................... 189For More Information ................................................................................................................... 189

D2_4E ................................................................................................................................................ 190

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Introduction................................................................................................................................. 190Logic Table .................................................................................................................................. 190Design Entry Method ................................................................................................................... 190For More Information ................................................................................................................... 190

D3_8E ................................................................................................................................................ 191Introduction................................................................................................................................. 191Logic Table .................................................................................................................................. 191Design Entry Method ................................................................................................................... 191For More Information ................................................................................................................... 191

D4_16E............................................................................................................................................... 192Introduction................................................................................................................................. 192Design Entry Method ................................................................................................................... 192For More Information ................................................................................................................... 192

DCM_CLKGEN.................................................................................................................................. 193Introduction................................................................................................................................. 193Port Descriptions.......................................................................................................................... 193Design Entry Method ................................................................................................................... 194Available Attributes ..................................................................................................................... 194For More Information ................................................................................................................... 195

DCM_SP ............................................................................................................................................ 196Introduction................................................................................................................................. 196Port Descriptions.......................................................................................................................... 196Design Entry Method ................................................................................................................... 197Available Attributes ..................................................................................................................... 197For More Information ................................................................................................................... 199

DEC_CC16 ......................................................................................................................................... 200Introduction................................................................................................................................. 200Logic Table .................................................................................................................................. 200Design Entry Method ................................................................................................................... 200For More Information ................................................................................................................... 200

DEC_CC4........................................................................................................................................... 201Introduction................................................................................................................................. 201Logic Table .................................................................................................................................. 201Design Entry Method ................................................................................................................... 201For More Information ................................................................................................................... 201

DEC_CC8........................................................................................................................................... 202Introduction................................................................................................................................. 202Logic Table .................................................................................................................................. 202Design Entry Method ................................................................................................................... 202For More Information ................................................................................................................... 202

DECODE16 ........................................................................................................................................ 203Introduction................................................................................................................................. 203Logic Table .................................................................................................................................. 203Design Entry Method ................................................................................................................... 203For More Information ................................................................................................................... 203

DECODE32 ........................................................................................................................................ 204Introduction................................................................................................................................. 204Logic Table .................................................................................................................................. 204Design Entry Method ................................................................................................................... 204For More Information ................................................................................................................... 204

DECODE4 .......................................................................................................................................... 205Introduction................................................................................................................................. 205Logic Table .................................................................................................................................. 205Design Entry Method ................................................................................................................... 205For More Information ................................................................................................................... 205

DECODE64 ........................................................................................................................................ 206Introduction................................................................................................................................. 206Logic Table .................................................................................................................................. 206Design Entry Method ................................................................................................................... 206

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For More Information ................................................................................................................... 206DECODE8 .......................................................................................................................................... 207

Introduction................................................................................................................................. 207Logic Table .................................................................................................................................. 207Design Entry Method ................................................................................................................... 207For More Information ................................................................................................................... 207

DNA_PORT ....................................................................................................................................... 208Introduction................................................................................................................................. 208Port Descriptions.......................................................................................................................... 208Design Entry Method ................................................................................................................... 208Available Attributes ..................................................................................................................... 208For More Information ................................................................................................................... 209

DSP48A1............................................................................................................................................ 210Introduction................................................................................................................................. 210Port Descriptions.......................................................................................................................... 211Design Entry Method ................................................................................................................... 212Available Attributes ..................................................................................................................... 212For More Information ................................................................................................................... 213

FD ..................................................................................................................................................... 214Introduction................................................................................................................................. 214Logic Table .................................................................................................................................. 214Design Entry Method ................................................................................................................... 214Available Attributes ..................................................................................................................... 214For More Information ................................................................................................................... 214

FD_1 .................................................................................................................................................. 215Introduction................................................................................................................................. 215Logic Table .................................................................................................................................. 215Design Entry Method ................................................................................................................... 215Available Attributes ..................................................................................................................... 215For More Information ................................................................................................................... 215

FD16CE.............................................................................................................................................. 216Introduction................................................................................................................................. 216Logic Table .................................................................................................................................. 216Design Entry Method ................................................................................................................... 216Available Attributes ..................................................................................................................... 216For More Information ................................................................................................................... 216

FD16RE.............................................................................................................................................. 217Introduction................................................................................................................................. 217Logic Table .................................................................................................................................. 217Design Entry Method ................................................................................................................... 217Available Attributes ..................................................................................................................... 217For More Information ................................................................................................................... 217

FD4CE ............................................................................................................................................... 218Introduction................................................................................................................................. 218Logic Table .................................................................................................................................. 218Design Entry Method ................................................................................................................... 218Available Attributes ..................................................................................................................... 218For More Information ................................................................................................................... 218

FD4RE ............................................................................................................................................... 219Introduction................................................................................................................................. 219Logic Table .................................................................................................................................. 219Design Entry Method ................................................................................................................... 219Available Attributes ..................................................................................................................... 219For More Information ................................................................................................................... 219

FD8CE ............................................................................................................................................... 220Introduction................................................................................................................................. 220Logic Table .................................................................................................................................. 220Design Entry Method ................................................................................................................... 220Available Attributes ..................................................................................................................... 220

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For More Information ................................................................................................................... 220FD8RE ............................................................................................................................................... 221

Introduction................................................................................................................................. 221Logic Table .................................................................................................................................. 221Design Entry Method ................................................................................................................... 221Available Attributes ..................................................................................................................... 221For More Information ................................................................................................................... 221

FDC ................................................................................................................................................... 222Introduction................................................................................................................................. 222Logic Table .................................................................................................................................. 222Design Entry Method ................................................................................................................... 222Available Attributes ..................................................................................................................... 222For More Information ................................................................................................................... 222

FDC_1................................................................................................................................................ 223Introduction................................................................................................................................. 223Logic Table .................................................................................................................................. 223Design Entry Method ................................................................................................................... 223Available Attributes ..................................................................................................................... 223For More Information ................................................................................................................... 223

FDCE ................................................................................................................................................. 224Introduction................................................................................................................................. 224Logic Table .................................................................................................................................. 224Design Entry Method ................................................................................................................... 224Available Attributes ..................................................................................................................... 224For More Information ................................................................................................................... 224

FDCE_1.............................................................................................................................................. 225Introduction................................................................................................................................. 225Logic Table .................................................................................................................................. 225Design Entry Method ................................................................................................................... 225Available Attributes ..................................................................................................................... 225For More Information ................................................................................................................... 225

FDE ................................................................................................................................................... 226Introduction................................................................................................................................. 226Logic Table .................................................................................................................................. 226Design Entry Method ................................................................................................................... 226Available Attributes ..................................................................................................................... 226For More Information ................................................................................................................... 226

FDE_1 ................................................................................................................................................ 227Introduction................................................................................................................................. 227Logic Table .................................................................................................................................. 227Design Entry Method ................................................................................................................... 227Available Attributes ..................................................................................................................... 227For More Information ................................................................................................................... 227

FDP ................................................................................................................................................... 228Introduction................................................................................................................................. 228Logic Table .................................................................................................................................. 228Design Entry Method ................................................................................................................... 228Available Attributes ..................................................................................................................... 228For More Information ................................................................................................................... 228

FDP_1 ................................................................................................................................................ 229Introduction................................................................................................................................. 229Logic Table .................................................................................................................................. 229Design Entry Method ................................................................................................................... 229Available Attributes ..................................................................................................................... 229For More Information ................................................................................................................... 229

FDPE ................................................................................................................................................. 230Introduction................................................................................................................................. 230Logic Table .................................................................................................................................. 230Design Entry Method ................................................................................................................... 230

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Available Attributes ..................................................................................................................... 230For More Information ................................................................................................................... 230

FDPE_1 .............................................................................................................................................. 231Introduction................................................................................................................................. 231Logic Table .................................................................................................................................. 231Design Entry Method ................................................................................................................... 231Available Attributes ..................................................................................................................... 231For More Information ................................................................................................................... 231

FDR ................................................................................................................................................... 232Introduction................................................................................................................................. 232Logic Table .................................................................................................................................. 232Design Entry Method ................................................................................................................... 232Available Attributes ..................................................................................................................... 232For More Information ................................................................................................................... 232

FDR_1................................................................................................................................................ 233Introduction................................................................................................................................. 233Logic Table .................................................................................................................................. 233Design Entry Method ................................................................................................................... 233Available Attributes ..................................................................................................................... 233For More Information ................................................................................................................... 233

FDRE ................................................................................................................................................. 234Introduction................................................................................................................................. 234Logic Table .................................................................................................................................. 234Design Entry Method ................................................................................................................... 234Available Attributes ..................................................................................................................... 234For More Information ................................................................................................................... 234

FDRE_1.............................................................................................................................................. 235Introduction................................................................................................................................. 235Logic Table .................................................................................................................................. 235Design Entry Method ................................................................................................................... 235Available Attributes ..................................................................................................................... 235For More Information ................................................................................................................... 235

FDS.................................................................................................................................................... 236Introduction................................................................................................................................. 236Logic Table .................................................................................................................................. 236Design Entry Method ................................................................................................................... 236Available Attributes ..................................................................................................................... 236For More Information ................................................................................................................... 236

FDS_1 ................................................................................................................................................ 237Introduction................................................................................................................................. 237Logic Table .................................................................................................................................. 237Design Entry Method ................................................................................................................... 237Available Attributes ..................................................................................................................... 237For More Information ................................................................................................................... 237

FDSE.................................................................................................................................................. 238Introduction................................................................................................................................. 238Logic Table .................................................................................................................................. 238Design Entry Method ................................................................................................................... 238Available Attributes ..................................................................................................................... 238For More Information ................................................................................................................... 238

FDSE_1 .............................................................................................................................................. 239Introduction................................................................................................................................. 239Logic Table .................................................................................................................................. 239Design Entry Method ................................................................................................................... 239Available Attributes ..................................................................................................................... 239For More Information ................................................................................................................... 239

FJKC .................................................................................................................................................. 240Introduction................................................................................................................................. 240Logic Table .................................................................................................................................. 240

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Design Entry Method ................................................................................................................... 240Available Attributes ..................................................................................................................... 240For More Information ................................................................................................................... 240

FJKCE ................................................................................................................................................ 241Introduction................................................................................................................................. 241Logic Table .................................................................................................................................. 241Design Entry Method ................................................................................................................... 241Available Attributes ..................................................................................................................... 241For More Information ................................................................................................................... 241

FJKP .................................................................................................................................................. 242Introduction................................................................................................................................. 242Logic Table .................................................................................................................................. 242Design Entry Method ................................................................................................................... 242Available Attributes ..................................................................................................................... 242For More Information ................................................................................................................... 242

FJKPE ................................................................................................................................................ 243Introduction................................................................................................................................. 243Logic Table .................................................................................................................................. 243Design Entry Method ................................................................................................................... 243Available Attributes ..................................................................................................................... 243For More Information ................................................................................................................... 243

FJKRSE .............................................................................................................................................. 244Introduction................................................................................................................................. 244Logic Table .................................................................................................................................. 244Design Entry Method ................................................................................................................... 244Available Attributes ..................................................................................................................... 244For More Information ................................................................................................................... 245

FJKSRE .............................................................................................................................................. 246Introduction................................................................................................................................. 246Logic Table .................................................................................................................................. 246Design Entry Method ................................................................................................................... 246Available Attributes ..................................................................................................................... 246For More Information ................................................................................................................... 247

FTC.................................................................................................................................................... 248Introduction................................................................................................................................. 248Logic Table .................................................................................................................................. 248Design Entry Method ................................................................................................................... 248Available Attributes ..................................................................................................................... 248For More Information ................................................................................................................... 248

FTCE.................................................................................................................................................. 249Introduction................................................................................................................................. 249Logic Table .................................................................................................................................. 249Design Entry Method ................................................................................................................... 249Available Attributes ..................................................................................................................... 249For More Information ................................................................................................................... 249

FTCLE ............................................................................................................................................... 250Introduction................................................................................................................................. 250Logic Table .................................................................................................................................. 250Design Entry Method ................................................................................................................... 250Available Attributes ..................................................................................................................... 250For More Information ................................................................................................................... 250

FTCLEX ............................................................................................................................................. 251Introduction................................................................................................................................. 251Logic Table .................................................................................................................................. 251Design Entry Method ................................................................................................................... 251Available Attributes ..................................................................................................................... 251For More Information ................................................................................................................... 251

FTP .................................................................................................................................................... 252Introduction................................................................................................................................. 252

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Logic Table .................................................................................................................................. 252Design Entry Method ................................................................................................................... 252Available Attributes ..................................................................................................................... 252For More Information ................................................................................................................... 252

FTPE.................................................................................................................................................. 253Introduction................................................................................................................................. 253Logic Table .................................................................................................................................. 253Design Entry Method ................................................................................................................... 253Available Attributes ..................................................................................................................... 253For More Information ................................................................................................................... 253

FTPLE................................................................................................................................................ 254Introduction................................................................................................................................. 254Logic Table .................................................................................................................................. 254Design Entry Method ................................................................................................................... 254Available Attributes ..................................................................................................................... 254For More Information ................................................................................................................... 254

FTRSE ................................................................................................................................................ 255Introduction................................................................................................................................. 255Logic Table .................................................................................................................................. 255Design Entry Method ................................................................................................................... 255Available Attributes ..................................................................................................................... 255For More Information ................................................................................................................... 255

FTRSLE.............................................................................................................................................. 256Introduction................................................................................................................................. 256Logic Table .................................................................................................................................. 256Design Entry Method ................................................................................................................... 256Available Attributes ..................................................................................................................... 256For More Information ................................................................................................................... 257

FTSRE................................................................................................................................................ 258Introduction................................................................................................................................. 258Logic Table .................................................................................................................................. 258Design Entry Method ................................................................................................................... 258Available Attributes ..................................................................................................................... 258For More Information ................................................................................................................... 258

FTSRLE.............................................................................................................................................. 259Introduction................................................................................................................................. 259Logic Table .................................................................................................................................. 259Design Entry Method ................................................................................................................... 259Available Attributes ..................................................................................................................... 259For More Information ................................................................................................................... 260

GND.................................................................................................................................................. 261Introduction................................................................................................................................. 261Design Entry Method ................................................................................................................... 261For More Information ................................................................................................................... 261

GTPA1_DUAL.................................................................................................................................... 262Introduction................................................................................................................................. 262Design Entry Method ................................................................................................................... 263For More Information ................................................................................................................... 263

IBUF .................................................................................................................................................. 264Introduction................................................................................................................................. 264Port Descriptions.......................................................................................................................... 264Design Entry Method ................................................................................................................... 264Available Attributes ..................................................................................................................... 264For More Information ................................................................................................................... 264

IBUF16 ............................................................................................................................................... 265Introduction................................................................................................................................. 265Design Entry Method ................................................................................................................... 265Available Attributes ..................................................................................................................... 265For More Information ................................................................................................................... 265

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IBUF4................................................................................................................................................. 266Introduction................................................................................................................................. 266Design Entry Method ................................................................................................................... 266Available Attributes ..................................................................................................................... 266For More Information ................................................................................................................... 266

IBUF8................................................................................................................................................. 267Introduction................................................................................................................................. 267Design Entry Method ................................................................................................................... 267Available Attributes ..................................................................................................................... 267For More Information ................................................................................................................... 267

IBUFDS.............................................................................................................................................. 268Introduction................................................................................................................................. 268Logic Table .................................................................................................................................. 268Port Descriptions.......................................................................................................................... 268Design Entry Method ................................................................................................................... 268Available Attributes ..................................................................................................................... 268For More Information ................................................................................................................... 268

IBUFDS_DLY_ADJ.............................................................................................................................. 269Introduction................................................................................................................................. 269Port Descriptions.......................................................................................................................... 269Design Entry Method ................................................................................................................... 269Available Attributes ..................................................................................................................... 269For More Information ................................................................................................................... 269

IBUFG................................................................................................................................................ 270Introduction................................................................................................................................. 270Port Descriptions.......................................................................................................................... 270Design Entry Method ................................................................................................................... 270Available Attributes ..................................................................................................................... 270For More Information ................................................................................................................... 270

IBUFGDS ........................................................................................................................................... 271Introduction................................................................................................................................. 271Logic Table .................................................................................................................................. 271Port Descriptions.......................................................................................................................... 271Design Entry Method ................................................................................................................... 271Available Attributes ..................................................................................................................... 271For More Information ................................................................................................................... 272

ICAP_SPARTAN6............................................................................................................................... 273Introduction................................................................................................................................. 273Port Descriptions.......................................................................................................................... 273Design Entry Method ................................................................................................................... 273For More Information ................................................................................................................... 273

IDDR2................................................................................................................................................ 274Introduction................................................................................................................................. 274Logic Table .................................................................................................................................. 274Design Entry Method ................................................................................................................... 274Available Attributes ..................................................................................................................... 275For More Information ................................................................................................................... 275

IFD .................................................................................................................................................... 276Introduction................................................................................................................................. 276Logic Table .................................................................................................................................. 276Design Entry Method ................................................................................................................... 276For More Information ................................................................................................................... 276

IFD_1 ................................................................................................................................................. 277Introduction................................................................................................................................. 277Logic Table .................................................................................................................................. 277Design Entry Method ................................................................................................................... 277For More Information ................................................................................................................... 277

IFD16 ................................................................................................................................................. 278Introduction................................................................................................................................. 278

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Logic Table .................................................................................................................................. 278Design Entry Method ................................................................................................................... 278For More Information ................................................................................................................... 278

IFD4................................................................................................................................................... 279Introduction................................................................................................................................. 279Logic Table .................................................................................................................................. 279Design Entry Method ................................................................................................................... 279For More Information ................................................................................................................... 279

IFD8................................................................................................................................................... 280Introduction................................................................................................................................. 280Logic Table .................................................................................................................................. 280Design Entry Method ................................................................................................................... 280For More Information ................................................................................................................... 280

IFDI ................................................................................................................................................... 281Introduction................................................................................................................................. 281Logic Table .................................................................................................................................. 281Design Entry Method ................................................................................................................... 281For More Information ................................................................................................................... 281

IFDI_1................................................................................................................................................ 282Introduction................................................................................................................................. 282Logic Table .................................................................................................................................. 282Design Entry Method ................................................................................................................... 282For More Information ................................................................................................................... 282

IFDX .................................................................................................................................................. 283Introduction................................................................................................................................. 283Logic Table .................................................................................................................................. 283Design Entry Method ................................................................................................................... 283For More Information ................................................................................................................... 283

IFDX_1............................................................................................................................................... 284Introduction................................................................................................................................. 284Logic Table .................................................................................................................................. 284Design Entry Method ................................................................................................................... 284For More Information ................................................................................................................... 284

IFDX16............................................................................................................................................... 285Introduction................................................................................................................................. 285Logic Table .................................................................................................................................. 285Design Entry Method ................................................................................................................... 285For More Information ................................................................................................................... 285

IFDX4 ................................................................................................................................................ 286Introduction................................................................................................................................. 286Logic Table .................................................................................................................................. 286Design Entry Method ................................................................................................................... 286For More Information ................................................................................................................... 286

IFDX8 ................................................................................................................................................ 287Introduction................................................................................................................................. 287Logic Table .................................................................................................................................. 287Design Entry Method ................................................................................................................... 287For More Information ................................................................................................................... 287

IFDXI ................................................................................................................................................. 288Introduction................................................................................................................................. 288Logic Table .................................................................................................................................. 288Design Entry Method ................................................................................................................... 288For More Information ................................................................................................................... 288

IFDXI_1.............................................................................................................................................. 289Introduction................................................................................................................................. 289Logic Table .................................................................................................................................. 289Design Entry Method ................................................................................................................... 289For More Information ................................................................................................................... 289

ILD .................................................................................................................................................... 290

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Introduction................................................................................................................................. 290Logic Table .................................................................................................................................. 290Design Entry Method ................................................................................................................... 290For More Information ................................................................................................................... 290

ILD_1................................................................................................................................................. 291Introduction................................................................................................................................. 291Logic Table .................................................................................................................................. 291Design Entry Method ................................................................................................................... 291For More Information ................................................................................................................... 291

ILD16................................................................................................................................................. 292Introduction................................................................................................................................. 292Logic Table .................................................................................................................................. 292Design Entry Method ................................................................................................................... 292For More Information ................................................................................................................... 292

ILD4 .................................................................................................................................................. 293Introduction................................................................................................................................. 293Logic Table .................................................................................................................................. 293Design Entry Method ................................................................................................................... 293For More Information ................................................................................................................... 293

ILD8 .................................................................................................................................................. 294Introduction................................................................................................................................. 294Logic Table .................................................................................................................................. 294Design Entry Method ................................................................................................................... 294For More Information ................................................................................................................... 294

ILDI ................................................................................................................................................... 295Introduction................................................................................................................................. 295Logic Table .................................................................................................................................. 295Design Entry Method ................................................................................................................... 295For More Information ................................................................................................................... 295

ILDI_1................................................................................................................................................ 296Introduction................................................................................................................................. 296Logic Table .................................................................................................................................. 296Design Entry Method ................................................................................................................... 296For More Information ................................................................................................................... 296

ILDX.................................................................................................................................................. 297Introduction................................................................................................................................. 297Logic Table .................................................................................................................................. 297Design Entry Method ................................................................................................................... 297For More Information ................................................................................................................... 297

ILDX_1............................................................................................................................................... 298Introduction................................................................................................................................. 298Logic Table .................................................................................................................................. 298Design Entry Method ................................................................................................................... 298For More Information ................................................................................................................... 298

ILDX16............................................................................................................................................... 299Introduction................................................................................................................................. 299Logic Table .................................................................................................................................. 299Design Entry Method ................................................................................................................... 299For More Information ................................................................................................................... 299

ILDX4 ................................................................................................................................................ 300Introduction................................................................................................................................. 300Logic Table .................................................................................................................................. 300Design Entry Method ................................................................................................................... 300For More Information ................................................................................................................... 300

ILDX8 ................................................................................................................................................ 301Introduction................................................................................................................................. 301Logic Table .................................................................................................................................. 301Design Entry Method ................................................................................................................... 301For More Information ................................................................................................................... 301

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ILDXI................................................................................................................................................. 302Introduction................................................................................................................................. 302Logic Table .................................................................................................................................. 302Design Entry Method ................................................................................................................... 302For More Information ................................................................................................................... 302

ILDXI_1 ............................................................................................................................................. 303Introduction................................................................................................................................. 303Logic Table .................................................................................................................................. 303Design Entry Method ................................................................................................................... 303For More Information ................................................................................................................... 303

INV.................................................................................................................................................... 304Introduction................................................................................................................................. 304Design Entry Method ................................................................................................................... 304For More Information ................................................................................................................... 304

INV16 ................................................................................................................................................ 305Introduction................................................................................................................................. 305Design Entry Method ................................................................................................................... 305For More Information ................................................................................................................... 305

INV4.................................................................................................................................................. 306Introduction................................................................................................................................. 306Design Entry Method ................................................................................................................... 306For More Information ................................................................................................................... 306

INV8.................................................................................................................................................. 307Introduction................................................................................................................................. 307Design Entry Method ................................................................................................................... 307For More Information ................................................................................................................... 307

IOBUF................................................................................................................................................ 308Introduction................................................................................................................................. 308Logic Table .................................................................................................................................. 308Port Descriptions.......................................................................................................................... 308Design Entry Method ................................................................................................................... 308Available Attributes ..................................................................................................................... 308For More Information ................................................................................................................... 309

IOBUFDS ........................................................................................................................................... 310Introduction................................................................................................................................. 310Logic Table .................................................................................................................................. 310Port Descriptions.......................................................................................................................... 310Design Entry Method ................................................................................................................... 310Available Attributes ..................................................................................................................... 310For More Information ................................................................................................................... 311

IODELAY2 ......................................................................................................................................... 312Introduction................................................................................................................................. 312Port Descriptions.......................................................................................................................... 312Design Entry Method ................................................................................................................... 313Available Attributes ..................................................................................................................... 313For More Information ................................................................................................................... 314

IODRP2.............................................................................................................................................. 315Introduction................................................................................................................................. 315For More Information ................................................................................................................... 315

ISERDES2........................................................................................................................................... 316Introduction................................................................................................................................. 316Port Descriptions.......................................................................................................................... 316Design Entry Method ................................................................................................................... 317Available Attributes ..................................................................................................................... 317For More Information ................................................................................................................... 318

KEEPER ............................................................................................................................................. 319Introduction................................................................................................................................. 319Port Descriptions.......................................................................................................................... 319Design Entry Method ................................................................................................................... 319

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For More Information ................................................................................................................... 319LD ..................................................................................................................................................... 320

Introduction................................................................................................................................. 320Logic Table .................................................................................................................................. 320Design Entry Method ................................................................................................................... 320Available Attributes ..................................................................................................................... 320For More Information ................................................................................................................... 320

LD_1.................................................................................................................................................. 321Introduction................................................................................................................................. 321Logic Table .................................................................................................................................. 321Design Entry Method ................................................................................................................... 321Available Attributes ..................................................................................................................... 321For More Information ................................................................................................................... 321

LD16.................................................................................................................................................. 322Introduction................................................................................................................................. 322Logic Table .................................................................................................................................. 322Design Entry Method ................................................................................................................... 322Available Attributes ..................................................................................................................... 322For More Information ................................................................................................................... 322

LD16CE ............................................................................................................................................. 323Introduction................................................................................................................................. 323Logic Table .................................................................................................................................. 323Design Entry Method ................................................................................................................... 323Available Attributes ..................................................................................................................... 323For More Information ................................................................................................................... 323

LD4.................................................................................................................................................... 324Introduction................................................................................................................................. 324Logic Table .................................................................................................................................. 324Design Entry Method ................................................................................................................... 324Available Attributes ..................................................................................................................... 324For More Information ................................................................................................................... 324

LD4CE ............................................................................................................................................... 325Introduction................................................................................................................................. 325Logic Table .................................................................................................................................. 325Design Entry Method ................................................................................................................... 325Available Attributes ..................................................................................................................... 325For More Information ................................................................................................................... 325

LD8.................................................................................................................................................... 326Introduction................................................................................................................................. 326Logic Table .................................................................................................................................. 326Design Entry Method ................................................................................................................... 326Available Attributes ..................................................................................................................... 326For More Information ................................................................................................................... 326

LD8CE ............................................................................................................................................... 327Introduction................................................................................................................................. 327Logic Table .................................................................................................................................. 327Design Entry Method ................................................................................................................... 327Available Attributes ..................................................................................................................... 327For More Information ................................................................................................................... 327

LDC................................................................................................................................................... 328Introduction................................................................................................................................. 328Logic Table .................................................................................................................................. 328Design Entry Method ................................................................................................................... 328Available Attributes ..................................................................................................................... 328For More Information ................................................................................................................... 328

LDC_1................................................................................................................................................ 329Introduction................................................................................................................................. 329Logic Table .................................................................................................................................. 329Design Entry Method ................................................................................................................... 329

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Available Attributes ..................................................................................................................... 329For More Information ................................................................................................................... 329

LDCE................................................................................................................................................. 330Introduction................................................................................................................................. 330Logic Table .................................................................................................................................. 330Design Entry Method ................................................................................................................... 330Available Attributes ..................................................................................................................... 330For More Information ................................................................................................................... 330

LDCE_1 ............................................................................................................................................. 331Introduction................................................................................................................................. 331Logic Table .................................................................................................................................. 331Design Entry Method ................................................................................................................... 331Available Attributes ..................................................................................................................... 331For More Information ................................................................................................................... 331

LDE ................................................................................................................................................... 332Introduction................................................................................................................................. 332Logic Table .................................................................................................................................. 332Design Entry Method ................................................................................................................... 332Available Attributes ..................................................................................................................... 332For More Information ................................................................................................................... 332

LDE_1................................................................................................................................................ 333Introduction................................................................................................................................. 333Logic Table .................................................................................................................................. 333Design Entry Method ................................................................................................................... 333Available Attributes ..................................................................................................................... 333For More Information ................................................................................................................... 333

LDP ................................................................................................................................................... 334Introduction................................................................................................................................. 334Logic Table .................................................................................................................................. 334Design Entry Method ................................................................................................................... 334Available Attributes ..................................................................................................................... 334For More Information ................................................................................................................... 334

LDP_1................................................................................................................................................ 335Introduction................................................................................................................................. 335Logic Table .................................................................................................................................. 335Design Entry Method ................................................................................................................... 335Available Attributes ..................................................................................................................... 335For More Information ................................................................................................................... 335

LDPE ................................................................................................................................................. 336Introduction................................................................................................................................. 336Logic Table .................................................................................................................................. 336Design Entry Method ................................................................................................................... 336Available Attributes ..................................................................................................................... 336For More Information ................................................................................................................... 336

LDPE_1.............................................................................................................................................. 337Introduction................................................................................................................................. 337Logic Table .................................................................................................................................. 337Design Entry Method ................................................................................................................... 337Available Attributes ..................................................................................................................... 337For More Information ................................................................................................................... 337

LUT1 ................................................................................................................................................. 338Introduction................................................................................................................................. 338Logic Table .................................................................................................................................. 338Design Entry Method ................................................................................................................... 338Available Attributes ..................................................................................................................... 338For More Information ................................................................................................................... 339

LUT1_D ............................................................................................................................................. 340Introduction................................................................................................................................. 340Logic Table .................................................................................................................................. 340

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Design Entry Method ................................................................................................................... 340Available Attributes ..................................................................................................................... 340For More Information ................................................................................................................... 340

LUT1_L.............................................................................................................................................. 341Introduction................................................................................................................................. 341Logic Table .................................................................................................................................. 341Design Entry Method ................................................................................................................... 341Available Attributes ..................................................................................................................... 341For More Information ................................................................................................................... 341

LUT2 ................................................................................................................................................. 342Introduction................................................................................................................................. 342Logic Table .................................................................................................................................. 342Design Entry Method ................................................................................................................... 342Available Attributes ..................................................................................................................... 342For More Information ................................................................................................................... 343

LUT2_D ............................................................................................................................................. 344Introduction................................................................................................................................. 344Logic Table .................................................................................................................................. 344Design Entry Method ................................................................................................................... 344Available Attributes ..................................................................................................................... 344For More Information ................................................................................................................... 344

LUT2_L.............................................................................................................................................. 345Introduction................................................................................................................................. 345Logic Table .................................................................................................................................. 345Design Entry Method ................................................................................................................... 345Available Attributes ..................................................................................................................... 345For More Information ................................................................................................................... 346

LUT3 ................................................................................................................................................. 347Introduction................................................................................................................................. 347Logic Table .................................................................................................................................. 347Design Entry Method ................................................................................................................... 347Available Attributes ..................................................................................................................... 348For More Information ................................................................................................................... 348

LUT3_D ............................................................................................................................................. 349Introduction................................................................................................................................. 349Logic Table .................................................................................................................................. 349Design Entry Method ................................................................................................................... 349Available Attributes ..................................................................................................................... 350For More Information ................................................................................................................... 350

LUT3_L.............................................................................................................................................. 351Introduction................................................................................................................................. 351Logic Table .................................................................................................................................. 351Design Entry Method ................................................................................................................... 351Available Attributes ..................................................................................................................... 352For More Information ................................................................................................................... 352

LUT4 ................................................................................................................................................. 353Introduction................................................................................................................................. 353Logic Table .................................................................................................................................. 354Design Entry Method ................................................................................................................... 354Available Attributes ..................................................................................................................... 354For More Information ................................................................................................................... 354

LUT4_D ............................................................................................................................................. 355Introduction................................................................................................................................. 355Logic Table .................................................................................................................................. 356Design Entry Method ................................................................................................................... 356Available Attributes ..................................................................................................................... 356For More Information ................................................................................................................... 356

LUT4_L.............................................................................................................................................. 357Introduction................................................................................................................................. 357

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Logic Table .................................................................................................................................. 358Design Entry Method ................................................................................................................... 358Available Attributes ..................................................................................................................... 358For More Information ................................................................................................................... 358

LUT5 ................................................................................................................................................. 359Introduction................................................................................................................................. 359Logic Table .................................................................................................................................. 360Port Description ........................................................................................................................... 361Design Entry Method ................................................................................................................... 361Available Attributes ..................................................................................................................... 361For More Information ................................................................................................................... 361

LUT5_D ............................................................................................................................................. 362Introduction................................................................................................................................. 362Logic Table .................................................................................................................................. 363Port Description ........................................................................................................................... 364Design Entry Method ................................................................................................................... 364Available Attributes ..................................................................................................................... 364For More Information ................................................................................................................... 364

LUT5_L.............................................................................................................................................. 365Introduction................................................................................................................................. 365Logic Table .................................................................................................................................. 366Port Description ........................................................................................................................... 367Design Entry Method ................................................................................................................... 367Available Attributes ..................................................................................................................... 367For More Information ................................................................................................................... 367

LUT6 ................................................................................................................................................. 368Introduction................................................................................................................................. 368Logic Table .................................................................................................................................. 368Port Description ........................................................................................................................... 370Design Entry Method ................................................................................................................... 370Available Attributes ..................................................................................................................... 370For More Information ................................................................................................................... 370

LUT6_2 .............................................................................................................................................. 371Introduction................................................................................................................................. 371Logic Table .................................................................................................................................. 371Port Descriptions.......................................................................................................................... 373Design Entry Method ................................................................................................................... 373Available Attributes ..................................................................................................................... 373For More Information ................................................................................................................... 373

LUT6_D ............................................................................................................................................. 374Introduction................................................................................................................................. 374Logic Table .................................................................................................................................. 374Port Description ........................................................................................................................... 376Design Entry Method ................................................................................................................... 376Available Attributes ..................................................................................................................... 376For More Information ................................................................................................................... 376

LUT6_L.............................................................................................................................................. 377Introduction................................................................................................................................. 377Logic Table .................................................................................................................................. 377Port Description ........................................................................................................................... 379Design Entry Method ................................................................................................................... 379Available Attributes ..................................................................................................................... 379For More Information ................................................................................................................... 379

M16_1E .............................................................................................................................................. 380Introduction................................................................................................................................. 380Logic Table .................................................................................................................................. 380Design Entry Method ................................................................................................................... 381For More Information ................................................................................................................... 381

M2_1.................................................................................................................................................. 382

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Introduction................................................................................................................................. 382Logic Table .................................................................................................................................. 382Design Entry Method ................................................................................................................... 382For More Information ................................................................................................................... 382

M2_1B1 .............................................................................................................................................. 383Introduction................................................................................................................................. 383Logic Table .................................................................................................................................. 383Design Entry Method ................................................................................................................... 383For More Information ................................................................................................................... 383

M2_1B2 .............................................................................................................................................. 384Introduction................................................................................................................................. 384Logic Table .................................................................................................................................. 384Design Entry Method ................................................................................................................... 384For More Information ................................................................................................................... 384

M2_1E................................................................................................................................................ 385Introduction................................................................................................................................. 385Logic Table .................................................................................................................................. 385Design Entry Method ................................................................................................................... 385For More Information ................................................................................................................... 385

M4_1E................................................................................................................................................ 386Introduction................................................................................................................................. 386Logic Table .................................................................................................................................. 386Design Entry Method ................................................................................................................... 386For More Information ................................................................................................................... 386

M8_1E................................................................................................................................................ 387Introduction................................................................................................................................. 387Logic Table .................................................................................................................................. 387Design Entry Method ................................................................................................................... 387For More Information ................................................................................................................... 387

MULT_AND....................................................................................................................................... 388Introduction................................................................................................................................. 388Logic Table .................................................................................................................................. 388Design Entry Method ................................................................................................................... 388For More Information ................................................................................................................... 388

MULT18X18SIO.................................................................................................................................. 389Introduction................................................................................................................................. 389Design Entry Method ................................................................................................................... 389Available Attributes ..................................................................................................................... 389For More Information ................................................................................................................... 389

MUXCY ............................................................................................................................................. 390Introduction................................................................................................................................. 390Logic Table .................................................................................................................................. 390Design Entry Method ................................................................................................................... 390For More Information ................................................................................................................... 390

MUXCY_D ......................................................................................................................................... 391Introduction................................................................................................................................. 391Logic Table .................................................................................................................................. 391Design Entry Method ................................................................................................................... 391For More Information ................................................................................................................... 391

MUXCY_L.......................................................................................................................................... 392Introduction................................................................................................................................. 392Logic Table .................................................................................................................................. 392Design Entry Method ................................................................................................................... 392For More Information ................................................................................................................... 392

MUXF5 .............................................................................................................................................. 393Introduction................................................................................................................................. 393Logic Table .................................................................................................................................. 393Design Entry Method ................................................................................................................... 393For More Information ................................................................................................................... 393

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MUXF5_D .......................................................................................................................................... 394Introduction................................................................................................................................. 394Logic Table .................................................................................................................................. 394Design Entry Method ................................................................................................................... 394For More Information ................................................................................................................... 394

MUXF5_L........................................................................................................................................... 395Introduction................................................................................................................................. 395Logic Table .................................................................................................................................. 395Design Entry Method ................................................................................................................... 395For More Information ................................................................................................................... 395

MUXF6 .............................................................................................................................................. 396Introduction................................................................................................................................. 396Logic Table .................................................................................................................................. 396Design Entry Method ................................................................................................................... 396For More Information ................................................................................................................... 396

MUXF6_D .......................................................................................................................................... 397Introduction................................................................................................................................. 397Logic Table .................................................................................................................................. 397Design Entry Method ................................................................................................................... 397For More Information ................................................................................................................... 397

MUXF6_L........................................................................................................................................... 398Introduction................................................................................................................................. 398Logic Table .................................................................................................................................. 398Design Entry Method ................................................................................................................... 398For More Information ................................................................................................................... 398

MUXF7 .............................................................................................................................................. 399Introduction................................................................................................................................. 399Logic Table .................................................................................................................................. 399Port Descriptions.......................................................................................................................... 399Design Entry Method ................................................................................................................... 399For More Information ................................................................................................................... 399

MUXF7_D .......................................................................................................................................... 400Introduction................................................................................................................................. 400Logic Table .................................................................................................................................. 400Port Descriptions.......................................................................................................................... 400Design Entry Method ................................................................................................................... 400For More Information ................................................................................................................... 400

MUXF7_L........................................................................................................................................... 401Introduction................................................................................................................................. 401Logic Table .................................................................................................................................. 401Port Descriptions.......................................................................................................................... 401Design Entry Method ................................................................................................................... 401For More Information ................................................................................................................... 401

MUXF8 .............................................................................................................................................. 402Introduction................................................................................................................................. 402Logic Table .................................................................................................................................. 402Port Descriptions.......................................................................................................................... 402Design Entry Method ................................................................................................................... 402For More Information ................................................................................................................... 402

MUXF8_D .......................................................................................................................................... 403Introduction................................................................................................................................. 403Logic Table .................................................................................................................................. 403Port Descriptions.......................................................................................................................... 403Design Entry Method ................................................................................................................... 403For More Information ................................................................................................................... 403

MUXF8_L........................................................................................................................................... 404Introduction................................................................................................................................. 404Logic Table .................................................................................................................................. 404Port Descriptions.......................................................................................................................... 404

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Design Entry Method ................................................................................................................... 404For More Information ................................................................................................................... 404

NAND12............................................................................................................................................ 405Introduction................................................................................................................................. 405Design Entry Method ................................................................................................................... 405For More Information ................................................................................................................... 405

NAND16............................................................................................................................................ 406Introduction................................................................................................................................. 406Design Entry Method ................................................................................................................... 406For More Information ................................................................................................................... 406

NAND2 ............................................................................................................................................. 407Introduction................................................................................................................................. 407Design Entry Method ................................................................................................................... 407For More Information ................................................................................................................... 407

NAND2B1.......................................................................................................................................... 408Introduction................................................................................................................................. 408Design Entry Method ................................................................................................................... 408For More Information ................................................................................................................... 408

NAND2B2.......................................................................................................................................... 409Introduction................................................................................................................................. 409Design Entry Method ................................................................................................................... 409For More Information ................................................................................................................... 409

NAND3 ............................................................................................................................................. 410Introduction................................................................................................................................. 410Design Entry Method ................................................................................................................... 410For More Information ................................................................................................................... 410

NAND3B1.......................................................................................................................................... 411Introduction................................................................................................................................. 411Design Entry Method ................................................................................................................... 411For More Information ................................................................................................................... 411

NAND3B2.......................................................................................................................................... 412Introduction................................................................................................................................. 412Design Entry Method ................................................................................................................... 412For More Information ................................................................................................................... 412

NAND3B3.......................................................................................................................................... 413Introduction................................................................................................................................. 413Design Entry Method ................................................................................................................... 413For More Information ................................................................................................................... 413

NAND4 ............................................................................................................................................. 414Introduction................................................................................................................................. 414Design Entry Method ................................................................................................................... 414For More Information ................................................................................................................... 414

NAND4B1.......................................................................................................................................... 415Introduction................................................................................................................................. 415Design Entry Method ................................................................................................................... 415For More Information ................................................................................................................... 415

NAND4B2.......................................................................................................................................... 416Introduction................................................................................................................................. 416Design Entry Method ................................................................................................................... 416For More Information ................................................................................................................... 416

NAND4B3.......................................................................................................................................... 417Introduction................................................................................................................................. 417Design Entry Method ................................................................................................................... 417For More Information ................................................................................................................... 417

NAND4B4.......................................................................................................................................... 418Introduction................................................................................................................................. 418Design Entry Method ................................................................................................................... 418For More Information ................................................................................................................... 418

NAND5 ............................................................................................................................................. 419

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Introduction................................................................................................................................. 419Design Entry Method ................................................................................................................... 419For More Information ................................................................................................................... 419

NAND5B1.......................................................................................................................................... 420Introduction................................................................................................................................. 420Design Entry Method ................................................................................................................... 420For More Information ................................................................................................................... 420

NAND5B2.......................................................................................................................................... 421Introduction................................................................................................................................. 421Design Entry Method ................................................................................................................... 421For More Information ................................................................................................................... 421

NAND5B3.......................................................................................................................................... 422Introduction................................................................................................................................. 422Design Entry Method ................................................................................................................... 422For More Information ................................................................................................................... 422

NAND5B4.......................................................................................................................................... 423Introduction................................................................................................................................. 423Design Entry Method ................................................................................................................... 423For More Information ................................................................................................................... 423

NAND5B5.......................................................................................................................................... 424Introduction................................................................................................................................. 424Design Entry Method ................................................................................................................... 424For More Information ................................................................................................................... 424

NAND6 ............................................................................................................................................. 425Introduction................................................................................................................................. 425Design Entry Method ................................................................................................................... 425For More Information ................................................................................................................... 425

NAND7 ............................................................................................................................................. 426Introduction................................................................................................................................. 426Design Entry Method ................................................................................................................... 426For More Information ................................................................................................................... 426

NAND8 ............................................................................................................................................. 427Introduction................................................................................................................................. 427Design Entry Method ................................................................................................................... 427For More Information ................................................................................................................... 427

NAND9 ............................................................................................................................................. 428Introduction................................................................................................................................. 428Design Entry Method ................................................................................................................... 428For More Information ................................................................................................................... 428

NOR12............................................................................................................................................... 429Introduction................................................................................................................................. 429Design Entry Method ................................................................................................................... 429For More Information ................................................................................................................... 429

NOR16............................................................................................................................................... 430Introduction................................................................................................................................. 430Design Entry Method ................................................................................................................... 430For More Information ................................................................................................................... 430

NOR2................................................................................................................................................. 431Introduction................................................................................................................................. 431Design Entry Method ................................................................................................................... 431For More Information ................................................................................................................... 431

NOR2B1............................................................................................................................................. 432Introduction................................................................................................................................. 432Design Entry Method ................................................................................................................... 432For More Information ................................................................................................................... 432

NOR2B2............................................................................................................................................. 433Introduction................................................................................................................................. 433Design Entry Method ................................................................................................................... 433For More Information ................................................................................................................... 433

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NOR3................................................................................................................................................. 434Introduction................................................................................................................................. 434Design Entry Method ................................................................................................................... 434For More Information ................................................................................................................... 434

NOR3B1............................................................................................................................................. 435Introduction................................................................................................................................. 435Design Entry Method ................................................................................................................... 435For More Information ................................................................................................................... 435

NOR3B2............................................................................................................................................. 436Introduction................................................................................................................................. 436Design Entry Method ................................................................................................................... 436For More Information ................................................................................................................... 436

NOR3B3............................................................................................................................................. 437Introduction................................................................................................................................. 437Design Entry Method ................................................................................................................... 437For More Information ................................................................................................................... 437

NOR4................................................................................................................................................. 438Introduction................................................................................................................................. 438Design Entry Method ................................................................................................................... 438For More Information ................................................................................................................... 438

NOR4B1............................................................................................................................................. 439Introduction................................................................................................................................. 439Design Entry Method ................................................................................................................... 439For More Information ................................................................................................................... 439

NOR4B2............................................................................................................................................. 440Introduction................................................................................................................................. 440Design Entry Method ................................................................................................................... 440For More Information ................................................................................................................... 440

NOR4B3............................................................................................................................................. 441Introduction................................................................................................................................. 441Design Entry Method ................................................................................................................... 441For More Information ................................................................................................................... 441

NOR4B4............................................................................................................................................. 442Introduction................................................................................................................................. 442Design Entry Method ................................................................................................................... 442For More Information ................................................................................................................... 442

NOR5................................................................................................................................................. 443Introduction................................................................................................................................. 443Design Entry Method ................................................................................................................... 443For More Information ................................................................................................................... 443

NOR5B1............................................................................................................................................. 444Introduction................................................................................................................................. 444Design Entry Method ................................................................................................................... 444For More Information ................................................................................................................... 444

NOR5B2............................................................................................................................................. 445Introduction................................................................................................................................. 445Design Entry Method ................................................................................................................... 445For More Information ................................................................................................................... 445

NOR5B3............................................................................................................................................. 446Introduction................................................................................................................................. 446Design Entry Method ................................................................................................................... 446For More Information ................................................................................................................... 446

NOR5B4............................................................................................................................................. 447Introduction................................................................................................................................. 447Design Entry Method ................................................................................................................... 447For More Information ................................................................................................................... 447

NOR5B5............................................................................................................................................. 448Introduction................................................................................................................................. 448Design Entry Method ................................................................................................................... 448

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For More Information ................................................................................................................... 448NOR6................................................................................................................................................. 449

Introduction................................................................................................................................. 449Design Entry Method ................................................................................................................... 449For More Information ................................................................................................................... 449

NOR7................................................................................................................................................. 450Introduction................................................................................................................................. 450Design Entry Method ................................................................................................................... 450For More Information ................................................................................................................... 450

NOR8................................................................................................................................................. 451Introduction................................................................................................................................. 451Design Entry Method ................................................................................................................... 451For More Information ................................................................................................................... 451

NOR9................................................................................................................................................. 452Introduction................................................................................................................................. 452Design Entry Method ................................................................................................................... 452For More Information ................................................................................................................... 452

OBUF................................................................................................................................................. 453Introduction................................................................................................................................. 453Port Descriptions.......................................................................................................................... 453Design Entry Method ................................................................................................................... 453Available Attributes ..................................................................................................................... 453For More Information ................................................................................................................... 453

OBUF16 ............................................................................................................................................. 454Introduction................................................................................................................................. 454Design Entry Method ................................................................................................................... 454Available Attributes ..................................................................................................................... 454For More Information ................................................................................................................... 454

OBUF4 ............................................................................................................................................... 455Introduction................................................................................................................................. 455Design Entry Method ................................................................................................................... 455Available Attributes ..................................................................................................................... 455For More Information ................................................................................................................... 455

OBUF8 ............................................................................................................................................... 456Introduction................................................................................................................................. 456Design Entry Method ................................................................................................................... 456Available Attributes ..................................................................................................................... 456For More Information ................................................................................................................... 456

OBUFDS ............................................................................................................................................ 457Introduction................................................................................................................................. 457Logic Table .................................................................................................................................. 457Port Descriptions.......................................................................................................................... 457Design Entry Method ................................................................................................................... 457Available Attributes ..................................................................................................................... 457For More Information ................................................................................................................... 457

OBUFT............................................................................................................................................... 458Introduction................................................................................................................................. 458Logic Table .................................................................................................................................. 458Port Descriptions.......................................................................................................................... 458Design Entry Method ................................................................................................................... 458Available Attributes ..................................................................................................................... 458For More Information ................................................................................................................... 458

OBUFT16 ........................................................................................................................................... 459Introduction................................................................................................................................. 459Logic Table .................................................................................................................................. 459Design Entry Method ................................................................................................................... 459Available Attributes ..................................................................................................................... 459For More Information ................................................................................................................... 459

OBUFT4 ............................................................................................................................................. 460

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Introduction................................................................................................................................. 460Logic Table .................................................................................................................................. 460Design Entry Method ................................................................................................................... 460Available Attributes ..................................................................................................................... 460For More Information ................................................................................................................... 460

OBUFT8 ............................................................................................................................................. 461Introduction................................................................................................................................. 461Logic Table .................................................................................................................................. 461Design Entry Method ................................................................................................................... 461Available Attributes ..................................................................................................................... 461For More Information ................................................................................................................... 461

OBUFTDS .......................................................................................................................................... 462Introduction................................................................................................................................. 462Logic Table .................................................................................................................................. 462Port Descriptions.......................................................................................................................... 462Design Entry Method ................................................................................................................... 462Available Attributes ..................................................................................................................... 462For More Information ................................................................................................................... 462

ODDR2 .............................................................................................................................................. 463Introduction................................................................................................................................. 463Logic Table .................................................................................................................................. 463Design Entry Method ................................................................................................................... 463Available Attributes ..................................................................................................................... 464For More Information ................................................................................................................... 464

OFD................................................................................................................................................... 465Introduction................................................................................................................................. 465Logic Table .................................................................................................................................. 465Design Entry Method ................................................................................................................... 465For More Information ................................................................................................................... 465

OFD_1 ............................................................................................................................................... 466Introduction................................................................................................................................. 466Logic Table .................................................................................................................................. 466Design Entry Method ................................................................................................................... 466For More Information ................................................................................................................... 466

OFD16 ............................................................................................................................................... 467Introduction................................................................................................................................. 467Logic Table .................................................................................................................................. 467Design Entry Method ................................................................................................................... 467For More Information ................................................................................................................... 467

OFD4 ................................................................................................................................................. 468Introduction................................................................................................................................. 468Logic Table .................................................................................................................................. 468Design Entry Method ................................................................................................................... 468For More Information ................................................................................................................... 468

OFD8 ................................................................................................................................................. 469Introduction................................................................................................................................. 469Logic Table .................................................................................................................................. 469Design Entry Method ................................................................................................................... 469For More Information ................................................................................................................... 469

OFDE................................................................................................................................................. 470Introduction................................................................................................................................. 470Logic Table .................................................................................................................................. 470Design Entry Method ................................................................................................................... 470For More Information ................................................................................................................... 470

OFDE_1 ............................................................................................................................................. 471Introduction................................................................................................................................. 471Logic Table .................................................................................................................................. 471Design Entry Method ................................................................................................................... 471For More Information ................................................................................................................... 471

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OFDE16 ............................................................................................................................................. 472Introduction................................................................................................................................. 472Logic Table .................................................................................................................................. 472Design Entry Method ................................................................................................................... 472For More Information ................................................................................................................... 472

OFDE4 ............................................................................................................................................... 473Introduction................................................................................................................................. 473Logic Table .................................................................................................................................. 473Design Entry Method ................................................................................................................... 473For More Information ................................................................................................................... 473

OFDE8 ............................................................................................................................................... 474Introduction................................................................................................................................. 474Logic Table .................................................................................................................................. 474Design Entry Method ................................................................................................................... 474For More Information ................................................................................................................... 474

OFDI.................................................................................................................................................. 475Introduction................................................................................................................................. 475Logic Table .................................................................................................................................. 475Design Entry Method ................................................................................................................... 475For More Information ................................................................................................................... 475

OFDI_1 .............................................................................................................................................. 476Introduction................................................................................................................................. 476Logic Table .................................................................................................................................. 476Design Entry Method ................................................................................................................... 476For More Information ................................................................................................................... 476

OFDT................................................................................................................................................. 477Introduction................................................................................................................................. 477Logic Table .................................................................................................................................. 477Design Entry Method ................................................................................................................... 477For More Information ................................................................................................................... 477

OFDT_1 ............................................................................................................................................. 478Introduction................................................................................................................................. 478Logic Table .................................................................................................................................. 478Design Entry Method ................................................................................................................... 478For More Information ................................................................................................................... 478

OFDT16 ............................................................................................................................................. 479Introduction................................................................................................................................. 479Logic Table .................................................................................................................................. 479Design Entry Method ................................................................................................................... 479For More Information ................................................................................................................... 479

OFDT4 ............................................................................................................................................... 480Introduction................................................................................................................................. 480Logic Table .................................................................................................................................. 480Design Entry Method ................................................................................................................... 480For More Information ................................................................................................................... 480

OFDT8 ............................................................................................................................................... 481Introduction................................................................................................................................. 481Logic Table .................................................................................................................................. 481Design Entry Method ................................................................................................................... 481For More Information ................................................................................................................... 481

OFDX................................................................................................................................................. 482Introduction................................................................................................................................. 482Logic Table .................................................................................................................................. 482Design Entry Method ................................................................................................................... 482For More Information ................................................................................................................... 482

OFDX_1 ............................................................................................................................................. 483Introduction................................................................................................................................. 483Logic Table .................................................................................................................................. 483Design Entry Method ................................................................................................................... 483

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For More Information ................................................................................................................... 483OFDX16 ............................................................................................................................................. 484

Introduction................................................................................................................................. 484Logic Table .................................................................................................................................. 484Design Entry Method ................................................................................................................... 484For More Information ................................................................................................................... 484

OFDX4............................................................................................................................................... 485Introduction................................................................................................................................. 485Logic Table .................................................................................................................................. 485Design Entry Method ................................................................................................................... 485For More Information ................................................................................................................... 485

OFDX8............................................................................................................................................... 486Introduction................................................................................................................................. 486Logic Table .................................................................................................................................. 486Design Entry Method ................................................................................................................... 486For More Information ................................................................................................................... 486

OFDXI ............................................................................................................................................... 487Introduction................................................................................................................................. 487Logic Table .................................................................................................................................. 487Design Entry Method ................................................................................................................... 487For More Information ................................................................................................................... 487

OFDXI_1 ............................................................................................................................................ 488Introduction................................................................................................................................. 488Logic Table .................................................................................................................................. 488Design Entry Method ................................................................................................................... 488For More Information ................................................................................................................... 488

OR12.................................................................................................................................................. 489Introduction................................................................................................................................. 489Design Entry Method ................................................................................................................... 489For More Information ................................................................................................................... 489

OR16.................................................................................................................................................. 490Introduction................................................................................................................................. 490Design Entry Method ................................................................................................................... 490For More Information ................................................................................................................... 490

OR2 ................................................................................................................................................... 491Introduction................................................................................................................................. 491Design Entry Method ................................................................................................................... 491For More Information ................................................................................................................... 491

OR2B1................................................................................................................................................ 492Introduction................................................................................................................................. 492Design Entry Method ................................................................................................................... 492For More Information ................................................................................................................... 492

OR2B2................................................................................................................................................ 493Introduction................................................................................................................................. 493Design Entry Method ................................................................................................................... 493For More Information ................................................................................................................... 493

OR2L ................................................................................................................................................. 494Introduction................................................................................................................................. 494Logic Table .................................................................................................................................. 494Port Descriptions.......................................................................................................................... 494Design Entry Method ................................................................................................................... 494For More Information ................................................................................................................... 494

OR3 ................................................................................................................................................... 495Introduction................................................................................................................................. 495Design Entry Method ................................................................................................................... 495For More Information ................................................................................................................... 495

OR3B1................................................................................................................................................ 496Introduction................................................................................................................................. 496Design Entry Method ................................................................................................................... 496

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For More Information ................................................................................................................... 496OR3B2................................................................................................................................................ 497

Introduction................................................................................................................................. 497Design Entry Method ................................................................................................................... 497For More Information ................................................................................................................... 497

OR3B3................................................................................................................................................ 498Introduction................................................................................................................................. 498Design Entry Method ................................................................................................................... 498For More Information ................................................................................................................... 498

OR4 ................................................................................................................................................... 499Introduction................................................................................................................................. 499Design Entry Method ................................................................................................................... 499For More Information ................................................................................................................... 499

OR4B1................................................................................................................................................ 500Introduction................................................................................................................................. 500Design Entry Method ................................................................................................................... 500For More Information ................................................................................................................... 500

OR4B2................................................................................................................................................ 501Introduction................................................................................................................................. 501Design Entry Method ................................................................................................................... 501For More Information ................................................................................................................... 501

OR4B3................................................................................................................................................ 502Introduction................................................................................................................................. 502Design Entry Method ................................................................................................................... 502For More Information ................................................................................................................... 502

OR4B4................................................................................................................................................ 503Introduction................................................................................................................................. 503Design Entry Method ................................................................................................................... 503For More Information ................................................................................................................... 503

OR5 ................................................................................................................................................... 504Introduction................................................................................................................................. 504Design Entry Method ................................................................................................................... 504For More Information ................................................................................................................... 504

OR5B1................................................................................................................................................ 505Introduction................................................................................................................................. 505Design Entry Method ................................................................................................................... 505For More Information ................................................................................................................... 505

OR5B2................................................................................................................................................ 506Introduction................................................................................................................................. 506Design Entry Method ................................................................................................................... 506For More Information ................................................................................................................... 506

OR5B3................................................................................................................................................ 507Introduction................................................................................................................................. 507Design Entry Method ................................................................................................................... 507For More Information ................................................................................................................... 507

OR5B4................................................................................................................................................ 508Introduction................................................................................................................................. 508Design Entry Method ................................................................................................................... 508For More Information ................................................................................................................... 508

OR5B5................................................................................................................................................ 509Introduction................................................................................................................................. 509Design Entry Method ................................................................................................................... 509For More Information ................................................................................................................... 509

OR6 ................................................................................................................................................... 510Introduction................................................................................................................................. 510Design Entry Method ................................................................................................................... 510For More Information ................................................................................................................... 510

OR7 ................................................................................................................................................... 511Introduction................................................................................................................................. 511

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Design Entry Method ................................................................................................................... 511For More Information ................................................................................................................... 511

OR8 ................................................................................................................................................... 512Introduction................................................................................................................................. 512Design Entry Method ................................................................................................................... 512For More Information ................................................................................................................... 512

OR9 ................................................................................................................................................... 513Introduction................................................................................................................................. 513Design Entry Method ................................................................................................................... 513For More Information ................................................................................................................... 513

OSERDES2 ......................................................................................................................................... 514Introduction................................................................................................................................. 514Port Descriptions.......................................................................................................................... 515Design Entry Method ................................................................................................................... 515Available Attributes ..................................................................................................................... 516For More Information ................................................................................................................... 516

PCIE_A1 ............................................................................................................................................ 517Introduction................................................................................................................................. 518Design Entry Method ................................................................................................................... 518For More Information ................................................................................................................... 518

PLL_BASE.......................................................................................................................................... 519Introduction................................................................................................................................. 519Port Descriptions.......................................................................................................................... 519Design Entry Method ................................................................................................................... 519Available Attributes ..................................................................................................................... 520For More Information ................................................................................................................... 521

POST_CRC_INTERNAL...................................................................................................................... 522Introduction................................................................................................................................. 522Port Descriptions.......................................................................................................................... 522Design Entry Method ................................................................................................................... 522For More Information ................................................................................................................... 522

PULLDOWN...................................................................................................................................... 523Introduction................................................................................................................................. 523Port Descriptions.......................................................................................................................... 523Design Entry Method ................................................................................................................... 523For More Information ................................................................................................................... 523

PULLUP............................................................................................................................................. 524Introduction................................................................................................................................. 524Port Descriptions.......................................................................................................................... 524Design Entry Method ................................................................................................................... 524For More Information ................................................................................................................... 524

RAM128X1D ...................................................................................................................................... 525Introduction................................................................................................................................. 525Port Descriptions.......................................................................................................................... 525Design Entry Method ................................................................................................................... 525Available Attributes ..................................................................................................................... 526For More Information ................................................................................................................... 526

RAM16X1D ........................................................................................................................................ 527Introduction................................................................................................................................. 527Logic Table .................................................................................................................................. 527Design Entry Method ................................................................................................................... 528Available Attributes ..................................................................................................................... 528For More Information ................................................................................................................... 528

RAM16X1D_1..................................................................................................................................... 529Introduction................................................................................................................................. 529Logic Table .................................................................................................................................. 529Port Descriptions.......................................................................................................................... 530Design Entry Method ................................................................................................................... 530Available Attributes ..................................................................................................................... 530

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For More Information ................................................................................................................... 530RAM16X1S......................................................................................................................................... 531

Introduction................................................................................................................................. 531Logic Table .................................................................................................................................. 531Design Entry Method ................................................................................................................... 531Available Attributes ..................................................................................................................... 531For More Information ................................................................................................................... 531

RAM16X1S_1...................................................................................................................................... 532Introduction................................................................................................................................. 532Logic Table .................................................................................................................................. 532Design Entry Method ................................................................................................................... 532Available Attributes ..................................................................................................................... 532For More Information ................................................................................................................... 533

RAM16X2S......................................................................................................................................... 534Introduction................................................................................................................................. 534Logic Table .................................................................................................................................. 534Design Entry Method ................................................................................................................... 534Available Attributes ..................................................................................................................... 535For More Information ................................................................................................................... 535

RAM16X4S......................................................................................................................................... 536Introduction................................................................................................................................. 536Logic Table .................................................................................................................................. 536Design Entry Method ................................................................................................................... 536Available Attributes ..................................................................................................................... 536For More Information ................................................................................................................... 537

RAM16X8S......................................................................................................................................... 538Introduction................................................................................................................................. 538Logic Table .................................................................................................................................. 538Design Entry Method ................................................................................................................... 538Available Attributes ..................................................................................................................... 538For More Information ................................................................................................................... 538

RAM256X1S ....................................................................................................................................... 539Introduction................................................................................................................................. 539Port Descriptions.......................................................................................................................... 539Design Entry Method ................................................................................................................... 539Available Attributes ..................................................................................................................... 539For More Information ................................................................................................................... 540

RAM32M ........................................................................................................................................... 541Introduction................................................................................................................................. 541Port Descriptions.......................................................................................................................... 541Design Entry Method ................................................................................................................... 542Available Attributes ..................................................................................................................... 542For More Information ................................................................................................................... 542

RAM32X1S......................................................................................................................................... 543Introduction................................................................................................................................. 543Logic Table .................................................................................................................................. 543Design Entry Method ................................................................................................................... 543Available Attributes ..................................................................................................................... 543For More Information ................................................................................................................... 543

RAM32X1S_1...................................................................................................................................... 544Introduction................................................................................................................................. 544Logic Table .................................................................................................................................. 544Design Entry Method ................................................................................................................... 544Available Attributes ..................................................................................................................... 544For More Information ................................................................................................................... 544

RAM32X2S......................................................................................................................................... 545Introduction................................................................................................................................. 545Logic Table .................................................................................................................................. 545Design Entry Method ................................................................................................................... 545

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Available Attributes ..................................................................................................................... 545For More Information ................................................................................................................... 546

RAM32X4S......................................................................................................................................... 547Introduction................................................................................................................................. 547Logic Table .................................................................................................................................. 547Design Entry Method ................................................................................................................... 547Available Attributes ..................................................................................................................... 548For More Information ................................................................................................................... 548

RAM32X8S......................................................................................................................................... 549Introduction................................................................................................................................. 549Logic Table .................................................................................................................................. 549Design Entry Method ................................................................................................................... 549Available Attributes ..................................................................................................................... 550For More Information ................................................................................................................... 550

RAM64M ........................................................................................................................................... 551Introduction................................................................................................................................. 551Port Descriptions.......................................................................................................................... 552Design Entry Method ................................................................................................................... 552Available Attributes ..................................................................................................................... 553For More Information ................................................................................................................... 553

RAM64X1D ........................................................................................................................................ 554Introduction................................................................................................................................. 554Logic Table .................................................................................................................................. 554Design Entry Method ................................................................................................................... 554Available Attributes ..................................................................................................................... 555For More Information ................................................................................................................... 555

RAM64X1S......................................................................................................................................... 556Introduction................................................................................................................................. 556Logic Table .................................................................................................................................. 556Design Entry Method ................................................................................................................... 556Available Attributes ..................................................................................................................... 556For More Information ................................................................................................................... 557

RAM64X1S_1...................................................................................................................................... 558Introduction................................................................................................................................. 558Logic Table .................................................................................................................................. 558Design Entry Method ................................................................................................................... 558Available Attributes ..................................................................................................................... 558For More Information ................................................................................................................... 558

RAM64X2S......................................................................................................................................... 559Introduction................................................................................................................................. 559Logic Table .................................................................................................................................. 559Design Entry Method ................................................................................................................... 559Available Attributes ..................................................................................................................... 559For More Information ................................................................................................................... 560

RAMB16BWER................................................................................................................................... 561Introduction................................................................................................................................. 561Port Descriptions.......................................................................................................................... 561Design Entry Method ................................................................................................................... 562Available Attributes ..................................................................................................................... 562For More Information ................................................................................................................... 564

RAMB8BWER..................................................................................................................................... 565Introduction................................................................................................................................. 565Port Descriptions.......................................................................................................................... 565Design Entry Method ................................................................................................................... 567Available Attributes ..................................................................................................................... 567For More Information ................................................................................................................... 568

ROM128X1 ......................................................................................................................................... 569Introduction................................................................................................................................. 569Logic Table .................................................................................................................................. 569

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Design Entry Method ................................................................................................................... 569Available Attributes ..................................................................................................................... 570For More Information ................................................................................................................... 570

ROM16X1........................................................................................................................................... 571Introduction................................................................................................................................. 571Logic Table .................................................................................................................................. 571Design Entry Method ................................................................................................................... 571Available Attributes ..................................................................................................................... 572For More Information ................................................................................................................... 572

ROM256X1 ......................................................................................................................................... 573Introduction................................................................................................................................. 573Logic Table .................................................................................................................................. 573Design Entry Method ................................................................................................................... 574Available Attributes ..................................................................................................................... 574For More Information ................................................................................................................... 574

ROM32X1........................................................................................................................................... 575Introduction................................................................................................................................. 575Logic Table .................................................................................................................................. 575Design Entry Method ................................................................................................................... 575Available Attributes ..................................................................................................................... 576For More Information ................................................................................................................... 576

ROM64X1........................................................................................................................................... 577Introduction................................................................................................................................. 577Logic Table .................................................................................................................................. 577Design Entry Method ................................................................................................................... 577Available Attributes ..................................................................................................................... 578For More Information ................................................................................................................... 578

SOP3.................................................................................................................................................. 579Introduction................................................................................................................................. 579Design Entry Method ................................................................................................................... 579For More Information ................................................................................................................... 579

SOP3B1A ........................................................................................................................................... 580Introduction................................................................................................................................. 580Design Entry Method ................................................................................................................... 580For More Information ................................................................................................................... 580

SOP3B1B ............................................................................................................................................ 581Introduction................................................................................................................................. 581Design Entry Method ................................................................................................................... 581For More Information ................................................................................................................... 581

SOP3B2A ........................................................................................................................................... 582Introduction................................................................................................................................. 582Design Entry Method ................................................................................................................... 582For More Information ................................................................................................................... 582

SOP3B2B ............................................................................................................................................ 583Introduction................................................................................................................................. 583Design Entry Method ................................................................................................................... 583For More Information ................................................................................................................... 583

SOP3B3 .............................................................................................................................................. 584Introduction................................................................................................................................. 584Design Entry Method ................................................................................................................... 584For More Information ................................................................................................................... 584

SOP4.................................................................................................................................................. 585Introduction................................................................................................................................. 585Design Entry Method ................................................................................................................... 585For More Information ................................................................................................................... 585

SOP4B1 .............................................................................................................................................. 586Introduction................................................................................................................................. 586Design Entry Method ................................................................................................................... 586For More Information ................................................................................................................... 586

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SOP4B2A ........................................................................................................................................... 587Introduction................................................................................................................................. 587Design Entry Method ................................................................................................................... 587For More Information ................................................................................................................... 587

SOP4B2B ............................................................................................................................................ 588Introduction................................................................................................................................. 588Design Entry Method ................................................................................................................... 588For More Information ................................................................................................................... 588

SOP4B3 .............................................................................................................................................. 589Introduction................................................................................................................................. 589Design Entry Method ................................................................................................................... 589For More Information ................................................................................................................... 589

SOP4B4 .............................................................................................................................................. 590Introduction................................................................................................................................. 590Design Entry Method ................................................................................................................... 590For More Information ................................................................................................................... 590

SPI_ACCESS ...................................................................................................................................... 591Introduction................................................................................................................................. 591Port Descriptions.......................................................................................................................... 591Design Entry Method ................................................................................................................... 591Available Attributes ..................................................................................................................... 591For More Information ................................................................................................................... 592

SR16CE .............................................................................................................................................. 593Introduction................................................................................................................................. 593Logic Table .................................................................................................................................. 593Design Entry Method ................................................................................................................... 593For More Information ................................................................................................................... 593

SR16CLE ............................................................................................................................................ 594Introduction................................................................................................................................. 594Logic Table .................................................................................................................................. 594Design Entry Method ................................................................................................................... 594For More Information ................................................................................................................... 595

SR16CLED.......................................................................................................................................... 596Introduction................................................................................................................................. 596Logic Table .................................................................................................................................. 596Design Entry Method ................................................................................................................... 596For More Information ................................................................................................................... 597

SR16RE .............................................................................................................................................. 598Introduction................................................................................................................................. 598Logic Table .................................................................................................................................. 598Design Entry Method ................................................................................................................... 598For More Information ................................................................................................................... 598

SR16RLE ............................................................................................................................................ 599Introduction................................................................................................................................. 599Logic Table .................................................................................................................................. 599Design Entry Method ................................................................................................................... 599For More Information ................................................................................................................... 600

SR16RLED.......................................................................................................................................... 601Introduction................................................................................................................................. 601Logic Table .................................................................................................................................. 601Design Entry Method ................................................................................................................... 601For More Information ................................................................................................................... 602

SR4CE................................................................................................................................................ 603Introduction................................................................................................................................. 603Logic Table .................................................................................................................................. 603Design Entry Method ................................................................................................................... 603For More Information ................................................................................................................... 603

SR4CLE.............................................................................................................................................. 604Introduction................................................................................................................................. 604

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Logic Table .................................................................................................................................. 604Design Entry Method ................................................................................................................... 604For More Information ................................................................................................................... 605

SR4CLED ........................................................................................................................................... 606Introduction................................................................................................................................. 606Logic Table .................................................................................................................................. 606Design Entry Method ................................................................................................................... 606For More Information ................................................................................................................... 607

SR4RE................................................................................................................................................ 608Introduction................................................................................................................................. 608Logic Table .................................................................................................................................. 608Design Entry Method ................................................................................................................... 608For More Information ................................................................................................................... 608

SR4RLE.............................................................................................................................................. 609Introduction................................................................................................................................. 609Logic Table .................................................................................................................................. 609Design Entry Method ................................................................................................................... 610For More Information ................................................................................................................... 610

SR4RLED ........................................................................................................................................... 611Introduction................................................................................................................................. 611Logic Table .................................................................................................................................. 611Design Entry Method ................................................................................................................... 612For More Information ................................................................................................................... 612

SR8CE................................................................................................................................................ 613Introduction................................................................................................................................. 613Logic Table .................................................................................................................................. 613Design Entry Method ................................................................................................................... 613For More Information ................................................................................................................... 613

SR8CLE.............................................................................................................................................. 614Introduction................................................................................................................................. 614Logic Table .................................................................................................................................. 614Design Entry Method ................................................................................................................... 614For More Information ................................................................................................................... 615

SR8CLED ........................................................................................................................................... 616Introduction................................................................................................................................. 616Logic Table .................................................................................................................................. 616Design Entry Method ................................................................................................................... 616For More Information ................................................................................................................... 617

SR8RE................................................................................................................................................ 618Introduction................................................................................................................................. 618Logic Table .................................................................................................................................. 618Design Entry Method ................................................................................................................... 618For More Information ................................................................................................................... 618

SR8RLE.............................................................................................................................................. 619Introduction................................................................................................................................. 619Logic Table .................................................................................................................................. 619Design Entry Method ................................................................................................................... 619For More Information ................................................................................................................... 620

SR8RLED ........................................................................................................................................... 621Introduction................................................................................................................................. 621Logic Table .................................................................................................................................. 621Design Entry Method ................................................................................................................... 621For More Information ................................................................................................................... 622

SRL16 ................................................................................................................................................ 623Introduction................................................................................................................................. 623Logic Table .................................................................................................................................. 623Design Entry Method ................................................................................................................... 623Available Attributes ..................................................................................................................... 623For More Information ................................................................................................................... 624

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SRL16_1 ............................................................................................................................................. 625Introduction................................................................................................................................. 625Logic Table .................................................................................................................................. 625Design Entry Method ................................................................................................................... 625Available Attributes ..................................................................................................................... 625For More Information ................................................................................................................... 626

SRL16E .............................................................................................................................................. 627Introduction................................................................................................................................. 627Logic Table .................................................................................................................................. 627Port Descriptions.......................................................................................................................... 628Design Entry Method ................................................................................................................... 628Available Attributes ..................................................................................................................... 628For More Information ................................................................................................................... 628

SRL16E_1 ........................................................................................................................................... 629Introduction................................................................................................................................. 629Logic Table .................................................................................................................................. 629Design Entry Method ................................................................................................................... 629Available Attributes ..................................................................................................................... 629For More Information ................................................................................................................... 630

SRLC16 .............................................................................................................................................. 631Introduction................................................................................................................................. 631Logic Table .................................................................................................................................. 631Design Entry Method ................................................................................................................... 631Available Attributes ..................................................................................................................... 631For More Information ................................................................................................................... 632

SRLC16_1........................................................................................................................................... 633Introduction................................................................................................................................. 633Logic Table .................................................................................................................................. 633Design Entry Method ................................................................................................................... 633Available Attributes ..................................................................................................................... 633For More Information ................................................................................................................... 634

SRLC16E ............................................................................................................................................ 635Introduction................................................................................................................................. 635Logic Table .................................................................................................................................. 635Design Entry Method ................................................................................................................... 635Available Attributes ..................................................................................................................... 636For More Information ................................................................................................................... 636

SRLC16E_1......................................................................................................................................... 637Introduction................................................................................................................................. 637Logic Table .................................................................................................................................. 637Design Entry Method ................................................................................................................... 637Available Attributes ..................................................................................................................... 638For More Information ................................................................................................................... 638

SRLC32E ............................................................................................................................................ 639Introduction................................................................................................................................. 639Port Descriptions.......................................................................................................................... 639Design Entry Method ................................................................................................................... 639Available Attributes ..................................................................................................................... 640For More Information ................................................................................................................... 640

STARTUP_SPARTAN6........................................................................................................................ 641Introduction................................................................................................................................. 641Port Descriptions.......................................................................................................................... 641Design Entry Method ................................................................................................................... 641For More Information ................................................................................................................... 641

SUSPEND_SYNC................................................................................................................................ 642Introduction................................................................................................................................. 642Port Descriptions.......................................................................................................................... 642Design Entry Method ................................................................................................................... 642For More Information ................................................................................................................... 642

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VCC................................................................................................................................................... 643Introduction................................................................................................................................. 643Design Entry Method ................................................................................................................... 643For More Information ................................................................................................................... 643

XNOR2 .............................................................................................................................................. 644Introduction................................................................................................................................. 644Logic Table .................................................................................................................................. 644Design Entry Method ................................................................................................................... 644For More Information ................................................................................................................... 644

XNOR3 .............................................................................................................................................. 645Introduction................................................................................................................................. 645Logic Table .................................................................................................................................. 645Design Entry Method ................................................................................................................... 645For More Information ................................................................................................................... 645

XNOR4 .............................................................................................................................................. 646Introduction................................................................................................................................. 646Logic Table .................................................................................................................................. 646Design Entry Method ................................................................................................................... 646For More Information ................................................................................................................... 646

XNOR5 .............................................................................................................................................. 647Introduction................................................................................................................................. 647Logic Table .................................................................................................................................. 647Design Entry Method ................................................................................................................... 647For More Information ................................................................................................................... 647

XNOR6 .............................................................................................................................................. 648Introduction................................................................................................................................. 648Logic Table .................................................................................................................................. 648Design Entry Method ................................................................................................................... 648For More Information ................................................................................................................... 648

XNOR7 .............................................................................................................................................. 649Introduction................................................................................................................................. 649Logic Table .................................................................................................................................. 649Design Entry Method ................................................................................................................... 649For More Information ................................................................................................................... 649

XNOR8 .............................................................................................................................................. 650Introduction................................................................................................................................. 650Logic Table .................................................................................................................................. 650Design Entry Method ................................................................................................................... 650For More Information ................................................................................................................... 650

XNOR9 .............................................................................................................................................. 651Introduction................................................................................................................................. 651Logic Table .................................................................................................................................. 651Design Entry Method ................................................................................................................... 651For More Information ................................................................................................................... 651

XOR2 ................................................................................................................................................. 652Introduction................................................................................................................................. 652Design Entry Method ................................................................................................................... 652For More Information ................................................................................................................... 652

XOR3 ................................................................................................................................................. 653Introduction................................................................................................................................. 653Design Entry Method ................................................................................................................... 653For More Information ................................................................................................................... 653

XOR4 ................................................................................................................................................. 654Introduction................................................................................................................................. 654Design Entry Method ................................................................................................................... 654For More Information ................................................................................................................... 654

XOR5 ................................................................................................................................................. 655Introduction................................................................................................................................. 655Design Entry Method ................................................................................................................... 655

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For More Information ................................................................................................................... 655XOR6 ................................................................................................................................................. 656

Introduction................................................................................................................................. 656Design Entry Method ................................................................................................................... 656For More Information ................................................................................................................... 656

XOR7 ................................................................................................................................................. 657Introduction................................................................................................................................. 657Design Entry Method ................................................................................................................... 657For More Information ................................................................................................................... 657

XOR8 ................................................................................................................................................. 658Introduction................................................................................................................................. 658Design Entry Method ................................................................................................................... 658For More Information ................................................................................................................... 658

XOR9 ................................................................................................................................................. 659Introduction................................................................................................................................. 659Design Entry Method ................................................................................................................... 659For More Information ................................................................................................................... 659

XORCY .............................................................................................................................................. 660Introduction................................................................................................................................. 660Logic Table .................................................................................................................................. 660Design Entry Method ................................................................................................................... 660For More Information ................................................................................................................... 660

XORCY_D.......................................................................................................................................... 661Introduction................................................................................................................................. 661Logic Table .................................................................................................................................. 661Design Entry Method ................................................................................................................... 661For More Information ................................................................................................................... 661

XORCY_L .......................................................................................................................................... 662Introduction................................................................................................................................. 662Logic Table .................................................................................................................................. 662Design Entry Method ................................................................................................................... 662For More Information ................................................................................................................... 662

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Spartan-6 Libraries Guide for Schematic Designs44 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 1

About this GuideThis schematic guide is part of the ISE documentation collection. A separate version of this guide is available ifyou prefer to work with HDL.

This guide contains the following:

• Introduction.

• A list of design elements supported in this architecture, organized by functional categories.

• Individual descriptions of each available primitive.

About Design ElementsThis version of the Libraries Guide describes design elements available for this architecture. There are severalcategories of design elements:

• Primitives - The simplest design elements in the Xilinx libraries. Primitives are the design element "atoms."Examples of Xilinx primitives are the simple buffer, BUF, and the D flip-flop with clock enable and clear,FDCE.

• Macros - The design element "molecules" of the Xilinx libraries. Macros can be created from the designelement primitives or macros. For example, the FD4CE flip-flop macro is a composite of 4 FDCE primitives.

Xilinx maintains software libraries with hundreds of functional design elements (macros and primitives) fordifferent device architectures. New functional elements are assembled with each release of development systemsoftware. This guide is one in a series of architecture-specific libraries.

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Chapter 2

Functional CategoriesThis section categorizes, by function, the circuit design elements described in detail later in this guide. Theelements ( primitives and macros) are listed in alphanumeric order under each functional category.

Advanced Decoder Logic

Arithmetic Flip Flop LUT

Buffer General Memory

Carry Logic Input/Output Functions MUX

Clocking Resources IO Shift Register

Comparator IO FlipFlop Shifter

Counter IO Latch

DDR Flip Flop Latch

AdvancedDesign Element Description

GTPA1_DUAL Primitive: Dual Gigabit Transceiver

PCIE_A1 Primitive: PCI Express

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Chapter 2: Functional Categories

ArithmeticDesign Element Description

ACC16 Macro: 16-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, andSynchronous Reset

ACC4 Macro: 4-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, andSynchronous Reset

ACC8 Macro: 8-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, andSynchronous Reset

ADD16 Macro: 16-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow

ADD4 Macro: 4-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow

ADD8 Macro: 8-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow

ADSU16 Macro: 16-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow

ADSU4 Macro: 4-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow

ADSU8 Macro: 8-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow

DSP48A1 Primitive: Multi-Functional, Cascadable, 48-bit Output, Arithmetic Block

MULT18X18SIO Primitive: 18 x 18 Cascadable Signed Multiplier with Optional Input and OutputRegisters, Clock Enable, and Synchronous Reset

BufferDesign Element Description

BUF Primitive: General Purpose Buffer

BUFCF Primitive: Fast Connect Buffer

BUFG Primitive: Global Clock Buffer

BUFGCE Primitive: Global Clock Buffer with Clock Enable

BUFGCE_1 Primitive: Global Clock Buffer with Clock Enable and Output State 1

BUFGMUX Primitive: Global Clock MUX Buffer

BUFGMUX_1 Primitive: Global Clock MUX Buffer with Output State 1

Carry LogicDesign Element Description

CARRY4 Primitive: Fast Carry Logic with Look Ahead

MUXCY Primitive: 2-to-1 Multiplexer for Carry Logic with General Output

MUXCY_D Primitive: 2-to-1 Multiplexer for Carry Logic with Dual Output

MUXCY_L Primitive: 2-to-1 Multiplexer for Carry Logic with Local Output

XORCY Primitive: XOR for Carry Logic with General Output

XORCY_D Primitive: XOR for Carry Logic with Dual Output

XORCY_L Primitive: XOR for Carry Logic with Local Output

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Chapter 2: Functional Categories

Clocking ResourcesDesign Element Description

BUFH Primitive: Clock buffer for a single clocking region

BUFIO2 Primitive: Dual Clock Buffer and Strobe Pulse

BUFIO2_2CLK Primitive: Dual Clock Buffer and Strobe Pulse with Differential Input

BUFIO2FB Primitive: Feedback Clock Buffer.

BUFPLL Primitive: PLL Buffer

DCM_CLKGEN Primitive: Digital Clock Manager.

DCM_SP Primitive: Digital Clock Manager

PLL_BASE Primitive: Basic Phase Locked Loop Clock Circuit

ComparatorDesign Element Description

COMP16 Macro: 16-Bit Identity Comparator

COMP2 Macro: 2-Bit Identity Comparator

COMP4 Macro: 4-Bit Identity Comparator

COMP8 Macro: 8-Bit Identity Comparator

COMPM16 Macro: 16-Bit Magnitude Comparator

COMPM2 Macro: 2-Bit Magnitude Comparator

COMPM4 Macro: 4-Bit Magnitude Comparator

COMPM8 Macro: 8-Bit Magnitude Comparator

COMPMC16 Macro: 16-Bit Magnitude Comparator

COMPMC8 Macro: 8-Bit Magnitude Comparator

CounterDesign Element Description

CB16CE Macro: 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

CB16CLE Macro: 16-Bit Loadable Cascadable Binary Counters with Clock Enable andAsynchronous Clear

CB16CLED Macro: 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enableand Asynchronous Clear

CB16RE Macro: 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

CB2CE Macro: 2-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

CB2CLE Macro: 2-Bit Loadable Cascadable Binary Counters with Clock Enable andAsynchronous Clear

CB2CLED Macro: 2-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enableand Asynchronous Clear

CB2RE Macro: 2-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

CB4CE Macro: 4-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

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Chapter 2: Functional Categories

Design Element Description

CB4CLE Macro: 4-Bit Loadable Cascadable Binary Counters with Clock Enable andAsynchronous Clear

CB4CLED Macro: 4-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enableand Asynchronous Clear

CB4RE Macro: 4-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

CB8CE Macro: 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

CB8CLE Macro: 8-Bit Loadable Cascadable Binary Counters with Clock Enable andAsynchronous Clear

CB8CLED Macro: 8-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enableand Asynchronous Clear

CB8RE Macro: 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

CC16CE Macro: 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

CC16CLE Macro: 16-Bit Loadable Cascadable Binary Counter with Clock Enable andAsynchronous Clear

CC16CLED Macro: 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enableand Asynchronous Clear

CC16RE Macro: 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

CC8CE Macro: 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

CC8CLE Macro: 8-Bit Loadable Cascadable Binary Counter with Clock Enable andAsynchronous Clear

CC8CLED Macro: 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enableand Asynchronous Clear

CC8RE Macro: 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

CD4CE Macro: 4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous Clear

CD4CLE Macro: 4-Bit Loadable Cascadable BCD Counter with Clock Enable and AsynchronousClear

CD4RE Macro: 4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset

CD4RLE Macro: 4-Bit Loadable Cascadable BCD Counter with Clock Enable and SynchronousReset

CJ4CE 4-Bit Johnson Counter with Clock Enable and Asynchronous Clear

CJ4RE Macro: 4-Bit Johnson Counter with Clock Enable and Synchronous Reset

CJ5CE Macro: 5-Bit Johnson Counter with Clock Enable and Asynchronous Clear

CJ5RE Macro: 5-Bit Johnson Counter with Clock Enable and Synchronous Reset

CJ8CE Macro: 8-Bit Johnson Counter with Clock Enable and Asynchronous Clear

CJ8RE Macro: 8-Bit Johnson Counter with Clock Enable and Synchronous Reset

CR16CE Macro: 16-Bit Negative-Edge Binary Ripple Counter with Clock Enable andAsynchronous Clear

CR8CE Macro: 8-Bit Negative-Edge Binary Ripple Counter with Clock Enable andAsynchronous Clear

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Chapter 2: Functional Categories

DDR Flip FlopDesign Element Description

IDDR2 Primitive: Double Data Rate Input D Flip-Flop with Optional Data Alignment, ClockEnable and Programmable Synchronous or Asynchronous Set/Reset

ODDR2 Primitive: Dual Data Rate Output D Flip-Flop with Optional Data Alignment, ClockEnable and Programmable Synchronous or Asynchronous Set/Reset

DecoderDesign Element Description

D2_4E Macro: 2- to 4-Line Decoder/Demultiplexer with Enable

D3_8E Macro: 3- to 8-Line Decoder/Demultiplexer with Enable

D4_16E Macro: 4- to 16-Line Decoder/Demultiplexer with Enable

DEC_CC16 Macro: 16-Bit Active Low Decoder

DEC_CC4 Macro: 4-Bit Active Low Decoder

DEC_CC8 Macro: 8-Bit Active Low Decoder

DECODE16 Macro: 16-Bit Active-Low Decoder

DECODE32 Macro: 32-Bit Active-Low Decoder

DECODE4 Macro: 4-Bit Active-Low Decoder

DECODE64 Macro: 64-Bit Active-Low Decoder

DECODE8 Macro: 8-Bit Active-Low Decoder

Flip FlopDesign Element Description

FD Primitive: D Flip-Flop

FD_1 Primitive: D Flip-Flop with Negative-Edge Clock

FD16CE Macro: 16-Bit Data Register with Clock Enable and Asynchronous Clear

FD16RE Macro: 16-Bit Data Register with Clock Enable and Synchronous Reset

FD4CE Macro: 4-Bit Data Register with Clock Enable and Asynchronous Clear

FD4RE Macro: 4-Bit Data Register with Clock Enable and Synchronous Reset

FD8CE Macro: 8-Bit Data Register with Clock Enable and Asynchronous Clear

FD8RE Macro: 8-Bit Data Register with Clock Enable and Synchronous Reset

FDC Primitive: D Flip-Flop with Asynchronous Clear

FDC_1 Primitive: D Flip-Flop with Negative-Edge Clock and Asynchronous Clear

FDCE Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear

FDCE_1 Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and AsynchronousClear

FDE Primitive: D Flip-Flop with Clock Enable

FDE_1 Primitive: D Flip-Flop with Negative-Edge Clock and Clock Enable

FDP Primitive: D Flip-Flop with Asynchronous Preset

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Chapter 2: Functional Categories

Design Element Description

FDP_1 Primitive: D Flip-Flop with Negative-Edge Clock and Asynchronous Preset

FDPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset

FDPE_1 Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and AsynchronousPreset

FDR Primitive: D Flip-Flop with Synchronous Reset

FDR_1 Primitive: D Flip-Flop with Negative-Edge Clock and Synchronous Reset

FDRE Primitive: D Flip-Flop with Clock Enable and Synchronous Reset

FDRE_1 Primitive: D Flip-Flop with Negative-Clock Edge, Clock Enable, and SynchronousReset

FDS Primitive: D Flip-Flop with Synchronous Set

FDS_1 Primitive: D Flip-Flop with Negative-Edge Clock and Synchronous Set

FDSE Primitive: D Flip-Flop with Clock Enable and Synchronous Set

FDSE_1 Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and Synchronous Set

FJKC Macro: J-K Flip-Flop with Asynchronous Clear

FJKCE Macro: J-K Flip-Flop with Clock Enable and Asynchronous Clear

FJKP Macro: J-K Flip-Flop with Asynchronous Preset

FJKPE Macro: J-K Flip-Flop with Clock Enable and Asynchronous Preset

FJKRSE Macro: J-K Flip-Flop with Clock Enable and Synchronous Reset and Set

FJKSRE Macro: J-K Flip-Flop with Clock Enable and Synchronous Set and Reset

FTC Macro: Toggle Flip-Flop with Asynchronous Clear

FTCE Macro: Toggle Flip-Flop with Clock Enable and Asynchronous Clear

FTCLE Macro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Clear

FTCLEX Macro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Clear

FTP Macro: Toggle Flip-Flop with Asynchronous Preset

FTPE Macro: Toggle Flip-Flop with Clock Enable and Asynchronous Preset

FTPLE Macro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Preset

FTRSE Macro: Toggle Flip-Flop with Clock Enable and Synchronous Reset and Set

FTRSLE Macro: Toggle/Loadable Flip-Flop with Clock Enable and Synchronous Reset and Set

FTSRE Macro: Toggle Flip-Flop with Clock Enable and Synchronous Set and Reset

FTSRLE Macro: Toggle/Loadable Flip-Flop with Clock Enable and Synchronous Set and Reset

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Chapter 2: Functional Categories

GeneralDesign Element Description

BSCAN_SPARTAN6 Primitive: Spartan®-6 JTAG Boundary Scan Logic Control Circuit

DNA_PORT Primitive: Device DNA Data Access Port

GND Primitive: Ground-Connection Signal Tag

ICAP_SPARTAN6 Primitive: Internal Configuration Access Port

KEEPER Primitive: KEEPER Symbol

POST_CRC_INTERNAL Primitive: Post-configuration CRC error detection

PULLDOWN Primitive: Resistor to GND for Input Pads, Open-Drain, and 3-State Outputs

PULLUP Primitive: Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs

SPI_ACCESS Primitive: Internal Logic Access to the Serial Peripheral Interface (SPI) PROM Data

STARTUP_SPARTAN6 Primitive: Spartan®-6 Global Set/Reset, Global 3-State and Configuration Start-UpClock Interface

SUSPEND_SYNC Primitive: Suspend Mode Access

VCC Primitive: VCC-Connection Signal Tag

Input/Output FunctionsDesign Element Description

IODELAY2 Primitive: Input and Output Fixed or Variable Delay Element

IODRP2 Primitive: I/O Control Port

ISERDES2 Primitive: Input SERial/DESerializer.

OSERDES2 Primitive: Dedicated IOB Output Serializer

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Chapter 2: Functional Categories

IODesign Element Description

IBUF Primitive: Input Buffer

IBUF16 Macro: 16-Bit Input Buffer

IBUF4 Macro: 4-Bit Input Buffer

IBUF8 Macro: 8-Bit Input Buffer

IBUFDS Primitive: Differential Signaling Input Buffer

IBUFDS_DLY_ADJ Primitive: Dynamically Adjustable Differential Input Delay Buffer

IBUFG Primitive: Dedicated Input Clock Buffer

IBUFGDS Primitive: Differential Signaling Dedicated Input Clock Buffer and Optional Delay

IOBUF Primitive: Bi-Directional Buffer

IOBUFDS Primitive: 3-State Differential Signaling I/O Buffer with Active Low Output Enable

OBUF Primitive: Output Buffer

OBUF16 Macro: 16-Bit Output Buffer

OBUF4 Macro: 4-Bit Output Buffer

OBUF8 Macro: 8-Bit Output Buffer

OBUFDS Primitive: Differential Signaling Output Buffer

OBUFT Primitive: 3-State Output Buffer with Active Low Output Enable

OBUFT16 Macro: 16-Bit 3-State Output Buffer with Active Low Output Enable

OBUFT4 Macro: 4-Bit 3-State Output Buffers with Active-Low Output Enable

OBUFT8 Macro: 8-Bit 3-State Output Buffers with Active-Low Output Enable

OBUFTDS Primitive: 3-State Output Buffer with Differential Signaling, Active-Low OutputEnable

IO FlipFlopDesign Element Description

IFD Macro: Input D Flip-Flop

IFD_1 Macro: Input D Flip-Flop with Inverted Clock (Asynchronous Preset)

IFD16 Macro: 16-Bit Input D Flip-Flop

IFD4 Macro: 4-Bit Input D Flip-Flop

IFD8 Macro: 8-Bit Input D Flip-Flop

IFDI Macro: Input D Flip-Flop (Asynchronous Preset)

IFDI_1 Macro: Input D Flip-Flop with Inverted Clock (Asynchronous Preset)

IFDX Macro: Input D Flip-Flop with Clock Enable

IFDX_1 Macro: Input D Flip-Flop with Inverted Clock and Clock Enable

IFDX16 Macro: 16-Bit Input D Flip-Flops with Clock Enable

IFDX4 Macro: 4-Bit Input D Flip-Flop with Clock Enable

IFDX8 Macro: 8-Bit Input D Flip-Flop with Clock Enable

IFDXI Macro: Input D Flip-Flop with Clock Enable (Asynchronous Preset)

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Chapter 2: Functional Categories

Design Element Description

IFDXI_1 Macro: Input D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)

OFD Macro: Output D Flip-Flop

OFD_1 Macro: Output D Flip-Flop with Inverted Clock

OFD16 Macro: 16-Bit Output D Flip-Flop

OFD4 Macro: 4-Bit Output D Flip-Flop

OFD8 Macro: 8-Bit Output D Flip-Flop

OFDE Macro: D Flip-Flop with Active-High Enable Output Buffers

OFDE_1 Macro: D Flip-Flop with Active-High Enable Output Buffer and Inverted Clock

OFDE16 Macro: 16-Bit D Flip-Flop with Active-High Enable Output Buffers

OFDE4 Macro: 4-Bit D Flip-Flop with Active-High Enable Output Buffers

OFDE8 Macro: 8-Bit D Flip-Flop with Active-High Enable Output Buffers

OFDI Macro: Output D Flip-Flop (Asynchronous Preset)

OFDI_1 Macro: Output D Flip-Flop with Inverted Clock (Asynchronous Preset)

OFDT Macro: D Flip-Flop with Active-Low 3-State Output Buffer

OFDT_1 Macro: D Flip-Flop with Active-Low 3-State Output Buffer and Inverted Clock

OFDT16 Macro: 16-Bit D Flip-Flop with Active-Low 3-State Output Buffers

OFDT4 Macro: 4-Bit D Flip-Flop with Active-Low 3-State Output Buffers

OFDT8 Macro: 8-Bit D Flip-Flop with Active-Low 3-State Output Buffers

OFDX Macro: Output D Flip-Flop with Clock Enable

OFDX_1 Macro: Output D Flip-Flop with Inverted Clock and Clock Enable

OFDX16 Macro: 16-Bit Output D Flip-Flop with Clock Enable

OFDX4 Macro: 4-Bit Output D Flip-Flop with Clock Enable

OFDX8 Macro: 8-Bit Output D Flip-Flop with Clock Enable

OFDXI Macro: Output D Flip-Flop with Clock Enable (Asynchronous Preset)

OFDXI_1 Macro: Output D Flip-Flop with Inverted Clock and Clock Enable (AsynchronousPreset)

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Chapter 2: Functional Categories

IO LatchDesign Element Description

ILD Macro: Transparent Input Data Latch

ILD_1 Macro: Transparent Input Data Latch with Inverted Gate

ILD16 Macro: Transparent Input Data Latch

ILD4 Macro: Transparent Input Data Latch

ILD8 Macro: Transparent Input Data Latch

ILDI Macro: Transparent Input Data Latch (Asynchronous Preset)

ILDI_1 Macro: Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)

ILDX Macro: Transparent Input Data Latch

ILDX_1 Macro: Transparent Input Data Latch with Inverted Gate

ILDX16 Macro: Transparent Input Data Latch

ILDX4 Macro: Transparent Input Data Latch

ILDX8 Macro: Transparent Input Data Latch

ILDXI Macro: Transparent Input Data Latch (Asynchronous Preset)

ILDXI_1 Macro: Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)

LatchDesign Element Description

LD Primitive: Transparent Data Latch

LD_1 Primitive: Transparent Data Latch with Inverted Gate

LD16 Macro: Multiple Transparent Data Latch

LD16CE Macro: Transparent Data Latch with Asynchronous Clear and Gate Enable

LD4 Macro: Multiple Transparent Data Latch

LD4CE Macro: Transparent Data Latch with Asynchronous Clear and Gate Enable

LD8 Macro: Multiple Transparent Data Latch

LD8CE Macro: Transparent Data Latch with Asynchronous Clear and Gate Enable

LDC Primitive: Macro: Transparent Data Latch with Asynchronous Clear

LDC_1 Primitive: Transparent Data Latch with Asynchronous Clear and Inverted Gate

LDCE Primitive: Transparent Data Latch with Asynchronous Clear and Gate Enable

LDCE_1 Primitive: Transparent Data Latch with Asynchronous Clear, Gate Enable, andInverted Gate

LDE Primitive: Transparent Data Latch with Gate Enable

LDE_1 Primitive: Transparent Data Latch with Gate Enable and Inverted Gate

LDP Primitive: Macro: Transparent Data Latch with Asynchronous Preset

LDP_1 Primitive: Transparent Data Latch with Asynchronous Preset and Inverted Gate

LDPE Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable

LDPE_1 Primitive: Transparent Data Latch with Asynchronous Preset, Gate Enable, andInverted Gate

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Chapter 2: Functional Categories

LogicDesign Element Description

AND12 Macro: 12- Input AND Gate with Non-Inverted Inputs

AND16 Unknown type: 16- Input AND Gate with Non-Inverted Inputs

AND2 Primitive: 2-Input AND Gate with Non-Inverted Inputs

AND2B1 Primitive: 2-Input AND Gate with 1 Inverted and 1 Non-Inverted Inputs

AND2B1L Primitive: Two input AND gate implemented in place of a Slice Latch

AND2B2 Primitive: 2-Input AND Gate with Inverted Inputs

AND3 Primitive: 3-Input AND Gate with Non-Inverted Inputs

AND3B1 Primitive: 3-Input AND Gate with 1 Inverted and 2 Non-Inverted Inputs

AND3B2 Primitive: 3-Input AND Gate with 2 Inverted and 1 Non-Inverted Inputs

AND3B3 Primitive: 3-Input AND Gate with Inverted Inputs

AND4 Primitive: 4-Input AND Gate with Non-Inverted Inputs

AND4B1 Primitive: 4-Input AND Gate with 1 Inverted and 3 Non-Inverted Inputs

AND4B2 Primitive: 4-Input AND Gate with 2 Inverted and 2 Non-Inverted Inputs

AND4B3 Primitive: 4-Input AND Gate with 3 Inverted and 1 Non-Inverted Inputs

AND4B4 Primitive: 4-Input AND Gate with Inverted Inputs

AND5 Primitive: 5-Input AND Gate with Non-Inverted Inputs

AND5B1 Primitive: 5-Input AND Gate with 1 Inverted and 4 Non-Inverted Inputs

AND5B2 Primitive: 5-Input AND Gate with 2 Inverted and 3 Non-Inverted Inputs

AND5B3 Primitive: 5-Input AND Gate with 3 Inverted and 2 Non-Inverted Inputs

AND5B4 Primitive: 5-Input AND Gate with 4 Inverted and 1 Non-Inverted Inputs

AND5B5 Primitive: 5-Input AND Gate with Inverted Inputs

AND6 Macro: 6-Input AND Gate with Non-Inverted Inputs

AND7 Macro: 7-Input AND Gate with Non-Inverted Inputs

AND8 Macro: 8-Input AND Gate with Non-Inverted Inputs

AND9 Macro: 9-Input AND Gate with Non-Inverted Inputs

INV Primitive: Inverter

INV16 Macro: 16 Inverters

INV4 Macro: Four Inverters

INV8 Macro: Eight Inverters

MULT_AND Primitive: Fast Multiplier AND

NAND12 Macro: 12- Input NAND Gate with Non-Inverted Inputs

NAND16 Macro: 16- Input NAND Gate with Non-Inverted Inputs

NAND2 Primitive: 2-Input NAND Gate with Non-Inverted Inputs

NAND2B1 Primitive: 2-Input NAND Gate with 1 Inverted and 1 Non-Inverted Inputs

NAND2B2 Primitive: 2-Input NAND Gate with Inverted Inputs

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Chapter 2: Functional Categories

Design Element Description

NAND3 Primitive: 3-Input NAND Gate with Non-Inverted Inputs

NAND3B1 Primitive: 3-Input NAND Gate with 1 Inverted and 2 Non-Inverted Inputs

NAND3B2 Primitive: 3-Input NAND Gate with 2 Inverted and 1 Non-Inverted Inputs

NAND3B3 Primitive: 3-Input NAND Gate with Inverted Inputs

NAND4 Primitive: 4-Input NAND Gate with Non-Inverted Inputs

NAND4B1 Primitive: 4-Input NAND Gate with 1 Inverted and 3 Non-Inverted Inputs

NAND4B2 Primitive: 4-Input NAND Gate with 2 Inverted and 2 Non-Inverted Inputs

NAND4B3 Primitive: 4-Input NAND Gate with 3 Inverted and 1 Non-Inverted Inputs

NAND4B4 Primitive: 4-Input NAND Gate with Inverted Inputs

NAND5 Primitive: 5-Input NAND Gate with Non-Inverted Inputs

NAND5B1 Primitive: 5-Input NAND Gate with 1 Inverted and 4 Non-Inverted Inputs

NAND5B2 Primitive: 5-Input NAND Gate with 2 Inverted and 3 Non-Inverted Inputs

NAND5B3 Primitive: 5-Input NAND Gate with 3 Inverted and 2 Non-Inverted Inputs

NAND5B4 Primitive: 5-Input NAND Gate with 4 Inverted and 1 Non-Inverted Inputs

NAND5B5 Primitive: 5-Input NAND Gate with Inverted Inputs

NAND6 Macro: 6-Input NAND Gate with Non-Inverted Inputs

NAND7 Macro: 7-Input NAND Gate with Non-Inverted Inputs

NAND8 Macro: 8-Input NAND Gate with Non-Inverted Inputs

NAND9 Macro: 9-Input NAND Gate with Non-Inverted Inputs

NOR12 Macro: 12-Input NOR Gate with Non-Inverted Inputs

NOR16 Macro: 16-Input NOR Gate with Non-Inverted Inputs

NOR2 Primitive: 2-Input NOR Gate with Non-Inverted Inputs

NOR2B1 Primitive: 2-Input NOR Gate with 1 Inverted and 1 Non-Inverted Inputs

NOR2B2 Primitive: 2-Input NOR Gate with Inverted Inputs

NOR3 Primitive: 3-Input NOR Gate with Non-Inverted Inputs

NOR3B1 Primitive: 3-Input NOR Gate with 1 Inverted and 2 Non-Inverted Inputs

NOR3B2 Primitive: 3-Input NOR Gate with 2 Inverted and 1 Non-Inverted Inputs

NOR3B3 Primitive: 3-Input NOR Gate with Inverted Inputs

NOR4 Primitive: 4-Input NOR Gate with Non-Inverted Inputs

NOR4B1 Primitive: 4-Input NOR Gate with 1 Inverted and 3 Non-Inverted Inputs

NOR4B2 Primitive: 4-Input NOR Gate with 2 Inverted and 2 Non-Inverted Inputs

NOR4B3 Primitive: 4-Input NOR Gate with 3 Inverted and 1 Non-Inverted Inputs

NOR4B4 Primitive: 4-Input NOR Gate with Inverted Inputs

NOR5 Primitive: 5-Input NOR Gate with Non-Inverted Inputs

NOR5B1 Primitive: 5-Input NOR Gate with 1 Inverted and 4 Non-Inverted Inputs

NOR5B2 Primitive: 5-Input NOR Gate with 2 Inverted and 3 Non-Inverted Inputs

NOR5B3 Primitive: 5-Input NOR Gate with 3 Inverted and 2 Non-Inverted Inputs

NOR5B4 Primitive: 5-Input NOR Gate with 4 Inverted and 1 Non-Inverted Inputs

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Chapter 2: Functional Categories

Design Element Description

NOR5B5 Primitive: 5-Input NOR Gate with Inverted Inputs

NOR6 Macro: 6-Input NOR Gate with Non-Inverted Inputs

NOR7 Macro: 7-Input NOR Gate with Non-Inverted Inputs

NOR8 Macro: 8-Input NOR Gate with Non-Inverted Inputs

NOR9 Macro: 9-Input NOR Gate with Non-Inverted Inputs

OR12 Macro: 12-Input OR Gate with Non-Inverted Inputs

OR16 Macro: 16-Input OR Gate with Non-Inverted Inputs

OR2 Primitive: 2-Input OR Gate with Non-Inverted Inputs

OR2B1 Primitive: 2-Input OR Gate with 1 Inverted and 1 Non-Inverted Inputs

OR2B2 Primitive: 2-Input OR Gate with Inverted Inputs

OR2L Primitive: Two input OR gate implemented in place of a Slice Latch

OR3 Primitive: 3-Input OR Gate with Non-Inverted Inputs

OR3B1 Primitive: 3-Input OR Gate with 1 Inverted and 2 Non-Inverted Inputs

OR3B2 Primitive: 3-Input OR Gate with 2 Inverted and 1 Non-Inverted Inputs

OR3B3 Primitive: 3-Input OR Gate with Inverted Inputs

OR4 Primitive: 4-Input OR Gate with Non-Inverted Inputs

OR4B1 Primitive: 4-Input OR Gate with 1 Inverted and 3 Non-Inverted Inputs

OR4B2 Primitive: 4-Input OR Gate with 2 Inverted and 2 Non-Inverted Inputs

OR4B3 Primitive: 4-Input OR Gate with 3 Inverted and 1 Non-Inverted Inputs

OR4B4 Primitive: 4-Input OR Gate with Inverted Inputs

OR5 Primitive: 5-Input OR Gate with Non-Inverted Inputs

OR5B1 Primitive: 5-Input OR Gate with 1 Inverted and 4 Non-Inverted Inputs

OR5B2 Primitive: 5-Input OR Gate with 2 Inverted and 3 Non-Inverted Inputs

OR5B3 Primitive: 5-Input OR Gate with 3 Inverted and 2 Non-Inverted Inputs

OR5B4 Primitive: 5-Input OR Gate with 4 Inverted and 1 Non-Inverted Inputs

OR5B5 Primitive: 5-Input OR Gate with Inverted Inputs

OR6 Macro: 6-Input OR Gate with Non-Inverted Inputs

OR7 Macro: 7-Input OR Gate with Non-Inverted Inputs

OR8 Macro: 8-Input OR Gate with Non-Inverted Inputs

OR9 Macro: 9-Input OR Gate with Non-Inverted Inputs

SOP3 Macro: 3–Input Sum of Products

SOP3B1A Macro: 3–Input Sum of Products with One Inverted Input (Option A)

SOP3B1B Macro: 3–Input Sum of Products with One Inverted Input (Option B)

SOP3B2A Macro: 3–Input Sum of Products with Two Inverted Inputs (Option A)

SOP3B2B Macro: 3–Input Sum of Products with Two Inverted Inputs (Option B)

SOP3B3 Macro: 3–Input Sum of Products with Inverted Inputs

SOP4 Macro: 4–Input Sum of Products

SOP4B1 Macro: 4–Input Sum of Products with One Inverted Input

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Chapter 2: Functional Categories

Design Element Description

SOP4B2A Macro: 4–Input Sum of Products with Two Inverted Inputs (Option A)

SOP4B2B Macro: 4–Input Sum of Products with Two Inverted Inputs (Option B)

SOP4B3 Macro: 4–Input Sum of Products with Three Inverted Inputs

SOP4B4 Macro: 4–Input Sum of Products with Inverted Inputs

XNOR2 Primitive: 2-Input XNOR Gate with Non-Inverted Inputs

XNOR3 Primitive: 3-Input XNOR Gate with Non-Inverted Inputs

XNOR4 Primitive: 4-Input XNOR Gate with Non-Inverted Inputs

XNOR5 Primitive: 5-Input XNOR Gate with Non-Inverted Inputs

XNOR6 Macro: 6-Input XNOR Gate with Non-Inverted Inputs

XNOR7 Macro: 7-Input XNOR Gate with Non-Inverted Inputs

XNOR8 Macro: 8-Input XNOR Gate with Non-Inverted Inputs

XNOR9 Macro: 9-Input XNOR Gate with Non-Inverted Inputs

XOR2 Primitive: 2-Input XOR Gate with Non-Inverted Inputs

XOR3 Primitive: 3-Input XOR Gate with Non-Inverted Inputs

XOR4 Primitive: 4-Input XOR Gate with Non-Inverted Inputs

XOR5 Primitive: 5-Input XOR Gate with Non-Inverted Inputs

XOR6 Macro: 6-Input XOR Gate with Non-Inverted Inputs

XOR7 Macro: 7-Input XOR Gate with Non-Inverted Inputs

XOR8 Macro: 8-Input XOR Gate with Non-Inverted Inputs

XOR9 Macro: 9-Input XOR Gate with Non-Inverted Inputs

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Chapter 2: Functional Categories

LUTDesign Element Description

CFGLUT5 Primitive: 5-input Dynamically Reconfigurable Look-Up Table (LUT)

LUT1 Macro: 1-Bit Look-Up Table with General Output

LUT1_D Macro: 1-Bit Look-Up Table with Dual Output

LUT1_L Macro: 1-Bit Look-Up Table with Local Output

LUT2 Macro: 2-Bit Look-Up Table with General Output

LUT2_D Macro: 2-Bit Look-Up Table with Dual Output

LUT2_L Macro: 2-Bit Look-Up Table with Local Output

LUT3 Macro: 3-Bit Look-Up Table with General Output

LUT3_D Macro: 3-Bit Look-Up Table with Dual Output

LUT3_L Macro: 3-Bit Look-Up Table with Local Output

LUT4 Macro: 4-Bit Look-Up-Table with General Output

LUT4_D Macro: 4-Bit Look-Up Table with Dual Output

LUT4_L Macro: 4-Bit Look-Up Table with Local Output

LUT5 Primitive: 5-Input Lookup Table with General Output

LUT5_D Primitive: 5-Input Lookup Table with General and Local Outputs

LUT5_L Primitive: 5-Input Lookup Table with Local Output

LUT6 Primitive: 6-Input Lookup Table with General Output

LUT6_2 Primitive: Six-input, 2-output, Look-Up Table

LUT6_D Primitive: 6-Input Lookup Table with General and Local Outputs

LUT6_L Primitive: 6-Input Lookup Table with Local Output

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Chapter 2: Functional Categories

MemoryDesign Element Description

RAM128X1D Primitive: 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)

RAM16X1D Primitive: 16-Deep by 1-Wide Static Dual Port Synchronous RAM

RAM16X1D_1 Primitive: 16-Deep by 1-Wide Static Dual Port Synchronous RAM with Negative-EdgeClock

RAM16X1S Primitive: 16-Deep by 1-Wide Static Synchronous RAM

RAM16X1S_1 Primitive: 16-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock

RAM16X2S Primitive: 16-Deep by 2-Wide Static Synchronous RAM

RAM16X4S Primitive: 16-Deep by 4-Wide Static Synchronous RAM

RAM16X8S Primitive: 16-Deep by 8-Wide Static Synchronous RAM

RAM256X1S Primitive: 256-Deep by 1-Wide Random Access Memory (Select RAM)

RAM32M Primitive: 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)

RAM32X1S Primitive: 32-Deep by 1-Wide Static Synchronous RAM

RAM32X1S_1 Primitive: 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock

RAM32X2S Primitive: 32-Deep by 2-Wide Static Synchronous RAM

RAM32X4S Primitive: 32-Deep by 4-Wide Static Synchronous RAM

RAM32X8S Primitive: 32-Deep by 8-Wide Static Synchronous RAM

RAM64M Primitive: 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)

RAM64X1D Primitive: 64-Deep by 1-Wide Dual Port Static Synchronous RAM

RAM64X1S Primitive: 64-Deep by 1-Wide Static Synchronous RAM

RAM64X1S_1 Primitive: 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock

RAM64X2S Primitive: 64-Deep by 2-Wide Static Synchronous RAM

RAMB16BWER Primitive: 16K-bit Data and 2K-bit Parity Configurable Synchronous Dual Port BlockRAM with Optional Output Registers

RAMB8BWER Primitive: 8K-bit Data and 1K-bit Parity Configurable Synchronous Dual Port BlockRAM with Optional Output Registers

ROM128X1 Primitive: 128-Deep by 1-Wide ROM

ROM16X1 Primitive: 16-Deep by 1-Wide ROM

ROM256X1 Primitive: 256-Deep by 1-Wide ROM

ROM32X1 Primitive: 32-Deep by 1-Wide ROM

ROM64X1 Primitive: 64-Deep by 1-Wide ROM

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Chapter 2: Functional Categories

MUXDesign Element Description

M16_1E Macro: 16-to-1 Multiplexer with Enable

M2_1 Macro: 2-to-1 Multiplexer

M2_1B1 Macro: 2-to-1 Multiplexer with D0 Inverted

M2_1B2 Macro: 2-to-1 Multiplexer with D0 and D1 Inverted

M2_1E Macro: 2-to-1 Multiplexer with Enable

M4_1E Macro: 4-to-1 Multiplexer with Enable

M8_1E Macro: 8-to-1 Multiplexer with Enable

MUXF5 Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

MUXF5_D Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

MUXF5_L Primitive: 2-to-1 Look-Up Table Multiplexer with Local Output

MUXF6 Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

MUXF6_D Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

MUXF6_L Primitive: 2-to-1 Look-Up Table Multiplexer with Local Output

MUXF7 Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

MUXF7_D Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

MUXF7_L Primitive: 2-to-1 look-up table Multiplexer with Local Output

MUXF8 Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

MUXF8_D Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

MUXF8_L Primitive: 2-to-1 Look-Up Table Multiplexer with Local Output

Shift RegisterDesign Element Description

SR16CE Macro: 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable andAsynchronous Clear

SR16CLE Macro: 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Asynchronous Clear

SR16CLED Macro: 16-Bit Shift Register with Clock Enable and Asynchronous Clear

SR16RE Macro: 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and SynchronousReset

SR16RLE Macro: 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Synchronous Reset

SR16RLED Macro: 16-Bit Shift Register with Clock Enable and Synchronous Reset

SR4CE Macro: 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and AsynchronousClear

SR4CLE Macro: 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Asynchronous Clear

SR4CLED Macro: 4-Bit Shift Register with Clock Enable and Asynchronous Clear

SR4RE Macro: 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and SynchronousReset

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Chapter 2: Functional Categories

Design Element Description

SR4RLE Macro: 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Synchronous Reset

SR4RLED Macro: 4-Bit Shift Register with Clock Enable and Synchronous Reset

SR8CE Macro: 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and AsynchronousClear

SR8CLE Macro: 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Asynchronous Clear

SR8CLED Macro: 8-Bit Shift Register with Clock Enable and Asynchronous Clear

SR8RE Macro: 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and SynchronousReset

SR8RLE Macro: 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Synchronous Reset

SR8RLED Macro: 8-Bit Shift Register with Clock Enable and Synchronous Reset

SRL16 Primitive: 16-Bit Shift Register Look-Up Table (LUT)

SRL16_1 Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Negative-Edge Clock

SRL16E Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Clock Enable

SRL16E_1 Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Negative-Edge Clock andClock Enable

SRLC16 Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Carry

SRLC16_1 Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Carry and Negative-EdgeClock

SRLC16E Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Carry and Clock Enable

SRLC16E_1 Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Carry, Negative-Edge Clock,and Clock Enable

SRLC32E Primitive: 32 Clock Cycle, Variable Length Shift Register Look-Up Table (LUT) withClock Enable

ShifterDesign Element Description

BRLSHFT4 Macro: 4-Bit Barrel Shifter

BRLSHFT8 Macro: 8-Bit Barrel Shifter

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Chapter 3

About Design ElementsThis section describes the design elements that can be used with this architecture. The design elements areorganized alphabetically.

The following information is provided for each design element, where applicable:

• Name of element

• Brief description

• Schematic symbol (if any)

• Logic Table (if any)

• Port Descriptions (if any)

• Design Entry Method

• Available Attributes (if any)

• For more information

You can find examples of VHDL and Verilog instantiation code in the ISE software (in the main menu, select Edit> Language Templates or in the Libraries Guide for HDL Designs for this architecture.

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Chapter 3: About Design Elements

ACC16Macro: 16-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset

IntroductionThis design element can add or subtract a 16-bit unsigned-binary, respectively or two’s-complement word toor from the contents of a 16-bit data register and store the results in the register. The register can be loadedwith the 16-bit word.

When the load input (L) is High, CE is ignored and the data on the D inputs is loaded into the register during theLow-to-High clock (C) transition. ACC16 loads the data on inputs D15 : D0 into the 16-bit register.

This design element operates on either 16-bit unsigned binary numbers or 16-bit two’s-complement numbers. Ifthe inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as two’s complement, the output can be interpreted as two’s complement. The only functionaldifference between an unsigned binary operation and a two’s-complement operation is how they determinewhen “overflow” occurs. Unsigned binary uses carry-out (CO), while two’s complement uses OFL to determinewhen “overflow” occurs.• For unsigned binary operation, ACC16 can represent numbers between 0 and 15, inclusive. In add mode,

CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is anactive-Low borrow-out and goes Low when the difference exceeds the bounds. The carry-out (CO) isnot registered synchronously with the data outputs. CO always reflects the accumulation of the B inputs(B15 : B0 for ACC16). This allows the cascading of ACC16s by connecting CO of one stage to CI of thenext stage. An unsigned binary “overflow” that is always active-High can be generated by gating theADD signal and CO as follows:unsigned overflow = CO XOR ADD

Ignore OFL in unsigned binary operation.• For two’s-complement operation, ACC16 represents numbers between -8 and +7, inclusive. If an addition

or subtraction operation result exceeds this range, the OFL output goes High. The overflow (OFL) is notregistered synchronously with the data outputs. OFL always reflects the accumulation of the B inputs (B15 :B0 for ACC16) and the contents of the register, which allows cascading of ACC4s by connecting OFL of onestage to CI of the next stage.Ignore CO in two’s-complement operation.

The synchronous reset (R) has priority over all other inputs, and when set to High, causes all outputs to go tologic level zero during the Low-to-High clock (C) transition. Clock (C) transitions are ignored when clockenable (CE) is Low.

This design element is asynchronously cleared, outputs Low, when power is applied. For FPGA devices,power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can beinverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

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Chapter 3: About Design Elements

Logic TableInput Output

R L CE ADD D C Q

1 x x x x ↑ 0

0 1 x x Dn ↑ Dn

0 0 1 1 x ↑ Q0+Bn+CI

0 0 1 0 x ↑ Q0-Bn-CI

0 0 0 x x ↑ No Change

Q0: Previous value of Q

Bn: Value of Data input B

CI: Value of input CI

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ACC4Macro: 4-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset

IntroductionThis design element can add or subtract a 4-bit unsigned-binary, respectively or two’s-complement word to orfrom the contents of a 4-bit data register and store the results in the register. The register can be loaded with the4-bit word.

When the load input (L) is High, CE is ignored and the data on the D inputs is loaded into the register during theLow-to-High clock (C) transition. ACC4 loads the data on inputs D3 : D0 into the 4-bit register.

This design element operates on either 4-bit unsigned binary numbers or 4-bit two’s-complement numbers. Ifthe inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as two’s complement, the output can be interpreted as two’s complement. The only functionaldifference between an unsigned binary operation and a two’s-complement operation is how they determinewhen “overflow” occurs. Unsigned binary uses carry-out (CO), while two’s complement uses OFL to determinewhen “overflow” occurs.

• For unsigned binary operation, ACC4 can represent numbers between 0 and 15, inclusive. In add mode,CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is anactive-Low borrow-out and goes Low when the difference exceeds the bounds. The carry-out (CO) isnot registered synchronously with the data outputs. CO always reflects the accumulation of the B inputs(B3 : B0 for ACC4). This allows the cascading of ACC4s by connecting CO of one stage to CI of the nextstage. An unsigned binary “overflow” that is always active-High can be generated by gating the ADDsignal and CO as follows:

unsigned overflow = CO XOR ADD

Ignore OFL in unsigned binary operation.

• For two’s-complement operation, ACC4 represents numbers between -8 and +7, inclusive. If an additionor subtraction operation result exceeds this range, the OFL output goes High. The overflow (OFL) is notregistered synchronously with the data outputs. OFL always reflects the accumulation of the B inputs (B3 :B0 for ACC4) and the contents of the register, which allows cascading of ACC4s by connecting OFL of onestage to CI of the next stage.

Ignore CO in two’s-complement operation.

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Chapter 3: About Design Elements

The synchronous reset (R) has priority over all other inputs, and when set to High, causes all outputs to go tologic level zero during the Low-to-High clock (C) transition. Clock (C) transitions are ignored when clockenable (CE) is Low.

This design element is asynchronously cleared, outputs Low, when power is applied. For FPGA devices,power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can beinverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInput Output

R L CE ADD D C Q

1 x x x x ↑ 0

0 1 x x Dn ↑ Dn

0 0 1 1 x ↑ Q0+Bn+CI

0 0 1 0 x ↑ Q0-Bn-CI

0 0 0 x x ↑ No Change

Q0: Previous value of Q

Bn: Value of Data input B

CI: Value of input CI

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ACC8Macro: 8-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset

IntroductionThis design element can add or subtract a 8-bit unsigned-binary, respectively or two’s-complement word to orfrom the contents of a 8-bit data register and store the results in the register. The register can be loaded with the8-bit word.

When the load input (L) is High, CE is ignored and the data on the D inputs is loaded into the register during theLow-to-High clock (C) transition. ACC8 loads the data on inputs D7 : D0 into the 8-bit register.

This design element operates on either 8-bit unsigned binary numbers or 8-bit two’s-complement numbers. Ifthe inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as two’s complement, the output can be interpreted as two’s complement. The only functionaldifference between an unsigned binary operation and a two’s-complement operation is how they determinewhen “overflow” occurs. Unsigned binary uses carry-out (CO), while two’s complement uses OFL to determinewhen “overflow” occurs.• For unsigned binary operation, ACC8 can represent numbers between 0 and 255, inclusive. In add mode,

CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is anactive-Low borrow-out and goes Low when the difference exceeds the bounds. The carry-out (CO) isnot registered synchronously with the data outputs. CO always reflects the accumulation of the B inputs(B3 : B0 for ACC4). This allows the cascading of ACC8s by connecting CO of one stage to CI of the nextstage. An unsigned binary “overflow” that is always active-High can be generated by gating the ADDsignal and CO as follows:unsigned overflow = CO XOR ADD

Ignore OFL in unsigned binary operation.• For two’s-complement operation, ACC8 represents numbers between -128 and +127, inclusive. If an addition

or subtraction operation result exceeds this range, the OFL output goes High. The overflow (OFL) is notregistered synchronously with the data outputs. OFL always reflects the accumulation of the B inputs (B3 :B0 for ACC8) and the contents of the register, which allows cascading of ACC8s by connecting OFL of onestage to CI of the next stage.Ignore CO in two’s-complement operation.

The synchronous reset (R) has priority over all other inputs, and when set to High, causes all outputs to go tologic level zero during the Low-to-High clock (C) transition. Clock (C) transitions are ignored when clockenable (CE) is Low.

This design element is asynchronously cleared, outputs Low, when power is applied. For FPGA devices,power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can beinverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

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Chapter 3: About Design Elements

Logic TableInput Output

R L CE ADD D C Q

1 x x x x ↑ 0

0 1 x x Dn ↑ Dn

0 0 1 1 x ↑ Q0+Bn+CI

0 0 1 0 x ↑ Q0-Bn-CI

0 0 0 x x ↑ No Change

Q0: Previous value of Q

Bn: Value of Data input B

CI: Value of input CI

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ADD16Macro: 16-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow

IntroductionThis design element adds two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow(OFL). The factors added are A15:A0, B15:B0 and CI, producing the sum output S15:S0 and CO (or OFL).

Logic TableInput Output

A B S

An Bn An+Bn+CI

CI: Value of input CI.

Unsigned Binary Versus Two’s Complement

This design element can operate on either 16-bit unsigned binary numbers or 16-bit two’s-complement numbers,respectively. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. Ifthe inputs are interpreted as two’s complement, the output can be interpreted as two’s complement. The onlyfunctional difference between an unsigned binary operation and a two’s-complement operation is the way theydetermine when “overflow” occurs. Unsigned binary uses CO, while two’s-complement uses OFL to determinewhen “overflow” occurs. To interpret the inputs as unsigned binary, follow the CO output. To interpret theinputs as two’s complement, follow the OFL output.

Unsigned Binary Operation

For unsigned binary operation, this element represents numbers between 0 and 65535, inclusive. OFL is ignoredin unsigned binary operation.

Two’s-Complement Operation

For two’s-complement operation, this element can represent numbers between -32768 and +32767, inclusive. OFLis active (High) when the sum exceeds the bounds of the adder. CO is ignored in two’s-complement operation.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ADD4Macro: 4-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow

IntroductionThis design element adds two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow(OFL). The factors added are A3:A0, B3:B0, and CI producing the sum output S3:S0 and CO (or OFL).

Logic TableInput Output

A B S

An Bn An+Bn+CI

CI: Value of input CI.

Unsigned Binary Versus Two’s Complement

This design element can operate on either 4-bit unsigned binary numbers or 4-bit two’s-complement numbers,respectively. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. Ifthe inputs are interpreted as two’s complement, the output can be interpreted as two’s complement. The onlyfunctional difference between an unsigned binary operation and a two’s-complement operation is the way theydetermine when “overflow” occurs. Unsigned binary uses CO, while two’s-complement uses OFL to determinewhen “overflow” occurs. To interpret the inputs as unsigned binary, follow the CO output. To interpret theinputs as two’s complement, follow the OFL output.

Unsigned Binary Operation

For unsigned binary operation, this element represents numbers from 0 to 15, inclusive. OFL is ignoredin unsigned binary operation.

Two’s-Complement Operation

For two’s-complement operation, this element can represent numbers between -8 and +7, inclusive. OFL is active(High) when the sum exceeds the bounds of the adder. CO is ignored in two’s-complement operation.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ADD8Macro: 8-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow

IntroductionThis design element adds two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow(OFL). The factors added are A7:A0, B7:B0, and CI, producing the sum output S7:S0 and CO (or OFL).

Logic TableInput Output

A B S

An Bn An+Bn+CI

CI: Value of input CI.

Unsigned Binary Versus Two’s Complement

This design element can operate on either 8-bit unsigned binary numbers or 8-bit two’s-complement numbers,respectively. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. Ifthe inputs are interpreted as two’s complement, the output can be interpreted as two’s complement. The onlyfunctional difference between an unsigned binary operation and a two’s-complement operation is the way theydetermine when “overflow” occurs. Unsigned binary uses CO, while two’s-complement uses OFL to determinewhen “overflow” occurs. To interpret the inputs as unsigned binary, follow the CO output. To interpret theinputs as two’s complement, follow the OFL output.

Unsigned Binary Operation

For unsigned binary operation, this element represents numbers between 0 and 255, inclusive. OFL is ignoredin unsigned binary operation.

Two’s-Complement Operation

For two’s-complement operation, this element can represent numbers between -128 and +127, inclusive. OFL isactive (High) when the sum exceeds the bounds of the adder. CO is ignored in two’s-complement operation.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ADSU16Macro: 16-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow

IntroductionWhen the ADD input is High, this element adds two 16-bit words (A15:A0 and B15:B0) and a carry-in (CI),producing a 16-bit sum output (S15:S0) and carry-out (CO) or overflow (OFL).

When the ADD input is Low, this element subtracts B15:B0 from A15:A0, producing a difference output anda carry-out (CO) or an overflow (OFL).

In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low. OFL is active-High inadd and subtract modes.

Logic TableInput Output

ADD A B S

1 An Bn An+Bn+CI*

0 An Bn An-Bn-CI*

CI*: ADD = 0, CI, CO active LOW

CI*: ADD = 1, CI, CO active HIGH

Unsigned Binary Versus Two’s Complement

This design element can operate on either 16-bit unsigned binary numbers or 16-bit two’s-complement numbers.If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as two’s complement, the output can be interpreted as two’s complement. The only functionaldifference between an unsigned binary operation and a two’s-complement operation is the way they determinewhen “overflow” occurs. Unsigned binary uses CO, while two’s complement uses OFL to determine when“overflow” occurs.

With adder/subtracters, either unsigned binary or two’s-complement operations cause an overflow. If theresult crosses the overflow boundary, an overflow is generated. Similarly, when the result crosses the carry-outboundary, a carry-out is generated.

Unsigned Binary Operation

For unsigned binary operation, this element can represent numbers between 0 and 65535, inclusive. In addmode, CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is anactive-Low borrow-out and goes Low when the difference exceeds the bounds.

An unsigned binary “overflow” that is always active-High can be generated by gating the ADD signal and COas follows:

unsigned overflow = CO XOR ADD

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Chapter 3: About Design Elements

OFL is ignored in unsigned binary operation.

Two’s-Complement Operation

For two’s-complement operation, this element can represent numbers between -32768 and +32767, inclusive.

If an addition or subtraction operation result exceeds this range, the OFL output goes High. CO is ignored intwo’s-complement operation.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ADSU4Macro: 4-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow

IntroductionWhen the ADD input is High, this element adds two 4-bit words (A3:A0 and B3:B0) and a carry-in (CI),producing a 4-bit sum output (S3:S0) and a carry-out (CO) or an overflow (OFL).

When the ADD input is Low, this element subtracts B3:B0 from A3:A0, producing a 4-bit difference output(S3:S0) and a carry-out (CO) or an overflow (OFL).

In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low. OFL is active-High inadd and subtract modes.

Logic TableInput Output

ADD A B S

1 An Bn An+Bn+CI*

0 An Bn An-Bn-CI*

CI*: ADD = 0, CI, CO active LOW

CI*: ADD = 1, CI, CO active HIGH

Unsigned Binary Versus Two’s Complement

This design element can operate on either 4-bit unsigned binary numbers or 4-bit two’s-complement numbers. Ifthe inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as two’s complement, the output can be interpreted as two’s complement. The only functionaldifference between an unsigned binary operation and a two’s-complement operation is the way they determinewhen “overflow” occurs. Unsigned binary uses CO, while two’s complement uses OFL to determine when“overflow” occurs.

With adder/subtracters, either unsigned binary or two’s-complement operations cause an overflow. If theresult crosses the overflow boundary, an overflow is generated. Similarly, when the result crosses the carry-outboundary, a carry-out is generated.

Unsigned Binary Operation

For unsigned binary operation, ADSU4 can represent numbers between 0 and 15, inclusive. In add mode, CO isactive (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is an active-Lowborrow-out and goes Low when the difference exceeds the bounds.

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Chapter 3: About Design Elements

An unsigned binary “overflow” that is always active-High can be generated by gating the ADD signal and COas follows:

unsigned overflow = CO XOR ADD

OFL is ignored in unsigned binary operation.

Two’s-Complement Operation

For two’s-complement operation, this element can represent numbers between -8 and +7, inclusive.

If an addition or subtraction operation result exceeds this range, the OFL output goes High. CO is ignored intwo’s-complement operation.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ADSU8Macro: 8-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow

IntroductionWhen the ADD input is High, this element adds two 8-bit words (A7:A0 and B7:B0) and a carry-in (CI),producing, an 8-bit sum output (S7:S0) and carry-out (CO) or an overflow (OFL).

When the ADD input is Low, this element subtracts B7:B0 from A7:A0, producing an 8-bit difference output(S7:S0) and a carry-out (CO) or an overflow (OFL).

In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low. OFL is active-High inadd and subtract modes.

Logic TableInput Output

ADD A B S

1 An Bn An+Bn+CI*

0 An Bn An-Bn-CI*

CI*: ADD = 0, CI, CO active LOW

CI*: ADD = 1, CI, CO active HIGH

Unsigned Binary Versus Two’s Complement

This design element can operate on either 8-bit unsigned binary numbers or 8-bit two’s-complement numbers. Ifthe inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as two’s complement, the output can be interpreted as two’s complement. The only functionaldifference between an unsigned binary operation and a two’s-complement operation is the way they determinewhen “overflow” occurs. Unsigned binary uses CO, while two’s complement uses OFL to determine when“overflow” occurs.

With adder/subtracters, either unsigned binary or two’s-complement operations cause an overflow. If theresult crosses the overflow boundary, an overflow is generated. Similarly, when the result crosses the carry-outboundary, a carry-out is generated.

Unsigned Binary Operation

For unsigned binary operation, this element can represent numbers between 0 and 255, inclusive. In add mode,CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is anactive-Low borrow-out and goes Low when the difference exceeds the bounds.

An unsigned binary “overflow” that is always active-High can be generated by gating the ADD signal and COas follows:unsigned overflow = CO XOR ADD

OFL is ignored in unsigned binary operation.

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Chapter 3: About Design Elements

Two’s-Complement Operation

For two’s-complement operation, this element can represent numbers between -128 and +127, inclusive.

If an addition or subtraction operation result exceeds this range, the OFL output goes High. CO is ignored intwo’s-complement operation.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND12Macro: 12- Input AND Gate with Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND1616- Input AND Gate with Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND2Primitive: 2-Input AND Gate with Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND2B1Primitive: 2-Input AND Gate with 1 Inverted and 1 Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND2B1LPrimitive: Two input AND gate implemented in place of a Slice Latch

IntroductionThis element allows the specification of a configurable Slice latch to take the function of a two input ANDgate with one input inverted (see Logic Table). The use of this element can reduce logic levels and increaselogic density of the part by trading off register/latch resources for logic. Xilinx suggests caution when usingthis component as it can affect register packing and density since specifying one or more AND2B1L or OR2Lcomponents in a Slice disallows the use of the remaining registers and latches.

Logic TableInputs Outputs

DI SRI O

0 0 0

0 1 0

1 0 1

1 1 0

Port DescriptionsPort Type Width Function

O Output 1 Output of the AND gate.

DI Input 1 Active high input that is generally connected to sourcing LUT locatedin the same Slice.

SRI Input 1 Active low input that is generally source from outside of the Slice.

Note To allow more than one AND2B1L or OR2B1L to be packed intoa single Slice, a common signal must be connected to this input.

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

AND2B2Primitive: 2-Input AND Gate with Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND3Primitive: 3-Input AND Gate with Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND3B1Primitive: 3-Input AND Gate with 1 Inverted and 2 Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND3B2Primitive: 3-Input AND Gate with 2 Inverted and 1 Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND3B3Primitive: 3-Input AND Gate with Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND4Primitive: 4-Input AND Gate with Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND4B1Primitive: 4-Input AND Gate with 1 Inverted and 3 Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND4B2Primitive: 4-Input AND Gate with 2 Inverted and 2 Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND4B3Primitive: 4-Input AND Gate with 3 Inverted and 1 Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND4B4Primitive: 4-Input AND Gate with Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND5Primitive: 5-Input AND Gate with Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND5B1Primitive: 5-Input AND Gate with 1 Inverted and 4 Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND5B2Primitive: 5-Input AND Gate with 2 Inverted and 3 Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND5B3Primitive: 5-Input AND Gate with 3 Inverted and 2 Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND5B4Primitive: 5-Input AND Gate with 4 Inverted and 1 Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND5B5Primitive: 5-Input AND Gate with Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND6Macro: 6-Input AND Gate with Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND7Macro: 7-Input AND Gate with Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND8Macro: 8-Input AND Gate with Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

AND9Macro: 9-Input AND Gate with Non-Inverted Inputs

IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

BRLSHFT4Macro: 4-Bit Barrel Shifter

IntroductionThis design element is a 4-bit barrel shifter that can rotate four inputs (I3 : I0) up to four places. The controlinputs (S1 and S0) determine the number of positions, from one to four, that the data is rotated. The four outputs(O3 : O0) reflect the shifted data inputs.

Logic TableInputs Outputs

S1 S0 I0 I1 I2 I3 O0 O1 O2 O3

0 0 a b c d a b c d

0 1 a b c d b c d a

1 0 a b c d c d a b

1 1 a b c d d a b c

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

BRLSHFT8Macro: 8-Bit Barrel Shifter

IntroductionThis design element is an 8-bit barrel shifter, can rotate the eight inputs (I7 : I0) up to eight places. The controlinputs (S2 : S0) determine the number of positions, from one to eight, that the data is rotated. The eight outputs(O7 : O0) reflect the shifted data inputs.

Logic TableInputs Outputs

S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 O0 O1 O2 O3 O4 O5 O6 O7

0 0 0 a b c d e f g h a b c d e f g h

0 0 1 a b c d e f g h b c d e f g h a

0 1 0 a b c d e f g h c d e f g h a b

0 1 1 a b c d e f g h d e f g h a b c

1 0 0 a b c d e f g h e f g h a b c d

1 0 1 a b c d e f g h f g h a b c d e

1 1 0 a b c d e f g h g h a b c d e f

1 1 1 a b c d e f g h h a b c d e f g

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

BSCAN_SPARTAN6Primitive: Spartan®-6 JTAG Boundary Scan Logic Control Circuit

IntroductionThis design element allows access to and from internal logic by the JTAG Boundary Scan logic controller. Thisallows for communication between the internal running design and the dedicated JTAG pins of the FPGA.

Each instance of this design element will handle one JTAG USER instruction (USER1 through USER4) as set withthe JTAG_CHAIN attribute. To handle all four USER instuctions, instantiate four of these elements and set theJTAG_CHAIN attribute appropriately.

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Chapter 3: About Design Elements

Port DescriptionsPort Type Width Function

CAPTURE Output 1 Active upon the loading of the USER instruction. Asserts High whenthe JTAG TAP controller is in the CAPTURE-DR state.

DRCK Output 1 A mirror of the TCK input pin to the FPGA when the JTAG USERinstruction assigned by JTAG_CHAIN is loaded and the JTAG TAPcontroller is in the SHIFT-DR state or in the CAPTURE-DR state.

RESET Output 1 Active upon the loading of the USER instruction. It asserts High whenthe JTAG TAP controller is in the TEST-LOGIC-RESET state.

RUNTEST Output 1 Indicates JTAG is in Run Test/Idle state.

SEL Output 1 Indicates when the USER instruction has been loaded into the JTAGInstruction Register. Becomes active in the UPDATE-IR state, and staysactive until a new instruction is loaded.

SHIFT Output 1 Active upon the loading of the USER instruction. It asserts High whenthe JTAG TAP controller is in the SHIFT-DR state.

TCK Output 1 The value of the TCK input pin to the FPGA.

TDI Output 1 A mirror of the TDI pin.

TMS Output 1 The value of the TMS input pin to the FPGA.

UPDATE Output 1 Active upon the loading of the USER instruction. It asserts High whenthe JTAG TAP controller is in the UPDATE-DR state.

TDO Input 1 Active upon the loading of the USER instruction. External JTAG TDOpin will reflect data input to the macro’s TDO pin.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

JTAG_CHAIN Integer 1, 2, 3, 4 1 Sets the JTAGUSER instruction number that this instanceof the element will handle.

For More Information• See the Spartan-6 FPGA Configuration User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

BUFPrimitive: General Purpose Buffer

IntroductionThis is a general-purpose, non-inverting buffer.

This element is not necessary and is removed by the partitioning software (MAP).

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

BUFCFPrimitive: Fast Connect Buffer

IntroductionThis design element is a single fast connect buffer used to connect the outputs of the LUTs and some dedicatedlogic directly to the input of another LUT. Using this buffer implies CLB packing. No more than four LUTsmay be connected together as a group.

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

BUFGPrimitive: Global Clock Buffer

IntroductionThis design element is a high-fanout buffer that connects signals to the global routing resources for low skewdistribution of the signal. BUFGs are typically used on clock nets.

Port DescriptionsPort Type Width Function

I Input 1 Clock buffer output

O Output 1 Clock buffer input

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Clocking Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

BUFGCEPrimitive: Global Clock Buffer with Clock Enable

IntroductionThis design element is a global clock buffer with a single gated input. Its O output is "0" when clock enable (CE)is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output.

Logic TableInputs Outputs

I CE O

X 0 0

I 1 I

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Clocking Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

BUFGCE_1Primitive: Global Clock Buffer with Clock Enable and Output State 1

IntroductionThis design element is a multiplexed global clock buffer with a single gated input. Its O output is High (1) whenclock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output.

Logic TableInputs Outputs

I CE O

X 0 1

I 1 I

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Clocking Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

BUFGMUXPrimitive: Global Clock MUX Buffer

IntroductionBUFGMUX is a multiplexed global clock buffer that can select between two input clocks: I0 and I1. When theselect input (S) is Low, the signal on I0 is selected for output (O). When the select input (S) is High, the signal onI1 is selected for output.

BUFGMUX and BUFGMUX_1 are distinguished by the state the output assumes when that output switchesbetween clocks in response to a change in its select input. BUGFMUX assumes output state 0 and BUFGMUX_1assumes output state 1.

Note BUFGMUX guarantees that when S is toggled, the state of the output remains in the inactive state until thenext active clock edge (either I0 or I1) occurs.

Logic TableInputs Outputs

I0 I1 S O

I0 X 0 I0

X I1 1 I1

X X ↑ 0

X X ↓ 0

Port DescriptionsPort Type Width Function

I0 Input 1 Clock0 input

I1 Input 1 Clock1 input

O Output 1 Clock MUX output

S Input 1 Clock select input

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

CLK_SEL_TYPE String “SYNC”, “ASYNC” “SYNC” Specifies synchronous or asynchronousclock.

DISABLE_VALUE String “HIGH”, “LOW” “LOW” Specifies the state the output assumeswhen switching between inputs.

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For More Information• See the Spartan-6 FPGA Clocking Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

BUFGMUX_1Primitive: Global Clock MUX Buffer with Output State 1

IntroductionThis design element is a multiplexed global clock buffer that can select between two input clocks: I0 and I1.When the select input (S) is Low, the signal on I0 is selected for output (0). When the select input (S) is High, thesignal on I1 is selected for output.

This design element is distinguished from BUFGMUX by the state the output assumes when that output switchesbetween clocks in response to a change in its select input. BUFGMUX assumes output state 0 and BUFGMUX_1assumes output state 1.

Logic TableInputs Outputs

I0 I1 S O

I0 X 0 I0

X I1 1 I1

X X ↑ 1

X X ↓ 1

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Clocking Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

BUFHPrimitive: Clock buffer for a single clocking region

IntroductionThe BUFH primitive is provided to allow instantiation capability to access the HCLK clock buffer resources.

Port DescriptionsPort Type Width Function

I Input 1 Clock Input

O Output 1 Clock Output

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

BUFIO2Primitive: Dual Clock Buffer and Strobe Pulse

IntroductionThis primitive takes a clock input and generates two clock outputs and a strobe pulse. The IOCLK output isa buffered version of the input clock. The period and duty cycle of the DIVCLK output is dependent on theattribute setting. If the DIVIDE_BYPASS is set to TRUE then the DIVCLK output is a buffered version of theinput clock and the SERDESSTOBE output is driven to 1. If DIVIDE_BYPASS is set to FALSE then the DIVCLKand SERDESSTROBE output are divided input clock by the setting of the divide attribute.

Port DescriptionsPort Type Width Function

DIVCLK Output 1 Divided clock

I Input 1 Clock input

IOCLK Output 1 Clock output

SERDESSTROBE Output 1 SERDES strobe (Clock Enable)

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

DIVIDE Decimal 1, 2, 3, 4, 5, 6, 7, 8 1 Set the DIVCLK divider divide-by value.

DIVIDE_BYPASS Boolean TRUE, FALSE TRUE DIVCLK output sourced from Divider(FALSE) or from I input, bypassing Divider(TRUE).

For More Information• See the Spartan-6 FPGA Clocking Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

BUFIO2_2CLKPrimitive: Dual Clock Buffer and Strobe Pulse with Differential Input

IntroductionThe BUFIO2_2CLK is used in conjunction with a BUFIO2 element when Double Data Rate (DDR) IO clocking isrequired. The this element is used to generate a SERDES strobe signal for the input and output serialiser blocksif required and also one of the necessary IO DDR clocks and a divided clock signal for forwarding to a globalbuffer, PLL or DCM. The second BUFIO2 generates the other required DDR IO clock.

The BUFIO2_2CLK can normally be replaced by a BUFIO2 using the “USE_DOUBLER” attribute set to “TRUE”when both the inverting and non-inverting inputs are connected to the same signal. One exception is when adifferential input clock is required together with an input delay. In that case the ‘P’ input signal is applied to thenon-inverting input (I) of the BUFIO2_2CLK via an input delay element, and the “N” input signal is applied tothe inverting input (IB) via a different input delay element.

Design Entry MethodTo instantiate this component, use MIG or an associated core containing the component. Xilinx does notrecommend direct instantiation of this component.

This design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Clocking Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

BUFIO2FBPrimitive: Feedback Clock Buffer.

IntroductionThis component is a simple buffer that has an attribute to determine the output delay. If DIVIDE_BYPASS is setto TRUE then the delays are equivalent to the BUFIO2 bypass delay. When set to FALSE, the delays are similar tothe BUFIO2 DIVCLK outputs to keep the outputs of the BUFIO2 and BUFIO2FB phase aligned.

Port DescriptionsPort Type Width Function

I Input 1 Input feedback clock.

O Output 1 Output feedback clock

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

DIVIDE_BYPASS Boolean TRUE, FALSE TRUE DIVCLK output sourced from Divider(FALSE) or from I input, bypassing Divider(TRUE). If FALSE, also need to set CLKDIVDIVIDE value to 1.

For More Information• See the Spartan-6 FPGA Clocking Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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BUFPLLPrimitive: PLL Buffer

IntroductionThe BUFPLL is intended to be used in high speed IO routing to generate SERDES clocks and strobe pulses andalso to align the LOCKED output of the PLL with the GCLK, SERDES strobe and PLL clocks. The IOCLK outputis a buffered version of the input clock. The LOCK output is not aligned to any clocks. The LOCKED outputserves the exact same function as the PLL locked signals except that they do not go High until the PLL has lockedand the BUFPLL has aligned the SERDESSTROBE signal correctly.

Port DescriptionsPort Type Width Function

GCLK Input 1 GCLK clock input.

IOCLK Output 1 PLL clock output.

LOCK Output 1 Synchronized LOCK output.

LOCKED Input 1 LOCKED sign from PLL input.

PLLIN Input 1 PLL clock input.

SERDESSTROBE Output 1 SERDES strobe (clock enable).

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

DIVIDE Integer 1, 2, 3, 4, 5, 6, 7, 8 1 Sets the PLLIN divider divide-by valuefor SERDESSTROBE.

For More Information• See the Spartan-6 FPGA Clocking Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

CARRY4Primitive: Fast Carry Logic with Look Ahead

IntroductionThis circuit design represents the fast carry logic for a slice. The carry chain consists of a series of four MUXesand four XORs that connect to the other logic (LUTs) in the slice via dedicated routes to form more complexfunctions. The fast carry logic is useful for building arithmetic functions like adders, counters, subtractors andadd/subs, as well as such other logic functions as wide comparators, address decoders, and some logic gates(specifically, AND and OR).

Port DescriptionsPort Direction Width Function

O Output 4 Carry chain XOR general data out

CO Output 4 Carry-out of each stage of the carry chain

DI Input 4 Carry-MUX data input

S Input 4 Carry-MUX select line

CYINIT Input 1 Carry-in initialization input

CI Input 1 Carry cascade input

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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CB16CEMacro: 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is an asynchronously clearable, cascadable binary counter. The asynchronous clear (CLR)input, when High, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out(CEO) to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input(CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE C Qz-Q0 TC CEO

1 X X 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB16CLEMacro: 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear

IntroductionThis element is a synchronously loadable, asynchronously clearable, cascadable binary counter. Theasynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs, terminalcount (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data on theD inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clocktransition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during theLow-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is Highwhen all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

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Logic TableInputs Outputs

CLR L CE C Dz-D0 Qz-Q0 TC CEO

1 X X X X 0 0 0

0 1 X ↑ Dn Dn TC CEO

0 0 0 X X No change No change 0

0 0 1 ↑ X Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB16CLEDMacro: 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable andAsynchronous Clear

IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. The asynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs,terminal count (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data onthe D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock(C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High andUP is Low during the Low-to- High clock transition. The Q outputs increment when CE and UP are High. Thecounter ignores clock transitions when CE is Low.

For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.

For CPLD parts, see “CB2X1”, “CB4X1”, “CB8X1”, “CB16X1” for high-performance cascadable, bidirectionalcounters.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE C UP Dz-D0 Qz-Q0 TC CEO

1 X X X X X 0 0 0

0 1 X ↑ X Dn Dn TC CEO

0 0 0 X X X No change No change 0

0 0 1 ↑ 1 X Inc TC CEO

0 0 1 ↑ 0 X Dec TC CEO

z = bit width - 1

TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)

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Chapter 3: About Design Elements

Inputs Outputs

CLR L CE C UP Dz-D0 Qz-Q0 TC CEO

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB16REMacro: 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

IntroductionThis design element is a synchronous, resettable, cascadable binary counter. The synchronous reset (R), whenHigh, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out (CEO) tozero on the Low-to-High clock transition. The Q outputs increment when the clock enable input (CE) is Highduring the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TCoutput is High when both Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE C Qz-Q0 TC CEO

1 X ↑ 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0)

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB2CEMacro: 2-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is an asynchronously clearable, cascadable binary counter. The asynchronous clear (CLR)input, when High, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out(CEO) to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input(CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE C Qz-Q0 TC CEO

1 X X 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB2CLEMacro: 2-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear

IntroductionThis element is a synchronously loadable, asynchronously clearable, cascadable binary counter. Theasynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs, terminalcount (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data on theD inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clocktransition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during theLow-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is Highwhen all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE C Dz-D0 Qz-Q0 TC CEO

1 X X X X 0 0 0

0 1 X ↑ Dn Dn TC CEO

0 0 0 X X No change No change 0

0 0 1 ↑ X Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 131

Chapter 3: About Design Elements

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB2CLEDMacro: 2-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable andAsynchronous Clear

IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. The asynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs,terminal count (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data onthe D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock(C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High andUP is Low during the Low-to- High clock transition. The Q outputs increment when CE and UP are High. Thecounter ignores clock transitions when CE is Low.

For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.

For CPLD parts, see “CB2X1”, “CB4X1”, “CB8X1”, “CB16X1” for high-performance cascadable, bidirectionalcounters.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE C UP Dz-D0 Qz-Q0 TC CEO

1 X X X X X 0 0 0

0 1 X ↑ X Dn Dn TC CEO

0 0 0 X X X No change No change 0

0 0 1 ↑ 1 X Inc TC CEO

0 0 1 ↑ 0 X Dec TC CEO

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Inputs Outputs

CLR L CE C UP Dz-D0 Qz-Q0 TC CEO

z = bit width - 1

TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB2REMacro: 2-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

IntroductionThis design element is a synchronous, resettable, cascadable binary counter. The synchronous reset (R), whenHigh, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out (CEO) tozero on the Low-to-High clock transition. The Q outputs increment when the clock enable input (CE) is Highduring the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TCoutput is High when both Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE C Qz-Q0 TC CEO

1 X ↑ 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0)

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB4CEMacro: 4-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is an asynchronously clearable, cascadable binary counter. The asynchronous clear (CLR)input, when High, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out(CEO) to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input(CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE C Qz-Q0 TC CEO

1 X X 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB4CLEMacro: 4-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear

IntroductionThis element is a synchronously loadable, asynchronously clearable, cascadable binary counter. Theasynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs, terminalcount (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data on theD inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clocktransition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during theLow-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is Highwhen all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE C Dz-D0 Qz-Q0 TC CEO

1 X X X X 0 0 0

0 1 X ↑ Dn Dn TC CEO

0 0 0 X X No change No change 0

0 0 1 ↑ X Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB4CLEDMacro: 4-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable andAsynchronous Clear

IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. The asynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs,terminal count (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data onthe D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock(C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High andUP is Low during the Low-to- High clock transition. The Q outputs increment when CE and UP are High. Thecounter ignores clock transitions when CE is Low.

For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.

For CPLD parts, see “CB2X1”, “CB4X1”, “CB8X1”, “CB16X1” for high-performance cascadable, bidirectionalcounters.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

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Chapter 3: About Design Elements

Logic TableInputs Outputs

CLR L CE C UP Dz-D0 Qz-Q0 TC CEO

1 X X X X X 0 0 0

0 1 X ↑ X Dn Dn TC CEO

0 0 0 X X X No change No change 0

0 0 1 ↑ 1 X Inc TC CEO

0 0 1 ↑ 0 X Dec TC CEO

z = bit width - 1

TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB4REMacro: 4-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

IntroductionThis design element is a synchronous, resettable, cascadable binary counter. The synchronous reset (R), whenHigh, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out (CEO) tozero on the Low-to-High clock transition. The Q outputs increment when the clock enable input (CE) is Highduring the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TCoutput is High when both Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE C Qz-Q0 TC CEO

1 X ↑ 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0)

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB8CEMacro: 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is an asynchronously clearable, cascadable binary counter. The asynchronous clear (CLR)input, when High, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out(CEO) to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input(CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE C Qz-Q0 TC CEO

1 X X 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB8CLEMacro: 8-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear

IntroductionThis element is a synchronously loadable, asynchronously clearable, cascadable binary counter. Theasynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs, terminalcount (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data on theD inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clocktransition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during theLow-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is Highwhen all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

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Chapter 3: About Design Elements

Logic TableInputs Outputs

CLR L CE C Dz-D0 Qz-Q0 TC CEO

1 X X X X 0 0 0

0 1 X ↑ Dn Dn TC CEO

0 0 0 X X No change No change 0

0 0 1 ↑ X Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB8CLEDMacro: 8-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable andAsynchronous Clear

IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. The asynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs,terminal count (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data onthe D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock(C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High andUP is Low during the Low-to- High clock transition. The Q outputs increment when CE and UP are High. Thecounter ignores clock transitions when CE is Low.

For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.

For CPLD parts, see “CB2X1”, “CB4X1”, “CB8X1”, “CB16X1” for high-performance cascadable, bidirectionalcounters.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE C UP Dz-D0 Qz-Q0 TC CEO

1 X X X X X 0 0 0

0 1 X ↑ X Dn Dn TC CEO

0 0 0 X X X No change No change 0

0 0 1 ↑ 1 X Inc TC CEO

0 0 1 ↑ 0 X Dec TC CEO

z = bit width - 1

TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)

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Inputs Outputs

CLR L CE C UP Dz-D0 Qz-Q0 TC CEO

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CB8REMacro: 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

IntroductionThis design element is a synchronous, resettable, cascadable binary counter. The synchronous reset (R), whenHigh, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out (CEO) tozero on the Low-to-High clock transition. The Q outputs increment when the clock enable input (CE) is Highduring the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TCoutput is High when both Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE C Qz-Q0 TC CEO

1 X ↑ 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0)

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CC16CEMacro: 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is an asynchronously clearable, cascadable binary counter. It is implemented using carrylogic with relative location constraints to ensure efficient logic placement. The asynchronous clear (CLR) is thehighest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), andclock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment whenthe clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clocktransitions when CE is Low. The TC output is High when all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE C Qz-Q0 TC CEO

1 X X 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CC16CLEMacro: 16-Bit Loadable Cascadable Binary Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable binary counter. It isimplemented using carry logic with relative location constraints to ensure efficient logic placement. Theasynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored;the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clocktransitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during theLow-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs increment whenCE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE C Dz-D0 Qz-Q0 TC CEO

1 X X X X 0 0 0

0 1 X ↑ Dn Dn TC CEO

0 0 0 X X No change No change 0

0 0 1 ↑ X Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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CC16CLEDMacro: 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable andAsynchronous Clear

IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. It is implemented using carry logic with relative location constraints, which assures most efficient logicplacement. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs areignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent ofclock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is Highduring the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputsdecrement when CE is High and UP is Low during the Low-to-High clock transition. The Q outputs incrementwhen CE and UP are High. The counter ignores clock transitions when CE is Low.

For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE C UP Dz-D0 Qz-Q0 TC CEO

1 X X X X X 0 0 0

0 1 X ↑ X Dn Dn TC CEO

0 0 0 X X X No change No change 0

0 0 1 ↑ 1 X Inc TC CEO

0 0 1 ↑ 0 X Dec TC CEO

z = bit width - 1

TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)

CEO = TC•CE

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Chapter 3: About Design Elements

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CC16REMacro: 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

IntroductionThis design element is a synchronous resettable, cascadable binary counter. These counters are implementedusing carry logic with relative location constraints to ensure efficient logic placement. The synchronous reset(R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count(TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock (C) transition. The Q outputsincrement when the clock enable input (CE) is High during the Low-to-High clock transition. The counterignores clock transitions when CE is Low. The TC output is High when all Q outputs and CE are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE C Qz-Q0 TC CEO

1 X ↑ 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0)

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CC8CEMacro: 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is an asynchronously clearable, cascadable binary counter. It is implemented using carrylogic with relative location constraints to ensure efficient logic placement. The asynchronous clear (CLR) is thehighest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), andclock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment whenthe clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clocktransitions when CE is Low. The TC output is High when all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE C Qz-Q0 TC CEO

1 X X 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CC8CLEMacro: 8-Bit Loadable Cascadable Binary Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable binary counter. It isimplemented using carry logic with relative location constraints to ensure efficient logic placement. Theasynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored;the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clocktransitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during theLow-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs increment whenCE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE C Dz-D0 Qz-Q0 TC CEO

1 X X X X 0 0 0

0 1 X ↑ Dn Dn TC CEO

0 0 0 X X No change No change 0

0 0 1 ↑ X Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

CC8CLEDMacro: 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable andAsynchronous Clear

IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. It is implemented using carry logic with relative location constraints, which assures most efficient logicplacement. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs areignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent ofclock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is Highduring the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputsdecrement when CE is High and UP is Low during the Low-to-High clock transition. The Q outputs incrementwhen CE and UP are High. The counter ignores clock transitions when CE is Low.

For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE C UP Dz-D0 Qz-Q0 TC CEO

1 X X X X X 0 0 0

0 1 X ↑ X Dn Dn TC CEO

0 0 0 X X X No change No change 0

0 0 1 ↑ 1 X Inc TC CEO

0 0 1 ↑ 0 X Dec TC CEO

z = bit width - 1

TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)

CEO = TC•CE

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Chapter 3: About Design Elements

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CC8REMacro: 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset

IntroductionThis design element is a synchronous resettable, cascadable binary counter. These counters are implementedusing carry logic with relative location constraints to ensure efficient logic placement. The synchronous reset(R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count(TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock (C) transition. The Q outputsincrement when the clock enable input (CE) is High during the Low-to-High clock transition. The counterignores clock transitions when CE is Low. The TC output is High when all Q outputs and CE are High.

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE C Qz-Q0 TC CEO

1 X ↑ 0 0 0

0 0 X No change No change 0

0 1 ↑ Inc TC CEO

z = bit width - 1

TC = Qz•Q(z-1)•Q(z-2)•...•Q0)

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CD4CEMacro: 4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous Clear

IntroductionCD4CE is a 4-bit (stage), asynchronous clearable, cascadable binary-coded-decimal (BCD) counter. Theasynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored;the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clocktransitions. The Q outputs increment when clock enable (CE) is High during the Low-to-High clock (C)transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 areHigh and Q2 and Q1 are Low.

The counter recovers from any of six possible illegal states and returns to a normal count sequence within twoclock cycles for Xilinx® devices, as shown in the following state diagram:

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

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Logic TableInputs Outputs

CLR CE C Q3 Q2 Q1 Q0 TC CEO

1 X X 0 0 0 0 0 0

0 1 ↑ Inc Inc Inc Inc TC CEO

0 0 X No Change No Change No Change No Change TC 0

0 1 X 1 0 0 1 1 1

TC = Q3•!Q2•!Q1•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CD4CLEMacro: 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Asynchronous Clear

IntroductionCD4CLE is a 4-bit (stage), synchronously loadable, asynchronously clearable, binarycoded- decimal (BCD)counter. The asynchronous clear input (CLR) is the highest priority input. When (CLR) is High, all other inputsare ignored; the (Q) outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independentof clock transitions. The data on the (D) inputs is loaded into the counter when the load enable input (L) is Highduring the Low-to-High clock (C) transition. The (Q) outputs increment when clock enable input (CE) is Highduring the Low- to-High clock transition. The counter ignores clock transitions when (CE) is Low. The (TC)output is High when Q3 and Q0 are High and Q2 and Q1 are Low.

The counter recovers from any of six possible illegal states and returns to a normal count sequence within twoclock cycles for Xilinx® devices, as shown in the following state diagram:

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

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Chapter 3: About Design Elements

Logic TableInputs Outputs

CLR L CE D3 : D0 C Q3 Q2 Q1 Q0 TC CEO

1 X X X X 0 0 0 0 0 0

0 1 X D3 : D0 ↑ D3 D2 D1 D0 TC CEO

0 0 1 X ↑ Inc Inc Inc Inc TC CEO

0 0 0 X X NoChange

NoChange

NoChange

NoChange

TC 0

0 0 1 X X 1 0 0 1 1 1

TC = Q3•!Q2•!Q1•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CD4REMacro: 4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset

IntroductionCD4RE is a 4-bit (stage), synchronous resettable, cascadable binary-coded-decimal (BCD) counter. Thesynchronous reset input (R) is the highest priority input. When (R) is High, all other inputs are ignored; the(Q) outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock(C) transition. The (Q) outputs increment when the clock enable input (CE) is High during the Low-to- Highclock transition. The counter ignores clock transitions when (CE) is Low. The (TC) output is High when Q3and Q0 are High and Q2 and Q1 are Low.

The counter recovers from any of six possible illegal states and returns to a normal count sequence within twoclock cycles for Xilinx® devices, as shown in the following state diagram:

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

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Chapter 3: About Design Elements

Logic TableInputs Outputs

R CE C Q3 Q2 Q1 Q0 TC CEO

1 X ↑ 0 0 0 0 0 0

0 1 ↑ Inc Inc Inc Inc TC CEO

0 0 X No Change No Change No Change No Change TC 0

0 1 X 1 0 0 1 1 1

TC = Q3•!Q2•!Q1•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CD4RLEMacro: 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Synchronous Reset

IntroductionCD4RLE is a 4-bit (stage), synchronous loadable, resettable, binary-coded-decimal (BCD) counter. Thesynchronous reset input (R) is the highest priority input. When R is High, all other inputs are ignored; theQ outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clocktransitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during theLow-to-High clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during theLow-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is Highwhen Q3 and Q0 are High and Q2 and Q1 are Low.

The counter recovers from any of six possible illegal states and returns to a normal count sequence within twoclock cycles for Xilinx® devices, as shown in the following state diagram:

Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

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Chapter 3: About Design Elements

Logic TableInputs Outputs

R L CE D3 : D0 C Q3 Q2 Q1 Q0 TC CEO

1 X X X ↑ 0 0 0 0 0 0

0 1 X D3 : D0 ↑ D3 D D D0 TC CEO

0 0 1 X ↑ Inc Inc Inc Inc TC CEO

0 0 0 X X No Change NoChange

NoChange

NoChange

TC 0

0 0 1 X X 1 0 0 1 1 1

TC = Q3•!Q2•!Q1•Q0

CEO = TC•CE

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CFGLUT5Primitive: 5-input Dynamically Reconfigurable Look-Up Table (LUT)

IntroductionThis element is a runtime, dynamically reconfigurable, 5-input look-up table (LUT) that enables the changingof the logical function of the LUT during circuit operation. Using the CDI pin, a new INIT value can besynchronously shifted in serially to change the logical function. The O6 output pin produces the logical outputfunction, based on the current INIT value loaded into the LUT and the currently selected I0-I4 input pins.Optionally, you can use the O5 output in combination with the O6 output to create two individual 4-inputfunctions sharing the same inputs or a 5-input function and a 4-input function that uses a subset of the 5-inputlogic (see tables below). This component occupies one of the four 6-LUT components within a slice.

To cascade this element, connect the CDO pin from each element to the CDI input of the next element. This willallow a single serial chain of data (32-bits per LUT) to reconfigure multiple LUTs.

Port DescriptionsPort Direction Width Function

O6 Output 1 5-LUT output

O5 Output 1 4-LUT output

I0, I1, I2, I3, I4 Input 1 LUT inputs

CDO Output 1 Reconfiguration data cascaded output (optionally connect to the CDI inputof a subsequent LUT)

CDI Input 1 Reconfiguration data serial input

CLK Input 1 Reconfiguration clock

CE Input 1 Active high reconfiguration clock enable

Design Entry MethodThis design element can be used in schematics.• Connect the CLK input to the clock source used to supply the reconfiguration data.• Connect the CDI input to the source of the reconfiguration data.• Connect the CE pin to the active high logic if you need to enable/disable LUT reconfiguration.• Connect the I4-I0 pins to the source inputs to the logic equation. The logic function is output on O6 and O5.• To cascade this element, connect the CDO pin from each element to the CDI input of the next element to

allow a single serial chain of data to reconfigure multiple LUTs.

The INIT attribute should be placed on this design element to specify the initial logical function of the LUT. Anew INIT can be loaded into the LUT any time during circuit operation by shifting in 32-bits per LUT in thechain, representing the new INIT value. Disregard the O6 and O5 output data until all 32-bits of new INIT datahas been clocked into the LUT. The logical function of the LUT changes as new INIT data is shifted into it. Datashould be shifted in MSB (INIT[31]) first and LSB (INIT[0]) last.

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Chapter 3: About Design Elements

In order to understand the O6 and O5 logical value based on the current INIT, see the table below:

I4 I3 I2 I1 I0 O6 Value O5 Value

1 1 1 1 1 INIT[31] INIT[15]

1 1 1 1 0 INIT[30] INIT[14]. . . . . . . . .

1 0 0 0 1 INIT[17] INIT[1]

1 0 0 0 0 INIT[16] INIT[0]

0 1 1 1 1 INIT[15] INIT[15]

0 1 1 1 0 INIT[14] INIT[14]. . . . . . . . .

0 0 0 0 1 INIT[1] INIT[1]

0 0 0 0 0 INIT[0] INIT[0]

For instance, the INIT value of FFFF8000 would represent the following logical equations:

• O6 = I4 or (I3 and I2 and I1 and I0)

• O5 = I3 and I2 and I1 and I0

To use these elements as two, 4-input LUTs with the same inputs but different functions, tie the I4 signal to alogical one. The INIT[31:16] values apply to the logical values of the O6 output and INIT [15:0] apply to thelogical values of the O5 output.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 32-bit Value All zeros Specifies the initial logical expression ofthis element.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

CJ4CE4-Bit Johnson Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is a clearable Johnson/shift counter. The asynchronous clear (CLR) input, when High,overrides all other inputs and forces the data (Q) outputs to logic level zero, independent of clock (C) transitions.The counter increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when (CE) is Low.

The Q3 output is inverted and fed back to input Q0 to provide continuous counting operation.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE C Q0 Q1 through Q3

1 X X 0 0

0 0 X No change No change

0 1 ↑ !q3 q0 through q2

q = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CJ4REMacro: 4-Bit Johnson Counter with Clock Enable and Synchronous Reset

IntroductionThis design element is a resettable Johnson/shift counter. The synchronous reset (R) input, when High, overridesall other inputs and forces the data (Q) outputs to logic level zero during the Low-to-High clock (C) transition.The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when CE is Low.

The Q3 output is inverted and fed back to input Q0 to provide continuous counting operation.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE C Q0 Q1 through Q3

1 X ↑ 0 0

0 0 X No change No change

0 1 ↑ !q3 q0 through q2

q = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CJ5CEMacro: 5-Bit Johnson Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is a clearable Johnson/shift counter. The asynchronous clear (CLR) input, when High,overrides all other inputs and forces the data (Q) outputs to logic level zero, independent of clock (C) transitions.The counter increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when (CE) is Low.

The Q4 output is inverted and fed back to input Q0 to provide continuous counting operation.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE C Q0 Q1 through Q4

1 X X 0 0

0 0 X No change No change

0 1 ↑ !q4 q0 through q3

q = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CJ5REMacro: 5-Bit Johnson Counter with Clock Enable and Synchronous Reset

IntroductionThis design element is a resettable Johnson/shift counter. The synchronous reset (R) input, when High, overridesall other inputs and forces the data (Q) outputs to logic level zero during the Low-to-High clock (C) transition.The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when CE is Low.

The Q4 output is inverted and fed back to input Q0 to provide continuous counting operation.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE C Q0 Q1 through Q4

1 X ↑ 0 0

0 0 X No change No change

0 1 ↑ !q4 q0 through q3

q = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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CJ8CEMacro: 8-Bit Johnson Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is a clearable Johnson/shift counter. The asynchronous clear (CLR) input, when High,overrides all other inputs and forces the data (Q) outputs to logic level zero, independent of clock (C) transitions.The counter increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when (CE) is Low.

The Q7 output is inverted and fed back to input Q0 to provide continuous counting operation.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE C Q0 Q1 through Q8

1 X X 0 0

0 0 X No change No change

0 1 ↑ !q7 q0 through q7

q = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CJ8REMacro: 8-Bit Johnson Counter with Clock Enable and Synchronous Reset

IntroductionThis design element is a resettable Johnson/shift counter. The synchronous reset (R) input, when High, overridesall other inputs and forces the data (Q) outputs to logic level zero during the Low-to-High clock (C) transition.The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when CE is Low.

The Q7 output is inverted and fed back to input Q0 to provide continuous counting operation.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE C Q0 Q1 through Q7

1 X ↑ 0 0

0 0 X No change No change

0 1 ↑ !q7 q0 through q6

q = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

COMP16Macro: 16-Bit Identity Comparator

IntroductionThis design element is a 16-bit identity comparator. The equal output (EQ) is high when A15 : A0 and B15 :B0 are equal.

Equality is determined by a bit comparison of the two words. When any two of the corresponding bits fromeach word are not the same, the EQ output is Low.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

COMP2Macro: 2-Bit Identity Comparator

IntroductionThis design element is a 2-bit identity comparator. The equal output (EQ) is High when the two words A1 : A0and B1 : B0 are equal.

Equality is determined by a bit comparison of the two words. When any two of the corresponding bits fromeach word are not the same, the EQ output is Low.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

COMP4Macro: 4-Bit Identity Comparator

IntroductionThis design element is a 4-bit identity comparator. The equal output (EQ) is high when A3 : A0 and B3 : B0 areequal.

Equality is determined by a bit comparison of the two words. When any two of the corresponding bits fromeach word are not the same, the EQ output is Low.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

COMP8Macro: 8-Bit Identity Comparator

IntroductionThis design element is an 8-bit identity comparator. The equal output (EQ) is high when A7 : A0 and B7 :B0 are equal.

Equality is determined by a bit comparison of the two words. When any two of the corresponding bits fromeach word are not the same, the EQ output is Low.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

COMPM16Macro: 16-Bit Magnitude Comparator

IntroductionThis design element is a 16-bit magnitude comparator that compare two positive Binary-weighted words. Itcompares A15 : A0 and B15 : B0, where A15 and B15 are the most significant bits.

The greater-than output (GT) is High when A > B, and the less-than output (LT) is High when A < B Whenthe two words are equal, both GT and LT are Low. Equality can be measured with this macro by comparingboth outputs with a NOR gate.

Logic TableInputs Outputs

A7, B7 A6, B6 A5, B5 A4, B4 A3, B3 A2, B2 A1, B1 A0, B0 GT LT

A7>B7 X X X X X X X 1 0

A7<B7 X X X X X X X 0 1

A7=B7 A6>B6 X X X X X X 1 0

A7=B7 A6<B6 X X X X X X 0 1

A7=B7 A6=B6 A5>B5 X X X X X 1 0

A7=B7 A6=B6 A5<B5 X X X X X 0 1

A7=B7 A6=B6 A5=B5 A4>B4 X X X X 1 0

A7=B7 A6=B6 A5=B5 A4<B4 X X X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3>B3 X X X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3<B3 X X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2>B2 X X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2<B2 X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1>B1 X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1<B1 X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0>B0 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0<B0 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0=B0 0 0

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

COMPM2Macro: 2-Bit Magnitude Comparator

IntroductionThis design element is a 2-bit magnitude comparator that compare two positive binary-weighted words. Itcompares A1 : A0 and B1 : B0, where A1 and B1 are the most significant bits.

The greater-than output (GT) is High when A > B, and the less-than output (LT) is High when A < B Whenthe two words are equal, both GT and LT are Low. Equality can be measured with this macro by comparingboth outputs with a NOR gate.

Logic TableInputs Outputs

A1 B1 A0 B0 GT LT

0 0 0 0 0 0

0 0 1 0 1 0

0 0 0 1 0 1

0 0 1 1 0 0

1 1 0 0 0 0

1 1 1 0 1 0

1 1 0 1 0 1

1 1 1 1 0 0

1 0 X X 1 0

0 1 X X 0 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

COMPM4Macro: 4-Bit Magnitude Comparator

IntroductionThis design element is a 4-bit magnitude comparator that compare two positive Binary-weighted words. Itcompares A3 : A0 and B3 : B0, where A3 and B3 are the most significant bits.

The greater-than output (GT) is High when A > B, and the less-than output (LT) is High when A < B Whenthe two words are equal, both GT and LT are Low. Equality can be measured with this macro by comparingboth outputs with a NOR gate.

Logic TableInputs Outputs

A3, B3 A2, B2 A1, B1 A0, B0 GT LT

A3>B3 X X X 1 0

A3<B3 X X X 0 1

A3=B3 A2>B2 X X 1 0

A3=B3 A2<B2 X X 0 1

A3=B3 A2=B2 A1>B1 X 1 0

A3=B3 A2=B2 A1<B1 X 0 1

A3=B3 A2=A2 A1=B1 A0>B0 1 0

A3=B3 A2=B2 A1=B1 A0<B0 0 1

A3=B3 A2=B2 A1=B1 A0=B0 0 0

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

COMPM8Macro: 8-Bit Magnitude Comparator

IntroductionThis design element is an 8-bit magnitude comparator that compare two positive Binary-weighted words. Itcompares A7 : A0 and B7 : B0, where A7 and B7 are the most significant bits.

The greater-than output (GT) is High when A > B, and the less-than output (LT) is High when A < B Whenthe two words are equal, both GT and LT are Low. Equality can be measured with this macro by comparingboth outputs with a NOR gate.

Logic TableInputs Outputs

A7, B7 A6, B6 A5, B5 A4, B4 A3, B3 A2, B2 A1, B1 A0, B0 GT LT

A7>B7 X X X X X X X 1 0

A7<B7 X X X X X X X 0 1

A7=B7 A6>B6 X X X X X X 1 0

A7=B7 A6<B6 X X X X X X 0 1

A7=B7 A6=B6 A5>B5 X X X X X 1 0

A7=B7 A6=B6 A5<B5 X X X X X 0 1

A7=B7 A6=B6 A5=B5 A4>B4 X X X X 1 0

A7=B7 A6=B6 A5=B5 A4<B4 X X X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3>B3 X X X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3<B3 X X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2>B2 X X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2<B2 X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1>B1 X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1<B1 X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0>B0 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0<B0 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0=B0 0 0

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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COMPMC16Macro: 16-Bit Magnitude Comparator

IntroductionThis design element is a 16-bit, magnitude comparator that compares two positive Binary weighted words A15 :A0 and B15 : B0, where A15 and B15 are the most significant bits.

This comparator is implemented using carry logic with relative location constraints to ensure efficient logicplacement.

The greater-than output (GT) is High when A>B, and the less-than output (LT) is High when A<B. When thetwo words are equal, both GT and LT are Low. Equality can be flagged with this macro by connecting bothoutputs to a NOR gate.

Logic TableInputs Outputs

A7, B7 A6, B6 A5, B5 A4, B4 A3, B3 A2, B2 A1, B1 A0, B0 GT LT

A7>B7 X X X X X X X 1 0

A7<B7 X X X X X X X 0 1

A7=B7 A6>B6 X X X X X X 1 0

A7=B7 A6<B6 X X X X X X 0 1

A7=B7 A6=B6 A5>B5 X X X X X 1 0

A7=B7 A6=B6 A5<B5 X X X X X 0 1

A7=B7 A6=B6 A5=B5 A4>B4 X X X X 1 0

A7=B7 A6=B6 A5=B5 A4<B4 X X X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3>B3 X X X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3<B3 X X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2>B2 X X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2<B2 X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1>B1 X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1<B1 X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0>B0 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0<B0 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0=B0 0 0

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

COMPMC8Macro: 8-Bit Magnitude Comparator

IntroductionThis design element is an 8-bit, magnitude comparator that compares two positive Binaryweighted words A7 :A0 and B7 : B0, where A7 and B7 are the most significant bits.

This comparator is implemented using carry logic with relative location constraints to ensure efficient logicplacement.

The greater-than output (GT) is High when A>B, and the less-than output (LT) is High when A<B. When thetwo words are equal, both GT and LT are Low. Equality can be flagged with this macro by connecting bothoutputs to a NOR gate.

Logic TableInputs Outputs

A7, B7 A6, B6 A5, B5 A4, B4 A3, B3 A2, B2 A1, B1 A0, B0 GT LT

A7>B7 X X X X X X X 1 0

A7<B7 X X X X X X X 0 1

A7=B7 A6>B6 X X X X X X 1 0

A7=B7 A6<B6 X X X X X X 0 1

A7=B7 A6=B6 A5>B5 X X X X X 1 0

A7=B7 A6=B6 A5<B5 X X X X X 0 1

A7=B7 A6=B6 A5=B5 A4>B4 X X X X 1 0

A7=B7 A6=B6 A5=B5 A4<B4 X X X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3>B3 X X X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3<B3 X X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2>B2 X X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2<B2 X X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1>B1 X 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1<B1 X 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0>B0 1 0

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0<B0 0 1

A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0=B0 0 0

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CR16CEMacro: 16-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is a 16-bit cascadable, clearable, binary ripple counter with clock enable and asynchronousclear.

Larger counters can be created by connecting the last Q output of the first stage to the clock input of the nextstage. CLR and CE inputs are connected in parallel. The clock period is not affected by the overall length of aripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the number of stages and the timetC - Q is the C-to-Qz propagation delay of each stage.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE C Qz : Q0

1 X X 0

0 0 X No Change

0 1 ↓ Inc

z = bit width - 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

CR8CEMacro: 8-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear

IntroductionThis design element is an 8-bit cascadable, clearable, binary, ripple counter with clock enable and asynchronousclear.

The asynchronous clear (CLR), when High, overrides all other inputs and causes the Q outputs to go to logiclevel zero. The counter increments when the clock enable input (CE) is High during the High-to-Low clock (C)transition. The counter ignores clock transitions when CE is Low.

Larger counters can be created by connecting the last Q output of the first stage to the clock input of the nextstage. CLR and CE inputs are connected in parallel. The clock period is not affected by the overall length of aripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the number of stages and the timetC - Q is the C-to-Qz propagation delay of each stage.

This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE C Qz : Q0

1 X X 0

0 0 X No Change

0 1 ↓ Inc

z = bit width - 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

D2_4EMacro: 2- to 4-Line Decoder/Demultiplexer with Enable

IntroductionThis design element is a decoder/demultiplexer. When the enable (E) input of this element is High, one of fouractive-High outputs (D3 : D0) is selected with a 2-bit binary address (A1 : A0) input. The non-selected outputsare Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the E input is thedata input.

Logic TableInputs Outputs

A1 A0 E D3 D2 D1 D0

X X 0 0 0 0 0

0 0 1 0 0 0 1

0 1 1 0 0 1 0

1 0 1 0 1 0 0

1 1 1 1 0 0 0

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

D3_8EMacro: 3- to 8-Line Decoder/Demultiplexer with Enable

IntroductionWhen the enable (E) input of the D3_8E decoder/demultiplexer is High, one of eight active-High outputs (D7 :D0) is selected with a 3-bit binary address (A2 : A0) input. The non-selected outputs are Low. Also, when the Einput is Low, all outputs are Low. In demultiplexer applications, the E input is the data input.

Logic TableInputs Outputs

A2 A1 A0 E D7 D6 D5 D4 D3 D2 D1 D0

X X X 0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0 1

0 0 1 1 0 0 0 0 0 0 1 0

0 1 0 1 0 0 0 0 0 1 0 0

0 1 1 1 0 0 0 0 1 0 0 0

1 0 0 1 0 0 0 1 0 0 0 0

1 0 1 1 0 0 1 0 0 0 0 0

1 1 0 1 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

D4_16EMacro: 4- to 16-Line Decoder/Demultiplexer with Enable

IntroductionThis design element is a decoder/demultiplexer. When the enable (E) input of this design element is High, oneof 16 active-High outputs (D15 : D0) is selected with a 4-bit binary address (A3 : A0) input. The non-selectedoutputs are Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the Einput is the data input.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

DCM_CLKGENPrimitive: Digital Clock Manager.

IntroductionSpartan®-6 devices contain up to 8 10 DCMs that are placed in the center column of the chip with PLLs. DigitalClock Managers (DCMs) provide flexible, complete control over clock frequency and provide advanced clockingcapabilities including clock network deskew, frequency synthesis and phase shift.

Port DescriptionsPort Type Width Function

CLKFX Output 1 Generated output clock.

CLKFXDV Output 1 Divided output clock, Divide value derived fromCLKFXDV_DIV attribute.

Note There is no phase alignment between CLKFXand CLKFXDV.

CLKFX180 Output 1 Generated output clock 180 degree out of phasefrom CLKFX.

CLKIN Input 1 The source clock (CLKIN) input pin provides thesource clock to the DCM.

In the case of Free-running oscillator mode, runningclock needs to be connected until DCM is lockedand DCM is frozen, then clock can be removed. Inthe other modes, a free running clock needs to beprovided and remain.

FREEZEDCM Input 1 Prevents tap adjustment drift in the event of a lostCLKIN input.

LOCKED Output 1 Synchronous output from the DCM that providesthe user with an indication that the DCM is readyfor operation.

PROGCLK Input 1 Clock input for M and/or D reconfiguration.

PROGDATA Input 1 Serial data input to supply information for thereprogramming of M and/or D values of the DCM.This input must be applied synchronous to thePROGCLK input.

PROGDONE Output 1 Active high output to indicate the successfulreprogramming of an M or D value.

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Port Type Width Function

PROGEN Input 1 Active high enable input for the reprogrammingof M/D values. This input must be appliedsynchronously to the PROGCLK input.

RST Input 1 Resets the DCM circuitry. The RST signal is an activeHigh asynchronous reset. Asserting the RST signalasynchronously forces all DCM outputs Low (theLOCKED signal, all status signals, and all outputclocks within four source clock cycles). Because thereset is asynchronous, the last cycle of the clocks canexhibit an unintended short pulse, severely distortedduty-cycle, and no longer phase adjust with respectto one another while deasserting. The RST pin mustbe used when reconfiguring the device or changingthe input frequency. Deasserting the RST signalsynchronously starts the locking process at the nextCLKIN cycle. To ensure a proper DCM reset andlocking process, the RST signal must be deassertedafter the CLKIN signal has been present and stablefor at least three clock cycles. In all designs, the DCMmust be held in reset until the clock is stable. Duringconfiguration, the DCM is automatically held inreset until GSR is released. If the clock is stable whenGSR is released, DCM reset after configuration isnot necessary.

STATUS[2:1] Output 2 Clock Status lines.

• STATUS[1] indicates that CLKIN has stopped.

• STATUS[2] indicates that CLKFX or CLKFX180has stopped.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

CLKFX_DIVIDE Integer 1 to 256 1 This value in conjunctionwith the input frequencyand CLKFX_MULTIPLY value,determines the resultant outputfrequency for the CLKFX andCLKFX180 outputs.

CLKFXDV_DIVIDE Integer 2, 4, 8, 16, 32 2 Specifies divide value forCLKFXDV.

CLKFX_MD_MAX 3 significantdigit Float

0.000 to256.000

0.000 When using the DCM_CLKGENwith variable M and D values, thiswould specify the maximum ratio ofM and D used during static timinganalysis.

CLKFX_MULTIPLY Integer 2 to 256 4 This value in conjunctionwith the input frequency andCLKFX_DIVIDE value, determinethe resultant output frequency forthe CLKFX and CLKFX180 outputs.

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Attribute Type Allowed Values Default Description

CLKIN_PERIOD String 0 bit String “10.0” This attribute specifies the sourceclock period which is used to helpthe DCM adjust for the optimumCLKFX/CLKFX180 outputs and alsoresult in faster locking time.

DFS_BANDWIDTH String “OPTIMIZED”,“HIGH”,“LOW”

“OPTIMIZED” Specifies the frequency adjustbandwidth of the DCM due toprocess, voltage, and temperature(PVT).

PROG_MD_BANDWIDTH

String “OPTIMIZED”,“HIGH”,“LOW”

“OPTIMIZED” Specifies the frequency adjustbandwidth of the DCM due tochange of programming of the Mand D values.

SPREAD_SPECTRUM String “NONE”,“CUSTOM”,“LOW_EMISSION_24_DOWN_SPREAD”,“VIDEO_LINK_75_CENTER_SPREAD”,“VIDEO_LINK_90_CENTER_SPREAD”

“NONE” Specifies a supported mode forSpread Spectrum. Must be used inconjunction with the appropriateIP to fully realize the frequencyhopping.

STARTUP_WAIT Boolean FALSE, TRUE FALSE Delays the configuration DONEsignal until DCM LOCKED signalgoes high.

For More Information• See the Spartan-6 FPGA Clocking Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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DCM_SPPrimitive: Digital Clock Manager

IntroductionThis design element is a digital clock manager that provides multiple functions. It can implement a clock delaylocked loop (DLL), a digital frequency synthesizer (DFS), and a digital phase shifter (DPS). DCM_SPs are usefulfor eliminating the clock delay coming on and off the chip, shifting the clock phase to improve data capture,deriving different frequency clocks, as well as other useful clocking functions.

Port DescriptionsPort Type Width Function

CLKDV Output 1 Divided version of CLK0. Divide value is programmable.

CLKFB Input 1 Feedback clock input to DCM. The feedback input is required unlessthe DFS is used stand-alone. The source of CLKFB must be CLK0 orCLK2X output from the DCM.

CLKFX Output 1 Digital Frequency Synthesizer output (DFS).

CLKFX180 Output 1 180 degree shifted version of the CLKFX clock.

CLKIN Input 1 Clock input for the DCM.

CLK0 Output 1 Same frequency as CLKIN, 0 degree phase shift.

CLK2X Output 1 Two times CLKIN frequency clock, aligned with CLK0.

CLK2X180 Output 1 180 degree shifted version of the CLK2X clock.

CLK90 Output 1 Same frequency as CLKIN, 90 degree phase shift.

CLK180 Output 1 Same frequency as CLKIN, 180 degree phase shift.

CLK270 Output 1 Same frequency as CLKIN, 180 degree phase shift.

LOCKED Output 1 Signal indicating when the DCM has LOCKed.

PSCLK Input 1 Phase shift clock input. The PSCLK input pin provides the source clockfor the DCM phase shift.

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Chapter 3: About Design Elements

Port Type Width Function

PSDONE Output 1 Output signal that indicates variable phase shift is done.

PSEN Input 1 Variable Phase Shift enable signal, synchronous with PSCLK.

PSINCDEC Input 1 The phase shift increment/decrement (PSINCDEC) input signal must besynchronous with PSCLK. The PSINCDEC signal is used to incrementor decrement the phase shift factor when PSEN is activated. ThePSINCDEC is asserted High for increment and Low for decrement.

RST Input 1 The reset input pin (RST) resets the DCM circuitry. The RST signal is anactive High asynchronous reset.

STATUS[7:0] Output 8 The status output bus provides DCM status.

• STATUS[0] - Variable Phase Shift Overflow.

• STATUS[1] - CLKIN Stopped.

• STATUS[2] - CLKFX or CLKFX180 Stopped.

• STATUS[7] - CLKFB stopped.

• STATUS[6:3] - Reserved.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed_Values Default Description

CLKDV_DIVIDE 1 significantdigit Float

2.0, 1.5, 2.5, 3.0,3.5, 4.0, 4.5, 5.0,5.5, 6.0, 6.5, 7.0,7.5, 8.0, 9.0, 10.0,11.0, 12.0, 13.0,14.0, 15.0, 16.0

2.0 Specifies the extent to which the CLKDLL,CLKDLLE, CLKDLLHF, or DCM_SPclock divider (CLKDV output) is to befrequency divided.

CLK_FEEDBACK String “1X”, “2X”,“NONE”

“1X” Defines the DCM feedbcak mode.

• 1X: CLK0 as feedback.

• 2X: CLK2X as feedback.

CLKFX_DIVIDE Integer 1 to 32 1 Specifies the frequency divider value forthe CLKFX output.

CLKFX_MULTIPLY Integer 2 to 32 4 Specifies the frequency multiplier valuefor the CLKFX output.

CLKIN_DIVIDE_BY_2

Boolean FALSE, TRUE FALSE Enables CLKIN divide by two features.

CLKIN_PERIOD String 0 bit String “10.0” Specifies the input period to the DCM_SPCLKIN input in ns.

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Attribute Type Allowed_Values Default Description

CLKOUT_PHASE_SHIFT

String “NONE”,“FIXED”,“VARIABLE”

“NONE” This attribute specifies the phase shiftmode.

• NONE: No phase shift capability.Any set value has no effect.

• FIXED: DCM outputs are a fixedphase shift from CLKIN. Value isspecified by PHASE_SHIFT attribute.

• VARIABLE: Allows the DCM outputsto be shifted in a positive and negativerange relative to CLKIN. Startingvalue is specified by PHASE_SHIFT.

DESKEW_ADJUST String “SYSTEM_SYNCHRONOUS”,“SOURCE_SYNCHRONOUS”

“SYSTEM_SYNCHRONOUS”

Sets configuration bits affecting the clockdelay alignment between the DCM_SPoutput clocks and an FPGA clock inputpin.

DLL_FREQUENCY_MODE

String “LOW”, “HIGH” “LOW” AUTO mode allows DLL to do automaticfrequency search to decide whether DLLwill operate in Low or High mode. Thisis a legacy attribute where the High andLow value has no affect, it is always inauto mode.

DSS_MODE String “NONE”,“SPREAD_2”,“SPREAD_4”,“SPREAD_6”,“SPREAD_8”

“NONE” Specifies a frequency spread for outputclocks.

• NONE - The default, specifies nospread factors. The digital spreadspectrum function is disabled.

• SPREAD_2 - Creates a new clockperiod that is +/- 50 ps of the currentclock period

• SPREAD_4 - Creates a new clockperiod that is +/- 100 ps of the currentclock period.

• SPREAD_6 - Creates a new clockperiod that is +/- 150 ps of the currentclock period.

• SPREAD_8 - Creates a new clockperiod that is +/- 200 ps of the currentclock period.

The spreading is cumulative as theSPREAD_# is increased. For example,SPREAD_2 creates two additional clockfrequencies at +/-50 ps relative to theinput clock frequency; SPREAD_4 doesthe same as SPREAD_2, plus it createstwo additional clock frequencies at +/-100ps.

DUTY_CYCLE_CORRECTION

Boolean TRUE, FALSE TRUE Corrects the duty cycle of the CLK0,CLK90, CLK180, and CLK270 outputs.

PHASE_SHIFT Integer -255 to 255 0 Defines the amount of fixed phase shiftfrom -255 to 255.

STARTUP_WAIT Boolean FALSE, TRUE FALSE Delays configuration DONE until DCMLOCK.

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For More Information• See the Spartan-6 FPGA Clocking Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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DEC_CC16Macro: 16-Bit Active Low Decoder

IntroductionThis design element is a 16-bit decoder that is used to build wide-decoder functions. It is implemented bycascading CY_MUX elements driven by look-up tables (LUTs). The C_IN pin can only be driven by the output (O)of a previous decode stage. When one or more of the inputs (A) are Low, the output is Low. When all the inputsare High and the C_IN input is High, the output is High. You can decode patterns by adding inverters to inputs.

Logic TableInputs Outputs

A0 A1 … Az C_IN O

1 1 1 1 1 1

X X X X 0 0

0 X X X X 0

X 0 X X X 0

X X X 0 X 0

z = 3 for DEC_CC4; z = 7 for DEC_CC8; z = 15 for DEC_CC16

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

DEC_CC4Macro: 4-Bit Active Low Decoder

IntroductionThis design element is a 4-bit decoder that is used to build wide-decoder functions. It is implemented bycascading CY_MUX elements driven by look-up tables (LUTs). The C_IN pin can only be driven by the output (O)of a previous decode stage. When one or more of the inputs (A) are Low, the output is Low. When all the inputsare High and the C_IN input is High, the output is High. You can decode patterns by adding inverters to inputs.

Logic TableInputs Outputs

A0 A1 … Az C_IN O

1 1 1 1 1 1

X X X X 0 0

0 X X X X 0

X 0 X X X 0

X X X 0 X 0

z = 3 for DEC_CC4; z = 7 for DEC_CC8; z = 15 for DEC_CC16

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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DEC_CC8Macro: 8-Bit Active Low Decoder

IntroductionThis design element is a 8-bit decoder that is used to build wide-decoder functions. It is implemented bycascading CY_MUX elements driven by look-up tables (LUTs). The C_IN pin can only be driven by the output (O)of a previous decode stage. When one or more of the inputs (A) are Low, the output is Low. When all the inputsare High and the C_IN input is High, the output is High. You can decode patterns by adding inverters to inputs.

Logic TableInputs Outputs

A0 A1 … Az C_IN O

1 1 1 1 1 1

X X X X 0 0

0 X X X X 0

X 0 X X X 0

X X X 0 X 0

z = 3 for DEC_CC4; z = 7 for DEC_CC8; z = 15 for DEC_CC16

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

DECODE16Macro: 16-Bit Active-Low Decoder

IntroductionThis design element is a 4-bit, active-low decoder that is implemented using combinations of LUTs and MUXCYs.

Logic TableInputs Outputs*

A0 A1 … Az O

1 1 1 1 1

0 X X X 0

X 0 X X 0

X X X 0 0

z = bitwidth -1

*A pull-up resistor must be connected to the output to establish High-level drive current.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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DECODE32Macro: 32-Bit Active-Low Decoder

IntroductionThis design element is a 32-bit active-low decoder that is implemented using combinations of LUTs andMUXCYs.

Logic TableInputs Outputs

A0 A1 … Az O

1 1 1 1 1

0 X X X 0

X 0 X X 0

X X X 0 0

z = 31 for DECODE32, z = 63 for DECODE64

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

DECODE4Macro: 4-Bit Active-Low Decoder

IntroductionThis design element is a 4-bit, active-low decoder that is implemented using combinations of LUTs and MUXCYs.

Logic TableInputs Outputs*

A0 A1 … Az O

1 1 1 1 1

0 X X X 0

X 0 X X 0

X X X 0 0

z = bitwidth -1

*A pull-up resistor must be connected to the output to establish High-level drive current.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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DECODE64Macro: 64-Bit Active-Low Decoder

IntroductionThis design element is a 64-bit active-low decoder that is implemented using combinations of LUTs andMUXCYs.

Logic TableInputs Outputs

A0 A1 … Az O

1 1 1 1 1

0 X X X 0

X 0 X X 0

X X X 0 0

z = 31 for DECODE32, z = 63 for DECODE64

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

DECODE8Macro: 8-Bit Active-Low Decoder

IntroductionThis design element is a 8-bit, active-low decoder that is implemented using combinations of LUTs andMUXCY’s.

Logic TableInputs Outputs*

A0 A1 … Az O

1 1 1 1 1

0 X X X 0

X 0 X X 0

X X X 0 0

z = bitwidth -1

*A pull-up resistor must be connected to the output to establish High-level drive current.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

DNA_PORTPrimitive: Device DNA Data Access Port

IntroductionThe DNA_PORT allows access to a dedicated shift register that can be loaded with the Device DNA data bits(unique ID) for a given device. In addition to shifting out the DNA data bits, this component allows for theinclusion of supplemental data bits for additional data, or allows for the DNA data to rollover (repeat DNA dataafter initial data has been shifted out). This component is primarily used in conjunction with other circuitry tobuild added copy protection for the FPGA bitstream from possible theft.

Port DescriptionsPort Type Width Function

CLK Input 1 Input clock to the shift register.

DIN Input 1 User data input to the shift register.

DOUT Output 1 Serial-shifted output register.

READ Input 1 Synchronous load of the shift register.

SHIFT Input 1 Active High shift enabled input.

Design Entry MethodThis design element can be used in schematics.

Connect all inputs and outputs to the design to ensure proper operation.

To access the Device DNA data, you must first load the shift register by setting the active high READ signal forone clock cycle. After the shift register is loaded, the data can be synchronously shifted out by enabling the activehigh SHIFT input and capturing the data out the DOUT output port. Additional data can be appended to the endof the 57-bit shift register by connecting the appropriate logic to the DIN port. If DNA data rollover is desired,connect the DOUT port directly to the DIN port to allow for the same data to be shifted out after completing the57-bit shift operation. If no additional data is necessary, the DIN port can be tied to a logic zero. The attributeSIM_DNA_VALUE can be optionally set to allow for simulation of a possible DNA data sequence. By default,the Device DNA data bits are all zeros in the simulation model.

Available AttributesAttribute Type Allowed Values Default Description

SIM_DNA_VALUE Hexa-decimal

57’h000000000000000 to57’h1ffffffffffffff

57’h000000000000000

Specifies a DNA value for simulationpurposes (the actual value is particular tothe specific device used).

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For More Information• See the Spartan-6 FPGA Configuration User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

• See the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

DSP48A1Primitive: Multi-Functional, Cascadable, 48-bit Output, Arithmetic Block

IntroductionThis element is a versatile, scalable, hard IP block that allows for the creation of compact, high-speed,arithmetic-intensive operations, such as those seen for many DSP algorithms. The block consists of a configurable,18-bit, pre-add/sub, followed by an 18x18 signed multiplier, followed by a 48-bit post-add/sub/accum. Severalconfigurable pipeline registers exist within the block, allowing for higher clock speeds with the trade-off ofadded latency. Opmode pins allow the block operation to change from one clock-cycle to the next, thus allowinga single block to serve several arithmetic functions within a design. Furthermore, multiple DSP48A1 blocks canbe cascaded to efficiently form larger multiplication and addition functions.

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Port DescriptionsPort Direction Width Function

Data Ports

A Input 18 18-bit data input to multiplier or post add/sub depending on thevalue of OPMODE[1:0].

B Input 18 18-bit data input to multiplier, pre-add/sub and, perhaps, apost-add/sub depending on the value of OPMODE[3:0].

C Input 48 48-bit data input to post-add/sub.

D Input 18 18-bit data input to pre-add/sub.

CARRYIN Input 1 External carry input to the post-add/sub. Connect only to theCARRYOUT pin of another DSP48A1 block.

P Output 48 Primary data output.

CARRYOUTF Output 1 Carry out signal for post-add/sub that can be routed into the fabric.

CARRYOUT Output 1 Carry out signal for post-add/sub. Connect only to the CARRYINpin of another DSP48A1.

Control Inputs

CLK Input 1 DSP48A1 clock

OPMODE Input 8 Control input to select the arithmetic operations of the DSP48A1.

Reset/Clock Enable Inputs

RSTA Input 1 Active high reset for the A port registers (A0REG=1 or A1REG=1).Tie to logic zero if not used. This reset is configurable to besynchronous or asynchronous, depending on the value of theRSTTYPE attribute.

RSTB Input 1 Active high reset for the B port registers (B0REG=1 or B1REG=1). Tieto logic zero if not used. This reset is configurable to be synchronousor asynchronous, depending on the value of the RSTTYPE attribute.

RSTC Input 1 Active high reset for the C port registers (CREG=1). Tie to logiczero if not used. This reset is configurable to be synchronous orasynchronous depending on the value of the RSTTYPE attribute.

RSTD Input 1 Active high reset for the D port registers (DREG=1). Tie to logiczero if not used. This reset is configurable to be synchronous orasynchronous depending on the value of the RSTTYPE attribute.

RSTM Input 1 Active high reset for the multiplier registers (MREG=1). Tie to logiczero if not used. This reset is configurable to be synchronous orasynchronous depending on the value of the RSTTYPE attribute.

RSTP Input 1 Active high, reset for the P output registers (PREG=1). Tie to logiczero if not used. This reset is configurable to be synchronous orasynchronous depending on the value of the RSTTYPE attribute.

RSTCARRYIN Input 1 Active high reset for the carry-in register (CARRYINREG =1). Tie tologic zero if not used. This reset is configurable to be synchronousor asynchronous depending on the value of the RSTTYPE attribute.

RSTOPMODE Input 1 Active high reset for the OPMODE registers (OPMODEREG=1). Tieto logic zero if not used. This reset is configurable to be synchronousor asynchronous depending on the value of the RSTTYPE attribute.

CEA Input 1 Active high clock enable for the A port registers (A0REG=1 orA1REG=1). Tie to logic one if not used and A0REG=1 or A1REG=1.Tie to logic zero if A0REG=0 and A1REG=0.

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Port Direction Width Function

CEB Input 1 Active high clock enable for the B port registers (B0REG=1 orB1REG=1). Tie to logic one if not used and B0REG=1 or B1REG=1.Tie to logic zero if B0REG=0 and B1REG=0.

CEC Input 1 Active high clock enable for the C port registers (CREG=1). Tie tologic one if not used and CREG=1. Tie to logic zero if CREG=0.

CED Input 1 Active high clock enable for the D port registers (DREG=1). Tie tologic one if not used and DREG=1. Tie to logic zero if DREG=0.

CEM Input 1 Active high clock enable for the multiplier registers (MREG=1). Tieto logic one if not used and MREG=1. Tie to logic zero if MREG=0.

CEP Input 1 Active high, clock enable for the output port registers (PREG=1). Tieto logic one if not used and PREG=1. Tie to logic zero if PREG=0.

CECARRYIN Input 1 Active high, clock enable for the carry-in registers(CARRYINREG=1). Tie to logic one if not used andCARRYINREG=1. Tie to a logic zero if CARRINREG=0.

CEOPMODE Input 1 Active high clock enable for the OPMODE input registers(OPMODEREG=1). Tie to logic one if not used andOPMODEREG=1. Tie to logic zero if OPMODEREG=0.

Cascade Ports

PCIN Input 48 Cascade input for Port P. If used, connect to PCOUT of upstreamcascaded DSP48A1. If not used, tie port to all zeros.

PCOUT Output 48 Cascade output for Port P. If used, connect to PCIN of downstreamcascaded DSP48A1. If not used, leave unconnected.

BCOUT Output 18 Cascade output for Port B. If used, connect to the B port ofdownstream cascaded DSP48A1. If not used, leave unconnected.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

A0REG Integer 0, 1 0 Selects whether to register the first stage A inputto the DSP48A1.

A1REG Integer 1, 0 1 Selects whether to register the second stage Ainput to the DSP48A1.

B0REG Integer 0, 1 0 Selects whether to register the first stage B inputto the DSP48A1.

B1REG Integer 1, 0 1 Selects whether to register the second stage Binput to the DSP48A1.

CARRYINREG Integer 1, 0 1 Selects usage of CARRYOUT output pipelineregisters. Set to 1 to use the CARRYOUTpipeline registers. The registered outputs willinclude CARRYOUT and CARRYOUTF.

CARRYINSEL String “CARRYIN”,“OPMODE5”

“OPMODE5” Selects whether the post add/sub carry-insignal should be sourced from the CARRYINpin (connected to the CARRYOUT of anotherDSP48A1) or dynamically controlled from theFPGA fabric by the OPMODE[5] input.

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Chapter 3: About Design Elements

Attribute Type Allowed Values Default Description

CARRYOUTREG Integer 1, 0 1 Output pipeline register. Enable=1/disable=0

CREG Integer 1, 0 1 Selects whether to register the C input to theDSP48A1.

DREG Integer 1, 0 1 Selects usage of D pre-adder input pipelineregisters. Set to 1 to use the D pipeline registers.

MREG Integer 1, 0 1 Selects whether to register the multiplier stageof the DSP48A1. Enable=1/disable=0.

OPMODEREG Integer 1, 0 1 Selects usage of OPMODE input pipelineregisters. Set to 1 to use the OPMODE pipelineregisters.

PREG Integer 1, 0 1 Selects whether to register the C input to theDSP48A1.

RSTTYPE String “SYNC”,“ASYNC”

“SYNC” Selects whether all resets for the DSP48A1should have a synchronous or asynchronousreset capability. Due to improved timing andcircuit stability, it is recommended to alwayshave this set to ’SYNC’ unless an asynchronousreset is absolutely necessary.

For More Information• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

• See the Spartan-6 FPGA DSP48A1 Slice User Guide.

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Chapter 3: About Design Elements

FDPrimitive: D Flip-Flop

IntroductionThis design element is a D-type flip-flop with data input (D) and data output (Q). The data on the D inputs isloaded into the flip-flop during the Low-to-High clock (C) transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

0 ↑ 0

1 ↑ 1

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FD_1Primitive: D Flip-Flop with Negative-Edge Clock

IntroductionThis design element is a single D-type flip-flop with data input (D) and data output (Q). The data on the (D)input is loaded into the flip-flop during the High-to-Low clock (C) transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

0 ↓ 0

1 ↓ 1

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FD16CEMacro: 16-Bit Data Register with Clock Enable and Asynchronous Clear

IntroductionThis design element is a 16-bit data register with clock enable and asynchronous clear. When clock enable (CE) isHigh and asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the correspondingdata outputs (Q) during the Low-to-High clock (C) transition. When CLR is High, it overrides all other inputsand resets the data outputs (Q) Low. When CE is Low, clock transitions are ignored.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE Dz : D0 C Qz : Q0

1 X X X 0

0 0 X X No Change

0 1 Dn ↑ Dn

z = bit-width - 1

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary Any 16-bitValue

All zeros Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FD16REMacro: 16-Bit Data Register with Clock Enable and Synchronous Reset

IntroductionThis design element is a 16-bit data registers. When the clock enable (CE) input is High, and the synchronousreset (R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q0)during the Low-to-High clock (C) transition. When R is High, it overrides all other inputs and resets the dataoutputs (Q) Low on the Low-to-High clock transition. When CE is Low, clock transitions are ignored.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE Dz : D0 C Qz : Q0

1 X X ↑ 0

0 0 X X No Change

0 1 Dn ↑ Dn

z = bit-width - 1

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary Any 16-Bit Value All zeros Sets the initial value of Q output afterconfiguration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FD4CEMacro: 4-Bit Data Register with Clock Enable and Asynchronous Clear

IntroductionThis design element is a 4-bit data register with clock enable and asynchronous clear. When clock enable (CE) isHigh and asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the correspondingdata outputs (Q) during the Low-to-High clock (C) transition. When CLR is High, it overrides all other inputsand resets the data outputs (Q) Low. When CE is Low, clock transitions are ignored.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE Dz : D0 C Qz : Q0

1 X X X 0

0 0 X X No Change

0 1 Dn ↑ Dn

z = bit-width - 1

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary Any 4-Bit Value All zeros Sets the initial value of Q output afterconfiguration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FD4REMacro: 4-Bit Data Register with Clock Enable and Synchronous Reset

IntroductionThis design element is a 4-bit data registers. When the clock enable (CE) input is High, and the synchronous reset(R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q0) during theLow-to-High clock (C) transition. When R is High, it overrides all other inputs and resets the data outputs (Q)Low on the Low-to-High clock transition. When CE is Low, clock transitions are ignored.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE Dz : D0 C Qz : Q0

1 X X ↑ 0

0 0 X X No Change

0 1 Dn ↑ Dn

z = bit-width - 1

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary Any 4-Bit Value All zeros Sets the initial value of Q output after configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FD8CEMacro: 8-Bit Data Register with Clock Enable and Asynchronous Clear

IntroductionThis design element is a 8-bit data register with clock enable and asynchronous clear. When clock enable (CE) isHigh and asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the correspondingdata outputs (Q) during the Low-to-High clock (C) transition. When CLR is High, it overrides all other inputsand resets the data outputs (Q) Low. When CE is Low, clock transitions are ignored.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE Dz : D0 C Qz : Q0

1 X X X 0

0 0 X X No Change

0 1 Dn ↑ Dn

z = bit-width - 1

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary Any 8-Bit Value All zeros Sets the initial value of Q output afterconfiguration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FD8REMacro: 8-Bit Data Register with Clock Enable and Synchronous Reset

IntroductionThis design element is an 8-bit data register. When the clock enable (CE) input is High, and the synchronous reset(R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q0) during theLow-to-High clock (C) transition. When R is High, it overrides all other inputs and resets the data outputs (Q)Low on the Low-to-High clock transition. When CE is Low, clock transitions are ignored.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE Dz : D0 C Qz : Q0

1 X X ↑ 0

0 0 X X No Change

0 1 Dn ↑ Dn

z = bit-width - 1

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary Any 8-Bit Value Allzeros

Sets the initial value of Q output afterconfiguration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDCPrimitive: D Flip-Flop with Asynchronous Clear

IntroductionThis design element is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and dataoutput (Q). The asynchronous CLR, when High, overrides all other inputs and sets the (Q) output Low. The dataon the (D) input is loaded into the flip-flop when CLR is Low on the Low-to-High clock transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR D C Q

1 X X 0

0 D ↑ D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDC_1Primitive: D Flip-Flop with Negative-Edge Clock and Asynchronous Clear

IntroductionFDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input (CLR), and data output (Q). Theasynchronous CLR, when active, overrides all other inputs and sets the (Q) output Low. The data on the (D)input is loaded into the flip-flop during the High-to-Low clock (C) transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR D C Q

1 X X 0

0 D ↓ D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDCEPrimitive: D Flip-Flop with Clock Enable and Asynchronous Clear

IntroductionThis design element is a single D-type flip-flop with clock enable and asynchronous clear. When clock enable(CE) is High and asynchronous clear (CLR) is Low, the data on the data input (D) of this design element istransferred to the corresponding data output (Q) during the Low-to-High clock (C) transition. When CLR is High,it overrides all other inputs and resets the data output (Q) Low. When CE is Low, clock transitions are ignored.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE D C Q

1 X X X 0

0 0 X X No Change

0 1 D ↑ D

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0 0 Sets the initial value of Q output after configuration.

For Spartan®-6 devices, the INIT value shouldalways match the polarity of the set or reset. In thecase of FDCE, the INIT should be 0. If set to 1, anasynchronous circuit must be created to exhibit thisbehavior, which Xilinx does not recommend.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

FDCE_1Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Clear

IntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), asynchronous clear (CLR) inputs,and data output (Q). The asynchronous CLR input, when High, overrides all other inputs and sets the Q outputLow. The data on the (D) input is loaded into the flip-flop when CLR is Low and CE is High on the High-to-Lowclock (C) transition. When CE is Low, the clock transitions are ignored.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE D C Q

1 X X X 0

0 0 X X No Change

0 1 D ↓ D

Design Entry MethodThis design element can be used in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 0,1 0 Sets the initial value of Q output after configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDEPrimitive: D Flip-Flop with Clock Enable

IntroductionThis design element is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).When clock enable is High, the data on the (D) input is loaded into the flip-flop during the Low-to-High clock(C) transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

0 X X No Change

1 0 ↑ 0

1 1 ↑ 1

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDE_1Primitive: D Flip-Flop with Negative-Edge Clock and Clock Enable

IntroductionThis design element is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).When clock enable is High, the data on the (D) input is loaded into the flip-flop during the High-to-Low clock(C) transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

0 X X No Change

1 0 ↓ 0

1 1 ↓ 1

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDPPrimitive: D Flip-Flop with Asynchronous Preset

IntroductionThis design element is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and dataoutput (Q). The asynchronous PRE, when High, overrides all other inputs and presets the (Q) output High. Thedata on the (D) input is loaded into the flip-flop when PRE is Low on the Low-to-High clock (C) transition.

For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE C D Q

1 X X 1

0 ↑ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDP_1Primitive: D Flip-Flop with Negative-Edge Clock and Asynchronous Preset

IntroductionThis design element is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and dataoutput (Q). The asynchronous PRE, when High, overrides all other inputs and presets the Q output High. Thedata on the D input is loaded into the flip-flop when PRE is Low on the High-to-Low clock (C) transition.

This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE C D Q

1 X X 1

0 ↓ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDPEPrimitive: D Flip-Flop with Clock Enable and Asynchronous Preset

IntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset(PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the(Q) output High. Data on the (D) input is loaded into the flip-flop when PRE is Low and CE is High on theLow-to-High clock (C) transition. When CE is Low, the clock transitions are ignored.

For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE CE D C Q

1 X X X 1

0 0 X X No Change

0 1 D ↑ D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 1 1 Sets the initial value of Q output after configuration.

For Spartan®-6 devices the INIT value should alwaysmatch the polarity of the set or reset. In the case ofFDPE, the init should be 1. If set to 0, an asynchronouscircuit must be created to exhibit this behavior, whichXilinx does not recommend.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

FDPE_1Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset

IntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset(PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the(Q) output High. Data on the (D) input is loaded into the flip-flop when PRE is Low and CE is High on theHigh-to-Low clock (C) transition. When CE is Low, the clock transitions are ignored.

For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE CE D C Q

1 X X X 1

0 0 X X No Change

0 1 D ↓ D

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDRPrimitive: D Flip-Flop with Synchronous Reset

IntroductionThis design element is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output(Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q) output Low onthe Low-to-High clock (C) transition. The data on the (D) input is loaded into the flip-flop when R is Lowduring the Low-to- High clock transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R D C Q

1 X ↑ 0

0 D ↑ D

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 0, 1 0 Sets the initial value ofQ output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDR_1Primitive: D Flip-Flop with Negative-Edge Clock and Synchronous Reset

IntroductionThis design element is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output(Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q) output Low onthe High-to-Low clock (C) transition. The data on the (D) input is loaded into the flip-flop when R is Lowduring the High-to- Low clock transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R D C Q

1 X ↓ 0

0 D ↓ D

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDREPrimitive: D Flip-Flop with Clock Enable and Synchronous Reset

IntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputsand data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q)output Low on the Low-to-High clock (C) transition. The data on the (D) input is loaded into the flip-flop when Ris Low and CE is High during the Low-to-High clock transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE D C Q

1 X X ↑ 0

0 0 X X No Change

0 1 D ↑ D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0 0 Sets the initial value of Q output after configuration.

For Spartan®-6 the INIT value should always matchthe polarity of the set or reset. In the case of FDRE, theINIT should be 0. If set to 1, extra logic is inserted.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

FDRE_1Primitive: D Flip-Flop with Negative-Clock Edge, Clock Enable, and Synchronous Reset

IntroductionFDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and dataoutput (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q) output Lowon the High-to-Low clock (C) transition. The data on the (D) input is loaded into the flip-flop when R is Low andCE is High during the High-to-Low clock transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE D C Q

1 X X ↓ 0

0 0 X X No Change

0 1 D ↓ D

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDSPrimitive: D Flip-Flop with Synchronous Set

IntroductionFDS is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). Thesynchronous set input, when High, sets the Q output High on the Low-to-High clock (C) transition. The data onthe D input is loaded into the flip-flop when S is Low during the Low-to-High clock (C) transition.

For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

S D C Q

1 X ↑ 1

0 D ↑ D

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDS_1Primitive: D Flip-Flop with Negative-Edge Clock and Synchronous Set

IntroductionFDS is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). Thesynchronous set input, when High, sets the Q output High on the Low-to-High clock (C) transition. The data onthe D input is loaded into the flip-flop when S is Low during the Low-to-High clock (C) transition.

This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

S D C Q

1 X ↓ 1

0 D ↓ D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output afterconfiguration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FDSEPrimitive: D Flip-Flop with Clock Enable and Synchronous Set

IntroductionFDSE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output(Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Q output Highduring the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when S is Lowand CE is High during the Low-to-High clock (C) transition.

For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

S CE D C Q

1 X X ↑ 1

0 0 X X No Change

0 1 D ↑ D

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 1 1 Sets the initial value of Q output after configuration.

For Spartan®-6 devices the INIT value should always match thepolarity of the set or reset. In the case of FDSE, the init should be 1.If set to 0, extra logic is inserted.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

FDSE_1Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and Synchronous Set

IntroductionFDSE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and dataoutput (Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Qoutput High during the High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flopwhen S is Low and CE is High during the High-to-Low clock (C) transition.

This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

S CE D C Q

1 X X ↓ 1

0 0 X X No Change

0 1 D ↓ D

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FJKCMacro: J-K Flip-Flop with Asynchronous Clear

IntroductionThis design element is a single J-K-type flip-flop with J, K, and asynchronous clear (CLR) inputs and data output(Q). The asynchronous clear (CLR) input, when High, overrides all other inputs and resets the Q output Low.When CLR is Low, the output responds to the state of the J and K inputs, as shown in the following logictable, during the Low-to-High clock (C) transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR J K C Q

1 X X X 0

0 0 0 ↑ No Change

0 0 1 ↑ 0

0 1 0 ↑ 1

0 1 1 ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FJKCEMacro: J-K Flip-Flop with Clock Enable and Asynchronous Clear

IntroductionThis design element is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous clear (CLR)inputs and data output (Q). The asynchronous clear (CLR), when High, overrides all other inputs and resets theQ output Low. When CLR is Low and CE is High, Q responds to the state of the J and K inputs, as shown in thefollowing logic table, during the Low-to-High clock transition. When CE is Low, the clock transitions are ignored.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE J K C Q

1 X X X X 0

0 0 X X X No Change

0 1 0 0 X No Change

0 1 0 1 ↑ 0

0 1 1 0 ↑ 1

0 1 1 1 ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FJKPMacro: J-K Flip-Flop with Asynchronous Preset

IntroductionThis design element is a single J-K-type flip-flop with J, K, and asynchronous preset (PRE) inputs and dataoutput (Q). The asynchronous preset (PRE) input, when High, overrides all other inputs and sets the (Q) outputHigh. When (PRE) is Low, the (Q) output responds to the state of the J and K inputs, as shown in the followinglogic table, during the Low-to-High clock transition.

For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE J K C Q

1 X X X 1

0 0 0 X No Change

0 0 1 ↑ 0

0 1 0 ↑ 1

0 1 1 ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FJKPEMacro: J-K Flip-Flop with Clock Enable and Asynchronous Preset

IntroductionThis design element is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous preset (PRE)inputs and data output (Q). The asynchronous preset (PRE), when High, overrides all other inputs and sets the(Q) output High. When (PRE) is Low and (CE) is High, the (Q) output responds to the state of the J and Kinputs, as shown in the logic table, during the Low-to-High clock (C) transition. When (CE) is Low, clocktransitions are ignored.

For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE CE J K C Q

1 X X X X 1

0 0 X X X No Change

0 1 0 0 X No Change

0 1 0 1 ↑ 0

0 1 1 0 ↑ 1

0 1 1 1 ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FJKRSEMacro: J-K Flip-Flop with Clock Enable and Synchronous Reset and Set

IntroductionThis design element is a single J-K-type flip-flop with J, K, synchronous reset (R), synchronous set (S), and clockenable (CE) inputs and data output (Q). When synchronous reset (R) is High during the Low-to-High clock (C)transition, all other inputs are ignored and output (Q) is reset Low. When synchronous set (S) is High and (R) isLow, output (Q) is set High. When (R) and (S) are Low and (CE) is High, output (Q) responds to the state ofthe J and K inputs, according to the following logic table, during the Low-to-High clock (C) transition. When(CE) is Low, clock transitions are ignored.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R S CE J K C Q

1 X X X X ↑ 0

0 1 X X X ↑ 1

0 0 0 X X X No Change

0 0 1 0 0 X No Change

0 0 1 0 1 ↑ 0

0 0 1 1 0 ↑ 1

0 0 1 1 0 ↑ 1

0 0 1 1 1 ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

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Chapter 3: About Design Elements

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FJKSREMacro: J-K Flip-Flop with Clock Enable and Synchronous Set and Reset

IntroductionThis design element is a single J-K-type flip-flop with J, K, synchronous set (S), synchronous reset (R), and clockenable (CE) inputs and data output (Q). When synchronous set (S) is High during the Low-to-High clock (C)transition, all other inputs are ignored and output (Q) is set High. When synchronous reset (R) is High and (S) isLow, output (Q) is reset Low. When (S) and (R) are Low and (CE) is High, output (Q) responds to the state ofthe J and K inputs, as shown in the following logic table, during the Low-to-High clock (C) transition. When(CE) is Low, clock transitions are ignored.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

S R CE J K C Q

1 X X X X ↑ 1

0 1 X X X ↑ 0

0 0 0 X X X No Change

0 0 1 0 0 X No Change

0 0 1 0 1 ↑ 0

0 0 1 1 0 ↑ 1

0 0 1 1 1 ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration

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Chapter 3: About Design Elements

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FTCMacro: Toggle Flip-Flop with Asynchronous Clear

IntroductionThis design element is a synchronous, resettable toggle flip-flop. The asynchronous clear (CLR) input, whenHigh, overrides all other inputs and resets the data output (Q) Low. The (Q) output toggles, or changes state,when the toggle enable (T) input is High and (CLR) is Low during the Low-to-High clock transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR T C Q

1 X X 0

0 0 X No Change

0 1 ↑ Toggle

Design Entry MethodYou can instantiate this element when targeting a CPLD, but not when you are targeting an FPGA.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FTCEMacro: Toggle Flip-Flop with Clock Enable and Asynchronous Clear

IntroductionThis design element is a toggle flip-flop with toggle and clock enable and asynchronous clear. When theasynchronous clear (CLR) input is High, all other inputs are ignored and the data output (Q) is reset Low. WhenCLR is Low and toggle enable (T) and clock enable (CE) are High, Q output toggles, or changes state, during theLow-to-High clock (C) transition. When CE is Low, clock transitions are ignored.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE T C Q

1 X X X 0

0 0 X X No Change

0 1 0 X No Change

0 1 1 ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FTCLEMacro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Clear

IntroductionThis design element is a toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. Whenthe asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When loadenable input (L) is High and CLR is Low, clock enable (CE) is overridden and the data on data input (D) isloaded into the flip-flop during the Low-to-High clock (C) transition. When toggle enable (T) and CE are Highand L and CLR are Low, output Q toggles, or changes state, during the Low- to-High clock transition. WhenCE is Low, clock transitions are ignored.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE T D C Q

1 X X X X X 0

0 1 X X D ↑ D

0 0 0 X X X No Change

0 0 1 0 X X No Change

0 0 1 1 X ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FTCLEXMacro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Clear

IntroductionThis design element is a toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. Whenthe asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When loadenable input (L) is High, CLR is Low, and CE is High, the data on data input (D) is loaded into the flip-flop duringthe Low-to-High clock (C) transition. When toggle enable (T) and CE are High and L and CLR are Low, output Qtoggles, or changes state, during the Low- to-High clock transition. When CE is Low, clock transitions are ignored.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE T D C Q

1 X X X X X 0

0 1 X X D ↑ D

0 0 0 X X X No Change

0 0 1 0 X X No Change

0 0 1 1 X ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FTPMacro: Toggle Flip-Flop with Asynchronous Preset

IntroductionThis design element is a toggle flip-flop with toggle enable and asynchronous preset. When the asynchronouspreset (PRE) input is High, all other inputs are ignored and output (Q) is set High. When toggle-enable input (T)is High and (PRE) is Low, output (Q) toggles, or changes state, during the Low-to-High clock (C) transition.

For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE T C Q

1 X X 1

0 0 X No Change

0 1 ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FTPEMacro: Toggle Flip-Flop with Clock Enable and Asynchronous Preset

IntroductionThis design element is a toggle flip-flop with toggle and clock enable and asynchronous preset. When theasynchronous preset (PRE) input is High, all other inputs are ignored and output (Q) is set High. When thetoggle enable input (T) is High, clock enable (CE) is High, and (PRE) is Low, output (Q) toggles, or changes state,during the Low-to-High clock transition. When (CE) is Low, clock transitions are ignored.

For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE CE T C Q

1 X X X 1

0 0 X X No Change

0 1 0 X No Change

0 1 1 ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FTPLEMacro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Preset

IntroductionThis design element is a toggle/loadable flip-flop with toggle and clock enable and asynchronous preset. Whenthe asynchronous preset input (PRE) is High, all other inputs are ignored and output (Q) is set High. When theload enable input (L) is High and (PRE) is Low, the clock enable (CE) is overridden and the data (D) is loadedinto the flip-flop during the Low-to-High clock transition. When L and PRE are Low and toggle-enable input(T) and (CE) are High, output (Q) toggles, or changes state, during the Low-to-High clock transition. When(CE) is Low, clock transitions are ignored.

For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE L CE T D C Q

1 X X X X X 1

0 1 X X D ↑ D

0 0 0 X X X No Change

0 0 1 0 X X No Change

0 0 1 1 X ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FTRSEMacro: Toggle Flip-Flop with Clock Enable and Synchronous Reset and Set

IntroductionThis design element is a toggle flip-flop with toggle and clock enable and synchronous reset and set. When thesynchronous reset input (R) is High, it overrides all other inputs and the data output (Q) is reset Low. When thesynchronous set input (S) is High and (R) is Low, clock enable input (CE) is overridden and output (Q) is setHigh. (Reset has precedence over Set.) When toggle enable input (T) and (CE) are High and (R) and (S) are Low,output (Q) toggles, or changes state, during the Low-to-High clock transition.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R S CE T C Q

1 X X X ↑ 0

0 1 X X ↑ 1

0 0 0 X X No Change

0 0 1 0 X No Change

0 0 1 1 ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FTRSLEMacro: Toggle/Loadable Flip-Flop with Clock Enable and Synchronous Reset and Set

IntroductionThis design element is a toggle/loadable flip-flop with toggle and clock enable and synchronous reset and set.The synchronous reset input (R), when High, overrides all other inputs and resets the data output (Q) Low.(Reset has precedence over Set.) When R is Low and synchronous set input (S) is High, the clock enable input(CE) is overridden and output Q is set High. When R and S are Low and load enable input (L) is High, CE isoverridden and data on data input (D) is loaded into the flip-flop during the Low-to-High clock transition. WhenR, S, and L are Low, CE is High and T is High, output Q toggles, or changes state, during the Low-to-High clocktransition. When CE is Low, clock transitions are ignored.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R S L CE T D C Q

1 0 X X X X ↑ 0

0 1 X X X X ↑ 1

0 0 1 X X 1 ↑ 1

0 0 1 X X 0 ↑ 0

0 0 0 0 X X X No Change

0 0 0 1 0 X X No Change

0 0 0 1 1 X ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

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Chapter 3: About Design Elements

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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FTSREMacro: Toggle Flip-Flop with Clock Enable and Synchronous Set and Reset

IntroductionThis design element is a toggle flip-flop with toggle and clock enable and synchronous set and reset. Thesynchronous set input, when High, overrides all other inputs and sets data output (Q) High. (Set has precedenceover Reset.) When synchronous reset input (R) is High and S is Low, clock enable input (CE) is overridden andoutput Q is reset Low. When toggle enable input (T) and CE are High and S and R are Low, output Q toggles, orchanges state, during the Low-to-High clock transition. When CE is Low, clock transitions are ignored.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

S R CE T C Q

1 X X X ↑ 1

0 1 X X ↑ 0

0 0 0 X X No Change

0 0 1 0 X No Change

0 0 1 1 ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

FTSRLEMacro: Toggle/Loadable Flip-Flop with Clock Enable and Synchronous Set and Reset

IntroductionThis design element is a toggle/loadable flip-flop with toggle and clock enable and synchronous set and reset.The synchronous set input (S), when High, overrides all other inputs and sets data output (Q) High. (Set hasprecedence over Reset.) When synchronous reset (R) is High and (S) is Low, clock enable input (CE) is overriddenand output (Q) is reset Low. When load enable input (L) is High and S and R are Low, CE is overridden and dataon data input (D) is loaded into the flip-flop during the Low-to-High clock transition. When the toggle enableinput (T) and (CE) are High and (S), (R), and (L) are Low, output (Q) toggles, or changes state, during the Low-to-High clock transition. When (CE) is Low, clock transitions are ignored.

For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaultsto active-High but can be inverted by adding an inverter in front of the GSR input of the appropriateSTARTUP_architecture symbol.

Logic TableInputs Outputs

S R L CE T D C Q

1 X X X X X ↑ 1

0 1 X X X X ↑ 0

0 0 1 X X 1 ↑ 1

0 0 1 X X 0 ↑ 0

0 0 0 0 X X X No Change

0 0 0 1 0 X X No Change

0 0 0 1 1 X ↑ Toggle

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Sets the initial value of Q output after configuration

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For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

GNDPrimitive: Ground-Connection Signal Tag

IntroductionThe GND signal tag, or parameter, forces a net or input function to a Low logic level. A net tied to GND cannothave any other source.

When the logic-trimming software or fitter encounters a net or input function tied to GND, it removes any logicthat is disabled by the GND signal. The GND signal is only implemented when the disabled logic cannotbe removed.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

GTPA1_DUALPrimitive: Dual Gigabit Transceiver

IntroductionThis design element represents the Spartan®-6 FPGA RocketIO™ GTP transceiver, a power-efficient and highlyconfigurable transceiver. Refer to Spartan-6 FPGA RocketIO GTP Transceiver User Guide for detailed informationregarding this component. The Spartan-6 FPGA RocketIO GTX Transceiver Wizard is the preferred tool togenerate a wrapper to instantiate a GTPA1_DUAL primitive. The Wizard can be found in the Xilinx® COREGenerator™ tool.

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Chapter 3: About Design Elements

Design Entry MethodTo instantiate this component, use the Spartan-6 FPGA RocketIO GTX Transceiver Wizard or an associated corecontaining the component. Xilinx does not recommend direct instantiation of this component.

This design element can be used in schematics.

For More Information• See the Spartan-6 FPGA RocketIO GTP Transceivers User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

IBUFPrimitive: Input Buffer

IntroductionThis design element is automatically inserted (inferred) by the synthesis tool to any signal directly connectedto a top-level input or in-out port of the design. You should generally let the synthesis tool infer this buffer.However, it can be instantiated into the design if required. In order to do so, connect the input port (I) directly tothe associated top-level input or in-out port, and connect the output port (O) to the logic sourced by that port.Modify any necessary generic maps (VHDL) or named parameter value assignment (Verilog) in order to changethe default behavior of the component.

Port DescriptionsPort Direction Width Function

O Output 1 Buffer output

I Input 1 Buffer input

Design Entry MethodThis design element can be used in schematics.

In general, this element is inferred by the synthesis tool for any specified top-level input port to the design. It isgenerally not necessary to specify them in the source code. However, if desired, they be manually instantiated byeither copying the instantiation code from the appropriate Libraries Guide HDL template and pasting it into thetop-level entity/module of your code. It is recommended to always put all I/O components on the top-level of thedesign to help facilitate hierarchical design methods. Connect the I port directly to the top-level input port of thedesign and the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet. "DEFAULT" Assigns an I/O standard to the element.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

IBUF16Macro: 16-Bit Input Buffer

IntroductionInput Buffers isolate the internal circuit from the signals coming into the chip. This design element is containedin input/output blocks (IOBs) and allows the specification of the particular I/O Standard to configure the I/O. Ingeneral, an this element should be used for all single-ended data input or bidirectional pins.

Design Entry MethodThis design element can be used in schematics.

In general, this element is inferred by the synthesis tool for any specified top-level input port to the design. It isgenerally not necessary to specify them in the source code. However, if desired, they be manually instantiated byeither copying the instantiation code from the appropriate Libraries Guide HDL template and pasting it into thetop-level entity/module of your code. It is recommended to always put all I/O components on the top-level of thedesign to help facilitate hierarchical design methods. Connect the I port directly to the top-level input port of thedesign and the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet. "DEFAULT" Assigns an I/O standard to the element.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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IBUF4Macro: 4-Bit Input Buffer

IntroductionInput Buffers isolate the internal circuit from the signals coming into the chip. This design element is containedin input/output blocks (IOBs) and allows the specification of the particular I/O Standard to configure the I/O. Ingeneral, an this element should be used for all single-ended data input or bidirectional pins.

Design Entry MethodThis design element can be used in schematics.

In general, this element is inferred by the synthesis tool for any specified top-level input port to the design. It isgenerally not necessary to specify them in the source code. However, if desired, they be manually instantiated byeither copying the instantiation code from the appropriate Libraries Guide HDL template and pasting it into thetop-level entity/module of your code. It is recommended to always put all I/O components on the top-level of thedesign to help facilitate hierarchical design methods. Connect the I port directly to the top-level input port of thedesign and the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet. "DEFAULT" Assigns an I/O standard to the element.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IBUF8Macro: 8-Bit Input Buffer

IntroductionInput Buffers isolate the internal circuit from the signals coming into the chip. This design element is containedin input/output blocks (IOBs) and allows the specification of the particular I/O Standard to configure the I/O. Ingeneral, an this element should be used for all single-ended data input or bidirectional pins.

Design Entry MethodThis design element can be used in schematics.

In general, this element is inferred by the synthesis tool for any specified top-level input port to the design. It isgenerally not necessary to specify them in the source code. However, if desired, they be manually instantiated byeither copying the instantiation code from the appropriate Libraries Guide HDL template and pasting it into thetop-level entity/module of your code. It is recommended to always put all I/O components on the top-level of thedesign to help facilitate hierarchical design methods. Connect the I port directly to the top-level input port of thedesign and the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet. "DEFAULT" Assigns an I/O standard to the element.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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IBUFDSPrimitive: Differential Signaling Input Buffer

IntroductionThis design element is an input buffer that supports low-voltage, differential signaling. In IBUFDS, a designlevel interface signal is represented as two distinct ports (I and IB), one deemed the "master" and the other the"slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET_P andMYNET_N). Optionally, a programmable differential termination feature is available to help improve signalintegrity and reduce external components.

Logic TableInputs Outputs

I IB O

0 0 No Change

0 1 0

1 0 1

1 1 No Change

Port DescriptionsPort Type Width Function

I Input 1 Diff_p Buffer Input

IB Input 1 Diff_n Buffer Input

O Output 1 Buffer Output

Design Entry MethodThis design element can be used in schematics.

Put all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connectthe I port directly to the top-level "master" input port of the design, the IB port to the top-level "slave" inputport, and the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet. "DEFAULT" Assigns an I/O standard to the element.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

IBUFDS_DLY_ADJPrimitive: Dynamically Adjustable Differential Input Delay Buffer

IntroductionThis design element is a differential input buffer with an adjustable delay element allowing dynamic delayadjustment (delay tuning) of an input signal into the FPGA. This is particularly useful for data aligning andcapturing of high-speed input signals into the FPGA over process, voltage, and temperature variations. Thiscomponent consists of a 3-bit select bus, which allows 8 unique values of delay to be added to the incomingsignal. Additionally, the component can be programmed with a delay offset to delay adjustment within eitherthe lower 8 or upper 8 of the 16 contiguous delay values.

Port DescriptionsPort Direction Width Function

O Output 1 Delayed output from the buffer

I Input 1 Differential input data (positive)

IB Input 1 Differential input data (negative)

S Input 3 Dynamic delay adjustment select lines

Design Entry Method

Available AttributesAttribute Type Allowed Values Default Description

DELAY_OFFSET

String "OFF", "ON" "OFF" When set to OFF", the IBUFDS_DLY_ADJ operates at thelower range of delay values. This should be used when asmaller amount of additional delay is needed. When setto "ON", the component operates at the upper (longer)range of delay values. This should be used when a largeramount of additional delay is needed.

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IBUFGPrimitive: Dedicated Input Clock Buffer

IntroductionThe IBUFG is a dedicated input to the device which should be used to connect incoming clocks to the FPGA’sglobal clock routing resources. The IBUFG provides dedicated connections to the DCM, PLL, or BUFG resources.providing the minimum amount of clock delay and jitter to the device. The IBUFG input can only be drivenby the global clock (GC) pins.

Port DescriptionsPort Direction Width Function

O Output 1 Clock Buffer output

I Input 1 Clock Buffer input

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to theelement.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

IBUFGDSPrimitive: Differential Signaling Dedicated Input Clock Buffer and Optional Delay

IntroductionThis design element is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) orMMCM. In IBUFGDS, a design-level interface signal is represented as two distinct ports (I and IB), one deemedthe "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (forexample, MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available tohelp improve signal integrity and reduce external components. Also available is a programmable delay is toassist in the capturing of incoming data to the device.

Logic TableInputs Outputs

I IB O

0 0 No Change

0 1 0

1 0 1

1 1 No Change

Port DescriptionsPort Direction Width Function

O Output 1 Clock Buffer output

IB Input 1 Diff_n Clock Buffer Input

I Input 1 Diff_p Clock Buffer Input

Design Entry MethodThis design element can be used in schematics.

Put all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connect the Iport directly to the top-level "master" input port of the design, the IB port to the top-level "slave" input port andthe O port to an MMCM, BUFG or logic in which this input is to source. Some synthesis tools infer the BUFGautomatically if necessary, when connecting an IBUFG to the clock resources of the FPGA. Specify the desiredgeneric/defparam values in order to configure the proper behavior of the buffer.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to theelement.

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For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

ICAP_SPARTAN6Primitive: Internal Configuration Access Port

IntroductionThis design element allows users access to the configuration functions of the FPGA from the FPGA fabric.This component’s primary usage is to control Multiboot operations in FPGA devices. Using this component,commands and data can be written to and read from the configuration logic of the FPGA array. Because theimproper use of this function can have a negative effect on the functionality and reliability of the FPGA, you areencouraged to gain a thorough understanding of this component before incorporating it into your designs.

Port DescriptionsPort Type Width Function

BUSY Output 1 Active High busy status. Only used in read operations. BUSY remainsLow during writes.

CE Input 1 Active Low clock enable input.

CLK Input 1 Clock input.

I[15:0] Input 16 Configuration data input bus.

O[15:0] Output 16 Configuration data output bus.

WRITE Input 1 Active Low write input.

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Configuration User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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IDDR2Primitive: Double Data Rate Input D Flip-Flop with Optional Data Alignment, Clock Enable andProgrammable Synchronous or Asynchronous Set/Reset

IntroductionThis design element is a dedicated input register designed to receive external dual data rate (DDR) signals intoXilinx® FPGAs. The IDDR2 requires two clocks to be connected to the component, C0 and C1, so that data iscaptured at the positive edge of both C0 and C1 clocks. The IDDR2 features an active high clock enable port, CE,which be used to suspend the operation of the registers, and both set and reset ports that be configured to besynchronous or asynchronous to the respective clocks. The IDDR2 has an optional alignment feature that allowsboth output data ports to the component to be aligned to a single clock.

Logic TableInput Output

S R CE D C0 C1 Q0 Q1

1 x x x x x INIT_Q0 INIT_Q1

0 1 x x x x not INIT_Q0 not INIT_Q1

0 0 0 x x x No Change No Change

0 0 1 D ↑ x D No Change

0 0 1 D x ↑ No Change D

Set/Reset can be synchronous via SRTYPE value

Design Entry MethodThis design element can be used in schematics.

To change the default behavior of the IDDR2, modify attributes via the generic map (VHDL) or named parametervalue assignment (Verilog) as a part of the instantiated component. The IDDR2 can be connected directlyto a top-level input port in the design, where an appropriate input buffer can be inferred, or directly to aninstantiated IBUF, IOBUF, IBUFDS or IOBUFDS. All inputs and outputs of this component should either beconnected or properly tied off.

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Available AttributesAttribute Type Allowed Values Default Description

DDR_ALIGNMENT String NONE, "C0", "C1” “NONE” Sets the output alignment more for the DDR register

• NONE - Makes the data available on the Q0 andQ1 outputs shortly after the corresponding C0 orC1 positive clock edge.

• C0 – Makes the data on both Q0 and Q1 align tothe positive edge of the C0 clock.

• C1 - Makes the data on both Q0 and Q1 align tothe positive edge of the C1 clock.

INIT_Q0 Integer 0, 1 0 Sets initial state of the Q0 output to 0 or 1.

INIT_Q1 Integer 0, 1 0 Sets initial state of the Q1 output to 0 or 1.

SRTYPE String "SYNC", "ASYNC” "SYNC” Specifies SYNC" or "ASYNC" set/reset.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

IFDMacro: Input D Flip-Flop

IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected toan IPAD or an IOPAD (without using an IBUF). The (D) input provides data input for the flip-flop, whichsynchronizes data entering the chip. The data on input (D) is loaded into the flip-flop during the Low-to-Highclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IFD_1Macro: Input D Flip-Flop with Inverted Clock (Asynchronous Preset)

IntroductionThis design element is a D-type flip flop which is contained in an input/output block (IOB). The input (D) of theflip-flop is connected to an IPAD or an IOPAD. The D input also provides data input for the flip-flop, whichsynchronizes data entering the chip. The D input data is loaded into the flip-flop during the High-to-Lowclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

0 ↓ 0

1 ↓ 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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IFD16Macro: 16-Bit Input D Flip-Flop

IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected toan IPAD or an IOPAD (without using an IBUF). The (D) input provides data input for the flip-flop, whichsynchronizes data entering the chip. The data on input (D) is loaded into the flip-flop during the Low-to-Highclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IFD4Macro: 4-Bit Input D Flip-Flop

IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected toan IPAD or an IOPAD (without using an IBUF). The (D) input provides data input for the flip-flop, whichsynchronizes data entering the chip. The data on input (D) is loaded into the flip-flop during the Low-to-Highclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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IFD8Macro: 8-Bit Input D Flip-Flop

IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected toan IPAD or an IOPAD (without using an IBUF). The (D) input provides data input for the flip-flop, whichsynchronizes data entering the chip. The data on input (D) is loaded into the flip-flop during the Low-to-Highclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IFDIMacro: Input D Flip-Flop (Asynchronous Preset)

IntroductionThis design element is a D-type flip-flop which is contained in an input/output block (IOB). The input (D) ofthe flip-flop is connected to an IPAD or an IOPAD. The D input provides data input for the flip-flop, whichsynchronizes data entering the chip. The D input data is loaded into the flip-flop during the Low-to-Highclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IFDI_1Macro: Input D Flip-Flop with Inverted Clock (Asynchronous Preset)

IntroductionThe design element is a D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flopis connected to an IPAD or an IOPAD. The (D) input provides data input for the flip-flop, which synchronizes dataentering the chip. The data on input (D) is loaded into the flip-flop during the High-to-Low clock (C) transitionand appears at the output (Q). The clock input can be driven by internal logic or through another external pin.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

0 ↓ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IFDXMacro: Input D Flip-Flop with Clock Enable

IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connectedto an IPAD or an IOPAD (without using an IBUF). The D input provides data input for the flip-flop, whichsynchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during theLow-to-High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic orthrough another external pin. When CE is Low, flip-flop outputs do not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 D ↑ D

0 X X No Change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IFDX_1Macro: Input D Flip-Flop with Inverted Clock and Clock Enable

IntroductionThis design element is a D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flopis connected to an IPAD or an IOPAD. The D input also provides data input for the flip-flop, which synchronizesdata entering the chip. When CE is High, the data on input D is loaded into the flip-flop during the High-to-Lowclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin. When the CE pin is Low, the output (Q) does not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 D ↓ D

0 X X No Change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IFDX16Macro: 16-Bit Input D Flip-Flops with Clock Enable

IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connectedto an IPAD or an IOPAD (without using an IBUF). The D input provides data input for the flip-flop, whichsynchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during theLow-to-High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic orthrough another external pin. When CE is Low, flip-flop outputs do not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 D ↑ D

0 X X No Change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IFDX4Macro: 4-Bit Input D Flip-Flop with Clock Enable

IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connectedto an IPAD or an IOPAD (without using an IBUF). The D input provides data input for the flip-flop, whichsynchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during theLow-to-High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic orthrough another external pin. When CE is Low, flip-flop outputs do not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 D ↑ D

0 X X No Change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IFDX8Macro: 8-Bit Input D Flip-Flop with Clock Enable

IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connectedto an IPAD or an IOPAD (without using an IBUF). The D input provides data input for the flip-flop, whichsynchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during theLow-to-High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic orthrough another external pin. When CE is Low, flip-flop outputs do not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 D ↑ D

0 X X No Change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IFDXIMacro: Input D Flip-Flop with Clock Enable (Asynchronous Preset)

IntroductionThe design element is a D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flopis connected to an IPAD or an IOPAD. The D input provides data input for the flip-flop, which synchronizes dataentering the chip. When CE is High, the data on input D is loaded into the flip-flop during the Low-to-High clock(C) transition and appears at the output (Q). The clock input can be driven by internal logic or through anotherexternal pin. When the CE pin is Low, the output (Q) does not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 D ↑ D

0 X X No Change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IFDXI_1Macro: Input D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)

IntroductionThe design element is a D-type flip-flop that is contained in an input/output block (IOB). The input (D) ofthe flip-flop is connected to an IPAD or an IOPAD. The (D) input provides data input for the flip-flop, whichsynchronizes data entering the chip. When (CE) is High, the data on input (D) is loaded into the flip-flop duringthe High-to-Low clock (C) transition and appears at the output (Q). The clock input can be driven by internallogic or through another external pin. When the (CE) pin is Low, the output (Q) does not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 D ↓ D

0 X X No Change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILDMacro: Transparent Input Data Latch

IntroductionThis design element is a single, transparent data latch that holds transient data entering a chip. This latch iscontained in an input/output block (IOB). The latch input (D) is connected to an IPAD or an IOPAD (withoutusing an IBUF). When the gate input (G) is High, data on the input (D) appears on the output (Q). Data on the Dinput during the High-to-Low G transition is stored in the latch.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Output

G D Q

1 D D

0 X No Change

↓ D D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILD_1Macro: Transparent Input Data Latch with Inverted Gate

IntroductionThis design element is a transparent data latch that holds transient data entering a chip. When the gate input(G) is Low, data on the data input (D) appears on the data output (Q). Data on (D) during the Low-to-High (G)transition is stored in the latch.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

G D Q

0 D D

1 X No Change

↑ D D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILD16Macro: Transparent Input Data Latch

IntroductionThese design elements are multiple transparent data latches that hold transient data entering a chip. The ILDlatch is contained in an input/output block (IOB). The latch input (D) is connected to an IPAD or an IOPAD(without using an IBUF). When the gate input (G) is High, data on the inputs (D) appears on the outputs (Q).Data on the D inputs during the High-to-Low G transition is stored in the latch.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

G D Q

1 Dn Dn

0 X No Change

↓ Dn Dn

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILD4Macro: Transparent Input Data Latch

IntroductionThese design elements are multiple transparent data latches that hold transient data entering a chip. The ILDlatch is contained in an input/output block (IOB). The latch input (D) is connected to an IPAD or an IOPAD(without using an IBUF). When the gate input (G) is High, data on the inputs (D) appears on the outputs (Q).Data on the D inputs during the High-to-Low G transition is stored in the latch.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

G D Q

1 Dn Dn

0 X No Change

↓ Dn Dn

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILD8Macro: Transparent Input Data Latch

IntroductionThese design elements are multiple transparent data latches that hold transient data entering a chip. The ILDlatch is contained in an input/output block (IOB). The latch input (D) is connected to an IPAD or an IOPAD(without using an IBUF). When the gate input (G) is High, data on the inputs (D) appears on the outputs (Q).Data on the D inputs during the High-to-Low G transition is stored in the latch.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

G D Q

1 Dn Dn

0 X No Change

↓ Dn Dn

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILDIMacro: Transparent Input Data Latch (Asynchronous Preset)

IntroductionThis design element is a transparent data latch that holds transient data entering a chip. When the gate input(G) is High, data on the input (D) appears on the output (Q). Data on the D input during the High-to-Low Gtransition is stored in the latch.

The ILDI is the input flip-flop master latch. It is possible to access two different outputs from the inputflip-flop: one that responds to the level of the clock signal and another that responds to an edge of the clocksignal. When using both outputs from the same input flip-flop, a transparent High latch (ILDI) corresponds toa falling edge-triggered flip-flop (IFDI_1). Similarly, a transparent Low latch (ILDI_1) corresponds to a risingedge-triggered flip-flop (IFDI).

The latch is asynchronously preset, output High, when power is applied.

For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaultsto active-High but can be inverted by adding an inverter in front of the GSR input of the appropriateSTARTUP_architecture symbol.

Logic TableInputs Outputs

G D Q

1 D D

0 X D

↓ D D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILDI_1Macro: Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)

IntroductionThis design element is a transparent data latch that holds transient data entering a chip. When the gate input(G) is Low, data on the data input (D) appears on the data output (Q). Data on D during the Low-to-High Gtransition is stored in the latch.

The latch is asynchronously preset, output High, when power is applied.

For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaultsto active-High but can be inverted by adding an inverter in front of the GSR input of the appropriateSTARTUP_architecture symbol.

Logic TableInputs Outputs

G D Q

0 1 1

0 0 0

1 X No Change

↑ D D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILDXMacro: Transparent Input Data Latch

IntroductionThis design element is single or multiple transparent data latches that holds transient data entering a chip. Thelatch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).

The ILDX is the input flip-flop master latch. Two outputs can be accessed from the input flip-flop: one thatresponds to the level of the clock signal and another that responds to an edge of the clock signal. Whenusing both outputs from the same input flip-flop, a transparent High latch (ILDX) corresponds to a fallingedge-triggered flip-flop (IFDX_1). Similarly, a transparent Low latch (ILDX_1) corresponds to a risingedge-triggered flip-flop (IFDX)

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

GE G D Q

0 X X No Change

1 0 X No Change

1 1 1 1

1 1 0 0

1 ↓ D D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILDX_1Macro: Transparent Input Data Latch with Inverted Gate

IntroductionThis design element is a transparent data latch that holds transient data entering a chip. When the gate input(G) is Low, data on the data input (D) appears on the data output (Q). Data on D during the Low-to-High Gtransition is stored in the latch.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

GE G D Q

0 X X No Change

1 1 X No Change

1 0 1 1

1 0 0 0

1 ↑ D D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILDX16Macro: Transparent Input Data Latch

IntroductionThis design element is single or multiple transparent data latches that holds transient data entering a chip. Thelatch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).

The ILDX is the input flip-flop master latch. Two outputs can be accessed from the input flip-flop: one thatresponds to the level of the clock signal and another that responds to an edge of the clock signal. Whenusing both outputs from the same input flip-flop, a transparent High latch (ILDX) corresponds to a fallingedge-triggered flip-flop (IFDX_1). Similarly, a transparent Low latch (ILDX_1) corresponds to a risingedge-triggered flip-flop (IFDX)

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

GE G D Q

0 X X No Change

1 0 X No Change

1 1 Dn Dn

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILDX4Macro: Transparent Input Data Latch

IntroductionThis design element is single or multiple transparent data latches that holds transient data entering a chip. Thelatch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).

The ILDX is the input flip-flop master latch. Two outputs can be accessed from the input flip-flop: one thatresponds to the level of the clock signal and another that responds to an edge of the clock signal. Whenusing both outputs from the same input flip-flop, a transparent High latch (ILDX) corresponds to a fallingedge-triggered flip-flop (IFDX_1). Similarly, a transparent Low latch (ILDX_1) corresponds to a risingedge-triggered flip-flop (IFDX)

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

GE G D Q

0 X X No Change

1 0 X No Change

1 1 1 1

1 1 0 0

1 ↓ D D

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

ILDX8Macro: Transparent Input Data Latch

IntroductionThis design element is single or multiple transparent data latches that holds transient data entering a chip. Thelatch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).

The ILDX is the input flip-flop master latch. Two outputs can be accessed from the input flip-flop: one thatresponds to the level of the clock signal and another that responds to an edge of the clock signal. Whenusing both outputs from the same input flip-flop, a transparent High latch (ILDX) corresponds to a fallingedge-triggered flip-flop (IFDX_1). Similarly, a transparent Low latch (ILDX_1) corresponds to a risingedge-triggered flip-flop (IFDX)

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

GE G D Q

0 X X No Change

1 0 X No Change

1 1 Dn Dn

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILDXIMacro: Transparent Input Data Latch (Asynchronous Preset)

IntroductionThis design element is a transparent data latch that holds transient data entering a chip. When the gate input (G)is High, data on the input (D) appears on the output (Q). Data on the (D) input during the High-to-Low (G)transition is stored in the latch.

The ILDXI is the input flip-flop master latch. Two outputs can be accessed from the input flip-flop: one thatresponds to the level of the clock signal and another that responds to an edge of the clock signal. Whenusing both outputs from the same input flip-flop, a transparent High latch (ILDXI) corresponds to a fallingedge-triggered flip-flop (IFDXI_1). Similarly, a transparent Low latch (ILDXI_1) corresponds to a risingedge-triggered flip-flop (IFDXI).

The latch is asynchronously preset, output High, when power is applied.

For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaultsto active-High but can be inverted by adding an inverter in front of the GSR input of the appropriateSTARTUP_architecture symbol.

Logic TableInputs Outputs

GE G D Q

0 X X No Change

1 0 X No Change

1 1 D D

1 ↓ D D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ILDXI_1Macro: Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)

IntroductionThis design element is a transparent data latch that holds transient data entering a chip.

The latch is asynchronously preset, output High, when power is applied.

For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaultsto active-High but can be inverted by adding an inverter in front of the GSR input of the appropriateSTARTUP_architecture symbol.

Logic TableInputs Outputs

GE G D Q

0 X X No Change

1 1 X No Change

1 0 D D

1 ↑ D D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

INVPrimitive: Inverter

IntroductionThis design element is a single inverter that identifies signal inversions in a schematic.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

INV16Macro: 16 Inverters

IntroductionThis design element is a multiple inverter that identifies signal inversions in a schematic.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

INV4Macro: Four Inverters

IntroductionThis design element is a multiple inverter that identifies signal inversions in a schematic.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

INV8Macro: Eight Inverters

IntroductionThis design element is a multiple inverter that identifies signal inversions in a schematic.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

IOBUFPrimitive: Bi-Directional Buffer

IntroductionThe design element is a bidirectional single-ended I/O Buffer used to connect internal logic to an externalbidirectional pin.

Logic TableInputs Bidirectional Outputs

T I IO O

1 X Z X

0 1 1 1

0 0 0 0

Port DescriptionsPort Direction Width Function

O Output 1 Buffer output

IO Inout 1 Buffer inout

I Input 1 Buffer input

T Input 1 3-State enable input

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

DRIVE Integer 2, 4, 6, 8, 12, 16, 24 12 Selects output drive strength (mA)for the SelectIO™ buffers that usethe LVTTL, LVCMOS12, LVCMOS15,LVCMOS18, LVCMOS25, or LVCMOS33interface I/O standard.

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

SLEW String "SLOW", "FAST","QUIETIO"

"SLOW" Sets the output rise and fall time. See theData Sheet for recommendations of thebest setting for this attribute.

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Chapter 3: About Design Elements

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

IOBUFDSPrimitive: 3-State Differential Signaling I/O Buffer with Active Low Output Enable

IntroductionThe design element is a bidirectional buffer that supports low-voltage, differential signaling. For the IOBUFDS, adesign level interface signal is represented as two distinct ports (IO and IOB), one deemed the "master" andthe other the "slave." The master and the slave are opposite phases of the same logical signal (for example,MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available to helpimprove signal integrity and reduce external components. Also available is a programmable delay is to assist inthe capturing of incoming data to the device.

Logic TableInputs Bidirectional Outputs

I T IO IOB O

X 1 Z Z No Change

0 0 0 1 0

I 0 1 0 1

Port DescriptionsPort Direction Width Function

O Output 1 Buffer output

IO Inout 1 Diff_p inout

IOB Inout 1 Diff_n inout

I Input 1 Buffer input

T Input 1 3-state enable input

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

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For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

IODELAY2Primitive: Input and Output Fixed or Variable Delay Element

IntroductionThis design element can be used to provide a fixed delay or an adjustable delay to the input path and a fixeddelay for the output path of the Spartan®-6 FPGA. This delay can be useful for data alignment of incoming oroutgoing data to/from the chip. The output delay path is only available in a fixed delay. The IODELAY can alsobe used to add additional static or variable delay to an internal path (within the FPGA fabric). However, whenIODELAY is used that way, this device is no longer available to the associated I/O for input or output path delays.

Port DescriptionsPort Type Width Function

BUSY Output 1 Signals when calibration is complete or whensynchronous tap delay update is complete.

CAL Input 1 Invokes the IODELAY calibration sequence. Thecalibration sequence lasts between eight and 16 CLKcycles. Drives BUSY Low when complete.

CE Input 1 Active high enable increment/decrement function.

CLK Input 1 Global clock network input. This is the clock for theFPGA logic interconnect domain.

DATAOUT Output 1 Delayed data signal to D pin of ILOGIC2 orISERDES2 sites.

DATAOUT2 Output 1 Secondary delay for use in PCI™ applications.

DOUT Output 1 Delayed data signal to IOB when used as an outputdelay.

IDATAIN Input 1 Data input to device from the I/O (connect directlyto port, I/O Buffer).

INC Input 1 Increment/decrement signal. Used for adjustingthe tap setting up or down by one increment ordecrement.

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Chapter 3: About Design Elements

Port Type Width Function

IOCLK0 Input 1 Input from the I/O clock network. This is theprimary clock input when the clock doubler circuitis not engaged (see DATA_RATE attribute). Can beinverted.

IOCLK1 Input 1 I/O clock network input. This is the secondary clockinput and is only used when the clock doubleris engaged. (See DATA_RATE attribute). Can beinverted.

ODATAIN Input 1 Data input for the output data path from the device(connect to output data source).

RST Input 1 Active high, synchronous reset, resets delay chain toIDELAY_VALUE / ODELAY_VALUE tap. If no valueis specified, the default is 0.

T Input 1 3-state input control. Tie high for input-only orinternal delay or tie low for output only.

TOUT Output 1 Delayed 3-state signal to IOB when used as an outputdelay.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

COUNTER_WRAPAROUND

String “WRAPAROUND”,“STAY_AT_LIMIT”

“WRAPAROUND” Chooses the behavior whenmaximum or minimum tapcount is exceeded. Dependson whether tap setting is beingincremented or decremented.Ensures that tap count alwaysstays in the correct operatingrange.

DATA_RATE String “SDR”, “DDR” “SDR” Single Data Rate or DoubleData Rate operation.

DELAY_SRC String “IO”,“IDATAIN”,“ODATAIN”

“IO” Indicates where the IODELAY2input is coming from.

• ODATAIN indicates delaysource is the ODATAINpin from the OSERDES2 orOLOGIC2.

• IDATAIN indicates thedelay source is from aninput pin.

• IO indicates that the signalsource switches betweenIDATAIN and ODATAINdepending on the sense ofthe T (3-state) input.

IDELAY_MODE String “NORMAL”,“PCI”

“NORMAL” Do not specify or modify thisattribute.

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Attribute Type Allowed Values Default Description

IDELAY_TYPE String “DEFAULT”,“DIFF_PHASE_DETECTOR”,“FIXED”,“VARIABLE_FROM_HALF_MAX”,“VARIABLE_FROM_ZERO”

“DEFAULT” Chooses the type of delay.

• FIXED enables a fixedinput delay, and requiresno clocks applied to theblock.

• DEFAULT enables aguaranteed zero hold time.

• VARIABLE enables theincrement/decrementdelay mode and permitscalibration.

• VARIABLE_FROM_ZEROand VARIABLE_FROM_HALF_MAX enables thetype of reset behaviorwhen the RST pin isasserted.

• DIFF_PHASE_DETECTORenables a mode wherethe master and slaveIODELAY2s andISERDES2s are cascadedfor use with an optionalphase detector.

IDELAY_VALUE Integer 0 to 255 0 Specifies the number of taps ofdelay for the input path whenin fixed mode or the initialdelay tap value for variablemode.

IDELAY2_VALUE Integer 0 to 255 0 Defines the delay tap valuefor secondary input delaymode. Active only whenIDELAY_MODE is set to PCI.

ODELAY_VALUE Integer 0 to 255 0 Specifies the number of taps ofdelay for the output path.

SERDES_MODE String “NONE”,“MASTER”,“SLAVE”

“NONE” When IODELAY2 is used inconjunction with ISERDES2,the attribute defines whetherISERDES2 stands alone or is acascaded master or slave

SIM_TAPDELAY_VALUE

Integer 10 to 90 75 A simulation only attribute.Allows setting the nominal tapdelay to different settings forsimulation.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

IODRP2Primitive: I/O Control Port

IntroductionXilinx does not support the use of this element.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

ISERDES2Primitive: Input SERial/DESerializer.

IntroductionThis component is an input serial-to-parallel data converter that helps facilitate high-speed, source synchronous,serial data capturing. The component includes logic to assist in clocking and data alignment of either single datarate (SDR) or double data rate (DDR) data to/from 2- to 6-bit data widths for a single instance (MASTER) and 7-to 10-bit data widths for two cascaded ISERDES2 (MASTER/SLAVE). The component can be used in memory,networking or a number of different types of data interface applications. It can also be used in conjunction withan IODELAY component to assist in data alignment of the input serial data. In DDR mode, the component canbe clocked by either a single clock or two clocks for capturing data. When using it in two clock mode, higherperformance is possible. However, using it in this way might require more clocking resources, consume morepower, and require certain placement restriction. Use single clock mode when the highest I/O performance isnot needed.

Port Descriptions

Port Type Width Function

BITSLIP Input 1 Invoke Bitslip. This can be used with any DATA_WIDTH,cascaded or not. The amount of bitslip is fixed by theDATA_WIDTH selection.

CE0 Input 1 Clock enable input for final (global clock driven) register.

CFB0 Output 1 Feed-through route to allow a PLL or DCM generated clockto feed back to the PLL or DCM through a BUFIO2FB.

CFB1 Output 1 Secondary feed-through route to allow a PLL or DCMgenerated clock to feed back to the PLL or DCM througha BUFIO2FB.

CLKDIV Input 1 Global clock network input. This is the clock for the fabricdomain.

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Chapter 3: About Design Elements

Port Type Width Function

CLK0 Input 1 I/O Clock network input. Optionally Invertible. This is theprimary clock input used when the clock doubler circuit isnot engaged (see DATA_RATE attribute).

CLK1 Input 1 I/O clock network input. Optionally invertible. Thissecondary clock input is only used when the clock doubler isengaged (see DATA_RATE attribute).

D Input 1 Input data. This is the data input after being delayed by theIODELAY2 block.

DFB Output 1 Feed-through route to allow an input clock that has beendelayed in an IODELAY2 element to be forwarded to a DCM,PLL, or BUFG through a BUFIO2.

FABRICOUT Output 1 Asynchronous data for use in the FPGA logic.

INCDEC Output 1 Output of phase detector in master mode (dummy in slavemode). Indicates to the FPGA logic whether the receiveddata was sampled early or late.

IOCE Input 1 Data strobe signal derived from BUFIO CE. Strobes datacapture to be correctly timed with respect to the I/O andglobal clocks for the SerDes mode selected.

Q1 - Q4 Output 1 Registered output to fabric.

RST Input 1 Asynchronous reset only.

SHIFTIN Input 1 Cascade-in signal for master/slave I/O. Used when masterand slave sites are used together for DATA_WIDTHs greaterthan four. When the block is a master, it transfers data in foruse in the phase-detector mode. When the block is a slave, ittransfers serial data in to become parallel data.

SHIFTOUT Output 1 Cascade-out signal for master/slave I/O. In slave mode, it isused to send sampled data from the slave. In master mode,it sends serial data from the fourth stage of the input shiftregister to the slave.

VALID Output 1 Output of the phase detector in master mode (dummyin slave mode). If the input data contains no edges (noinformation for the phase detector to work with) the VALIDsignal transitions Low to indicate that the FPGA logic shouldignore the INCDEC signal.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

BITSLIP_ENABLE Boolean FALSE, TRUE FALSE Enables or disables the Bitslip functioncontrolled by the BITSLIP input pin. Thenumber of bits slipped is a function of theDATA_WIDTH selected. When disabled,the Bitslip CE always remains at the defaultvalue of one I/O clock before the IOCEclock enable.

DATA_RATE String “SDR”, “DDR” “SDR” Data rate setting. The DDR clock can besupplied by separate I/O clocks or by asingle I/O clock. If two clocks are supplied,

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Attribute Type Allowed Values Default Descriptionthey must be approximately 180°out ofphase.

DATA_WIDTH Integer 1, 2, 3, 4, 5, 6, 7, 8 1 Data width. Defines the parallel dataoutput width of the serial-to-parallelconverter. Values greater than four areonly valid when two ISERDES2 blocksare cascaded. In this case, the same valueshould be applied to both the master andslave blocks.

INTERFACE_TYPE String “NETWORKING”,”NETWORKING_PIPELINED”,"RETIMED”

“NETWORKING” Selects mode of operation and determineswhich set of parallel data is available to theFPGA logic.

SERDES_MODE String “NONE”,"MASTER”,”SLAVE”

“NONE” Indicates if the ISERDES is being usedalone, or as a master or slave, when twoISERDES2 blocks are cascaded.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

KEEPERPrimitive: KEEPER Symbol

IntroductionThe design element is a weak keeper element that retains the value of the net connected to its bidirectional O pin.For example, if a logic 1 is being driven onto the net, KEEPER drives a weak/resistive 1 onto the net. If the netdriver is then 3-stated, KEEPER continues to drive a weak/resistive 1 onto the net.

Port DescriptionsName Direction Width Function

O Output 1-Bit Keeper output

Design Entry MethodThis design element can be used in schematics.

This element can be connected to a net in the following locations on a top-level schematic file:

• A net connected to an input IO Marker

• A net connected to both an output IO Marker and 3-statable IO element, such as an OBUFT.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

LDPrimitive: Transparent Data Latch

IntroductionLD is a transparent data latch. The data output (Q) of the latch reflects the data (D) input while the gate enable(G) input is High. The data on the (D) input during the High-to-Low gate transition is stored in the latch. Thedata on the (Q) output remains unchanged as long as (G) remains Low.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

G D Q

1 D D

0 X No Change

↓ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LD_1Primitive: Transparent Data Latch with Inverted Gate

IntroductionThis design element is a transparent data latch with an inverted gate. The data output (Q) of the latch reflects thedata (D) input while the gate enable (G) input is Low. The data on the (D) input during the Low-to-High gatetransition is stored in the latch. The data on the (Q) output remains unchanged as long as (G) remains High.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

G D Q

0 D D

1 X No Change

↑ D D

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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LD16Macro: Multiple Transparent Data Latch

IntroductionThis design element has 16 transparent data latches with a common gate enable (G). The data output (Q) of thelatch reflects the data (D) input while the gate enable (G) input is High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) remains Low.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

G D Q

1 Dn Dn

0 X No Change

↓ Dn Dn

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary Any 16-Bit Value All zeros Sets the initial value of Q output afterconfiguration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LD16CEMacro: Transparent Data Latch with Asynchronous Clear and Gate Enable

IntroductionThis design element has 16 transparent data latches with asynchronous clear and gate enable. When theasynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) outputs Low. (Q)reflects the data (D) inputs while the gate (G) and gate enable (GE) are High, and (CLR) is Low. If (GE) is Low,data on (D) cannot be latched. The data on the (D) input during the High-to-Low gate transition is stored in thelatch. The data on the (Q) output remains unchanged as long as (G) or (GE) remains Low.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR GE G Dn Qn

1 X X X 0

0 0 X X No Change

0 1 1 Dn Dn

0 1 0 X No Change

0 1 ↓ Dn Dn

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary Any 16-BitValue

All zeros Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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LD4Macro: Multiple Transparent Data Latch

IntroductionThis design element has four transparent data latches with a common gate enable (G). The data output (Q) of thelatch reflects the data (D) input while the gate enable (G) input is High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) remains Low.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

G D Q

1 Dn Dn

0 X No Change

↓ Dn Dn

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary Any 4-Bit Value All zeros Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LD4CEMacro: Transparent Data Latch with Asynchronous Clear and Gate Enable

IntroductionThis design element has 4 transparent data latches with asynchronous clear and gate enable. When theasynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) outputs Low. (Q)reflects the data (D) inputs while the gate (G) and gate enable (GE) are High, and (CLR) is Low. If (GE) is Low,data on (D) cannot be latched. The data on the (D) input during the High-to-Low gate transition is stored in thelatch. The data on the (Q) output remains unchanged as long as (G) or (GE) remains Low.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR GE G Dn Qn

1 X X X 0

0 0 X X No Change

0 1 1 Dn Dn

0 1 0 X No Change

0 1 ↓ Dn Dn

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary Any 4-BitValue

All zeros Sets the initial value of Q output afterconfiguration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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LD8Macro: Multiple Transparent Data Latch

IntroductionThis design element has 8 transparent data latches with a common gate enable (G). The data output (Q) of thelatch reflects the data (D) input while the gate enable (G) input is High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) remains Low.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

G D Q

1 Dn Dn

0 X No Change

↓ Dn Dn

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary Any 8-Bit Value All zeros Sets the initial value of Q output after configuration

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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LD8CEMacro: Transparent Data Latch with Asynchronous Clear and Gate Enable

IntroductionThis design element has 8 transparent data latches with asynchronous clear and gate enable. When theasynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) outputs Low. (Q)reflects the data (D) inputs while the gate (G) and gate enable (GE) are High, and (CLR) is Low. If (GE) is Low,data on (D) cannot be latched. The data on the (D) input during the High-to-Low gate transition is stored in thelatch. The data on the (Q) output remains unchanged as long as (G) or (GE) remains Low.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR GE G Dn Qn

1 X X X 0

0 0 X X No Change

0 1 1 Dn Dn

0 1 0 X No Change

0 1 ↓ Dn Dn

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary Any 8-Bit Value All zeros Sets the initial value of Q output afterconfiguration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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LDCPrimitive: Macro: Transparent Data Latch with Asynchronous Clear

IntroductionThis design element is a transparent data latch with asynchronous clear. When the asynchronous clear input(CLR) is High, it overrides the other inputs and resets the data (Q) output Low. (Q) reflects the data (D) inputwhile the gate enable (G) input is High and (CLR) is Low. The data on the (D) input during the High-to-Low gatetransition is stored in the latch. The data on the (Q) output remains unchanged as long as (G) remains low.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR G D Q

1 X X 0

0 1 D D

0 0 X No Change

0 ↓ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output afterconfiguration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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LDC_1Primitive: Transparent Data Latch with Asynchronous Clear and Inverted Gate

IntroductionThis design element is a transparent data latch with asynchronous clear and inverted gate. When theasynchronous clear input (CLR) is High, it overrides the other inputs (D and G) and resets the data (Q) outputLow. (Q) reflects the data (D) input while the gate enable (G) input and CLR are Low. The data on the (D) inputduring the Low-to-High gate transition is stored in the latch. The data on the (Q) output remains unchanged aslong as (G) remains High.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR G D Q

1 X X 0

0 0 D D

0 1 X No Change

0 ↑ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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LDCEPrimitive: Transparent Data Latch with Asynchronous Clear and Gate Enable

IntroductionThis design element is a transparent data latch with asynchronous clear and gate enable. When the asynchronousclear input (CLR) is High, it overrides the other inputs and resets the data (Q) output Low. Q reflects the data (D)input while the gate (G) input and gate enable (GE) are High and CLR is Low. If (GE) is Low, data on (D) cannotbe latched. The data on the (D) input during the High-to-Low gate transition is stored in the latch. The data onthe (Q) output remains unchanged as long as (G) or (GE) remains low.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR GE G D Q

1 X X X 0

0 0 X X No Change

0 1 1 D D

0 1 0 X No Change

0 1 ↓ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output after configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LDCE_1Primitive: Transparent Data Latch with Asynchronous Clear, Gate Enable, and Inverted Gate

IntroductionThis design element is a transparent data latch with asynchronous clear, gate enable, and inverted gate. Whenthe asynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) output Low.(Q) reflects the data (D) input while the gate (G) input and (CLR) are Low and gate enable (GE) is High. Thedata on the (D) input during the Low-to-High gate transition is stored in the latch. The data on the (Q) outputremains unchanged as long as (G) remains High or (GE) remains Low

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR GE G D Q

1 X X X 0

0 0 X X No Change

0 1 0 D D

0 1 1 X No Change

0 1 ↑ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Sets the initial value of Q output afterconfiguration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LDEPrimitive: Transparent Data Latch with Gate Enable

IntroductionThis design element is a transparent data latch with data (D) and gate enable (GE) inputs. Output (Q) reflectsthe data (D) while the gate (G) input and gate enable (GE) are High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) or (GE) remains Low.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic Table

Inputs Outputs

GE G D Q

0 X X No Change

1 1 D D

1 0 X No Change

1 ↓ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Specifies the initial value upon power-up or the assertion ofGSR for the (Q) port.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LDE_1Primitive: Transparent Data Latch with Gate Enable and Inverted Gate

IntroductionThis design element is a transparent data latch with data (D), gate enable (GE), and inverted gate (G). Output (Q)reflects the data (D) while the gate (G) input is Low and gate enable (GE) is High. The data on the (D) inputduring the Low-to-High gate transition is stored in the latch. The data on the (Q) output remains unchanged aslong as (G) is High or (GE) is Low.

This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

GE G D Q

0 X X No Change

1 0 D D

1 1 X No Change

1 ↑ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 0 Specifies the initial value upon power-up or theassertion of GSR for the (Q) port.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LDPPrimitive: Macro: Transparent Data Latch with Asynchronous Preset

IntroductionThis design element is a transparent data latch with asynchronous preset (PRE). When PRE is High it overridesthe other inputs and presets the data (Q) output High. Q reflects the data (D) input while gate (G) input is Highand PRE is Low. The data on the (D) input during the High-to-Low gate transition is stored in the latch. The dataon the Q output remains unchanged as long as G remains Low.

The latch is asynchronously preset, output High, when power is applied. For FPGA devices, power-on conditionsare simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding aninverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE G D Q

1 X X 1

0 1 0 0

0 1 1 1

0 0 X No Change

0 ↓ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Specifies the initial value upon power-up or theassertion of GSR for the Q port.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LDP_1Primitive: Transparent Data Latch with Asynchronous Preset and Inverted Gate

IntroductionThis design element is a transparent data latch with asynchronous preset (PRE) and inverted gate (G). When the(PRE) input is High, it overrides the other inputs and presets the data (Q) output High. (Q) reflects the data (D)input while gate (G) input and (PRE) are Low. The data on the (D) input during the Low-to-High gate transitionis stored in the latch. The data on the (Q) output remains unchanged as long as (G) remains High.

The latch is asynchronously preset, output High, when power is applied. For FPGA devices, power-on conditionsare simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding aninverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE G D Q

1 X X 1

0 0 D D

0 1 X No Change

0 ↑ D D

Design Entry MethodThis design element is only for use in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Binary 0, 1 1 Specifies the initial value upon power-up or the assertion of GSRfor the (Q) port.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LDPEPrimitive: Transparent Data Latch with Asynchronous Preset and Gate Enable

IntroductionThis design element is a transparent data latch with asynchronous preset and gate enable. When theasynchronous preset (PRE) is High, it overrides the other input and presets the data (Q) output High. Q reflectsthe data (D) input while the gate (G) input and gate enable (GE) are High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) or (GE) remains Low.

The latch is asynchronously preset, output High, when power is applied. For FPGA devices, power-on conditionsare simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding aninverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE GE G D Q

1 X X X 1

0 0 X X No Change

0 1 1 D D

0 1 0 X No Change

0 1 ↓ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Specifies the initial value upon power-up or theassertion of GSR for the (Q) port.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LDPE_1Primitive: Transparent Data Latch with Asynchronous Preset, Gate Enable, and Inverted Gate

IntroductionThis design element is a transparent data latch with asynchronous preset, gate enable, and inverted gate. Whenthe asynchronous preset (PRE) is High, it overrides the other input and presets the data (Q) output High. (Q)reflects the data (D) input while the gate (G) and (PRE) are Low and gate enable (GE) is High. The data on the(D) input during the Low-to-High gate transition is stored in the latch. The data on the (Q) output remainsunchanged as long as (G) remains High or (GE) remains Low.

The latch is asynchronously preset, output High, when power is applied. For FPGA devices, power-on conditionsare simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding aninverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

PRE GE G D Q

1 X X X 1

0 0 X X No Change

0 1 0 D D

0 1 1 X No Change

0 1 ↑ D D

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Binary 0, 1 1 Specifies the initial value upon power-up or the assertionof GSR for the (Q) port.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LUT1Macro: 1-Bit Look-Up Table with General Output

IntroductionThis design element is a 1-bit look-up table (LUT) with general output (O).

An INIT attribute with an appropriate number of hexadecimal digits for the number of inputs must be attachedto the LUT to specify its function. This element provides a look-up table version of a buffer or inverter. Theseelements are the basic building blocks. Two LUTs are available in each CLB slice; four LUTs are available in eachCLB. Multiple variants of LUTs accommodate additional types of outputs that can be used by different timingmodels for more accurate pre-layout timing estimation.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I0 O

0 INIT[0]

1 INIT[1]

INIT = Binary number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 2-Bit Value All zeros Initializes look-up tables.

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Chapter 3: About Design Elements

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LUT1_DMacro: 1-Bit Look-Up Table with Dual Output

IntroductionThis design element is a 1-bit look-up table (LUT) with two functionally identical outputs, O and LO. It providesa look-up table version of a buffer or inverter.

The O output is a general interconnect. The LO output is used to connect to another output within the same CLBslice and to the fast connect buffer. A mandatory INIT attribute, with an appropriate number of hexadecimaldigits for the number of inputs, must be attached to the LUT to specify its function.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I0 O LO

0 INIT[0] INIT[0]

1 INIT[1] INIT[1]

INIT = Binary number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 2-Bit Value All zeros Initializes look-up tables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LUT1_LMacro: 1-Bit Look-Up Table with Local Output

IntroductionThis design element is a 1-bit look-up table (LUT) with a local output (LO) that is used to connect to anotheroutput within the same CLB slice and to the fast connect buffer. It provides a look-up table version of a bufferor inverter.

A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs,must be attached to the LUT to specify its function.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I0 LO

0 INIT[0]

1 INIT[1]

INIT = Binary number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 2-Bit Value All zeros Initializes look-up tables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LUT2Macro: 2-Bit Look-Up Table with General Output

IntroductionThis design element is a 2-bit look-up table (LUT) with general output (O).

An INIT attribute with an appropriate number of hexadecimal digits for the number of inputs must be attachedto the LUT to specify its function. This element provides a look-up table version of a buffer or inverter. Theseelements are the basic building blocks. Two LUTs are available in each CLB slice; four LUTs are available in eachCLB. Multiple variants of LUTs accommodate additional types of outputs that can be used by different timingmodels for more accurate pre-layout timing estimation.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I1 I0 O

0 0 INIT[0]

0 1 INIT[1]

1 0 INIT[2]

1 1 INIT[3]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 4-Bit Value All zeros Initializes look-up tables.

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Chapter 3: About Design Elements

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LUT2_DMacro: 2-Bit Look-Up Table with Dual Output

IntroductionThis design element is a 2-bit look-up table (LUT) with two functionally identical outputs, O and LO.

The O output is a general interconnect. The LO output is used to connect to another output within the same CLBslice and to the fast connect buffer. A mandatory INIT attribute, with an appropriate number of hexadecimaldigits for the number of inputs, must be attached to the LUT to specify its function.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The LogicTable Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I1 I0 O LO

0 0 INIT[0] INIT[0]

0 1 INIT[1] INIT[1]

1 0 INIT[2] INIT[2]

1 1 INIT[3] INIT[3]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 4-Bit Value All zeros Initializes look-up tables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LUT2_LMacro: 2-Bit Look-Up Table with Local Output

IntroductionThis design element is a 2-bit look-up table (LUT) with a local output (LO) that is used to connect to anotheroutput within the same CLB slice and to the fast connect buffer. It provides a look-up table version of a bufferor inverter.

A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs,must be attached to the LUT to specify its function.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I1 I0 LO

0 0 INIT[0]

0 1 INIT[1]

1 0 INIT[2]

1 1 INIT[3]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 4-Bit Value All zeros Initializes look-up tables.

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For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LUT3Macro: 3-Bit Look-Up Table with General Output

IntroductionThis design element is a 3-bit look-up table (LUT) with general output (O). A mandatory INIT attribute, withan appropriate number of hexadecimal digits for the number of inputs, must be attached to the LUT to specifyits function.

An INIT attribute with an appropriate number of hexadecimal digits for the number of inputs must be attachedto the LUT to specify its function. This element provides a look-up table version of a buffer or inverter. Theseelements are the basic building blocks. Two LUTs are available in each CLB slice; four LUTs are available in eachCLB. Multiple variants of LUTs accommodate additional types of outputs that can be used by different timingmodels for more accurate pre-layout timing estimation.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I2 I1 I0 O

0 0 0 INIT[0]

0 0 1 INIT[1]

0 1 0 INIT[2]

0 1 1 INIT[3]

1 0 0 INIT[4]

1 0 1 INIT[5]

1 1 0 INIT[6]

1 1 1 INIT[7]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

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Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 8-Bit Value All zeros Initializes look-up tables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LUT3_DMacro: 3-Bit Look-Up Table with Dual Output

IntroductionThis design element is a 3-bit look-up table (LUT) with two functionally identical outputs, O and LO.

The O output is a general interconnect. The LO output is used to connect to another output within the same CLBslice and to the fast connect buffer. A mandatory INIT attribute, with an appropriate number of hexadecimaldigits for the number of inputs, must be attached to the LUT to specify its function.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I2 I1 I0 O LO

0 0 0 INIT[0] INIT[0]

0 0 1 INIT[1] INIT[1]

0 1 0 INIT[2] INIT[2]

0 1 1 INIT[3] INIT[3]

1 0 0 INIT[4] INIT[4]

1 0 1 INIT[5] INIT[5]

1 1 0 INIT[6] INIT[6]

1 1 1 INIT[7] INIT[7]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

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Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 8-Bit Value All zeros Initializes look-up tables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs350 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

LUT3_LMacro: 3-Bit Look-Up Table with Local Output

IntroductionThis design element is a 3-bit look-up table (LUT) with a local output (LO) that is used to connect to anotheroutput within the same CLB slice and to the fast connect buffer. It provides a look-up table version of a bufferor inverter.

A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs,must be attached to the LUT to specify its function.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I2 I1 I0 LO

0 0 0 INIT[0]

0 0 1 INIT[1]

0 1 0 INIT[2]

0 1 1 INIT[3]

1 0 0 INIT[4]

1 0 1 INIT[5]

1 1 0 INIT[6]

1 1 1 INIT[7]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

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Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 8-Bit Value All zeros Initializes look-up tables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs352 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

LUT4Macro: 4-Bit Look-Up-Table with General Output

IntroductionThis design element is a 4-bit look-up table (LUT) with general output (O).

An INIT attribute with an appropriate number of hexadecimal digits for the number of inputs must be attachedto the LUT to specify its function. This element provides a look-up table version of a buffer or inverter. Theseelements are the basic building blocks. Two LUTs are available in each CLB slice; four LUTs are available in eachCLB. Multiple variants of LUTs accommodate additional types of outputs that can be used by different timingmodels for more accurate pre-layout timing estimation.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

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Logic TableInputs Outputs

I3 I2 I1 I0 O

0 0 0 0 INIT[0]

0 0 0 1 INIT[1]

0 0 1 0 INIT[2]

0 0 1 1 INIT[3]

0 1 0 0 INIT[4]

0 1 0 1 INIT[5]

0 1 1 0 INIT[6]

0 1 1 1 INIT[7]

1 0 0 0 INIT[8]

1 0 0 1 INIT[9]

1 0 1 0 INIT[10]

1 0 1 1 INIT[11]

1 1 0 0 INIT[12]

1 1 0 1 INIT[13]

1 1 1 0 INIT[14]

1 1 1 1 INIT[15]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Initializes look-up tables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

LUT4_DMacro: 4-Bit Look-Up Table with Dual Output

IntroductionThis design element is a 4-bit look-up table (LUT) with two functionally identical outputs, O and LO

The O output is a general interconnect. The LO output is used to connect to another output within the same CLBslice and to the fast connect buffer. A mandatory INIT attribute, with an appropriate number of hexadecimaldigits for the number of inputs, must be attached to the LUT to specify its function.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

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Chapter 3: About Design Elements

Logic TableInputs Outputs

I3 I2 I1 I0 O LO

0 0 0 0 INIT[0] INIT[0]

0 0 0 1 INIT[1] INIT[1]

0 0 1 0 INIT[2] INIT[2]

0 0 1 1 INIT[3] INIT[3]

0 1 0 0 INIT[4] INIT[4]

0 1 0 1 INIT[5] INIT[5]

0 1 1 0 INIT[6] INIT[6]

0 1 1 1 INIT[7] INIT[7]

1 0 0 0 INIT[8] INIT[8]

1 0 0 1 INIT[9] INIT[9]

1 0 1 0 INIT[10] INIT[10]

1 0 1 1 INIT[11] INIT[11]

1 1 0 0 INIT[12] INIT[12]

1 1 0 1 INIT[13] INIT[13]

1 1 1 0 INIT[14] INIT[14]

1 1 1 1 INIT[15] INIT[15]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Initializes look-up tables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs356 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

LUT4_LMacro: 4-Bit Look-Up Table with Local Output

IntroductionThis design element is a 4-bit look-up table (LUT) with a local output (LO) that is used to connect to anotheroutput within the same CLB slice and to the fast connect buffer. It provides a look-up table version of a bufferor inverter.

A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs,must be attached to the LUT to specify its function.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

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Chapter 3: About Design Elements

Logic TableInputs Outputs

I3 I2 I1 I0 LO

0 0 0 0 INIT[0]

0 0 0 1 INIT[1]

0 0 1 0 INIT[2]

0 0 1 1 INIT[3]

0 1 0 0 INIT[4]

0 1 0 1 INIT[5]

0 1 1 0 INIT[6]

0 1 1 1 INIT[7]

1 0 0 0 INIT[8]

1 0 0 1 INIT[9]

1 0 1 0 INIT[10]

1 0 1 1 INIT[11]

1 1 0 0 INIT[12]

1 1 0 1 INIT[13]

1 1 1 0 INIT[14]

1 1 1 1 INIT[15]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Initializes look-up tables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs358 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

LUT5Primitive: 5-Input Lookup Table with General Output

IntroductionThis design element is a 5-input, 1-output look-up table (LUT) that can either act as an asynchronous 32-bit ROM(with 5-bit addressing) or implement any 5-input logic function. LUTs are the basic logic building blocks andare used to implement most logic functions of the design. One LUT5 is packed into a LUT6 within a slice, ortwo LUT5s can be packed into a single LUT6 with some restrictions. The functionality of the LUT5, LUT5_Land LUT5_D is the same. However, the LUT5_L and LUT5_D allow the additional specification to connect theLUT5 output signal to an internal slice or CLB connection using the LO output. The LUT5_L specifies thatthe only connections from the LUT5 will be within a slice or CLB, while the LUT5_D allows the specificationto connect the output of the LUT to both inter-slice/CLB logic and external logic as well. The LUT5 does notstate any specific output connections and should be used in all cases except where internal slice or CLB signalconnections must be implicitly specified.

An INIT attribute consisting of a 32-bit hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to the corresponding INIT bit value when the associated inputsare applied. For instance, a Verilog INIT value of 32’h80000000 (X"80000000" for VHDL) makes the output zerounless all of the inputs are one (a 5-input AND gate). A Verilog INIT value of 32’hfffffffe (X"FFFFFFFE" forVHDL) makes the output one unless all zeros are on the inputs (a 5-input OR gate).

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

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Chapter 3: About Design Elements

Logic TableInputs Outputs

I4 I3 I2 I1 I0 LO

0 0 0 0 0 INIT[0]

0 0 0 0 1 INIT[1]

0 0 0 1 0 INIT[2]

0 0 0 1 1 INIT[3]

0 0 1 0 0 INIT[4]

0 0 1 0 1 INIT[5]

0 0 1 1 0 INIT[6]

0 0 1 1 1 INIT[7]

0 1 0 0 0 INIT[8]

0 1 0 0 1 INIT[9]

0 1 0 1 0 INIT[10]

0 1 0 1 1 INIT[11]

0 1 1 0 0 INIT[12]

0 1 1 0 1 INIT[13]

0 1 1 1 0 INIT[14]

0 1 1 1 1 INIT[15]

1 0 0 0 0 INIT[16]

1 0 0 0 1 INIT[17]

1 0 0 1 0 INIT[18]

1 0 0 1 1 INIT[19]

1 0 1 0 0 INIT[20]

1 0 1 0 1 INIT[21]

1 0 1 1 0 INIT[22]

1 0 1 1 1 INIT[23]

1 1 0 0 0 INIT[24]

1 1 0 0 1 INIT[25]

1 1 0 1 0 INIT[26]

1 1 0 1 1 INIT[27]

1 1 1 0 0 INIT[28]

1 1 1 0 1 INIT[29]

1 1 1 1 0 INIT[30]

1 1 1 1 1 INIT[31]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

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Chapter 3: About Design Elements

Port DescriptionName Direction Width Function

O Output 1 5-LUT output

I0, I1, I2, I3, I4 Input 1 LUT inputs

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 32-Bit Value All zeros Specifies the logic value for the look-uptables.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 361

Chapter 3: About Design Elements

LUT5_DPrimitive: 5-Input Lookup Table with General and Local Outputs

IntroductionThis design element is a 5-input, 1-output look-up table (LUT) that can either act as an asynchronous 32-bit ROM(with 5-bit addressing) or implement any 5-input logic function. LUTs are the basic logic building blocks and areused to implement most logic functions of the design. One LUT5 will be packed into a LUT6 within a slice, ortwo LUT5s can be packed into a single LUT6 with some restrictions. The functionality of the LUT5, LUT5_Land LUT5_D is the same. However, the LUT5_L and LUT5_D allow the additional specification to connect theLUT5 output signal to an internal slice or CLB connection using the LO output. The LUT5_L specifies thatthe only connections from the LUT5 will be within a slice or CLB, while the LUT5_D allows the specificationto connect the output of the LUT to both inter-slice/CLB logic and external logic as well. The LUT5 does notstate any specific output connections and should be used in all cases except where internal slice or CLB signalconnections must be implicitly specified.

An INIT attribute consisting of a 32-bit hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to the corresponding INIT bit value when the associated inputsare applied. For instance, a Verilog INIT value of 32’h80000000 (X"80000000" for VHDL) will make the outputzero unless all of the inputs are one (a 5-input AND gate). A Verilog INIT value of 32’hfffffffe (X"FFFFFFFE" forVHDL) will make the output one unless all zeros are on the inputs (a 5-input OR gate).

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod. However, this method does require the code to first specify the appropriate parameters.

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Chapter 3: About Design Elements

Logic TableInputs Outputs

I4 I3 I2 I1 I0 O LO

0 0 0 0 0 INIT[0] INIT[0]

0 0 0 0 1 INIT[1] INIT[1]

0 0 0 1 0 INIT[2] INIT[2]

0 0 0 1 1 INIT[3] INIT[3]

0 0 1 0 0 INIT[4] INIT[4]

0 0 1 0 1 INIT[5] INIT[5]

0 0 1 1 0 INIT[6] INIT[6]

0 0 1 1 1 INIT[7] INIT[7]

0 1 0 0 0 INIT[8] INIT[8]

0 1 0 0 1 INIT[9] INIT[9]

0 1 0 1 0 INIT[10] INIT[10]

0 1 0 1 1 INIT[11] INIT[11]

0 1 1 0 0 INIT[12] INIT[12]

0 1 1 0 1 INIT[13] INIT[13]

0 1 1 1 0 INIT[14] INIT[14]

0 1 1 1 1 INIT[15] INIT[15]

1 0 0 0 0 INIT[16] INIT[16]

1 0 0 0 1 INIT[17] INIT[17]

1 0 0 1 0 INIT[18] INIT[18]

1 0 0 1 1 INIT[19] INIT[19]

1 0 1 0 0 INIT[20] INIT[20]

1 0 1 0 1 INIT[21] INIT[21]

1 0 1 1 0 INIT[22] INIT[22]

1 0 1 1 1 INIT[23] INIT[23]

1 1 0 0 0 INIT[24] INIT[24]

1 1 0 0 1 INIT[25] INIT[25]

1 1 0 1 0 INIT[26] INIT[26]

1 1 0 1 1 INIT[27] INIT[27]

1 1 1 0 0 INIT[28] INIT[28]

1 1 1 0 1 INIT[29] INIT[29]

1 1 1 1 0 INIT[30] INIT[30]

1 1 1 1 1 INIT[31] INIT[31]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

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Chapter 3: About Design Elements

Port DescriptionName Direction Width Function

O Output 1 5-LUT output

L0 Output 1 5-LUT output for internal CLB connection

I0, I1, I2, I3, I4 Input 1 LUT inputs

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 32-Bit Value All zeros Specifies the logic value for the look-uptables.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

Spartan-6 Libraries Guide for Schematic Designs364 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

LUT5_LPrimitive: 5-Input Lookup Table with Local Output

IntroductionThis design element is a 5-input, 1-output look-up table (LUT) that can either act as an asynchronous 32-bit ROM(with 5-bit addressing) or implement any 5-input logic function. LUTs are the basic logic building blocks and areused to implement most logic functions of the design. One LUT5 will be packed into a LUT6 within a slice, ortwo LUT5s can be packed into a single LUT6 with some restrictions. The functionality of the LUT5, LUT5_Land LUT5_D is the same. However, the LUT5_L and LUT5_D allow the additional specification to connectthe LUT5 output signal to an internal slice or CLB connection using the LO output. The LUT5_L specifiesthat the only connections from the LUT5 is within a slice or CLB, while the LUT5_D allows the specificationto connect the output of the LUT to both inter-slice/CLB logic and external logic as well. The LUT5 does notstate any specific output connections and should be used in all cases except where internal slice or CLB signalconnections must be implicitly specified.

An INIT attribute consisting of a 32-bit hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to the corresponding INIT bit value when the associated inputsare applied. For instance, a Verilog INIT value of 32’h80000000 (X"80000000" for VHDL) makes the output zerounless all of the inputs are one (a 5-input AND gate). A Verilog INIT value of 32’hfffffffe (X"FFFFFFFE" forVHDL) makes the output one unless all zeros are on the inputs (a 5-input OR gate).

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed logic value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

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Chapter 3: About Design Elements

Logic TableInputs Outputs

I4 I3 I2 I1 I0 LO

0 0 0 0 0 INIT[0]

0 0 0 0 1 INIT[1]

0 0 0 1 0 INIT[2]

0 0 0 1 1 INIT[3]

0 0 1 0 0 INIT[4]

0 0 1 0 1 INIT[5]

0 0 1 1 0 INIT[6]

0 0 1 1 1 INIT[7]

0 1 0 0 0 INIT[8]

0 1 0 0 1 INIT[9]

0 1 0 1 0 INIT[10]

0 1 0 1 1 INIT[11]

0 1 1 0 0 INIT[12]

0 1 1 0 1 INIT[13]

0 1 1 1 0 INIT[14]

0 1 1 1 1 INIT[15]

1 0 0 0 0 INIT[16]

1 0 0 0 1 INIT[17]

1 0 0 1 0 INIT[18]

1 0 0 1 1 INIT[19]

1 0 1 0 0 INIT[20]

1 0 1 0 1 INIT[21]

1 0 1 1 0 INIT[22]

1 0 1 1 1 INIT[23]

1 1 0 0 0 INIT[24]

1 1 0 0 1 INIT[25]

1 1 0 1 0 INIT[26]

1 1 0 1 1 INIT[27]

1 1 1 0 0 INIT[28]

1 1 1 0 1 INIT[29]

1 1 1 1 0 INIT[30]

1 1 1 1 1 INIT[31]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

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Chapter 3: About Design Elements

Port DescriptionName Direction Width Function

L0 Output 1 6/5-LUT output for internal CLB connection

I0, I1, I2, I3, I4 Input 1 LUT inputs

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 32-Bit Value All zeros Specifies the logic value for the look-uptables.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 367

Chapter 3: About Design Elements

LUT6Primitive: 6-Input Lookup Table with General Output

IntroductionThis design element is a 6-input, 1-output look-up table (LUT) that can either act as an asynchronous 64-bit ROM(with 6-bit addressing) or implement any 6-input logic function. LUTs are the basic logic building blocks and areused to implement most logic functions of the design. A LUT6 is mapped to one of the four look-up tables in theslice. The functionality of the LUT6, LUT6_L and LUT6_D is the same. However, the LUT6_L and LUT6_D allowthe additional specification to connect the LUT6 output signal to an internal slice, or CLB connection, using theLO output. The LUT6_L specifies that the only connections from the LUT6 will be within a slice, or CLB, whilethe LUT6_D allows the specification to connect the output of the LUT to both inter-slice/CLB logic and externallogic as well. The LUT6 does not state any specific output connections and should be used in all cases exceptwhere internal slice or CLB signal connections must be implicitly specified.

An INIT attribute consisting of a 64-bit Hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to corresponding INIT bit value when the associated inputs areapplied. For instance, a Verilog INIT value of 64’h8000000000000000 (X"8000000000000000" for VHDL) makesthe output zero unless all of the inputs are one (a 6-input AND gate). A Verilog INIT value of 64’hfffffffffffffffe(X"FFFFFFFFFFFFFFFE" for VHDL) makes the output one unless all zeros are on the inputs (a 6-input OR gate).

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I5 I4 I3 I2 I1 I0 O

0 0 0 0 0 0 INIT[0]

0 0 0 0 0 1 INIT[1]

0 0 0 0 1 0 INIT[2]

0 0 0 0 1 1 INIT[3]

0 0 0 1 0 0 INIT[4]

0 0 0 1 0 1 INIT[5]

0 0 0 1 1 0 INIT[6]

0 0 0 1 1 1 INIT[7]

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Chapter 3: About Design Elements

Inputs Outputs

I5 I4 I3 I2 I1 I0 O

0 0 1 0 0 0 INIT[8]

0 0 1 0 0 1 INIT[9]

0 0 1 0 1 0 INIT[10]

0 0 1 0 1 1 INIT[11]

0 0 1 1 0 0 INIT[12]

0 0 1 1 0 1 INIT[13]

0 0 1 1 1 0 INIT[14]

0 0 1 1 1 1 INIT[15]

0 1 0 0 0 0 INIT[16]

0 1 0 0 0 1 INIT[17]

0 1 0 0 1 0 INIT[18]

0 1 0 0 1 1 INIT[19]

0 1 0 1 0 0 INIT[20]

0 1 0 1 0 1 INIT[21]

0 1 0 1 1 0 INIT[22]

0 1 0 1 1 1 INIT[23]

0 1 1 0 0 0 INIT[24]

0 1 1 0 0 1 INIT[25]

0 1 1 0 1 0 INIT[26]

0 1 1 0 1 1 INIT[27]

0 1 1 1 0 0 INIT[28]

0 1 1 1 0 1 INIT[29]

0 1 1 1 1 0 INIT[30]

0 1 1 1 1 1 INIT[31]

1 0 0 0 0 0 INIT[32]

1 0 0 0 0 1 INIT[33]

1 0 0 0 1 0 INIT[34]

1 0 0 0 1 1 INIT[35]

1 0 0 1 0 0 INIT[36]

1 0 0 1 0 1 INIT[37]

1 0 0 1 1 0 INIT[38]

1 0 0 1 1 1 INIT[39]

1 0 1 0 0 0 INIT[40]

1 0 1 0 0 1 INIT[41]

1 0 1 0 1 0 INIT[42]

1 0 1 0 1 1 INIT[43]

1 0 1 1 0 0 INIT[44]

1 0 1 1 0 1 INIT[45]

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Chapter 3: About Design Elements

Inputs Outputs

I5 I4 I3 I2 I1 I0 O

1 0 1 1 1 0 INIT[46]

1 0 1 1 1 1 INIT[47]

1 1 0 0 0 0 INIT[48]

1 1 0 0 0 1 INIT[49]

1 1 0 0 1 0 INIT[50]

1 1 0 0 1 1 INIT[51]

1 1 0 1 0 0 INIT[52]

1 1 0 1 0 1 INIT[53]

1 1 0 1 1 0 INIT[54]

1 1 0 1 1 1 INIT[55]

1 1 1 0 0 0 INIT[56]

1 1 1 0 0 1 INIT[57]

1 1 1 0 1 0 INIT[58]

1 1 1 0 1 1 INIT[59]

1 1 1 1 0 0 INIT[60]

1 1 1 1 0 1 INIT[61]

1 1 1 1 1 0 INIT[62]

1 1 1 1 1 1 INIT[63]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Port DescriptionName Direction Width Function

O Output 1 6/5-LUT output

I0, I1, I2, I3, I4, I5 Input 1 LUT inputs

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 64-Bit Value All zeros Specifies the logic value for thelook-up tables.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

Spartan-6 Libraries Guide for Schematic Designs370 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

LUT6_2Primitive: Six-input, 2-output, Look-Up Table

IntroductionThis design element is a 6-input, 2-output look-up table (LUT) that can either act as a dual asynchronous 32-bitROM (with 5-bit addressing), implement any two 5-input logic functions with shared inputs, or implement a6-input logic function and a 5-input logic function with shared inputs and shared logic values. LUTs are thebasic logic building blocks and are used to implement most logic functions of the design. A LUT6_2 will bemapped to one of the four look-up tables in the slice.

An INIT attribute consisting of a 64-bit hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to corresponding INIT bit value when the associated inputs areapplied. For instance, a Verilog INIT value of 64’hfffffffffffffffe (X"FFFFFFFFFFFFFFFE" for VHDL) makes the O6output 1 unless all zeros are on the inputs and the O5 output a 1, or unless I[4:0] are all zeroes (a 5-input and6-input OR gate). The lower half (bits 31:0) of the INIT values apply to the logic function of the O5 output.

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting than the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I5 I4 I3 I2 I1 I0 O5 O6

0 0 0 0 0 0 INIT[0] INIT[0]

0 0 0 0 0 1 INIT[1] INIT[1]

0 0 0 0 1 0 INIT[2] INIT[2]

0 0 0 0 1 1 INIT[3] INIT[3]

0 0 0 1 0 0 INIT[4] INIT[4]

0 0 0 1 0 1 INIT[5] INIT[5]

0 0 0 1 1 0 INIT[6] INIT[6]

0 0 0 1 1 1 INIT[7] INIT[7]

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Chapter 3: About Design Elements

Inputs Outputs

0 0 1 0 0 0 INIT[8] INIT[8]

0 0 1 0 0 1 INIT[9] INIT[9]

0 0 1 0 1 0 INIT[10] INIT[10]

0 0 1 0 1 1 INIT[11] INIT[11]

0 0 1 1 0 0 INIT[12] INIT[12]

0 0 1 1 0 1 INIT[13] INIT[13]

0 0 1 1 1 0 INIT[14] INIT[14]

0 0 1 1 1 1 INIT[15] INIT[15]

0 1 0 0 0 0 INIT[16] INIT[16]

0 1 0 0 0 1 INIT[17] INIT[17]

0 1 0 0 1 0 INIT[18] INIT[18]

0 1 0 0 1 1 INIT[19] INIT[19]

0 1 0 1 0 0 INIT[20] INIT[20]

0 1 0 1 0 1 INIT[21] INIT[21]

0 1 0 1 1 0 INIT[22] INIT[22]

0 1 0 1 1 1 INIT[23] INIT[23]

0 1 1 0 0 0 INIT[24] INIT[24]

0 1 1 0 0 1 INIT[25] INIT[25]

0 1 1 0 1 0 INIT[26] INIT[26]

0 1 1 0 1 1 INIT[27] INIT[27]

0 1 1 1 0 0 INIT[28] INIT[28]

0 1 1 1 0 1 INIT[29] INIT[29]

0 1 1 1 1 0 INIT[30] INIT[30]

0 1 1 1 1 1 INIT[31] INIT[31]

1 0 0 0 0 0 INIT[0] INIT[32]

1 0 0 0 0 1 INIT[1] INIT[33]

1 0 0 0 1 0 INIT[2] INIT[34]

1 0 0 0 1 1 INIT[3] INIT[35]

1 0 0 1 0 0 INIT[4] INIT[36]

1 0 0 1 0 1 INIT[5] INIT[37]

1 0 0 1 1 0 INIT[6] INIT[38]

1 0 0 1 1 1 INIT[7] INIT[39]

1 0 1 0 0 0 INIT[8] INIT[40]

1 0 1 0 0 1 INIT[9] INIT[41]

1 0 1 0 1 0 INIT[10] INIT[42]

1 0 1 0 1 1 INIT[11] INIT[43]

1 0 1 1 0 0 INIT[12] INIT[44]

1 0 1 1 0 1 INIT[13] INIT[45]

1 0 1 1 1 0 INIT[14] INIT[46]

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Chapter 3: About Design Elements

Inputs Outputs

1 0 1 1 1 1 INIT[15] INIT[47]

1 1 0 0 0 0 INIT[16] INIT[48]

1 1 0 0 0 1 INIT[17] INIT[49]

1 1 0 0 1 0 INIT[18] INIT[50]

1 1 0 0 1 1 INIT[19] INIT[51]

1 1 0 1 0 0 INIT[20] INIT[52]

1 1 0 1 0 1 INIT[21] INIT[53]

1 1 0 1 1 0 INIT[22] INIT[54]

1 1 0 1 1 1 INIT[23] INIT[55]

1 1 1 0 0 0 INIT[24] INIT[56]

1 1 1 0 0 1 INIT[25] INIT[57]

1 1 1 0 1 0 INIT[26] INIT[58]

1 1 1 0 1 1 INIT[27] INIT[59]

1 1 1 1 0 0 INIT[28] INIT[60]

1 1 1 1 0 1 INIT[29] INIT[61]

1 1 1 1 1 0 INIT[30] INIT[62]

1 1 1 1 1 1 INIT[31] INIT[63]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Port DescriptionsPort Direction Width Function

O6 Output 1 6/5-LUT output

O5 Output 1 5-LUT output

I0, I1, I2, I3, I4, I5 Input 1 LUT inputs

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 64-Bit Value All zeros Specifies the LUT5/6 output function.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

LUT6_DPrimitive: 6-Input Lookup Table with General and Local Outputs

IntroductionThis design element is a six-input, one-output look-up table (LUT) that can either act as an asynchronous 64-bitROM (with 6-bit addressing) or implement any 6-input logic function. LUTs are the basic logic building blocksand are used to implement most logic functions of the design. A LUT6 is mapped to one of the four look-uptables in the slice. The functionality of the LUT6, LUT6_L and LUT6_D is the same. However, the LUT6_Land LUT6_D allow the additional specification to connect the LUT6 output signal to an internal slice, or CLBconnection, using the LO output. The LUT6_L specifies that the only connections from the LUT6 will be within aslice, or CLB, while the LUT6_D allows the specification to connect the output of the LUT to both inter-slice/CLBlogic and external logic as well. The LUT6 does not state any specific output connections and should be used inall cases except where internal slice or CLB signal connections must be implicitly specified.

An INIT attribute consisting of a 64-bit Hexadecimal value must be specified to indicate the LUTs logical function.The INIT value is calculated by assigning a 1 to corresponding INIT bit value when the associated inputs areapplied. For instance, a Verilog INIT value of 64’h8000000000000000 (X"8000000000000000" for VHDL) makesthe output zero unless all of the inputs are one (a 6-input AND gate). A Verilog INIT value of 64’hfffffffffffffffe(X"FFFFFFFFFFFFFFFE" for VHDL) makes the output one unless all zeros are on the inputs (a 6-input OR gate).

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more is self-documenting that the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I5 I4 I3 I2 I1 I0 O LO

0 0 0 0 0 0 INIT[0] INIT[0]

0 0 0 0 0 1 INIT[1] INIT[1]

0 0 0 0 1 0 INIT[2] INIT[2]

0 0 0 0 1 1 INIT[3] INIT[3]

0 0 0 1 0 0 INIT[4] INIT[4]

0 0 0 1 0 1 INIT[5] INIT[5]

0 0 0 1 1 0 INIT[6] INIT[6]

0 0 0 1 1 1 INIT[7] INIT[7]

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Chapter 3: About Design Elements

Inputs Outputs

I5 I4 I3 I2 I1 I0 O LO

0 0 1 0 0 0 INIT[8] INIT[8]

0 0 1 0 0 1 INIT[9] INIT[9]

0 0 1 0 1 0 INIT[10] INIT[10]

0 0 1 0 1 1 INIT[11] INIT[11]

0 0 1 1 0 0 INIT[12] INIT[12]

0 0 1 1 0 1 INIT[13] INIT[13]

0 0 1 1 1 0 INIT[14] INIT[14]

0 0 1 1 1 1 INIT[15] INIT[15]

0 1 0 0 0 0 INIT[16] INIT[16]

0 1 0 0 0 1 INIT[17] INIT[17]

0 1 0 0 1 0 INIT[18] INIT[18]

0 1 0 0 1 1 INIT[19] INIT[19]

0 1 0 1 0 0 INIT[20] INIT[20]

0 1 0 1 0 1 INIT[21] INIT[21]

0 1 0 1 1 0 INIT[22] INIT[22]

0 1 0 1 1 1 INIT[23] INIT[23]

0 1 1 0 0 0 INIT[24] INIT[24]

0 1 1 0 0 1 INIT[25] INIT[25]

0 1 1 0 1 0 INIT[26] INIT[26]

0 1 1 0 1 1 INIT[27] INIT[27]

0 1 1 1 0 0 INIT[28] INIT[28]

0 1 1 1 0 1 INIT[29] INIT[29]

0 1 1 1 1 0 INIT[30] INIT[30]

0 1 1 1 1 1 INIT[31] INIT[31]

1 0 0 0 0 0 INIT[32] INIT[32]

1 0 0 0 0 1 INIT[33] INIT[33]

1 0 0 0 1 0 INIT[34] INIT[34]

1 0 0 0 1 1 INIT[35] INIT[35]

1 0 0 1 0 0 INIT[36] INIT[36]

1 0 0 1 0 1 INIT[37] INIT[37]

1 0 0 1 1 0 INIT[38] INIT[38]

1 0 0 1 1 1 INIT[39] INIT[39]

1 0 1 0 0 0 INIT[40] INIT[40]

1 0 1 0 0 1 INIT[41] INIT[41]

1 0 1 0 1 0 INIT[42] INIT[42]

1 0 1 0 1 1 INIT[43] INIT[43]

1 0 1 1 0 0 INIT[44] INIT[44]

1 0 1 1 0 1 INIT[45] INIT[45]

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Inputs Outputs

I5 I4 I3 I2 I1 I0 O LO

1 0 1 1 1 0 INIT[46] INIT[46]

1 0 1 1 1 1 INIT[47] INIT[47]

1 1 0 0 0 0 INIT[48] INIT[48]

1 1 0 0 0 1 INIT[49] INIT[49]

1 1 0 0 1 0 INIT[50] INIT[50]

1 1 0 0 1 1 INIT[51] INIT[51]

1 1 0 1 0 0 INIT[52] INIT[52]

1 1 0 1 0 1 INIT[53] INIT[53]

1 1 0 1 1 0 INIT[54] INIT[54]

1 1 0 1 1 1 INIT[55] INIT[55]

1 1 1 0 0 0 INIT[56] INIT[56]

1 1 1 0 0 1 INIT[57] INIT[57]

1 1 1 0 1 0 INIT[58] INIT[58]

1 1 1 0 1 1 INIT[59] INIT[59]

1 1 1 1 0 0 INIT[60] INIT[60]

1 1 1 1 0 1 INIT[61] INIT[61]

1 1 1 1 1 0 INIT[62] INIT[62]

1 1 1 1 1 1 INIT[63] INIT[63]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Port DescriptionName Direction Width Function

O6 Output 1 6/5-LUT output

O5 Output 1 5-LUT output

I0, I1, I2, I3, I4, I5 Input 1 LUT inputs

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 64-Bit Value All zeros Specifies the logic value for the look-uptables.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

LUT6_LPrimitive: 6-Input Lookup Table with Local Output

IntroductionThis design element is a 6-input, 1-output look-up table (LUT) that can either act as an asynchronous 64-bit ROM(with 6-bit addressing) or implement any 6-input logic function. LUTs are the basic logic building blocks and areused to implement most logic functions of the design. A LUT6 is mapped to one of the four look-up tables inthe slice. The functionality of the LUT6, LUT6_L and LUT6_D is the same. However, the LUT6_L and LUT6_Dallow the additional specification to connect the LUT6 output signal to an internal slice, or CLB connection, usingthe LO output. The LUT6_L specifies that the only connections from the LUT6 are within a slice, or CLB, whilethe LUT6_D allows the specification to connect the output of the LUT to both inter-slice/CLB logic and externallogic as well. The LUT6 does not state any specific output connections and should be used in all cases exceptwhere internal slice or CLB signal connections must be implicitly specified.

An INIT attribute consisting of a 64-bit hexadecimal value must be specified to indicate the LUT’s logicalfunction. The INIT value is calculated by assigning a 1 to the corresponding INIT bit value when the associatedinputs are applied. For instance, a Verilog INIT value of 64’h8000000000000000 (X"8000000000000000" forVHDL) will make the output zero unless all of the inputs are one (a 6-input AND gate). A Verilog INIT valueof 64’hfffffffffffffffe (X"FFFFFFFFFFFFFFFE" for VHDL) will make the output one unless all zeros are on theinputs (a 6-input OR gate).

The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:

The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.

The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting that the abovemethod. However, this method does require the code to first specify the appropriate parameters.

Logic TableInputs Outputs

I5 I4 I3 I2 I1 I0 LO

0 0 0 0 0 0 INIT[0]

0 0 0 0 0 1 INIT[1]

0 0 0 0 1 0 INIT[2]

0 0 0 0 1 1 INIT[3]

0 0 0 1 0 0 INIT[4]

0 0 0 1 0 1 INIT[5]

0 0 0 1 1 0 INIT[6]

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Chapter 3: About Design Elements

Inputs Outputs

I5 I4 I3 I2 I1 I0 LO

0 0 0 1 1 1 INIT[7]

0 0 1 0 0 0 INIT[8]

0 0 1 0 0 1 INIT[9]

0 0 1 0 1 0 INIT[10]

0 0 1 0 1 1 INIT[11]

0 0 1 1 0 0 INIT[12]

0 0 1 1 0 1 INIT[13]

0 0 1 1 1 0 INIT[14]

0 0 1 1 1 1 INIT[15]

0 1 0 0 0 0 INIT[16]

0 1 0 0 0 1 INIT[17]

0 1 0 0 1 0 INIT[18]

0 1 0 0 1 1 INIT[19]

0 1 0 1 0 0 INIT[20]

0 1 0 1 0 1 INIT[21]

0 1 0 1 1 0 INIT[22]

0 1 0 1 1 1 INIT[23]

0 1 1 0 0 0 INIT[24]

0 1 1 0 0 1 INIT[25]

0 1 1 0 1 0 INIT[26]

0 1 1 0 1 1 INIT[27]

0 1 1 1 0 0 INIT[28]

0 1 1 1 0 1 INIT[29]

0 1 1 1 1 0 INIT[30]

0 1 1 1 1 1 INIT[31]

1 0 0 0 0 0 INIT[32]

1 0 0 0 0 1 INIT[33]

1 0 0 0 1 0 INIT[34]

1 0 0 0 1 1 INIT[35]

1 0 0 1 0 0 INIT[36]

1 0 0 1 0 1 INIT[37]

1 0 0 1 1 0 INIT[38]

1 0 0 1 1 1 INIT[39]

1 0 1 0 0 0 INIT[40]

1 0 1 0 0 1 INIT[41]

1 0 1 0 1 0 INIT[42]

1 0 1 0 1 1 INIT[43]

1 0 1 1 0 0 INIT[44]

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Chapter 3: About Design Elements

Inputs Outputs

I5 I4 I3 I2 I1 I0 LO

1 0 1 1 0 1 INIT[45]

1 0 1 1 1 0 INIT[46]

1 0 1 1 1 1 INIT[47]

1 1 0 0 0 0 INIT[48]

1 1 0 0 0 1 INIT[49]

1 1 0 0 1 0 INIT[50]

1 1 0 0 1 1 INIT[51]

1 1 0 1 0 0 INIT[52]

1 1 0 1 0 1 INIT[53]

1 1 0 1 1 0 INIT[54]

1 1 0 1 1 1 INIT[55]

1 1 1 0 0 0 INIT[56]

1 1 1 0 0 1 INIT[57]

1 1 1 0 1 0 INIT[58]

1 1 1 0 1 1 INIT[59]

1 1 1 1 0 0 INIT[60]

1 1 1 1 0 1 INIT[61]

1 1 1 1 1 0 INIT[62]

1 1 1 1 1 1 INIT[63]

INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Port DescriptionName Direction Width Function

LO Output 1 6/5-LUT output or internal CLB connection

I0, I1, I2, I3, I4, I5 Input 1 LUT inputs

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 64-Bit Value All zeros Specifies the logic value for thelook-up tables.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

M16_1EMacro: 16-to-1 Multiplexer with Enable

IntroductionThis design element is a 16-to-1 multiplexer with enable. When the enable input (E) is High, the M16_1Emultiplexer chooses one data bit from 16 sources (D15 : D0) under the control of the select inputs (S3 : S0). Theoutput (O) reflects the state of the selected input as shown in the logic table. When (E) is Low, the output is Low.

Logic TableInputs Outputs

E S3 S2 S1 S0 D15-D0 O

0 X X X X X 0

1 0 0 0 0 D0 D0

1 0 0 0 1 D1 D1

1 0 0 1 0 D2 D2

1 0 0 1 1 D3 D3...

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.

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.

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.

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.

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.

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.

1 1 1 0 0 D12 D12

1 1 1 0 1 D13 D13

1 1 1 1 0 D14 D14

1 1 1 1 1 D15 D15

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Chapter 3: About Design Elements

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

M2_1Macro: 2-to-1 Multiplexer

IntroductionThis design element chooses one data bit from two sources (D1 or D0) under the control of the select input (S0).The output (O) reflects the state of the selected data input. When Low, S0 selects D0 and when High, S0 selects D1.

Logic TableInputs Outputs

S0 D1 D0 O

1 D1 X D1

0 X D0 D0

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

M2_1B1Macro: 2-to-1 Multiplexer with D0 Inverted

IntroductionThis design element chooses one data bit from two sources (D1 or D0) under the control of select input (S0).When S0 is Low, the output (O) reflects the inverted value of (D0). When S0 is High, (O) reflects the state of D1.

Logic TableInputs Outputs

S0 D1 D0 O

1 1 X 1

1 0 X 0

0 X 1 0

0 X 0 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

M2_1B2Macro: 2-to-1 Multiplexer with D0 and D1 Inverted

IntroductionThis design element chooses one data bit from two sources (D1 or D0) under the control of select input (S0). WhenS0 is Low, the output (O) reflects the inverted value of D0. When S0 is High, O reflects the inverted value of D1.

Logic TableInputs Outputs

S0 D1 D0 O

1 1 X 0

1 0 X 1

0 X 1 0

0 X 0 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

M2_1EMacro: 2-to-1 Multiplexer with Enable

IntroductionThis design element is a 2-to-1 multiplexer with enable. When the enable input (E) is High, the M2_1E choosesone data bit from two sources (D1 or D0) under the control of select input (S0). When Low, S0 selects D0 andwhen High, S0 selects D1. When (E) is Low, the output is Low.

Logic TableInputs Outputs

E S0 D1 D0 O

0 X X X 0

1 0 X 1 1

1 0 X 0 0

1 1 1 X 1

1 1 0 X 0

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

M4_1EMacro: 4-to-1 Multiplexer with Enable

IntroductionThis design element is a 4-to-1 multiplexer with enable. When the enable input (E) is High, the M4_1Emultiplexerchooses one data bit from four sources (D3, D2, D1, or D0) under the control of the select inputs (S1 : S0). Theoutput (O) reflects the state of the selected input as shown in the logic table. When (E) is Low, the output is Low.

Logic TableInputs Outputs

E S1 S0 D0 D1 D2 D3 O

0 X X X X X X 0

1 0 0 D0 X X X D0

1 0 1 X D1 X X D1

1 1 0 X X D2 X D2

1 1 1 X X X D3 D3

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

M8_1EMacro: 8-to-1 Multiplexer with Enable

IntroductionThis design element is an 8-to-1 multiplexer with enable. When the enable input (E) is High, the M8_1Emultiplexer chooses one data bit from eight sources (D7 : D0) under the control of the select inputs (S2 : S0). Theoutput (O) reflects the state of the selected input as shown in the logic table. When (E) is Low, the output is Low.

Logic TableInputs Outputs

E S2 S1 S0 D7-D0 O

0 X X X X 0

1 0 0 0 D0 D0

1 0 0 1 D1 D1

1 0 1 0 D2 D2

1 0 1 1 D3 D3

1 1 0 0 D4 D4

1 1 0 1 D5 D5

1 1 1 0 D6 D6

1 1 1 1 D7 D7

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MULT_ANDPrimitive: Fast Multiplier AND

IntroductionThe design element is an AND component located within the slice where the two inputs are shared with the4-input LUT and the output drives into the carry logic. This added logic is especially useful for building fastand smaller multipliers. However, it can be used for other purposes as well. The I1 and I0 inputs must beconnected to the I1 and I0 inputs of the associated LUT. The LO output must be connected to the DI input ofthe associated MUXCY, MUXCY_D, or MUXCY_L.

Logic TableInputs Outputs

I1 I0 LO

0 0 0

0 1 0

1 0 0

1 1 1

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MULT18X18SIOPrimitive: 18 x 18 Cascadable Signed Multiplier with Optional Input and Output Registers, ClockEnable, and Synchronous Reset

IntroductionThis design element is a 36-bit output, 18x18-bit input dedicated signed multiplier. This component can performasynchronous multiplication operations when the attributes AREG, BREG and PREG are all set to 0. Alternatively,synchronous multiplication operations of different latency and performance characteristics can be performedwhen any combination of those attributes is set to 1. When using the multiplier in synchronous operation, theMULT18X18SIO features active high clock enables for each set of register banks in the multiplier, CEA, CEB andCEP, as well as synchronous resets, RSTA, RSTB, and RSTP. Multiple MULT18X18SIOs can be cascaded to createlarger multiplication functions using the BCIN and BCOUT ports in combination with the B_INPUT attribute.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Descriptions

AREG Integer 0, 1 1 Specifies the use of the input registers on the Aport. A zero disables the use of the register; a oneenables the register.

BREG Integer 0, 1 1 Specifies the use of the input registers on the Bport. A zero disables the use of the register; a oneenables the register.

B_INPUT String "DIRECT" or "CASCADE" "DIRECT" Specifies whether the B port is connected to thegeneral FPGA fabric, “DIRECT” or is connectedto the BCOUT port of another MULT18X18SIO.

PREG Integer 0, 1 1 Specifies the use of the output registers of themultiplier. A zero disables the use of the register;a one enables the register.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MUXCYPrimitive: 2-to-1 Multiplexer for Carry Logic with General Output

IntroductionThe direct input (DI) of a slice is connected to the (DI) input of the MUXCY. The carry in (CI) input of an LCis connected to the CI input of the MUXCY. The select input (S) of the MUXCY is driven by the output of thelook-up table (LUT) and configured as a MUX function. The carry out (O) of the MUXCY reflects the state of theselected input and implements the carry out function of each LC. When Low, S selects DI; when High, S selects CI.

The variants “MUXCY_D” and “MUXCY_L” provide additional types of outputs that can be used by differenttiming models for more accurate pre-layout timing estimation.

Logic TableInputs Outputs

S DI CI O

0 1 X 1

0 0 X 0

1 X 1 1

1 X 0 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MUXCY_DPrimitive: 2-to-1 Multiplexer for Carry Logic with Dual Output

IntroductionThis design element implements a 1-bit, high-speed carry propagate function. One such function can beimplemented per logic cell (LC), for a total of 4-bits per configurable logic block (CLB). The direct input (DI) ofan LC is connected to the DI input of the MUXCY_D. The carry in (CI) input of an LC is connected to the CIinput of the MUXCY_D. The select input (S) of the MUX is driven by the output of the look-up table (LUT) andconfigured as an XOR function. The carry out (O and LO) of the MUXCY_D reflects the state of the selected inputand implements the carry out function of each LC. When Low, S selects DI; when High, S selects CI.

Outputs O and LO are functionally identical. The O output is a general interconnect. See also “MUXCY”and “MUXCY_L”.

Logic TableInputs Outputs

S DI CI O LO

0 1 X 1 1

0 0 X 0 0

1 X 1 1 1

1 X 0 0 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MUXCY_LPrimitive: 2-to-1 Multiplexer for Carry Logic with Local Output

IntroductionThis design element implements a 1-bit high-speed carry propagate function. One such function is implementedper logic cell (LC), for a total of 4-bits per configurable logic block (CLB). The direct input (DI) of an LC isconnected to the DI input of the MUXCY_L. The carry in (CI) input of an LC is connected to the CI input ofthe MUXCY_L. The select input (S) of the MUXCY_L is driven by the output of the look-up table (LUT) andconfigured as an XOR function. The carry out (LO) of the MUXCY_L reflects the state of the selected input andimplements the carry out function of each (LC). When Low, (S) selects DI; when High, (S) selects (CI).

See also “MUXCY” and “MUXCY_D.”

Logic TableInputs Outputs

S DI CI LO

0 1 X 1

0 0 X 0

1 X 1 1

1 X 0 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MUXF5Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

IntroductionThis design element provides a multiplexer function in a CLB slice for creating a function-of-5 look-up table ora 4-to-1 multiplexer in combination with the associated look-up tables. The local outputs (LO) from the twolook-up tables are connected to the I0 and I1 inputs of the MUXF5. The S input is driven from any internalnet. When Low, S selects I0. When High, S selects I1.

The variants, “MUXF5_D” and “MUXF5_L”, provide additional types of outputs that can be used by differenttiming models for more accurate pre-layout timing estimation.

Logic TableInputs Outputs

S I0 I1 O

0 1 X 1

0 0 X 0

1 X 1 1

1 X 0 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MUXF5_DPrimitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

IntroductionThis design element provides a multiplexer function in a CLB slice for creating a function-of-5 look-up table ora 4-to-1 multiplexer in combination with the associated look-up tables. The local outputs (LO) from the twolook-up tables are connected to the I0 and I1 inputs of the MUXF5. The S input is driven from any internalnet. When Low, S selects I0. When High, S selects I1.

Outputs O and LO are functionally identical. The O output is a general interconnect. The LO output connects toother inputs in the same CLB slice. See also “MUXF5” and “MUXF5_L”.

Logic TableInputs Outputs

S I0 I1 O LO

0 1 X 1 1

0 0 X 0 0

1 X 1 1 1

1 X 0 0 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MUXF5_LPrimitive: 2-to-1 Look-Up Table Multiplexer with Local Output

IntroductionThis design element provides a multiplexer function in a CLB slice for creating a function-of-5 look-up table ora 4-to-1 multiplexer in combination with the associated look-up tables. The local outputs (LO) from the twolook-up tables are connected to the I0 and I1 inputs of the MUXF5. The S input is driven from any internalnet. When Low, S selects I0. When High, S selects I1.

The LO output connects to other inputs in the same CLB slice.

See also “MUXF5” and “MUXF5_D”.

Logic TableInputs Output

S I0 I1 LO

0 1 X 1

0 0 X 0

1 X 1 1

1 X 0 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MUXF6Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

IntroductionThis design element provides a multiplexer function in two slices for creating a function-of-6 look-up table or an8-to-1 multiplexer in combination with the associated four look-up tables and two MUXF5s. The local outputs(LO) from the two MUXF5s in the CLB are connected to the I0 and I1 inputs of the MUXF6. The S input is drivenfrom any internal net. When Low, S selects I0. When High, S selects I1.

The variants, “MUXF6_D” and “MUXF6_L”, provide additional types of outputs that can be used by differenttiming models for more accurate pre-layout timing estimation.

Logic TableInputs Outputs

S I0 I1 O

0 1 X 1

0 0 X 0

1 X 1 1

1 X 0 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MUXF6_DPrimitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

IntroductionThis design element provides a multiplexer function in a two slices for creating a function-of-6 look-up table oran 8-to-1 multiplexer in combination with the associated four look-up tables and two MUXF5s. The local outputs(LO) from the two MUXF5s in the CLB are connected to the I0 and I1 inputs of the MUXF6. The S input is drivenfrom any internal net. When Low, S selects I0. When High, S selects I1.

Outputs O and LO are functionally identical. The O output is a general interconnect. The LO output connects toother inputs in the same CLB slice.

Logic TableInputs Outputs

S I0 I1 O LO

0 1 X 1 1

0 0 X 0 0

1 X 1 1 1

1 X 0 0 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MUXF6_LPrimitive: 2-to-1 Look-Up Table Multiplexer with Local Output

IntroductionThis design element provides a multiplexer function for use in creating a function-of-6 look-up table or an 8-to-1multiplexer in combination with the associated four look-up tables and two MUXF5s. The local outputs (LO)from the two MUXF5s in the CLB are connected to the I0 and I1 inputs of the MUXF6. The S input is drivenfrom any internal net. When Low, S selects I0. When High, S selects I1.

The LO output connects to other inputs in the same CLB slice.

Logic TableInputs Output

S I0 I1 LO

0 1 X 1

0 0 X 0

1 X 1 1

1 X 0 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

MUXF7Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

IntroductionThis design element provides a multiplexer function for use in creating a function-of-7 look-up table or an 8-to-1multiplexer in combination with the associated look-up tables. Local outputs (LO) of MUXF6 are connectedto the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0.When High, S selects I1.

The variants, “MUXF7_D” and “MUXF7_L”, provide additional types of outputs that can be used by differenttiming models for more accurate pre-layout timing estimation.

Logic TableInputs Outputs

S I0 I1 O

0 I0 X I0

1 X I1 I1

X 0 0 0

X 1 1 1

Port DescriptionsPort Direction Width Function

O Output 1 Output of MUX to general routing

I0 Input 1 Input (tie to MUXF6 LO out)

I1 Input 1 Input (tie to MUXF6 LO out)

S Input 1 Input select to MUX

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

MUXF7_DPrimitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

IntroductionThis design element provides a multiplexer function for use in creating a function-of-7 look-up table or a 16-to-1multiplexer in combination with the associated look-up tables. Local outputs (LO) of MUXF6 are connectedto the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0.When High, S selects I1.

Outputs O and LO are functionally identical. The O output is a general interconnect. The LO output connects toother inputs in the same CLB slice.

Logic TableInputs Outputs

S I0 I1 O LO

0 I0 X I0 I0

1 X I1 I1 I1

X 0 0 0 0

X 1 1 1 1

Port DescriptionsPort Direction Width Function

O Output 1 Output of MUX to general routing

LO Output 1 Output of MUX to local routing

I0 Input 1 Input (tie to MUXF6 LO out)

I1 Input 1 Input (tie to MUXF6 LO out)

S Input 1 Input select to MUX

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

MUXF7_LPrimitive: 2-to-1 look-up table Multiplexer with Local Output

IntroductionThis design element provides a multiplexer function for use in creating a function-of-7 look-up table or a 16-to-1multiplexer in combination with the associated look-up tables. Local outputs (LO) of MUXF6 are connectedto the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0.When High, S selects I1.

The LO output connects to other inputs in the same CLB slice.

Logic TableInputs Output

S I0 I1 LO

0 I0 X I0

1 X I1 I1

X 0 0 0

X 1 1 1

Port DescriptionsPort Direction Width Function

LO Output 1 Output of MUX to local routing

I0 Input 1 Input

I1 Input 1 Input

S Input 1 Input select to MUX

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

MUXF8Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

IntroductionThis design element provides a multiplexer function in eight slices for creating a function-of-8 look-up table or a16-to-1 multiplexer in combination with the associated look-up tables, MUXF5s, MUXF6s, and MUXF7s. Localoutputs (LO) of MUXF7 are connected to the I0 and I1 inputs of the MUXF8. The S input is driven from anyinternal net. When Low, S selects I0. When High, S selects I1.

Logic TableInputs Outputs

S I0 I1 O

0 I0 X I0

1 X I1 I1

X 0 0 0

X 1 1 1

Port DescriptionsPort Direction Width Function

O Output 1 Output of MUX to general routing

I0 Input 1 Input (tie to MUXF7 LO out)

I1 Input 1 Input (tie to MUXF7 LO out)

S Input 1 Input select to MUX

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

MUXF8_DPrimitive: 2-to-1 Look-Up Table Multiplexer with Dual Output

IntroductionThis design element provides a multiplexer function in eight slices for creating a function-of-8 look-up table or a32-to-1 multiplexer in combination with the associated four look-up tables and two MUXF8s. Local outputs(LO) of MUXF7 are connected to the I0 and I1 inputs of the MUXF8. The S input is driven from any internalnet. When Low, S selects I0. When High, S selects I1.

Outputs O and LO are functionally identical. The O output is a general interconnect. The LO output connects toother inputs in the same CLB slice.

Logic TableInputs Outputs

S I0 I1 O LO

0 I0 X I0 I0

1 X I1 I1 I1

X 0 0 0 0

X 1 1 1 1

Port DescriptionsPort Direction Width Function

O Output 1 Output of MUX to general routing

LO Output 1 Output of MUX to local routing

I0 Input 1 Input (tie to MUXF7 LO out)

I1 Input 1 Input (tie to MUXF7 LO out)

S Input 1 Input select to MUX

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

MUXF8_LPrimitive: 2-to-1 Look-Up Table Multiplexer with Local Output

IntroductionThis design element provides a multiplexer function in eight slices for creating a function-of-8 look-up table or a32-to-1 multiplexer in combination with the associated four look-up tables and two MUXF8s. Local outputs(LO) of MUXF7 are connected to the I0 and I1 inputs of the MUXF8. The S input is driven from any internalnet. When Low, S selects I0. When High, S selects I1.

The LO output connects to other inputs in the same CLB slice.

Logic TableInputs Output

S I0 I1 LO

0 I0 X I0

1 X I1 I1

X 0 0 0

X 1 1 1

Port DescriptionsPort Direction Width Function

LO Output 1 Output of MUX to local routing

I0 Input 1 Input (tie to MUXF7 LO out)

I1 Input 1 Input (tie to MUXF7 LO out)

S Input 1 Input select to MUX

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

NAND12Macro: 12- Input NAND Gate with Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND16Macro: 16- Input NAND Gate with Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND2Primitive: 2-Input NAND Gate with Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND2B1Primitive: 2-Input NAND Gate with 1 Inverted and 1 Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND2B2Primitive: 2-Input NAND Gate with Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND3Primitive: 3-Input NAND Gate with Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND3B1Primitive: 3-Input NAND Gate with 1 Inverted and 2 Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND3B2Primitive: 3-Input NAND Gate with 2 Inverted and 1 Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND3B3Primitive: 3-Input NAND Gate with Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND4Primitive: 4-Input NAND Gate with Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND4B1Primitive: 4-Input NAND Gate with 1 Inverted and 3 Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND4B2Primitive: 4-Input NAND Gate with 2 Inverted and 2 Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND4B3Primitive: 4-Input NAND Gate with 3 Inverted and 1 Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND4B4Primitive: 4-Input NAND Gate with Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

NAND5Primitive: 5-Input NAND Gate with Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 419

Chapter 3: About Design Elements

NAND5B1Primitive: 5-Input NAND Gate with 1 Inverted and 4 Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs420 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NAND5B2Primitive: 5-Input NAND Gate with 2 Inverted and 3 Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 421

Chapter 3: About Design Elements

NAND5B3Primitive: 5-Input NAND Gate with 3 Inverted and 2 Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs422 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NAND5B4Primitive: 5-Input NAND Gate with 4 Inverted and 1 Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 423

Chapter 3: About Design Elements

NAND5B5Primitive: 5-Input NAND Gate with Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs424 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NAND6Macro: 6-Input NAND Gate with Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 425

Chapter 3: About Design Elements

NAND7Macro: 7-Input NAND Gate with Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs426 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NAND8Macro: 8-Input NAND Gate with Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 427

Chapter 3: About Design Elements

NAND9Macro: 9-Input NAND Gate with Non-Inverted Inputs

IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs428 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR12Macro: 12-Input NOR Gate with Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 429

Chapter 3: About Design Elements

NOR16Macro: 16-Input NOR Gate with Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs430 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR2Primitive: 2-Input NOR Gate with Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 431

Chapter 3: About Design Elements

NOR2B1Primitive: 2-Input NOR Gate with 1 Inverted and 1 Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs432 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR2B2Primitive: 2-Input NOR Gate with Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 433

Chapter 3: About Design Elements

NOR3Primitive: 3-Input NOR Gate with Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs434 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR3B1Primitive: 3-Input NOR Gate with 1 Inverted and 2 Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 435

Chapter 3: About Design Elements

NOR3B2Primitive: 3-Input NOR Gate with 2 Inverted and 1 Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs436 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR3B3Primitive: 3-Input NOR Gate with Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 437

Chapter 3: About Design Elements

NOR4Primitive: 4-Input NOR Gate with Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs438 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR4B1Primitive: 4-Input NOR Gate with 1 Inverted and 3 Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 439

Chapter 3: About Design Elements

NOR4B2Primitive: 4-Input NOR Gate with 2 Inverted and 2 Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs440 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR4B3Primitive: 4-Input NOR Gate with 3 Inverted and 1 Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 441

Chapter 3: About Design Elements

NOR4B4Primitive: 4-Input NOR Gate with Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs442 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR5Primitive: 5-Input NOR Gate with Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 443

Chapter 3: About Design Elements

NOR5B1Primitive: 5-Input NOR Gate with 1 Inverted and 4 Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs444 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR5B2Primitive: 5-Input NOR Gate with 2 Inverted and 3 Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 445

Chapter 3: About Design Elements

NOR5B3Primitive: 5-Input NOR Gate with 3 Inverted and 2 Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs446 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR5B4Primitive: 5-Input NOR Gate with 4 Inverted and 1 Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 447

Chapter 3: About Design Elements

NOR5B5Primitive: 5-Input NOR Gate with Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs448 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR6Macro: 6-Input NOR Gate with Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 449

Chapter 3: About Design Elements

NOR7Macro: 7-Input NOR Gate with Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs450 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

NOR8Macro: 8-Input NOR Gate with Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 451

Chapter 3: About Design Elements

NOR9Macro: 9-Input NOR Gate with Non-Inverted Inputs

IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs452 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

OBUFPrimitive: Output Buffer

IntroductionThis design element is a simple output buffer used to drive output signals to the FPGA device pins that do notneed to be 3-stated (constantly driven). Either an OBUF, OBUFT, OBUFDS, or OBUFTDS must be connected toevery output port in the design.

This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists ininput/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard usedby this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.

Port DescriptionsPort Direction Width Function

O Output 1 Output of OBUF to be connected directly to top-level outputport.

I Input 1 Input of OBUF. Connect to the logic driving the output port.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 453

Chapter 3: About Design Elements

OBUF16Macro: 16-Bit Output Buffer

IntroductionThis design element is a multiple output buffer.

This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists ininput/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard usedby this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs454 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

OBUF4Macro: 4-Bit Output Buffer

IntroductionThis design element is a multiple output buffer.

This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists ininput/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard usedby this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 455

Chapter 3: About Design Elements

OBUF8Macro: 8-Bit Output Buffer

IntroductionThis design element is a multiple output buffer.

This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists ininput/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard usedby this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic Designs456 www.xilinx.com UG616 (v 11.4) December 2, 2009

Chapter 3: About Design Elements

OBUFDSPrimitive: Differential Signaling Output Buffer

IntroductionThis design element is a single output buffer that supports low-voltage, differential signaling (1.8 v CMOS).OBUFDS isolates the internal circuit and provides drive current for signals leaving the chip. Its output isrepresented as two distinct ports (O and OB), one deemed the "master" and the other the "slave." The master andthe slave are opposite phases of the same logical signal (for example, MYNET and MYNETB).

Logic TableInputs Outputs

I O OB

0 0 1

1 1 0

Port DescriptionsPort Direction Width Function

O Output 1 Diff_p output (connect directly to top level port)

OB Output 1 Diff_n output (connect directly to top level port)

I Input 1 Buffer input

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 457

Chapter 3: About Design Elements

OBUFTPrimitive: 3-State Output Buffer with Active Low Output Enable

IntroductionThis design element is a single, 3-state output buffer with input I, output O, and active-Low output enables (T).This element uses the LVTTL standard and has selectable drive and slew rates using the DRIVE and SLOW orFAST constraints. The defaults are DRIVE=12 mA and SLOW slew.

When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, theoutput is high impedance (off or Z state). OBUFTs are generally used when a single-ended output is neededwith a 3-state capability, such as the case when building bidirectional I/O.

Logic TableInputs Outputs

T I O

1 X Z

0 I F

Port DescriptionsPort Direction Width Function

O Output 1 Buffer output (connect directly to top-level port)

I Input 1 Buffer input

T Input 1 3-state enable input

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

OBUFT16Macro: 16-Bit 3-State Output Buffer with Active Low Output Enable

IntroductionThis design element is a multiple, 3-state output buffer with input I, output O, and active-Low output enables(T). This element uses the LVTTL standard and has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.

When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, theoutput is high impedance (off or Z state). OBUFTs are generally used when a single-ended output is neededwith a 3-state capability, such as the case when building bidirectional I/O.

Logic TableInputs Outputs

T I O

1 X Z

0 I F

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OBUFT4Macro: 4-Bit 3-State Output Buffers with Active-Low Output Enable

IntroductionThis design element is a multiple, 3-state output buffer with input I, output O, and active-Low output enables(T). This element uses the LVTTL standard and has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.

When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, theoutput is high impedance (off or Z state). OBUFTs are generally used when a single-ended output is neededwith a 3-state capability, such as the case when building bidirectional I/O.

Logic TableInputs Outputs

T I O

1 X Z

0 I F

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OBUFT8Macro: 8-Bit 3-State Output Buffers with Active-Low Output Enable

IntroductionThis design element is a multiple, 3-state output buffer with input I, output O, and active-Low output enables(T). This element uses the LVTTL standard and has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.

When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, theoutput is high impedance (off or Z state). OBUFTs are generally used when a single-ended output is neededwith a 3-state capability, such as the case when building bidirectional I/O.

Logic TableInputs Outputs

T I O

1 X Z

0 I F

Design Entry MethodThis design element is only for use in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OBUFTDSPrimitive: 3-State Output Buffer with Differential Signaling, Active-Low Output Enable

IntroductionThis design element is an output buffer that supports low-voltage, differential signaling. For the OBUFTDS,a design level interface signal is represented as two distinct ports (O and OB), one deemed the "master" andthe other the "slave." The master and the slave are opposite phases of the same logical signal (for example,MYNET_P and MYNET_N).

Logic TableInputs Outputs

I T O OB

X 1 Z Z

0 0 0 1

1 0 1 0

Port DescriptionsPort Direction Width Function

O Output 1 Diff_p output (connect directly to top level port)

OB Output 1 Diff_n output (connect directly to top level port)

I Input 1 Buffer input

T Input 1 3-state enable input

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

ODDR2Primitive: Dual Data Rate Output D Flip-Flop with Optional Data Alignment, Clock Enable andProgrammable Synchronous or Asynchronous Set/Reset

IntroductionThe design element is an output double data rate (DDR) register useful in producing double data rate signalsexiting the FPGA. The ODDR2 requires two clocks (C0 and C1) to be connected to the component so that data isprovided at the positive edge of both clocks. The ODDR2 features an active high clock enable port, CE, whichcan be used to suspend the operation of the registers and both set and reset ports that can be configured to besynchronous or asynchronous to the respective clocks. The ODDR2 has an optional alignment feature, whichallows data to be captured by a single clock and clocked out by two clocks.

Logic TableInputs Outputs

S R CE D0 D1 C0 C1 O

1 X X X X X X 1

0 1 X X X X X not INIT

0 0 0 X X X X No Change

0 0 1 D0 X ↑ X D0

0 0 1 X D1 X ↑ D1

Set/Reset can be synchronous via SRTYPE value

Design Entry MethodThis design element can be used in schematics.

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Chapter 3: About Design Elements

Available AttributesAttribute Type Allowed Values Default Descriptions

DDR_ALIGNMENT String "NONE", "C0","C1”

"NONE” Sets the input capture behavior for the DDRregister. "NONE" clocks in data to the D0input on the positive transition of the C0 clockand D1 on the positive transition of the C1clock. "C0" allows the input clocking of bothD0 and D1 align to the positive edge of theC0 clock. "C1" allows the input clocking ofboth D0 and D1 align to the positive edge ofthe C1 clock.

INIT Integer 0, 1 0 Sets initial state of the Q0 output to 0 or 1.

SRTYPE String "SYNC","ASYNC”

"SYNC” Specifies "SYNC" or "ASYNC" set/reset.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

OFDMacro: Output D Flip-Flop

IntroductionThis design element is a single output D flip-flop.

The outputs are connected to OPADs or IOPADs. The data on the (D) inputs is loaded into the flip-flops duringthe Low-to-High clock (C) transition and appears on the (Q) outputs.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFD_1Macro: Output D Flip-Flop with Inverted Clock

IntroductionThe design element is located in an input/output block (IOB). The output (Q) of the D flip-flop is connected to anOPAD or an IOPAD. The data on the (D) input is loaded into the flip-flop during the High-to-Low clock (C)transition and appears on the (Q) output.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↓ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFD16Macro: 16-Bit Output D Flip-Flop

IntroductionThis design element is a multiple output D flip-flop.

The outputs are connected to OPADs or IOPADs. The data on the (D) inputs is loaded into the flip-flops duringthe Low-to-High clock (C) transition and appears on the (Q) outputs.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFD4Macro: 4-Bit Output D Flip-Flop

IntroductionThis design element is a multiple output D flip-flop.

The outputs are connected to OPADs or IOPADs. The data on the (D) inputs is loaded into the flip-flops duringthe Low-to-High clock (C) transition and appears on the (Q) outputs.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFD8Macro: 8-Bit Output D Flip-Flop

IntroductionThis design element is a multiple output D flip-flop.

The outputs are connected to OPADs or IOPADs. The data on the (D) inputs is loaded into the flip-flops duringthe Low-to-High clock (C) transition and appears on the (Q) outputs.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDEMacro: D Flip-Flop with Active-High Enable Output Buffers

IntroductionThis is a single D flip-flop whose output is enabled by a 3-state buffer. The flip-flop data output (Q) is connectedto the input of output buffer (OBUFE). The OBUFE output (O) is connected to an OPAD or IOPAD. The data onthe data input (D) is loaded into the flip-flop during the Low-to-High clock (C) transition. When the active-Highenable input (E) is High, the data on the flip-flop output (Q) appears on the OBUFE (O) output. When (E) isLow, the output is high impedance (Z state or Off).

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Output

E D C O

0 X X Z

1 Dn ↑ Dn

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDE_1Macro: D Flip-Flop with Active-High Enable Output Buffer and Inverted Clock

IntroductionThis design element and its output buffer are located in an input/output block (IOB). The data output of theflip-flop (Q) is connected to the input of an output buffer or OBUFE. The output of the OBUFE is connected to anOPAD or an IOPAD. The data on the data input (D) is loaded into the flip-flop on the High-to-Low clock (C)transition. When the active-High enable input (E) is High, the data on the flip-flop output (Q) appears on the (O)output. When (E) is Low, the output is high impedance (Z state or Off).

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

E D C O

0 X X Z

1 D ↓ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDE16Macro: 16-Bit D Flip-Flop with Active-High Enable Output Buffers

IntroductionThis is a multiple D flip-flop whose outputs are enabled by 3-state buffers. The flip-flop data outputs (Q) areconnected to the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to OPADs or IOPADs.The data on the data inputs (D) is loaded into the flip-flops during the Low-to-High clock (C) transition. Whenthe active-High enable inputs (E) are High, the data on the flip-flop outputs (Q) appears on the OBUFE outputs(O). When (E) is Low, outputs are high impedance (Z state or Off).

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

E D C O

0 X X Z

1 Dn ↑ Dn

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDE4Macro: 4-Bit D Flip-Flop with Active-High Enable Output Buffers

IntroductionThis is a multiple D flip-flop whose outputs are enabled by 3-state buffers. The flip-flop data outputs (Q) areconnected to the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to OPADs or IOPADs.The data on the data inputs (D) is loaded into the flip-flops during the Low-to-High clock (C) transition. Whenthe active-High enable inputs (E) are High, the data on the flip-flop outputs (Q) appears on the OBUFE outputs(O). When (E) is Low, outputs are high impedance (Z state or Off).

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

E D C O

0 X X Z

1 Dn ↑ Dn

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDE8Macro: 8-Bit D Flip-Flop with Active-High Enable Output Buffers

IntroductionThis is a multiple D flip-flop whose outputs are enabled by 3-state buffers. The flip-flop data outputs (Q) areconnected to the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to OPADs or IOPADs.The data on the data inputs (D) is loaded into the flip-flops during the Low-to-High clock (C) transition. Whenthe active-High enable inputs (E) are High, the data on the flip-flop outputs (Q) appears on the OBUFE outputs(O). When (E) is Low, outputs are high impedance (Z state or Off).

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

E D C O

0 X X Z

1 Dn ↑ Dn

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDIMacro: Output D Flip-Flop (Asynchronous Preset)

IntroductionThe design element is contained in an input/output block (IOB). The output (Q) of the (D) flip-flop is connectedto an OPAD or an IOPAD. The data on the (D) input is loaded into the flip-flop during the Low-to-High clock (C)transition and appears at the output (Q).

This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDI_1Macro: Output D Flip-Flop with Inverted Clock (Asynchronous Preset)

IntroductionThis design element exists in an input/output block (IOB). The (D) flip-flop output (Q) is connected to an OPADor an IOPAD. The data on the (D) input is loaded into the flip-flop during the High-to-Low clock (C) transitionand appears on the (Q) output.

This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

D C Q

D ↓ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDTMacro: D Flip-Flop with Active-Low 3-State Output Buffer

IntroductionThis design element is a single D flip-flops whose output is enabled by a 3-state buffer.

The data outputs (Q) of the flip-flops are connected to the inputs of output buffers (OBUFT). The outputs of theOBUFTs (O) are connected to OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flopsduring the Low-to-High clock (C) transition. When the active-Low enable inputs (T) are Low, the data on theflip-flop outputs (Q) appears on the (O) outputs. When (T) is High, outputs are high impedance (Off).

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

T D C O

1 X X Z

0 D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDT_1Macro: D Flip-Flop with Active-Low 3-State Output Buffer and Inverted Clock

IntroductionThe design element and its output buffer are located in an input/output block (IOB). The flip-flop data output(Q) is connected to the input of an output buffer (OBUFT). The OBUFT output is connected to an OPAD or anIOPAD. The data on the data input (D) is loaded into the flip-flop on the High-to-Low clock (C) transition.When the active-Low enable input (T) is Low, the data on the flip-flop output (Q) appears on the (O) output.When (T) is High, the output is high impedance (Off).

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

T D C O

1 X X Z

0 D ↓ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDT16Macro: 16-Bit D Flip-Flop with Active-Low 3-State Output Buffers

IntroductionThis design element is a multiple D flip-flop whose output are enabled by 3-state buffers.

The data outputs (Q) of the flip-flops are connected to the inputs of output buffers (OBUFT). The outputs of theOBUFTs (O) are connected to OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flopsduring the Low-to-High clock (C) transition. When the active-Low enable inputs (T) are Low, the data on theflip-flop outputs (Q) appears on the (O) outputs. When (T) is High, outputs are high impedance (Off).

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

T D C O

1 X X Z

0 D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDT4Macro: 4-Bit D Flip-Flop with Active-Low 3-State Output Buffers

IntroductionThis design element is a multiple D flip-flop whose output are enabled by 3-state buffers.

The data outputs (Q) of the flip-flops are connected to the inputs of output buffers (OBUFT). The outputs of theOBUFTs (O) are connected to OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flopsduring the Low-to-High clock (C) transition. When the active-Low enable inputs (T) are Low, the data on theflip-flop outputs (Q) appears on the (O) outputs. When (T) is High, outputs are high impedance (Off).

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

T D C O

1 X X Z

0 D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDT8Macro: 8-Bit D Flip-Flop with Active-Low 3-State Output Buffers

IntroductionThis design element is a multiple D flip-flop whose output are enabled by 3-state buffers.

The data outputs (Q) of the flip-flops are connected to the inputs of output buffers (OBUFT). The outputs of theOBUFTs (O) are connected to OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flopsduring the Low-to-High clock (C) transition. When the active-Low enable inputs (T) are Low, the data on theflip-flop outputs (Q) appears on the (O) outputs. When (T) is High, outputs are high impedance (Off).

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

T D C O

1 X X Z

0 D ↑ D

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDXMacro: Output D Flip-Flop with Clock Enable

IntroductionThis design element is a single output D flip-flop. The (Q) output is connected to OPAD or IOPAD. The data onthe (D) input is loaded into the flip-flop during the Low-to-High clock (C) transition and appears on the (Q)output. When (CE) is Low, the flip-flop output does not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 Dn ↑ Dn

0 X X No change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDX_1Macro: Output D Flip-Flop with Inverted Clock and Clock Enable

IntroductionThe design element is located in an input/output block (IOB). The output (Q) of the (D) flip-flop is connected toan OPAD or an IOPAD. The data on the (D) input is loaded into the flip-flop during the High-to-Low clock (C)transition and appears on the (Q) output. When the (CE) pin is Low, the output (Q) does not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 D ↓ D

0 X X No Change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDX16Macro: 16-Bit Output D Flip-Flop with Clock Enable

IntroductionThis design element is a multiple output D flip-flop. The (Q) output is connected to OPAD or IOPAD. The dataon the (D) input is loaded into the flip-flop during the Low-to-High clock (C) transition and appears on the (Q)output. When (CE) is Low, the flip-flop output does not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 Dn ↑ Dn

0 X X No change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDX4Macro: 4-Bit Output D Flip-Flop with Clock Enable

IntroductionThis design element is a multiple output D flip-flop. The (Q) output is connected to OPAD or IOPAD. The dataon the (D) input is loaded into the flip-flop during the Low-to-High clock (C) transition and appears on the (Q)output. When (CE) is Low, the flip-flop output does not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 Dn ↑ Dn

0 X X No change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDX8Macro: 8-Bit Output D Flip-Flop with Clock Enable

IntroductionThis design element is a multiple output D flip-flop. The (Q) output is connected to OPAD or IOPAD. The dataon the (D) input is loaded into the flip-flop during the Low-to-High clock (C) transition and appears on the (Q)output. When (CE) is Low, the flip-flop output does not change.

This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 Dn ↑ Dn

0 X X No change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDXIMacro: Output D Flip-Flop with Clock Enable (Asynchronous Preset)

IntroductionThe design element is contained in an input/output block (IOB). The output (Q) of the D flip-flop is connected toan OPAD or an IOPAD. The data on the (D) input is loaded into the flip-flop during the Low-to-High clock (C)transition and appears at the output (Q). When( CE) is Low, the output does not change

This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 D ↑ D

0 X X No Change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OFDXI_1Macro: Output D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)

IntroductionThe design element is located in an input/output block (IOB). The D flip-flop output (Q) is connected to an OPADor an IOPAD. The data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition andappears on the Q output. When CE is Low, the output (Q) does not change.

This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CE D C Q

1 D ↓ D

0 X X No Change

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR12Macro: 12-Input OR Gate with Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR16Macro: 16-Input OR Gate with Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR2Primitive: 2-Input OR Gate with Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR2B1Primitive: 2-Input OR Gate with 1 Inverted and 1 Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR2B2Primitive: 2-Input OR Gate with Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR2LPrimitive: Two input OR gate implemented in place of a Slice Latch

IntroductionThis element allows the specification of a configurable Slice Latch to take the function of a two input OR gate (seeLogic Table). The use of this element can reduce logic levels and increase logic density of the part by trading offregister/latch resources for logic. Xilinx suggests caution when using this component as it can affect registerpacking and density since specifying one or more e AND2B1L or OR2L components in a Slice disallows the useof the remaining registers and latches.

Logic TableInputs Outputs

DI SRI O

0 0 0

0 1 1

1 0 1

1 1 1

Port DescriptionsPort Type Width Function

O Output 1 Output of the OR gate.

DI Input 1 Active high input that is generally connected to sourcing LUT locatedin the same Slice.

SRI Input 1 Active low input that is generally source from outside of the Slice.

Note To allow more than one AND2B1L or OR2B1L to be packed intoa single Slice, a common signal must be connected to this input.

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

OR3Primitive: 3-Input OR Gate with Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR3B1Primitive: 3-Input OR Gate with 1 Inverted and 2 Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR3B2Primitive: 3-Input OR Gate with 2 Inverted and 1 Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR3B3Primitive: 3-Input OR Gate with Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR4Primitive: 4-Input OR Gate with Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR4B1Primitive: 4-Input OR Gate with 1 Inverted and 3 Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR4B2Primitive: 4-Input OR Gate with 2 Inverted and 2 Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 501

Chapter 3: About Design Elements

OR4B3Primitive: 4-Input OR Gate with 3 Inverted and 1 Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR4B4Primitive: 4-Input OR Gate with Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 503

Chapter 3: About Design Elements

OR5Primitive: 5-Input OR Gate with Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR5B1Primitive: 5-Input OR Gate with 1 Inverted and 4 Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 505

Chapter 3: About Design Elements

OR5B2Primitive: 5-Input OR Gate with 2 Inverted and 3 Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR5B3Primitive: 5-Input OR Gate with 3 Inverted and 2 Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR5B4Primitive: 5-Input OR Gate with 4 Inverted and 1 Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR5B5Primitive: 5-Input OR Gate with Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 509

Chapter 3: About Design Elements

OR6Macro: 6-Input OR Gate with Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR7Macro: 7-Input OR Gate with Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR8Macro: 8-Input OR Gate with Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OR9Macro: 9-Input OR Gate with Non-Inverted Inputs

IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

OSERDES2Primitive: Dedicated IOB Output Serializer

IntroductionUse the OSERDES primitive to easily implement a source synchronous interface. This device helps you by savinglogic resources that would otherwise be implemented in the FPGA fabric. It also avoids additional timingcomplexities that you might encounter when you are designing circuitry in the FPGA fabric. This elementcontains multiple clock inputs to accommodate various applications, and will work in conjunction with theSelectIO features of Xilinx FPGAs.

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Chapter 3: About Design Elements

Port DescriptionsPort Type Width Function

CLKDIV Input 1 Global clock network input. This is the clock for the fabricdomain.

CLK0 Input 1 Optionally Invertible IO Clock network input. This is theprimary clock input used when the clock doubler circuit is notengaged. See DATA_RATE attribute for more information.

CLK1 Input 1 IO Clock network input. Optionally Invertible. Timing.

CLK1 should be 180 degrees out of phase with CLK0.D1 - D4 Input 1 Data input.

IOCE Input 1 Transfer Out enable signal derived from BUFIO CE. This is thestrobe that determines when the input data is sampled.

OCE Input 1 Clock enable for data inputs.

OQ Output 1 Data path output to pad or IODELAY2.

RST Input 1 Shared Data/Tristate Reset pin. Asynchronous only.

SHIFTIN1 -SHIFTIN2

Input 1 Cascade data input signals (dummy in Master). Used forDATA_WIDTHs greater than four.

SHIFTIN3 -SHIFTIN4

Input 1 Differential data input Signals (dummy in Slave).

SHIFTOUT1 -SHIFTOUT2

Output 1 Cascade data output signal (dummy in Slave). Used forDATA_WIDTHs greater than four.

SHIFTOUT3 -SHIFTOUT4

Output 1 Differential data output signals (dummy in Master).

TCE Input 1 Clock enable for tristate inputs.

TQ Output 1 Tristate path output to pad or IODELAY2.

TRAIN Input 1 Enable use of the training pattern. The Train function is a meansof specifying a fixed output pattern that is used to calibratethe receiver of the signal. This pin allows the fabric to controlwhether the output is that fixed pattern or the input data fromthe pins.

T1 - T4 Input 1 Parallel 3-State Inputs - Ports T1 to T4 are the location in which allparallel 3-state signals enters the OSERDES2 module. This portis connected to the FPGA fabric, and can be configured from 1 to4 bits. This feature is not supported in the extended width mode.

Design Entry MethodThis design element can be used in schematics.

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Chapter 3: About Design Elements

Available AttributesAttribute Type Allowed Values Default Description

DATA_RATE_OQ String “DDR”, “SDR” “DDR” Data rate setting. Defines whether the datachanges at every clock edge or every positiveclock edge with respect to CLK.

DATA_RATE_OT String “DDR”, “BUF”,“SDR”

“DDR” Tristate Data rate setting. Defines whetherthe 3-state changes at every clock edge, everypositive clock edge, or buffer configurationwith respect to CLK.

DATA_WIDTH Integer 2, 1, 3, 4, 5, 6, 7, 8 2 Sets howmany bits from the fabric to serializeto the IOB.

OUTPUT_MODE String “SINGLE_ENDED”,“DIFFERENTIAL”

“SINGLE_ENDED”

Output Mode.

SERDES_MODE String “MASTER”,“SLAVE”

“MASTER” Indicates whether SERDES is being used as aMaster or Slave when cascaded.

TRAIN_PATTERN Integer 0, 1, 2, 3, 4, 5, 6, 7, 8,9, 10, 11, 12, 13, 14,15

0 Training pattern. See comments for TRAINpin.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

PCIE_A1Primitive: PCI Express

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Chapter 3: About Design Elements

IntroductionThis design element is intended for use in conjunction with other resources located in the FPGA, such as theRocketIO™ transceiver, block RAMs, and various clocking resources. To implement an PCI EXPRESS® designusing PCIE_A1, designers must use the CORE Generator™ software tool (part of the ISE® Design Suite) tocreate a LogiCORE™ IP core for PCI EXPRESS designs. The LogiCORE IP instantiates the PCIE_A1 softwareprimitive, connects the interfaces to the correct FPGA resources, sets all attributes, and presents a simple,user-friendly interface.

Design Entry MethodTo instantiate this component, use the PCI EXPRESS® core or an associated core containing the component.Xilinx does not recommend direct instantiation of this component.

This design element can be used in schematics.

For More Information• See the Spartan-6 FPGA RocketIO GTP Transceivers User Guide.

• See the LogiCORE™ IP Spartan-6 FPGA Integrated Endpoint Block v1.1 for PCI EXPRESS® User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

PLL_BASEPrimitive: Basic Phase Locked Loop Clock Circuit

IntroductionThis design element is a direct sub-set of the PLL_ADV design element, an embedded Phase Locked Loop clockcircuit that provides added capabilities for clock synthesis and management both within the FPGA and incircuits external to the FPGA. The PLL_BASE is provided in order to ease the integration for most PLL clockingcircuits. However, this primitive does not contain all of the functionality that the PLL can possibly provide. Thiscomponent allows the input clock to be phase shifted, multiplied and divided, and supports other features, suchas modification of the duty cycle and jitter filtering.

Port DescriptionsPort Direction Width Function

Clock Outputs/Inputs

CLKOUT0-5 Output 1 One of six phase controlled output clocks from thePLL.

CLKFBOUT Output 1 Dedicated PLL feedback output used to determinehow the PLL compensates clock network delay.Depending on the type of compensation desired,this output might or might not need to be connected.

CLKIN Input 1 Clock source input to the PLL. This pin can bedriven by a dedicated clock pin to the FPGA, a DCMoutput clock pin, or a BUFG output.

CLKFBIN Input 1 Clock feedback input. This pin should only besourced from the CLKFBOUT port.

Status Outputs/Control Inputs

LOCKED Output 1 Synchronous output from the PLL that providesyou with an indication the PLL has achieved phasealignment and is ready for operation.

RST Input 1 Asynchronous reset of the PLL.

Design Entry MethodThis design element can be used in schematics.

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Available AttributesAttribute Type Allowed Values Default Description

COMPENSATION String "SYSTEM_SYNCHRONOUS","SOURCE_SYNCHRONOUS"

"SYSTEM_SYNCHRONOUS"

Specifies the PLL phasecompensation for the incomingclock.SYSTEM_SYNCHRONOUSattempts to compensate all clock delaywhile SOURCE_SYNCHRONOUS isused when a clock is provided withdata and thus phased with the clock.

BANDWIDTH String "HIGH", "LOW","OPTIMIZED"

"OPTIMIZED" Specifies the PLL programmingalgorithm affecting the jitter, phasemargin and other characteristics of thePLL.

CLKOUT0_DIVIDE,CLKOUT1_DIVIDE,CLKOUT2_DIVIDE,CLKOUT3_DIVIDE,CLKOUT4_DIVIDE,CLKOUT5_DIVIDE

Integer 1 to 128 1 Specifies the amount to divide theassociated CLKOUT clock outputif a different frequency is desired.This number in combination with theFBCLKOUT_MULT value determinesthe output frequency.

CLKOUT0_PHASE,CLKOUT1_PHASE,CLKOUT2_PHASE,CLKOUT3_PHASE,CLKOUT4_PHASE,CLKOUT5_PHASE

Real 0.01 to 360.0 0.0 Allows specification of the outputphase relationship of the associatedCLKOUT clock output in number ofdegrees offset (i.e. 90 indicates a 90degree or ¼ cycle offset phase offsetwhile 180 indicates a 180 degree offsetor ½ cycle phase offset).

CLKOUT0_DUTY_CYCLE,CLKOUT1_DUTY_CYCLE,CLKOUT2_DUTY_CYCLE,CLKOUT3_DUTY_CYCLE,CLKOUT4_DUTY_CYCLE,CLKOUT5_DUTY_CYCLE,

Real 0.01 to 0.99 0.50 Specifies the Duty Cycle of theassociated CLKOUT clock output inpercentage (i.e. 0.50 generates a 50%duty cycle).

CLKFBOUT_MULT Integer 1 to 64 1 Specifies the amount to multiply allCLKOUT clock outputs if a differentfrequency is desired. This numberin combination with the associatedCLKOUT#_DIVIDE value determinesthe output frequency.

DIVCLK_DIVIDE Integer 1 to 52 1 Specifies the division ratio for alloutput clocks.

CLKFBOUT_PHASE Real 0.0 to 360 0.0 Specifies the phase offset in degrees ofthe clock feedback output.

REF_JITTER Real 0.000 to 0.999 0.100 The reference clock jitter is specified interms of the UI which is a percentageof the reference clock. The numberprovided should be the maximumpeak to peak value on the input clock.

CLKIN_PERIOD Real 1.000 to 52.630 0.000 Specified the input period in ns to thePLL CLKIN input.

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For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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POST_CRC_INTERNALPrimitive: Post-configuration CRC error detection

IntroductionThis primitive provides fabric access to post CRC error. This new primitive is added to provide more flexibilityof POST_CRC usage. It is also the only access to POST CRC status when CRC_EXTSTAT_DISABLE is activated.

Port DescriptionsPort Type Width Function

CRCERROR Output 1 Post-configuration CRCerror

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Configuration User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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PULLDOWNPrimitive: Resistor to GND for Input Pads, Open-Drain, and 3-State Outputs

IntroductionThis resistor element is connected to input, output, or bidirectional pads to guarantee a logic Low level fornodes that might float.

Port DescriptionsPort Direction Width Function

O Output 1 Pulldown output (connect directly to top level port)

Design Entry MethodThis design element can be used in schematics.

This element can be connected to a net in the following locations on a top-level schematic file:

• A net connected to an input IO Marker.

• A net connected to both an output IO Marker and 3-statable IO element, such as an OBUFT.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

PULLUPPrimitive: Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs

IntroductionThis design element allows for an input, 3-state output or bi-directional port to be driven to a weak highvalue when not being driven by an internal or external source. This element establishes a High logic level foropen-drain elements and macros when all the drivers are off.

Port DescriptionsPort Direction Width Function

O Output 1 Pullup output (connect directly to top level port)

Design Entry MethodThis design element can be used in schematics.

This element can be connected to a net in the following locations on a top-level schematic file:

• A net connected to an input IO Marker

• A net connected to both an output IO Marker and 3-statable IO element, such as an OBUFT.

For More Information• See the Spartan-6 FPGA SelectIO Resources User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

RAM128X1DPrimitive: 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)

IntroductionThis design element is a 128-bit deep by 1-bit wide random access memory and has a read/write port that writesthe value on the D input data pin when the write enable (WE) is high to the location specified by the A addressbus. This happens shortly after the rising edge of the WCLK and that same value is reflected in the data outputSPO. When WE is low, an asynchronous read is initiated in which the contents of the memory location specifiedby the A address bus is output asynchronously to the SPO output. The read port can perform asynchronousread access of the memory by changing the value of the address bus DPRA, and by outputing that value to theDPO data output.

Port DescriptionsPort Direction Width Function

SPO Output 1 Read/Write port data output addressed by A

DPO Output 1 Read port data output addressed by DPRA

D Input 1 Write data input addressed by A

A Input 7 Read/Write port address bus

DPRA Input 7 Read port address bus

WE Input 1 Write Enable

WCLK Input 1 Write clock (reads are asynchronous)

If instantiated, the following connections should be made to this component:

• Tie the WCLK input to the desired clock source, the D input to the data source to be stored and the DPOoutput to an FDCE D input or other appropriate data destination.

• Optionally, the SPO output can also be connected to the appropriate data destination or else left unconnected.

• The WE clock enable pin should be connected to the proper write enable source in the design.

• The 7-bit A bus should be connected to the source for the read/write addressing and the 7-bit DPRA busshould be connected to the appropriate read address connections.

• An optional INIT attribute consisting of a 128-bit Hexadecimal value can be specified to indicate the initialcontents of the RAM.

If left unspecified, the initial contents default to all zeros.

Design Entry MethodThis design element can be used in schematics.

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Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 128-Bit Value All zeros Specifies the initial contents of theRAM.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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RAM16X1DPrimitive: 16-Deep by 1-Wide Static Dual Port Synchronous RAM

IntroductionThis element is a 16-word by 1-bit static dual port random access memory with synchronous write capability.The device has two address ports: the read address (DPRA3:DPRA0) and the write address (A3:A0). These twoaddress ports are asynchronous. The read address controls the location of the data driven out of the output pin(DPO), and the write address controls the destination of a valid write transaction. When the write enable (WE) isLow, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected.

When WE is High, any positive transition on (WCLK) loads the data on the data input (D) into the word selectedby the 4-bit write address. For predictable performance, write address and data inputs must be stable before aLow-to-High (WCLK) transition. This RAM block assumes an active-High (WCLK). (WCLK) can be active-Highor active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.

The SPO output reflects the data in the memory cell addressed by A3:A0. The DPO output reflects the datain the memory cell addressed by DPRA3:DPRA0.

Note The write process is not affected by the address on the read address port.

You can use the INIT attribute to directly specify an initial value. The value must be a hexadecimal number, forexample, INIT=ABAC. If the INIT attribute is not specified, the RAM is initialized with all zeros.

Logic TableMode selection is shown in the following logic table:

Inputs Outputs

WE (mode) WCLK D SPO DPO

0 (read) X X data_a data_d

1 (read) 0 X data_a data_d

1 (read) 1 X data_a data_d

1 (write) ↑ D D data_d

1 (read) ↓ X data_a data_d

data_a = word addressed by bits A3-A0

data_d = word addressed by bits DPRA3-DPRA0

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Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value Allzeros.

Initializes RAMs, registers, and look-uptables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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RAM16X1D_1Primitive: 16-Deep by 1-Wide Static Dual Port Synchronous RAM with Negative-Edge Clock

IntroductionThis is a 16-word by 1-bit static dual port random access memory with synchronous write capability andnegative-edge clock. The device has two separate address ports: the read address (DPRA3:DPRA0) and the writeaddress (A3:A0). These two address ports are asynchronous. The read address controls the location of the datadriven out of the output pin (DPO), and the write address controls the destination of a valid write transaction.

When the write enable (WE) is set to Low, transitions on the write clock (WCLK) are ignored and data stored inthe RAM is not affected. When (WE) is High, any negative transition on (WCLK) loads the data on the datainput (D) into the word selected by the 4-bit write address. For predictable performance, write address anddata inputs must be stable before a High-to-Low WCLK transition. This RAM block assumes an active-High(WCLK). (WCLK) can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbedinto the block.

You can initialize RAM16X1D_1 during configuration using the INIT attribute.

The SPO output reflects the data in the memory cell addressed by A3:A0. The DPO output reflects the datain the memory cell addressed by DPRA3:DPRA0.

Note The write process is not affected by the address on the read address port.

Logic TableMode selection is shown in the following logic table:

Inputs Outputs

WE (mode) WCLK D SPO DPO

0 (read) X X data_a data_d

1 (read) 0 X data_a data_d

1 (read) 1 X data_a data_d

1 (write) ↓ D D data_d

1 (read) ↑ X data_a data_d

data_a = word addressed by bits A3:A0

data_d = word addressed by bits DPRA3:DPRA0

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Port DescriptionsPort Direction Width Function

DPO Output 1 Read-only 1-Bit data output

SPO Output 1 R/W 1-Bit data output

A0 Input 1 R/W address[0] input

A1 Input 1 R/W address[1] input

A2 Input 1 R/W address[2] input

A3 Input 1 R/W address[3] input

D Input 1 Write 1-Bit data input

DPRA0 Input 1 Read-only address[0] input

DPRA1 Input 1 Read-only address[1] input

DPRA2 Input 1 Read-only address[2] input

DPRA3 Input 1 Read-only address[3] input

WCLK Input 1 Write clock input

WE Input 1 Write enable input

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Initializes RAMs, registers, and look-uptables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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RAM16X1SPrimitive: 16-Deep by 1-Wide Static Synchronous RAM

IntroductionThis element is a 16-word by 1-bit static random access memory with synchronous write capability. When thewrite enable (WE) is set Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM isnot affected. When WE is set High, any positive transition on WCLK loads the data on the data input (D) into theword selected by the 4-bit address (A3:A0). This RAM block assumes an active-High WCLK. However, WCLKcan be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by thevalues on the address pins. You can initialize RAM16X1S during configuration using the INIT attribute.

Logic TableInputs Outputs

WE(mode) WCLK D O

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↑ D D

1 (read) ↓ X Data

Data = word addressed by bits A3:A0

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Specifies initial contents of theRAM.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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RAM16X1S_1Primitive: 16-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock

IntroductionThis element is a 16-word by 1-bit static random access memory with synchronous write capability andnegative-edge clock. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignoredand data stored in the RAM is not affected. When (WE) is High, any negative transition on (WCLK) loads thedata on the data input (D) into the word selected by the 4-bit address (A3:A0). For predictable performance,address and data inputs must be stable before a High-to-Low WCLK transition. This RAM block assumes anactive-Low (WCLK). However, (WCLK) can be active-High or active-Low. Any inverter placed on the (WCLK)input net is absorbed into the block.

The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined bythe values on the address pins.

You can initialize this element during configuration using the INIT attribute.

Logic TableInputs Outputs

WE(mode) WCLK D O

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↓ D D

1 (read) ↑ X Data

Data = word addressed by bits A3:A0

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Specifies initial contents of theRAM.

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For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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RAM16X2SPrimitive: 16-Deep by 2-Wide Static Synchronous RAM

IntroductionThis element is a 16-word by 2-bit static random access memory with synchronous write capability. When thewrite enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When WE is High, any positive transition on WCLK loads the data on the data input (D1:D0) into theword selected by the 4-bit address (A3:A0). For predictable performance, address and data inputs must be stablebefore a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK canbe active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The signal output on the data output pins (O1:O0) is the data that is stored in the RAM at the location defined bythe values on the address pins.

You can use the INIT_xx properties to specify the initial contents of a wide RAM. INIT_00 initializes the RAMcells corresponding to the O0 output, INIT_01 initializes the cells corresponding to the O1 output, etc. Forexample, a RAM16X2S instance is initialized by INIT_00 and INIT_01 containing 4 hex characters each. ARAM16X8S instance is initialized by eight properties INIT_00 through INIT_07 containing 4 hex characterseach. A RAM64x2S instance is completely initialized by two properties INIT_00 and INIT_01 containing16 hex characters each.

Except for Virtex-4 devices, the initial contents of this element cannot be specified directly.

Logic TableInputs Outputs

WE (mode) WCLK D1:D0 O1:O0

0 (read) X X Data

1(read) 0 X Data

1(read) 1 X Data

1(write) ↑ D1:D0 D1:D0

1(read) ↓ X Data

Data = word addressed by bits A3:A0

Design Entry MethodThis design element can be used in schematics.

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Available AttributesAttribute Type Allowed Values Default Description

INIT_00 to INIT_01 Hexadecimal Any 16-Bit Value All zeros Initializes RAMs, registers, andlook-up tables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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RAM16X4SPrimitive: 16-Deep by 4-Wide Static Synchronous RAM

IntroductionThis element is a 16-word by 4-bit static random access memory with synchronous write capability. When thewrite enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When WE is High, any positive transition on WCLK loads the data on the data input (D3:D0) into theword selected by the 4-bit address (A3:A0). For predictable performance, address and data inputs must be stablebefore a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK canbe active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The signal output on the data output pins (O3:O0) is the data that is stored in the RAM at the location defined bythe values on the address pins.

Logic TableInputs Outputs

WE (mode) WCLK D3:D0 O3:O0

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↑ D3:D0 D3:D0

1 (read) ↓ X Data

Data = word addressed by bits A3:A0.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT_00 to INIT_03 Hexadecimal Any 16-Bit Value All zeros INIT for bit 0 of RAM

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For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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RAM16X8SPrimitive: 16-Deep by 8-Wide Static Synchronous RAM

IntroductionThis element is a 16-word by 8-bit static random access memory with synchronous write capability. When thewrite enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When WE is High, any positive transition on WCLK loads the data on data inputs (D7:D0) into theword selected by the 4-bit address (A3:A0). For predictable performance, address and data inputs must be stablebefore a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK canbe active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The signal output on the data output pins (O7:O0) is the data that is stored in the RAM at the location defined bythe values on the address pins.

Logic TableInputs Outputs

WE (mode) WCLK D7:D0 O7:O0

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↑ D7:D0 D7:D0

1 (read) ↓ X Data

Data = word addressed by bits A3–A0

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT_00 to INIT_07 Hexadecimal Any 16-Bit Value All zeros Initializes RAMs, registers, and look-uptables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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RAM256X1SPrimitive: 256-Deep by 1-Wide Random Access Memory (Select RAM)

IntroductionThis design element is a 256-bit deep by 1-bit wide random access memory with synchronous write andasynchronous read capability. This RAM is implemented using the LUT resources of the device (also knownas Select RAM), and does not consume any of the block RAM resources of the device. If a synchronous readcapability is preferred, a register can be attached to the output and placed in the same slice as long as thesame clock is used for both the RAM and the register. The RAM256X1S has an active, High write enable, WE,so that when that signal is High, and a rising edge occurs on the WCLK pin, a write is performed recordingthe value of the D input data pin into the memory array. The output O displays the contents of the memorylocation addressed by A, regardless of the WE value. When a write is performed, the output is updated to thenew value shortly after the write completes.

Port DescriptionsPort Direction Width Function

O Output 1 Read/Write port data output addressed by A

D Input 1 Write data input addressed by A

A Input 8 Read/Write port address bus

WE Input 1 Write Enable

WCLK Input 1 Write clock (reads are asynchronous)

Design Entry MethodIf instantiated, the following connections should be made to this component:

• Tie the WCLK input to the desired clock source, the D input to the data source to be stored, and the O outputto an FDCE D input or other appropriate data destination.

• The WE clock enable pin should be connected to the proper write enable source in the design.

• The 8-bit A bus should be connected to the source for the read/write.

• An optional INIT attribute consisting of a 256-bit Hexadecimal value can be specified to indicate the initialcontents of the RAM.

If left unspecified, the initial contents default to all zeros.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 256-Bit Value Allzeros

Specifies the initial contents of the RAM.

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For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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RAM32MPrimitive: 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)

IntroductionThis design element is a 32-bit deep by 8-bit wide, multi-port, random access memory with synchronous writeand asynchronous independent, 2-bit, wide-read capability. This RAM is implemented using the LUT resourcesof the device known as SelectRAM™, and does not consume any of the Block RAM resources of the device. TheRAM32M is implemented in a single slice and consists of one 8-bit write, 2-bit read port and three separate 2-bitread ports from the same memory. This configuration allows for byte-wide write and independent 2-bit readaccess RAM. If the DIA, DIB, DIC and DID inputs are all tied to the same data inputs, the RAM can becomea 1 read/write port, 3 independent read port, 32x2 quad port memory. If DID is grounded, DOD is not used,while ADDRA, ADDRB and ADDRC are tied to the same address, the RAM becomes a 32x6 simple dual portRAM. If ADDRD is tied to ADDRA, ADDRB, and ADDRC, then the RAM is a 32x8 single port RAM. There areseveral other possible configurations for this RAM.

Port DescriptionsPort Direction Width Function

DOA Output 2 Read port data outputs addressed by ADDRA

DOB Output 2 Read port data outputs addressed by ADDRB

DOC Output 2 Read port data outputs addressed by ADDRC

DOD Output 2 Read/Write port data outputs addressed by ADDRD

DIA Input 2 Write data inputs addressed by ADDRD (read output isaddressed by ADDRA)

DIB Input 2 Write data inputs addressed by ADDRD (read output isaddressed by ADDRB)

DIC Input 2 Write data inputs addressed by ADDRD (read output isaddressed by ADDRC)

DID Input 2 Write data inputs addressed by ADDRD

ADDRA Input 5 Read address bus A

ADDRB Input 5 Read address bus B

ADDRC Input 5 Read address bus C

ADDRD Input 5 8-bit data write port, 2-bit data read port address bus D

WE Input 1 Write Enable

WCLK Input 1 Write clock (reads are asynchronous)

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Design Entry MethodThis design element can be used in schematics.

This element can be inferred by some synthesis tools by describing a RAM with a synchronous write andasynchronous read capability. Consult your synthesis tool documentation for details on RAM inferencecapabilities and coding examples. Xilinx suggests that you instantiate RAM32Ms if you have a need to implicitlyspecify the RAM function, or if you need to manually place or relationally place the component. If a synchronousread capability is desired, the RAM32M outputs can be connected to an FDRSE (FDCPE is asynchronous set/resetis necessary) in order to improve the output timing of the function. However, this is not necessary for theproper operation of the RAM.

If you want to have the data clocked on the negative edge of a clock, an inverter can be described on the clockinput to this component. This inverter will be absorbed into the block, giving you the ability to write to the RAMon falling clock edges.

If instantiated, the following connections should be made to this component. Tie the WCLK input to the desiredclock source, the DIA, DIB, DIC and DID inputs to the data source to be stored and the DOA, DOB, DOC andDOD outputs to an FDCE D input or other appropriate data destination or left unconnected if not used. The WEclock enable pin should be connected to the proper write enable source in the design. The 5-bit ADDRD busshould be connected to the source for the read/write addressing and the 5-bit ADDRA, ADDRB and ADDRCbuses should be connected to the appropriate read address connections. The optional INIT_A, INIT_B, INIT_Cand INIT_D attributes consisting of a 64-bit hexadecimal values that specifies each port’s initial memory contentscan be specified. The INIT value correlates to the RAM addressing by the following equation: ADDRy[z] =INIT_y[2*z+1:2*z]. For instance, if the RAM ADDRC port is addressed to 00001, then the INIT_C[3:2] valueswould be the initial values shown on the DOC port before the first write occurs at that address. If left unspecified,the initial contents will default to all zeros.

Available AttributesAttribute Type Allowed Values Default Description

INIT_A Hexadecimal Any 64-Bit Value All zeros Specifies the initial contents of the RAM onthe A port.

INIT_B Hexadecimal Any 64-Bit Value All zeros Specifies the initial contents of the RAM onthe B port.

INIT_C Hexadecimal Any 64-Bit Value All zeros Specifies the initial contents of the RAM onthe C port.

INIT_D Hexadecimal Any 64-Bit Value All zeros Specifies the initial contents of the RAM onthe D port.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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RAM32X1SPrimitive: 32-Deep by 1-Wide Static Synchronous RAM

IntroductionThe design element is a 32-word by 1-bit static random access memory with synchronous write capability. Whenthe write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When (WE) is High, any positive transition on (WCLK) loads the data on the data input (D) into theword selected by the 5-bit address (A4-A0). For predictable performance, address and data inputs must be stablebefore a Low-to-High (WCLK) transition. This RAM block assumes an active-High (WCLK). However, (WCLK)can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.

The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by thevalues on the address pins. You can initialize RAM32X1S during configuration using the INIT attribute.

Logic TableInputs Outputs

WE (Mode) WCLK D O

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↓ D D

1 (read) ↑ X Data

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Descriptions

INIT Hexadecimal Any 32-Bit Value All zeros Specifies initial contents of the RAM.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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RAM32X1S_1Primitive: 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock

IntroductionThe design element is a 32-word by 1-bit static random access memory with synchronous write capability. Whenthe write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When (WE) is High, any negative transition on (WCLK) loads the data on the data input (D) into theword selected by the 5-bit address (A4:A0). For predictable performance, address and data inputs must be stablebefore a High-to-Low (WCLK) transition. This RAM block assumes an active-Low (WCLK). However, (WCLK)can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.

The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by thevalues on the address pins. You can initialize RAM32X1S_1 during configuration using the INIT attribute.

Logic TableInputs Outputs

WE (Mode) WCLK D O

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↓ D D

1 (read) ↑ X Data

Data = word addressed by bits A4:A0

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Descriptions

INIT Hexadecimal Any 32-Bit Value 0 Initializes RAMs, registers, and look-uptables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

RAM32X2SPrimitive: 32-Deep by 2-Wide Static Synchronous RAM

IntroductionThe design element is a 32-word by 2-bit static random access memory with synchronous write capability. Whenthe write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM isnot affected. When (WE) is High, any positive transition on (WCLK) loads the data on the data input (D1-D0)into the word selected by the 5-bit address (A4-A0). For predictable performance, address and data inputs mustbe stable before a Low-to-High (WCLK) transition. This RAM block assumes an active-High (WCLK). However,(WCLK) can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into theblock. The signal output on the data output pins (O1-O0) is the data that is stored in the RAM at the locationdefined by the values on the address pins.

You can use the INIT_00 and INIT_01 properties to specify the initial contents of RAM32X2S.

Logic TableInputs Outputs

WE (Mode) WCLK D O0-O1

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↑ D1:D0 D1:D0

1 (read) ↓ X Data

Data = word addressed by bits A4:A0

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Descriptions

INIT_00 Hexadecimal Any 32-Bit Value All zeros INIT for bit 0 of RAM.

INIT_01 Hexadecimal Any 32-Bit Value All zeros INIT for bit 1 of RAM.

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For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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RAM32X4SPrimitive: 32-Deep by 4-Wide Static Synchronous RAM

IntroductionThis design element is a 32-word by 4-bit static random access memory with synchronous write capability. Whenthe write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM isnot affected. When WE is High, any positive transition on WCLK loads the data on the data inputs (D3-D0)into the word selected by the 5-bit address (A4:A0). For predictable performance, address and data inputs mustbe stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However,WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The signal output on the data output pins (O3-O0) is the data that is stored in the RAM at the location defined bythe values on the address pins.

Logic TableInputs Outputs

WE WCLK D3-D0 O3-O0

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↑ D3:D0 D3:D0

1 (read) ↓ X Data

Data = word addressed by bits A4:A0

Design Entry MethodThis design element can be used in schematics.

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Available AttributesAttribute Type Allowed Values Default Description

INIT_00 Hexadecimal Any 32-Bit Value All zeros INIT for bit 0 of RAM.

INIT_01 Hexadecimal Any 32-Bit Value All zeros INIT for bit 1 of RAM.

INIT_02 Hexadecimal Any 32-Bit Value All zeros INIT for bit 2 of RAM.

INIT_03 Hexadecimal Any 32-Bit Value All zeros INIT for bit 3 of RAM.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

RAM32X8SPrimitive: 32-Deep by 8-Wide Static Synchronous RAM

IntroductionThis design element is a 32-word by 8-bit static random access memory with synchronous write capability. Whenthe write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM isnot affected. When WE is High, any positive transition on WCLK loads the data on the data inputs (D7:D0)into the word selected by the 5-bit address (A4:A0). For predictable performance, address and data inputs mustbe stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However,WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The signal output on the data output pins (O7:O0) is the data that is stored in the RAM at the location defined bythe values on the address pins.

Logic TableInputs Outputs

WE (mode) WCLK D7:D0 O7:O0

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↑ D7:D0 D7:D0

1 (read) ↓ X Data

Data = word addressed by bits A4:A0

Design Entry MethodThis design element can be used in schematics.

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Available AttributesAttribute Type Allowed Values Default Description

INIT_00 Hexadecimal Any 32-Bit Value All zeros INIT for bit 0 of RAM.

INIT_01 Hexadecimal Any 32-Bit Value All zeros INIT for bit 1 of RAM.

INIT_02 Hexadecimal Any 32-Bit Value All zeros INIT for bit 2 of RAM.

INIT_03 Hexadecimal Any 32-Bit Value All zeros INIT for bit 3 of RAM.

INIT_04 Hexadecimal Any 32-Bit Value All zeros INIT for bit 4 of RAM.

INIT_05 Hexadecimal Any 32-Bit Value All zeros INIT for bit 5 of RAM.

INIT_06 Hexadecimal Any 32-Bit Value All zeros INIT for bit 6 of RAM.

INIT_07 Hexadecimal Any 32-Bit Value All zeros INIT for bit 7 of RAM.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

RAM64MPrimitive: 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)

IntroductionThis design element is a 64-bit deep by 4-bit wide, multi-port, random access memory with synchronous writeand asynchronous independent bit wide read capability. This RAM is implemented using the LUT resources ofthe device (also known as SelectRAM™) and does not consume any of the block RAM resources of the device.The RAM64M component is implemented in a single slice, and consists of one 4-bit write, 1-bit read port,and three separate 1-bit read ports from the same memory allowing for 4-bit write and independent bit readaccess RAM. If the DIA, DIB, DIC and DID inputs are all tied to the same data inputs, the RAM can becomea 1 read/write port, 3 independent read port 64x1 quad port memory. If DID is grounded, DOD is not used.While ADDRA, ADDRB and ADDRC are tied to the same address the RAM becomes a 64x3 simple dual portRAM. If ADDRD is tied to ADDRA, ADDRB, and ADDRC; then the RAM is a 64x4 single port RAM. There areseveral other possible configurations for this RAM.

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Port DescriptionsPort Direction Width Function

DOA Output 1 Read port data outputs addressed by ADDRA

DOB Output 1 Read port data outputs addressed by ADDRB

DOC Output 1 Read port data outputs addressed by ADDRC

DOD Output 1 Read/Write port data outputs addressed byADDRD

DIA Input 1 Write data inputs addressed by ADDRD (readoutput is addressed by ADDRA)

DIB Input 1 Write data inputs addressed by ADDRD (readoutput is addressed by ADDRB)

DIC Input 1 Write data inputs addressed by ADDRD (readoutput is addressed by ADDRC)

DID Input 1 Write data inputs addressed by ADDRD

ADDRA Input 6 Read address bus A

ADDRB Input 6 Read address bus B

ADDRC Input 6 Read address bus C

ADDRD Input 6 4-bit data write port, 1-bit data read portaddress bus D

WE Input 1 Write Enable

WCLK Input 1 Write clock (reads are asynchronous)

Design Entry MethodThis design element can be used in schematics.

This element can be inferred by some synthesis tools by describing a RAM with a synchronous write andasynchronous read capability. Consult your synthesis tool documentation for details on RAM inferencecapabilities and coding examples. Xilinx suggests that you instantiate RAM64Ms if you have a need to implicitlyspecify the RAM function, or if you need to manually place or relationally place the component. If a synchronousread capability is desired, the RAM64M outputs can be connected to an FDRSE (FDCPE is asynchronous set/resetis necessary) in order to improve the output timing of the function. However, this is not necessary for theproper operation of the RAM. If you want to have the data clocked on the negative edge of a clock, an invertercan be described on the clock input to this component. This inverter will be absorbed into the block giving theability to write to the RAM on falling clock edges.

If instantiated, the following connections should be made to this component. Tie the WCLK input to thedesired clock source, the DIA, DIB, DIC and DID inputs to the data source to be stored and the DOA, DOB,DOC and DOD outputs to an FDCE D input or other appropriate data destination or left unconnected if notused. The WE clock enable pin should be connected to the proper write enable source in the design. The 5-bitADDRD bus should be connected to the source for the read/write addressing and the 5-bit ADDRA, ADDRBand ADDRC buses should be connected to the appropriate read address connections. The optional INIT_A,INIT_B, INIT_C and INIT_D attributes consisting of a 64-bit hexadecimal values that specifies each port’s initialmemory contents can be specified. The INIT value correlates to the RAM addressing by the following equation:ADDRy[z] = INIT_y[z].

For instance, if the RAM ADDRC port is addressed to 00001, then the INIT_C[1] values would be the initialvalues shown on the DOC port before the first write occurs at that address. If left unspecified, the initial contentswill default to all zeros.

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Available AttributesAttribute Type Allowed Values Default Description

INIT_A Hexadecimal Any 64-Bit Value All zero Specifies the initial contents of the RAM onthe A port.

INIT_B Hexadecimal Any 64-Bit Value All zero Specifies the initial contents of the RAM onthe B port.

INIT_C Hexadecimal Any 64-Bit Value All zero Specifies the initial contents of the RAM onthe C port.

INIT_D Hexadecimal Any 64-Bit Value All zero Specifies the initial contents of the RAM onthe D port.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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RAM64X1DPrimitive: 64-Deep by 1-Wide Dual Port Static Synchronous RAM

IntroductionThis design element is a 64-word by 1-bit static dual port random access memory with synchronous writecapability. The device has two separate address ports: the read address (DPRA5:DPRA0) and the write address(A5:A0). These two address ports are completely asynchronous. The read address controls the location ofthe data driven out of the output pin (DPO), and the write address controls the destination of a valid writetransaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and datastored in the RAM is not affected.

When WE is High, any positive transition on WCLK loads the data on the data input (D) into the word selectedby the 6-bit (A0:A5) write address. For predictable performance, write address and data inputs must be stablebefore a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. WCLK can beactive-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The SPO output reflects the data in the memory cell addressed by A5:A0. The DPO output reflects the datain the memory cell addressed by DPRA5:DPRA0.

Note The write process is not affected by the address on the read address port.

Logic TableInputs Outputs

WE (mode) WCLK D SPO DPO

0 (read) X X data_a data_d

1 (read) 0 X data_a data_d

1 (read) 1 X data_a data_d

1 (write) ↑ D D data_d

1 (read) ↓ X data_a data_d

data_a = word addressed by bits A5:A0

data_d = word addressed by bits DPRA5:DPRA0

Design Entry MethodThis design element can be used in schematics.

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Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 64-BitValue

All zeros Initializes RAMs, registers, and look-up tables.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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RAM64X1SPrimitive: 64-Deep by 1-Wide Static Synchronous RAM

IntroductionThis design element is a 64-word by 1-bit static random access memory (RAM) with synchronous write capability.When the write enable is set Low, transitions on the write clock (WCLK) are ignored and data stored in the RAMis not affected. When WE is set High, any positive transition on WCLK loads the data on the data input (D)into the word selected by the 6-bit address (A5:A0). This RAM block assumes an active-High WCLK. However,WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined bythe values on the address pins.

You can initialize this element during configuration using the INIT attribute.

Logic TableMode selection is shown in the following logic table

Inputs Outputs

WE (mode) WCLK D O

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↑ D D

1 (read) ↓ X Data

Data = word addressed by bits A5:A0

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 64-Bit Value All zeros Initializes ROMs, RAMs, registers, and look-uptables.

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For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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RAM64X1S_1Primitive: 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock

IntroductionThis design element is a 64-word by 1-bit static random access memory with synchronous write capability. Whenthe write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When (WE) is High, any negative transition on (WCLK) loads the data on the data input (D) into theword selected by the 6-bit address (A5:A0). For predictable performance, address and data inputs must be stablebefore a High-to-Low (WCLK) transition. This RAM block assumes an active-Low (WCLK). However, (WCLK)can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.

The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined bythe values on the address pins.

You can initialize this element during configuration using the INIT attribute.

Logic TableInputs Outputs

WE (mode) WCLK D O

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↓ D D

1 (read) ↑ X Data

Data = word addressed by bits A5:A0

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 64-Bit Value All zeros Initializes ROMs, RAMs, registers, and look-uptables.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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RAM64X2SPrimitive: 64-Deep by 2-Wide Static Synchronous RAM

IntroductionThis design element is a 64-word by 2-bit static random access memory with synchronous write capability. Whenthe write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAMis not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D1:D0)into the word selected by the 6-bit address (A5:A0). For predictable performance, address and data inputs mustbe stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However,WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The signal output on the data output pins (O1:O0) is the data that is stored in the RAM at the location defined bythe values on the address pins. You can use the INIT_00 and INIT_01 properties to specify the initial contentsof this design element.

Logic TableInputs Outputs

WE (mode) WCLK D0:D1 O0:O1

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) ↑ D1:D0 D1:D0

1 (read) ↓ X Data

Data = word addressed by bits A5:A0

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT_00 Hexadecimal Any 64-Bit Value All zeros Initializes RAMs, registers, and look-up tables.

INIT_01 Hexadecimal Any 64-Bit Value All zeros Initializes RAMs, registers, and look-up tables.

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For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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RAMB16BWERPrimitive: 16K-bit Data and 2K-bit Parity Configurable Synchronous Dual Port Block RAM withOptional Output Registers

IntroductionThis design element contains several block RAMmemories that can be configured as general-purpose 16kb data+ 2kb parity RAM/ROM memories. These block RAM memories offer fast and flexible storage of large amountsof on-chip data. This component can be configured and used as a 1-bit wide by 16K deep to a 36-bit wide by 512deep, single-port or dual port RAM. Both read and write operations are fully synchronous to the supplied clock(s)to the component. However, Port A and Port B can operate fully independently and asynchronously to each other,accessing the same memory array. When these ports are configured in the wider data width modes, byte-enablewrite operations are possible. This RAM also offers a configurable output register that can be enabled to improveclock-to-out times of the RAM while incurring an extra clock cycle of latency during the read operation.

Port DescriptionsThe following table shows the necessary input and output connections for the variable input ports for eachDATA_WIDTH value for either Port A or Port B.

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DATA_WIDTHValue

DI, DIPConnections

ADDRConnections WE Connections

1 DI[0] ADDR[13:0] Connect WE[3:0] to single user WE signal.

2 DI[1:0] ADDR[13:1] Connect WE[3:0] to single user WE signal.

4 DI[3:0] ADDR[13:2] Connect WE[3:0] to single user WE signal.

9 DI[7:0], DIP[0] ADDR[13:3] Connect WE[3:0] to single user WE signal.

18 DI[15:0], DIP[1:0] ADDR[13:4] Connect WE[0] and WE[2] to user WE[0] and WE[1] andWE[3] to user WE[1].

36 DI[31:0], DIP[3:0] ADDR[13:5] Connect each WE[3:0] signal to the associated byte writeenable.

Alternatively, the older RAMB16_Sm_Sn and RAMB16BWER_Sm_Sn elements can be instantiated if the outputregisters are not necessary. If any of these components are used, the software will automatically retarget themto a properly configured RAMB16BWER element.

Port Direction Width Function

DOA, DOB Output 32 Port A/B data output bus.

DOPA, DOPB Output 4 Port A/B parity output bus.

DIA, DIB Input 32 Port A/B data input bus.

DIPA, DIPB Input 4 Port A/B parity input bus.

ADDRA, ADDRB Input 14 Port A/B address input bus. MSB always exists onADDRA/B[13] while the LSB is determined by the settings forDATA_WIDTH_A/B.

WEA, WEB Input 4 Port A/B byte-wide write enable.

ENA, ENB Input 1 Port A/B enable.

REGCEA, REGCEB Input 1 Output register clock enable.

RSTA, RSTB Input 1 Port A/B output registers set/reset. This reset is configurable tobe synchronous or asynchronous, depending on the value ofthe RSTTYPE attribute.

CLKA, CLKB Input 1 Port A/B clock input.

Design Entry MethodThis design element can be used in schematics.

Connect all necessary inputs to the desired signals in the design. The CLKA/CLKB clock signals must be tied toan active clock for RAM operation, and the SRA/SRB reset signals must be either tied to a logic zero or to theproper reset signal. ENA/ENB must either be tied to a logic one or a proper RAM port enable signal. REGCEAand REGCEB must be tied to the proper output register clock enable, or a logic one if the respective DOA_REGor DOB_REG attribute is set to 1. If DOA_REG is set to 0, then REGCEA and REGCEB must be set to a logic 0.

Refer to the DATA_WIDTH column in the “Port Description” table (above) for the necessary data input, dataoutput, write enable and address connection information for each DATA_WIDTH setting, since the necessaryconnections for these signals change, based on this attribute. All other output signals can be left unconnected(open) and all unused input signals should be tied to a logic zero.

Available AttributesAttribute Type Allowed Values Default Description

DATA_WIDTH_A Integer 0, 1, 2, 4, 9, 18, 36 0 Specifies the configurable data width forPorts A.

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Attribute Type Allowed Values Default Description

DATA_WIDTH_B Integer 0, 1, 2, 4, 9, 18, 36 0 Specifies the configurable data width forPorts B.

DOA_REG Integer 0, 1 0 Specifies to use or bypass the outputregisters for the RAM.

DOB_REG Integer 0, 1 0 Specifies to use or bypass the outputregisters for the RAM.

EN_RSTRAM_A String “TRUE”, “FALSE” “TRUE” Specifies if the reset capability on theoutput latches is enabled.

EN_RSTRAM_B String “TRUE”, “FALSE” “TRUE” Specifies if the reset capability on theoutput latches is enabled.

INIT_A Hexa-decimal

36’h000000000 to36’h68719476735

All zeros Specifies the initial value on the Port Aoutput after configuration.

INIT_B Hexa-decimal

36’h000000000 to36’h68719476735

All zeros Specifies the initial value on the Port Boutput after configuration.

INIT_FILE String 0 bit String NONE Specifies the name of the file for specifyingthe initial values of the block RAM

INIT_00 toINIT_3F

Hexa-decimal

Any 256 bit value All zeros Specifies the initial contents of the 16 kbdata memory array.

INITP_01 toINITP_07

Hexa-decimal

Any 256 bit value All zeros Specifies the initial contents of the 2 kbparity data memory array.

RST_PRIORITY_A String “CE”, “SR” “CE” Specifies whether RSTA pin or ENA pin(latch mode) or REGCEA pin (outputregister mode) has priority.

RST_PRIORITY_B String “CE”, “SR” “CE” Specifies whether RSTB pin or ENB pin(latch mode) or REGCEB pin (outputregister mode) has priority.

RSTTYPE String “SYNC”, “ASYNC” “SYNC” Type of reset, synchronous orasynchronous.

SIM_COLLISION_CHECK

String “ALL”,“GENERATE_X_ONLY”,“WARNING_ONLY”,“NONE”

“ALL” Allows modification of the simulationbehavior so that if a memory collisionoccurs:

• ALL - Warning produced andaffected outputs/memory location gounknown (X).

• WARNING_ONLY - Warningproduced and affectedoutputs/memory location retainlast value.

• GENERATE_X_ONLY - No warning,but affected outputs/memory locationgo unknown (X).

• NONE - No warning and affectedoutputs/memory location retain lastvalue.

Note Setting this to a value other than“ALL” can allow problems in the designto go unnoticed during simulation. Careshould be taken when changing the valueof this attribute.

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Attribute Type Allowed Values Default Description

SRVAL_A Hexa-decimal

36’h000000000 to36’h68719476735

All zeros Specifies the output value of Port A uponthe assertion of the reset (RSTA) signal.

SRVAL_B Hexa-decimal

36’h000000000 to36’h68719476735

All zeros Specifies the output value of Port A uponthe assertion of the reset (RSTB) signal.

WRITE_MODE_A String “WRITE_FIRST”,“READ_FIRST”,“NO_CHANGE”

“WRITE_FIRST” Specifies the output behavior of Port A.

• WRITE_FIRST - Written value appearson output port of the RAM.

• READ_FIRST - Previous RAMcontents for that memory locationappear on the output port.

• NO_CHANGE - Previous value onthe output port remains the same.

WRITE_MODE_B String “WRITE_FIRST”,“READ_FIRST”,“NO_CHANGE”

“WRITE_FIRST” Specifies the output behavior of Port B.

• WRITE_FIRST - Written value appearson output port of the RAM.

• READ_FIRST - Previous RAMcontents for that memory locationappear on the output port.

• NO_CHANGE - Previous value onthe output port remains the same.

For More Information• See the Spartan-6 FPGA Block RAM User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

RAMB8BWERPrimitive: 8K-bit Data and 1K-bit Parity Configurable Synchronous Dual Port Block RAM withOptional Output Registers

IntroductionThis design element contains several block RAMmemories that can be configured as general-purpose 9 kb data +1 kb parity RAM/ROMmemories. These block RAMmemories offer fast and flexible storage of large amounts ofon-chip data. This component can be configured and used as a 1-bit wide by 8K deep to a 36-bit wide by 512deep, single port or simple dual port RAM. In true dual port mode, 1-bit wide by 8K deep to a 18-bit wide by1K deep is supported. Both read and write operations are fully synchronous to the supplied clock(s) in thecomponent. However, Port A and Port B can operate fully independently and asynchronously to each other,accessing the same memory array. When these ports are configured in the wider data width modes, byte-enablewrite operations are possible. This RAM also offers a configurable output register that can be enabled to improveclock-to-out times of the RAM while incurring an extra clock cycle of latency during the read operation.

Port DescriptionsPort Direction Width Function

DOADO Output 16 Port A data output bus.

DOBDO Output 16 Port B data output bus.

DOPADOP Output 2 In True Dual Port mode, this is the A port parity bus output. InSimple Dual Port mode, this is the parity bus output for thelower order bits. DOPBDOP has the higher order parity bits,if DATA_WIDTH is 36.

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Chapter 3: About Design Elements

Port Direction Width Function

DOPBDOP Output 2 In True Dual Port mode, this is the B port parity bus output. InSimple Dual Port mode, this is the parity bus output for thehigher order parity bits when DATA_WIDTH is 36. DOPADOPhas the lower order parity bits.

DIADI Input 16 In True Dual Port mode, this is the A port data bus. In SimpleDual Port Mode, this is the data bus for the lower order bits.DIBDI has the higher order data bits [16:31], if DATA_WIDTHis 36.

DIBDI Input 16 In True Dual Port mode, this is the B port data bus. In SimpleDual Port mode, this is the data bus for the higher order bits[16:31] when DATA_WIDTH is 36. DIADI has the lower orderaddress bits.

DIPADIP Input 2 In True Dual Port mode, this is the A port parity bus input.In Simple Dual Port mode, this is the parity bus input for thelower order bits. DIPBDIP has the higher order parity bits, ifDATA_WIDTH is 36.

DIPBDIP Input 2 In True Dual Port mode, this is the B port parity bus input.In Simple Dual Port mode, this is the parity bus input for thehigher order parity bits when DATA_WIDTH is 36. DIPADIPhas the lower order parity bits.

ADDRAWRADDR Input 13 In True Dual Port mode, this is the A port address bus. In SimpleDual Port mode, this is the address bus for the write port.

ADDRBRDADDR Input 13 In True Dual Port mode, this is the B port address bus. In SimpleDual Port mode, this is the address bus for the read port.

WEAWEL Input 2 In True Dual Port mode, this is the A port write enable. InSimple Dual Port mode, this is the write enable for the lowerorder bits.

WEBWEU Input 2 In True Dual Port mode, this is the B port write enable. InSimple Dual Port mode, this is the write enable for the upperorder bits when DATA_WIDTH is 36.

ENAWREN Input 1 In True Dual Port mode, this is the A port enable. In SimpleDual Port mode, this is the write enable.

ENBRDEN Input 1 In True Dual Port mode, this is the B port enable. In SimpleDual Port mode, this is the read enable.

REGCEA Input 1 In True Dual Port mode, this is the A port clock enable. InSimple Dual Port mode, this is unused and should be tied tologic 0.

REGCEBREGCE Input 1 In True Dual Port mode, this is the B port clock enable. InSimple Dual Port mode, this is the read clock enable.

RSTA Input 1 Port A output registers set/reset. This reset is configurable tobe synchronous or asynchronous, depending on the value ofthe RSTTYPE attribute.

RSTB Input 1 Port B output registers set/reset. This reset is configurable to besynchronous or asynchronous, depending on the value of theRSTTYPE attribute.

CLKAWRCLK Input 1 In True Dual Port mode, this is the A port clock input. In SimpleDual Port mode, this is the write mode clock input.

CLKBRDCLK Input 1 In True Dual Port mode, this is the B port clock input. In SimpleDual Port mode, this is the read clock input.

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Chapter 3: About Design Elements

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

DATA_WIDTH_A Integer 0, 1, 2, 4, 9, 18, 36 0 Specifies the configurable data width forPorts A. Data width of 36 only available inRAM_MODE=SDP.

DATA_WIDTH_B Integer 0, 1, 2, 4, 9, 18, 36 0 Specifies the configurable data width forPorts B. Data width of 36 only available inRAM_MODE=SDP.

DOA_REG Integer 0, 1 0 Specifies to use or bypass the outputregisters for the RAM.

DOB_REG Integer 0, 1 0 Specifies to use or bypass the outputregisters for the RAM.

EN_RSTRAM_A String “TRUE”, “FALSE” “TRUE” Specifies if the reset capability on theoutput latches is enabled.

EN_RSTRAM_B String “TRUE”, “FALSE” “TRUE” Specifies if the reset capability on theoutput latches is enabled.

INIT_A Hexa-decimal

36’h000000000 to36’h68719476735

All zeros Specifies the initial value on the PortA output after configuration. In SDPmode, when DATA_WIDTH is 36, INIT_Brepresents the higher order bits [31:16]and INIT_A the lower order bits.

INIT_B Hexa-decimal

36’h000000000 to36’h68719476735

All zeros Specifies the initial value on the PortB output after configuration. In SDPmode, when DATA_WIDTH is 36, INIT_Brepresents the higher order bits [31:16]and INIT_A the lower order bits.

INIT_FILE String 0 bit String NONE Specifies the name of the file for specifyingthe initial values of the block RAM

INIT_00 toINIT_3F

Hexa-decimal

Any 256 bit value All zeros Specifies the initial contents of the 16 kbdata memory array.

INITP_01 toINITP_07

Hexa-decimal

Any 256 bit value All zeros Specifies the initial contents of the 2 kbparity data memory array.

RAM_MODE String “TDP”, “SDP” “TDP” This attribute defines the portconfiguration of the block RAM.True Dual Port (TDP) allows each port tobe used as both a read and a write port.Simple Dual Port (SDP) assigns port A asthe write port and port B as the read port.

RST_PRIORITY_A String “CE”, “SR” “CE” Specifies whether RSTA pin or ENA pin(latch mode) or REGCEA pin (outputregister mode) has priority.

RST_PRIORITY_B String “CE”, “SR” “CE” Specifies whether RSTB pin or ENB pin(latch mode) or REGCEB pin (outputregister mode) has priority.

RSTTYPE String “SYNC”, “ASYNC” “SYNC” Type of reset, synchronous orasynchronous.

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Chapter 3: About Design Elements

Attribute Type Allowed Values Default Description

SIM_COLLISION_CHECK

String “ALL”,“GENERATE_X_ONLY”,“WARNING_ONLY”,“NONE”

ALL Allows modification of the simulationbehavior so that if a memory collisionoccurs:

• ALL - Warning produced andaffected outputs/memory location gounknown (X).

• WARNING_ONLY - Warningproduced and affectedoutputs/memory location retainlast value.

• GENERATE_X_ONLY - No warning,but affected outputs/memory locationgo unknown (X).

• NONE - No warning and affectedoutputs/memory location retain lastvalue.

Note Setting this to a value other than“ALL” can allow problems in the designto go unnoticed during simulation. Careshould be taken when changing the valueof this attribute.

SRVAL_A Hexa-decimal

36’h000000000 to36’h68719476735

All zeros Specifies the output value of Port A uponthe assertion of the reset (RSTA) signal. InSDP mode, when DATA_WIDTH is 36,SRVAL_B represents the higher order bits[31:16] and SRVAL_A the lower order bits.

SRVAL_B Hexa-decimal

36’h000000000 to36’h68719476735

All zeros Specifies the output value of Port A uponthe assertion of the reset (RSTB) signal. InSDP mode, when DATA_WIDTH is 36,SRVAL_B represents the higher order bits[31:16] and SRVAL_A the lower order bits.

WRITE_MODE_A String “WRITE_FIRST”,“READ_FIRST”,“NO_CHANGE”

“WRITE_FIRST” Specifies the output behavior of Port A.

• WRITE_FIRST - Written value appearson output port of the RAM.

• READ_FIRST - Previous RAMcontents for that memory locationappear on the output port.

• NO_CHANGE - Previous value onthe output port remains the same.

WRITE_MODE_B String “WRITE_FIRST”,“READ_FIRST”,“NO_CHANGE”

“WRITE_FIRST” Specifies the output behavior of Port B.

• WRITE_FIRST - Written value appearson output port of the RAM.

• READ_FIRST - Previous RAMcontents for that memory locationappear on the output port.

• NO_CHANGE - Previous value onthe output port remains the same.

For More Information• See the Spartan-6 FPGA Block RAM User Guide• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

ROM128X1Primitive: 128-Deep by 1-Wide ROM

IntroductionThis design element is a 128-word by 1-bit read-only memory. The data output (O) reflects the word selected bythe 7-bit address (A6:A0). The ROM is initialized to a known value during configuration with the INIT=valueparameter. The value consists of 32 hexadecimal digits that are written into the ROM from the most-significantdigit A=FH to the least-significant digit A=0H. An error occurs if the INIT=value is not specified.

Logic TableInput Output

I0 I1 I2 I3 O

0 0 0 0 INIT(0)

0 0 0 1 INIT(1)

0 0 1 0 INIT(2)

0 0 1 1 INIT(3)

0 1 0 0 INIT(4)

0 1 0 1 INIT(5)

0 1 1 0 INIT(6)

0 1 1 1 INIT(7)

1 0 0 0 INIT(8)

1 0 0 1 INIT(9)

1 0 1 0 INIT(10)

1 0 1 1 INIT(11)

1 1 0 0 INIT(12)

1 1 0 1 INIT(13)

1 1 1 0 INIT(14)

1 1 1 1 INIT(15)

Design Entry MethodThis design element can be used in schematics.

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Chapter 3: About Design Elements

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 128-Bit Value All zeros Specifies the contents of the ROM.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ROM16X1Primitive: 16-Deep by 1-Wide ROM

IntroductionThis design element is a 16-word by 1-bit read-only memory. The data output (O) reflects the word selected bythe 4-bit address (A3:A0). The ROM is initialized to a known value during configuration with the INIT=valueparameter. The value consists of four hexadecimal digits that are written into the ROM from the most-significantdigit A=FH to the least-significant digit A=0H. For example, the INIT=10A7 parameter produces the data stream:0001 0000 1010 0111 An error occurs if the INIT=value is not specified.

Logic TableInput Output

I0 I1 I2 I3 O

0 0 0 0 INIT(0)

0 0 0 1 INIT(1)

0 0 1 0 INIT(2)

0 0 1 1 INIT(3)

0 1 0 0 INIT(4)

0 1 0 1 INIT(5)

0 1 1 0 INIT(6)

0 1 1 1 INIT(7)

1 0 0 0 INIT(8)

1 0 0 1 INIT(9)

1 0 1 0 INIT(10)

1 0 1 1 INIT(11)

1 1 0 0 INIT(12)

1 1 0 1 INIT(13)

1 1 1 0 INIT(14)

1 1 1 1 INIT(15)

Design Entry MethodThis design element can be used in schematics.

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Chapter 3: About Design Elements

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Specifies the contents of the ROM.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ROM256X1Primitive: 256-Deep by 1-Wide ROM

IntroductionThis design element is a 256-word by 1-bit read-only memory. The data output (O) reflects the word selected bythe 8-bit address (A7:A0). The ROM is initialized to a known value during configuration with the INIT=valueparameter. The value consists of 64 hexadecimal digits that are written into the ROM from the most-significantdigit A=FH to the least-significant digit A=0H.

An error occurs if the INIT=value is not specified.

Logic TableInput Output

I0 I1 I2 I3 O

0 0 0 0 INIT(0)

0 0 0 1 INIT(1)

0 0 1 0 INIT(2)

0 0 1 1 INIT(3)

0 1 0 0 INIT(4)

0 1 0 1 INIT(5)

0 1 1 0 INIT(6)

0 1 1 1 INIT(7)

1 0 0 0 INIT(8)

1 0 0 1 INIT(9)

1 0 1 0 INIT(10)

1 0 1 1 INIT(11)

1 1 0 0 INIT(12)

1 1 0 1 INIT(13)

1 1 1 0 INIT(14)

1 1 1 1 INIT(15)

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Chapter 3: About Design Elements

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 256-Bit Value All zeros Specifies the contents of the ROM.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ROM32X1Primitive: 32-Deep by 1-Wide ROM

IntroductionThis design element is a 32-word by 1-bit read-only memory. The data output (O) reflects the word selected bythe 5-bit address (A4:A0). The ROM is initialized to a known value during configuration with the INIT=valueparameter. The value consists of eight hexadecimal digits that are written into the ROM from the most-significantdigit A=1FH to the least-significant digit A=00H.

For example, the INIT=10A78F39 parameter produces the data stream: 0001 0000 1010 0111 1000 1111 0011 1001.An error occurs if the INIT=value is not specified.

Logic TableInput Output

I0 I1 I2 I3 O

0 0 0 0 INIT(0)

0 0 0 1 INIT(1)

0 0 1 0 INIT(2)

0 0 1 1 INIT(3)

0 1 0 0 INIT(4)

0 1 0 1 INIT(5)

0 1 1 0 INIT(6)

0 1 1 1 INIT(7)

1 0 0 0 INIT(8)

1 0 0 1 INIT(9)

1 0 1 0 INIT(10)

1 0 1 1 INIT(11)

1 1 0 0 INIT(12)

1 1 0 1 INIT(13)

1 1 1 0 INIT(14)

1 1 1 1 INIT(15)

Design Entry MethodThis design element can be used in schematics.

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Chapter 3: About Design Elements

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 32-Bit Value All zeros Specifies the contents of the ROM.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

ROM64X1Primitive: 64-Deep by 1-Wide ROM

IntroductionThis design element is a 64-word by 1-bit read-only memory. The data output (O) reflects the word selected bythe 6-bit address (A5:A0). The ROM is initialized to a known value during configuration with the INIT=valueparameter. The value consists of 16 hexadecimal digits that are written into the ROM from the most-significantdigit A=FH to the least-significant digit A=0H. An error occurs if the INIT=value is not specified.

Logic TableInput Output

I0 I1 I2 I3 O

0 0 0 0 INIT(0)

0 0 0 1 INIT(1)

0 0 1 0 INIT(2)

0 0 1 1 INIT(3)

0 1 0 0 INIT(4)

0 1 0 1 INIT(5)

0 1 1 0 INIT(6)

0 1 1 1 INIT(7)

1 0 0 0 INIT(8)

1 0 0 1 INIT(9)

1 0 1 0 INIT(10)

1 0 1 1 INIT(11)

1 1 0 0 INIT(12)

1 1 0 1 INIT(13)

1 1 1 0 INIT(14)

1 1 1 1 INIT(15)

Design Entry MethodThis design element can be used in schematics.

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Chapter 3: About Design Elements

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 64-Bit Value All zeros Specifies the contents of the ROM.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP3Macro: 3–Input Sum of Products

IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP3B1AMacro: 3–Input Sum of Products with One Inverted Input (Option A)

IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP3B1BMacro: 3–Input Sum of Products with One Inverted Input (Option B)

IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP3B2AMacro: 3–Input Sum of Products with Two Inverted Inputs (Option A)

IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP3B2BMacro: 3–Input Sum of Products with Two Inverted Inputs (Option B)

IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP3B3Macro: 3–Input Sum of Products with Inverted Inputs

IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP4Macro: 4–Input Sum of Products

IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP4B1Macro: 4–Input Sum of Products with One Inverted Input

IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP4B2AMacro: 4–Input Sum of Products with Two Inverted Inputs (Option A)

IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP4B2BMacro: 4–Input Sum of Products with Two Inverted Inputs (Option B)

IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP4B3Macro: 4–Input Sum of Products with Three Inverted Inputs

IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SOP4B4Macro: 4–Input Sum of Products with Inverted Inputs

IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SPI_ACCESSPrimitive: Internal Logic Access to the Serial Peripheral Interface (SPI) PROM Data

IntroductionThis design element allows connection from the internal logic of the FPGA to an In-System Flash (ISF) Memorycontained within the device through an SPI serial protocol. For information regarding the initialization ofSPI_ACCESS model see the Synthesis and Simulation Design Guide

Port DescriptionsPort Direction Width Function

MISO Output 1 Serial output data from the ISF Memory.

MOSI Input 1 Serial input instructions/data to the ISF Memory.

CSB Input 1 ISF Memory enable.

CLK Input 1 ISF Memory clock.

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

SIM_DEVICE String “3S50AN”,”3S200AN”,”3S400AN”,”3S700AN”,”3S1400AN

“UNSPECIFIED” Specifies the target device so thatthe proper size ISF Memory isused. This attribute must be set.

SIM_USER_ID Hexadecimal Any 64-Byte Value All locationsdefault to 0xFF

Specifies the programmed USERID in the Security Register for theISF Memory.

SIM_MEM_FILE String Specified file anddirectory name.

"NONE" Optionally specifies a hex filecontaining the initializationmemory content for the ISFMemory.

SIM_FACTORY_ID Hexadecimal Any 64-Byte Value All locationsdefault to 0xFF

Specifies the Unique Identifiervalue in the Security Register forsimulation purposes (the actualHW value will be specific to theparticular device used).

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Chapter 3: About Design Elements

Attribute Type Allowed Values Default Description

SIM_DELAY_TYPE String “ACCURATE”,“SCALED”

“SCALED” Scales down some timing delaysfor faster simulation run.

• ACCURATE - timing anddelays consistent withdatasheet specs.

• SCALED - timing numbersscaled back to run fastersimulation, behavior notaffected.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SR16CEMacro: 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear

IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel outputs (Q), and clock enable(CE) and asynchronous clear (CLR) inputs. The (CLR) input, when High, overrides all other inputs and resets thedata outputs (Q) Low. When (CE) is High and (CLR) is Low, the data on the SLI input is loaded into the firstbit of the shift register during the Low-to- High clock (C) transition and appears on the (Q0) output. Duringsubsequent Low-to- High clock transitions, when (CE) is High and (CLR) is Low, data shifts to the next highestbit position as new data is loaded into (Q0) (SLI→Q0, Q0→Q1, Q1→Q2, and so forth). The register ignores clocktransitions when (CE) is Low.

Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stageand connecting clock, (CE), and (CLR) in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE SLI C Q0 Qz : Q1

1 X X X 0 0

0 0 X X No Change No Change

0 1 SLI ↑ SLI qn-1

z = bit width - 1

qn-1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SR16CLEMacro: 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andAsynchronous Clear

IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and asynchronous clear (CLR) . The register ignoresclock transitions when (L) and (CE) are Low. The asynchronous (CLR), when High, overrides all other inputsand resets the data outputs (Q) Low. When (L) is High and (CLR) is Low, data on the Dn -D0 inputs is loadedinto the corresponding Qn -(Q0) bits of the register.

When (CE) is High and (L) and (CLR) are Low, data on the SLI input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent clocktransitions, when (CE) is High and (L) and (CLR) are Low, the data shifts to the next highest bit position as newdata is loaded into (Q)0 (for example, SLI→Q0, Q0→Q1, and Q1→Q2).

Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (CLR) inputs in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE SLI Dn : D0 C Q0 Qz : Q1

1 X X X X X 0 0

0 1 X X Dn : D0 ↑ D0 Dn

0 0 1 SLI X ↑ SLI qn-1

0 0 0 X X X No Change No Change

z = bitwidth -1

qn-1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SR16CLEDMacro: 16-Bit Shift Register with Clock Enable and Asynchronous Clear

IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q), and four control inputs: clock enable (CE), load enable (L), shift left/right (LEFT), andasynchronous clear (CLR). The register ignores clock transitions when (CE) and (L) are Low. The asynchronousclear, when High, overrides all other inputs and resets the data outputs (Qn) Low.

When (L) is High and (CLR) is Low, the data on the (D) inputs is loaded into the corresponding (Q) bits of theregister. When (CE) is High and (L) and (CLR) are Low, data is shifted right or left, depending on the state of theLEFT input. If LEFT is High, data on the SLI is loaded into (Q0) during the Low-to-High clock transition andshifted left (for example, to Q1 or Q2) during subsequent clock transitions. If LEFT is Low, data on the SRI isloaded into the last (Q) output during the Low-to-High clock transition and shifted right during subsequentclock transitions. The logic tables indicate the state of the (Q) outputs under all input conditions.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE LEFT SLI SRID15 :D0 C Q0 Q15

Q14 :Q1

1 X X X X X X X 0 0 0

0 1 X X X X D15 : D0 ↑ D0 D15 Dn

0 0 0 X X X X X NoChange

NoChange

NoChange

0 0 1 1 SLI X X ↑ SLI q14 qn-1

0 0 1 0 X SRI X ↑ q1 SRI qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition.

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SR16REMacro: 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset

IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel outputs (Qn), clock enable (CE),and synchronous reset (R) inputs. The R input, when High, overrides all other inputs during the Low-to-Highclock (C) transition and resets the data outputs (Q) Low.

When (CE) is High and (R) is Low, the data on the (SLI) is loaded into the first bit of the shift register duringthe Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent Low-to-High clocktransitions, when (CE) is High and R is Low, data shifts to the next highest bit position as new data is loaded into(Q0) (for example, SLI→Q0, Q0→Q1, and Q1→Q2). The register ignores clock transitions when (CE) is Low.

Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), and (R) in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE SLI C Q0 Qz : Q1

1 X X ↑ 0 0

0 0 X X No Change No Change

0 1 SLI ↑ SLI qn-1

z = bitwidth -1

qn-1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SR16RLEMacro: 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andSynchronous Reset

IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and synchronous reset (R). The register ignores clocktransitions when (L) and (CE) are Low. The synchronous (R), when High, overrides all other inputs during theLow-to-High clock (C) transition and resets the data outputs (Q) Low. When (L) is High and (R) is Low duringthe Low-to-High clock transition, data on the (D) inputs is loaded into the corresponding Q bits of the register.

When (CE) is High and (L) and (R) are Low, data on the (SLI) input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the Q0 output. During subsequent clocktransitions, when (CE) is High and (L) and (R) are Low, the data shifts to the next highest bit position as newdata is loaded into Q0.

Registers can be cascaded by connecting the last Q output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (R) inputs in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R L CE SLI Dz : D0 C Q0 Qz : Q1

1 X X X X ↑ 0 0

0 1 X X Dz : D0 ↑ D0 Dn

0 0 1 SLI X ↑ SLI qn-1

0 0 0 X X X No Change No Change

z = bitwidth -1

qn-1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SR16RLEDMacro: 16-Bit Shift Register with Clock Enable and Synchronous Reset

IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q) and four control inputs — clock enable (CE), load enable (L), shift left/right (LEFT), andsynchronous reset (R). The register ignores clock transitions when (CE) and (L) are Low. The synchronous (R),when High, overrides all other inputs during the Low-to-High clock (C) transition and resets the data outputs(Q) Low. When (L) is High and (R) is Low during the Low-to-High clock transition, the data on the (D) inputs isloaded into the corresponding (Q) bits of the register.

When (CE) is High and (L) and (R) are Low, data shifts right or left, depending on the state of the LEFT input.If LEFT is High, data on (SLI) is loaded into (Q0) during the Low-to-High clock transition and shifted left (forexample, to Q1 and Q2) during subsequent clock transitions. If LEFT is Low, data on the (SRI) is loaded into thelast (Q) output during the Low-to-High clock transition and shifted right ) during subsequent clock transitions.The logic tables below indicates the state of the (Q) outputs under all input conditions.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R L CE LEFT SLI SRI D15:D0 C Q0 Q15 Q14:Q1

1 X X X X X X ↑ 0 0 0

0 1 X X X X D15:D0 ↑ D0 D15 Dn

0 0 0 X X X X X NoChange

NoChange

NoChange

0 0 1 1 SLI X X ↑ SLI q14 qn-1

0 0 1 0 X SRI X ↑ q1 SRI qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SR4CEMacro: 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear

IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel outputs (Q), and clock enable(CE) and asynchronous clear (CLR) inputs. The (CLR) input, when High, overrides all other inputs and resets thedata outputs (Q) Low. When (CE) is High and (CLR) is Low, the data on the SLI input is loaded into the firstbit of the shift register during the Low-to- High clock (C) transition and appears on the (Q0) output. Duringsubsequent Low-to- High clock transitions, when (CE) is High and (CLR) is Low, data shifts to the next highestbit position as new data is loaded into (Q0) (SLI→Q0, Q0→Q1, Q1→Q2, and so forth). The register ignores clocktransitions when (CE) is Low.

Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stageand connecting clock, (CE), and (CLR) in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE SLI C Q0 Qz : Q1

1 X X X 0 0

0 0 X X No Change No Change

0 1 SLI ↑ SLI qn-1

z = bit width - 1

qn-1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SR4CLEMacro: 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andAsynchronous Clear

IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and asynchronous clear (CLR) . The register ignoresclock transitions when (L) and (CE) are Low. The asynchronous (CLR), when High, overrides all other inputsand resets the data outputs (Q) Low. When (L) is High and (CLR) is Low, data on the Dn -D0 inputs is loadedinto the corresponding Qn -(Q0) bits of the register.

When (CE) is High and (L) and (CLR) are Low, data on the SLI input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent clocktransitions, when (CE) is High and (L) and (CLR) are Low, the data shifts to the next highest bit position as newdata is loaded into (Q)0 (for example, SLI→Q0, Q0→Q1, and Q1→Q2).

Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (CLR) inputs in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE SLI Dn : D0 C Q0 Qz : Q1

1 X X X X X 0 0

0 1 X X Dn : D0 ↑ D0 Dn

0 0 1 SLI X ↑ SLI qn-1

0 0 0 X X X No Change No Change

z = bitwidth -1

qn-1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SR4CLEDMacro: 4-Bit Shift Register with Clock Enable and Asynchronous Clear

IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q), and four control inputs: clock enable (CE), load enable (L), shift left/right (LEFT), andasynchronous clear (CLR). The register ignores clock transitions when (CE) and (L) are Low. The asynchronousclear, when High, overrides all other inputs and resets the data outputs (Qn) Low.

When (L) is High and (CLR) is Low, the data on the (D) inputs is loaded into the corresponding (Q) bits of theregister. When (CE) is High and (L) and (CLR) are Low, data is shifted right or left, depending on the state of theLEFT input. If LEFT is High, data on the SLI is loaded into (Q0) during the Low-to-High clock transition andshifted left (for example, to Q1 or Q2) during subsequent clock transitions. If LEFT is Low, data on the SRI isloaded into the last (Q) output during the Low-to-High clock transition and shifted right during subsequentclock transitions. The logic tables indicate the state of the (Q) outputs under all input conditions.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE LEFT SLI SRI D3 : D0 C Q0 Q3 Q2 : Q1

1 X X X X X X X 0 0 0

0 1 X X X X D3– D0 ↑ D0 D3 Dn

0 0 0 X X X X X NoChange

NoChange

NoChange

0 0 1 1 SLI X X ↑ SLI q2 qn-1

0 0 1 0 X SRI X ↑ q1 SRI qn+1

qn-1 and qn+1 = state of referenced output one setup time prior to active clock transition.

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SR4REMacro: 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset

IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel outputs (Qn), clock enable (CE),and synchronous reset (R) inputs. The R input, when High, overrides all other inputs during the Low-to-Highclock (C) transition and resets the data outputs (Q) Low.

When (CE) is High and (R) is Low, the data on the (SLI) is loaded into the first bit of the shift register duringthe Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent Low-to-High clocktransitions, when (CE) is High and R is Low, data shifts to the next highest bit position as new data is loaded into(Q0) (for example, SLI→Q0, Q0→Q1, and Q1→Q2). The register ignores clock transitions when (CE) is Low.

Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), and (R) in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE SLI C Q0 Qz : Q1

1 X X ↑ 0 0

0 0 X X No Change No Change

0 1 SLI ↑ SLI qn-1

z = bitwidth -1

qn-1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SR4RLEMacro: 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andSynchronous Reset

IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and synchronous reset (R). The register ignores clocktransitions when (L) and (CE) are Low. The synchronous (R), when High, overrides all other inputs during theLow-to-High clock (C) transition and resets the data outputs (Q) Low. When (L) is High and (R) is Low duringthe Low-to-High clock transition, data on the (D) inputs is loaded into the corresponding Q bits of the register.

When (CE) is High and (L) and (R) are Low, data on the (SLI) input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the Q0 output. During subsequent clocktransitions, when (CE) is High and (L) and (R) are Low, the data shifts to the next highest bit position as newdata is loaded into Q0.

Registers can be cascaded by connecting the last Q output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (R) inputs in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R L CE SLI Dz : D0 C Q0 Qz : Q1

1 X X X X ↑ 0 0

0 1 X X Dz : D0 ↑ D0 Dn

0 0 1 SLI X ↑ SLI qn-1

0 0 0 X X X No Change No Change

z = bitwidth -1

qn-1 = state of referenced output one setup time prior to active clock transition

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Chapter 3: About Design Elements

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SR4RLEDMacro: 4-Bit Shift Register with Clock Enable and Synchronous Reset

IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q) and four control inputs — clock enable (CE), load enable (L), shift left/right (LEFT), andsynchronous reset (R). The register ignores clock transitions when (CE) and (L) are Low. The synchronous (R),when High, overrides all other inputs during the Low-to-High clock (C) transition and resets the data outputs(Q) Low. When (L) is High and (R) is Low during the Low-to-High clock transition, the data on the (D) inputs isloaded into the corresponding (Q) bits of the register.

When (CE) is High and (L) and (R) are Low, data shifts right or left, depending on the state of the LEFT input.If LEFT is High, data on (SLI) is loaded into (Q0) during the Low-to-High clock transition and shifted left (forexample, to Q1 and Q2) during subsequent clock transitions. If LEFT is Low, data on the (SRI) is loaded into thelast (Q) output during the Low-to-High clock transition and shifted right ) during subsequent clock transitions.The logic tables below indicates the state of the (Q) outputs under all input conditions.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R L CE LEFT SLI SRI D3 : D0 C Q0 Q3 Q2 : Q1

1 X X X X X X ↑ 0 0 0

0 1 X X X X D3 : D0 ↑ D0 D3 Dn

0 0 0 X X X X X NoChange

NoChange

NoChange

0 0 1 1 SLI X X ↑ SLI q2 qn-1

0 0 1 0 X SRI X ↑ q1 SRI qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

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Chapter 3: About Design Elements

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SR8CEMacro: 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear

IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel outputs (Q), and clock enable(CE) and asynchronous clear (CLR) inputs. The (CLR) input, when High, overrides all other inputs and resets thedata outputs (Q) Low. When (CE) is High and (CLR) is Low, the data on the SLI input is loaded into the firstbit of the shift register during the Low-to- High clock (C) transition and appears on the (Q0) output. Duringsubsequent Low-to- High clock transitions, when (CE) is High and (CLR) is Low, data shifts to the next highestbit position as new data is loaded into (Q0) (SLI→Q0, Q0→Q1, Q1→Q2, and so forth). The register ignores clocktransitions when (CE) is Low.

Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stageand connecting clock, (CE), and (CLR) in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR CE SLI C Q0 Qz : Q1

1 X X X 0 0

0 0 X X No Change No Change

0 1 SLI ↑ SLI qn-1

z = bit width - 1

qn-1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SR8CLEMacro: 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andAsynchronous Clear

IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and asynchronous clear (CLR) . The register ignoresclock transitions when (L) and (CE) are Low. The asynchronous (CLR), when High, overrides all other inputsand resets the data outputs (Q) Low. When (L) is High and (CLR) is Low, data on the Dn -D0 inputs is loadedinto the corresponding Qn -(Q0) bits of the register.

When (CE) is High and (L) and (CLR) are Low, data on the SLI input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent clocktransitions, when (CE) is High and (L) and (CLR) are Low, the data shifts to the next highest bit position as newdata is loaded into (Q)0 (for example, SLI→Q0, Q0→Q1, and Q1→Q2).

Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (CLR) inputs in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE SLI Dn : D0 C Q0 Qz : Q1

1 X X X X X 0 0

0 1 X X Dn : D0 ↑ D0 Dn

0 0 1 SLI X ↑ SLI qn-1

0 0 0 X X X No Change No Change

z = bitwidth -1

qn-1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SR8CLEDMacro: 8-Bit Shift Register with Clock Enable and Asynchronous Clear

IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q), and four control inputs: clock enable (CE), load enable (L), shift left/right (LEFT), andasynchronous clear (CLR). The register ignores clock transitions when (CE) and (L) are Low. The asynchronousclear, when High, overrides all other inputs and resets the data outputs (Qn) Low.

When (L) is High and (CLR) is Low, the data on the (D) inputs is loaded into the corresponding (Q) bits of theregister. When (CE) is High and (L) and (CLR) are Low, data is shifted right or left, depending on the state of theLEFT input. If LEFT is High, data on the SLI is loaded into (Q0) during the Low-to-High clock transition andshifted left (for example, to Q1 or Q2) during subsequent clock transitions. If LEFT is Low, data on the SRI isloaded into the last (Q) output during the Low-to-High clock transition and shifted right during subsequentclock transitions. The logic tables indicate the state of the (Q) outputs under all input conditions.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

CLR L CE LEFT SLI SRI D7 : D0 C Q0 Q7 Q6 : Q1

1 X X X X X X X 0 0 0

0 1 X X X X D7 : D0 ↑ D0 D7 Dn

0 0 0 X X X X X NoChange

NoChange

NoChange

0 0 1 1 SLI X X ↑ SLI q6 qn-1

0 0 1 0 X SRI X ↑ q1 SRI qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition.

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SR8REMacro: 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset

IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel outputs (Qn), clock enable (CE),and synchronous reset (R) inputs. The R input, when High, overrides all other inputs during the Low-to-Highclock (C) transition and resets the data outputs (Q) Low.

When (CE) is High and (R) is Low, the data on the (SLI) is loaded into the first bit of the shift register duringthe Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent Low-to-High clocktransitions, when (CE) is High and R is Low, data shifts to the next highest bit position as new data is loaded into(Q0) (for example, SLI→Q0, Q0→Q1, and Q1→Q2). The register ignores clock transitions when (CE) is Low.

Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), and (R) in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R CE SLI C Q0 Qz : Q1

1 X X ↑ 0 0

0 0 X X No Change No Change

0 1 SLI ↑ SLI qn-1

z = bitwidth -1

qn-1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SR8RLEMacro: 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andSynchronous Reset

IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and synchronous reset (R). The register ignores clocktransitions when (L) and (CE) are Low. The synchronous (R), when High, overrides all other inputs during theLow-to-High clock (C) transition and resets the data outputs (Q) Low. When (L) is High and (R) is Low duringthe Low-to-High clock transition, data on the (D) inputs is loaded into the corresponding Q bits of the register.

When (CE) is High and (L) and (R) are Low, data on the (SLI) input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the Q0 output. During subsequent clocktransitions, when (CE) is High and (L) and (R) are Low, the data shifts to the next highest bit position as newdata is loaded into Q0.

Registers can be cascaded by connecting the last Q output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (R) inputs in parallel.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R L CE SLI Dz : D0 C Q0 Qz : Q1

1 X X X X ↑ 0 0

0 1 X X Dz : D0 ↑ D0 Dn

0 0 1 SLI X ↑ SLI qn-1

0 0 0 X X X No Change No Change

z = bitwidth -1

qn-1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SR8RLEDMacro: 8-Bit Shift Register with Clock Enable and Synchronous Reset

IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q) and four control inputs — clock enable (CE), load enable (L), shift left/right (LEFT), andsynchronous reset (R). The register ignores clock transitions when (CE) and (L) are Low. The synchronous (R),when High, overrides all other inputs during the Low-to-High clock (C) transition and resets the data outputs(Q) Low. When (L) is High and (R) is Low during the Low-to-High clock transition, the data on the (D) inputs isloaded into the corresponding (Q) bits of the register.

When (CE) is High and (L) and (R) are Low, data shifts right or left, depending on the state of the LEFT input.If LEFT is High, data on (SLI) is loaded into (Q0) during the Low-to-High clock transition and shifted left (forexample, to Q1 and Q2) during subsequent clock transitions. If LEFT is Low, data on the (SRI) is loaded into thelast (Q) output during the Low-to-High clock transition and shifted right ) during subsequent clock transitions.The logic tables below indicates the state of the (Q) outputs under all input conditions.

This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.

Logic TableInputs Outputs

R L CE LEFT SLI SRI D7 : D0 C Q0 Q7 Q6 : Q1

1 X X X X X X ↑ 0 0 0

0 1 X X X X D7 : D0 ↑ D0 D7 Dn

0 0 0 X X X X X NoChange

NoChange

NoChange

0 0 1 1 SLI X X ↑ SLI q6 qn-1

0 0 1 0 X SRI X ↑ q1 SRI qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

Design Entry MethodThis design element is only for use in schematics.

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Chapter 3: About Design Elements

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SRL16Primitive: 16-Bit Shift Register Look-Up Table (LUT)

IntroductionThis design element is a shift register look-up table (LUT). The inputs A3, A2, A1, and A0 select the outputlength of the shift register.

The shift register can be of a fixed, static length or it can be dynamically adjusted.• To create a fixed-length shift register -Drive the A3 through A0 inputs with static values. The length of

the shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.

• To change the length of the shift register dynamically -Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.

The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transition. Duringsubsequent Low-to-High clock transitions data shifts to the next highest bit position while new data is loaded.The data appears on the Q output when the shift register length determined by the address inputs is reached.

Logic TableInputs Output

Am CLK D Q

Am X X Q(Am)

Am ↑ D Q(Am - 1)

m= 0, 1, 2, 3

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Sets the initial value of Q output afterconfiguration.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SRL16_1Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Negative-Edge Clock

IntroductionThis design element is a shift register look-up table (LUT). The inputs A3, A2, A1, and A0 select the outputlength of the shift register.

The shift register can be of a fixed, static length or it can be dynamically adjusted.• To create a fixed-length shift register -Drive the A3 through A0 inputs with static values. The length of

the shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.

• To change the length of the shift register dynamically -Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.

The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

The data (D) is loaded into the first bit of the shift register during the High-to-Low clock (CLK) transition. Duringsubsequent High-to-Low clock transitions data shifts to the next highest bit position as new data is loaded. Thedata appears on the Q output when the shift register length determined by the address inputs is reached.

Logic TableInputs Output

Am CLK D Q

Am X X Q(Am)

Am ↓ D Q(Am - 1)

m= 0, 1, 2, 3

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Sets the initial value of Q output afterconfiguration

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Chapter 3: About Design Elements

SRL16EPrimitive: 16-Bit Shift Register Look-Up Table (LUT) with Clock Enable

IntroductionThis design element is a shift register look-up table (LUT). The inputs A3, A2, A1, and A0 select the outputlength of the shift register.

The shift register can be of a fixed, static length or it can be dynamically adjusted.

• To create a fixed-length shift register -Drive the A3 through A0 inputs with static values. The length ofthe shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.

• To change the length of the shift register dynamically -Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.

The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

When CE is High, the data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK)transition. During subsequent Low-to-High clock transitions, when CE is High, data shifts to the next highest bitposition as new data is loaded. The data appears on the Q output when the shift register length determined bythe address inputs is reached. When CE is Low, the register ignores clock transitions.

Logic TableInputs Output

Am CE CLK D Q

Am 0 X X Q(Am)

Am 1 ↑ D Q(Am - 1)

m= 0, 1, 2, 3

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Chapter 3: About Design Elements

Port DescriptionsPort Direction Width Function

Q Output 1 Shift register data output

D Input 1 Shift register data input

CLK Input 1 Clock

CE Input 1 Active high clock enable

A Input 4 Dynamic depth selection of the SRL

• A=0000 ==> 1-bit shift length

• A=1111 ==> 16-bit shift length

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexa-decimal

Any 16-Bit Value All zeros Sets the initial value of content and output of shiftregister after configuration.

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Chapter 3: About Design Elements

SRL16E_1Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Negative-Edge Clock and Clock Enable

IntroductionThis design element is a shift register look-up table (LUT) with clock enable (CE). The inputs A3, A2, A1,and A0 select the output length of the shift register.

The shift register can be of a fixed, static length or it can be dynamically adjusted.• To create a fixed-length shift register -Drive the A3 through A0 inputs with static values. The length of

the shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.

• To change the length of the shift register dynamically -Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.

The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

When CE is High, the data (D) is loaded into the first bit of the shift register during the High-to-Low clock (CLK)transition. During subsequent High-to-Low clock transitions, when CE is High, data is shifted to the next highestbit position as new data is loaded. The data appears on the Q output when the shift register length determinedby the address inputs is reached. When CE is Low, the register ignores clock transitions.

Logic TableInputs Output

Am CE CLK D Q

Am 0 X X Q(Am)

Am 1 ↓ D Q(Am - 1)

m= 0, 1, 2, 3

Design Entry MethodThis design element can be used in schematics.

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Hexadecimal Any 16-BitValue

All zeros Sets the initial value of content and output of shiftregister after configuration.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SRLC16Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Carry

IntroductionThis design element is a shift register look-up table (LUT) with Carry. The inputs A3, A2, A1, and A0 select theoutput length of the shift register.

The shift register can be of a fixed, static length or it can be dynamically adjusted.• To create a fixed-length shift register -Drive the A3 through A0 inputs with static values. The length of

the shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.

• To change the length of the shift register dynamically -Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.

The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transition. Duringsubsequent Low-to-High clock transitions data shifts to the next highest bit position as new data is loaded. Thedata appears on the Q output when the shift register length determined by the address inputs is reached.

Note The Q15 output is available for you in cascading to multiple shift register LUTs to create larger shiftregisters.

Logic TableInputs Output

Am CLK D Q

Am X X Q(Am)

Am ↑ D Q(Am - 1)

m= 0, 1, 2, 3

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Sets the initial value of content and output of shiftregister after configuration.

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Chapter 3: About Design Elements

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SRLC16_1Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Carry and Negative-Edge Clock

IntroductionThis design element is a shift register look-up table (LUT) with carry and a negative-edge clock. The inputs A3,A2, A1, and A0 select the output length of the shift register.

The shift register can be of a fixed, static length or it can be dynamically adjusted.

• To create a fixed-length shift register -Drive the A3 through A0 inputs with static values. The length ofthe shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.

• To change the length of the shift register dynamically -Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.

The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

Note The Q15 output is available for your use in cascading multiple shift register LUTs to create larger shiftregisters.

Logic TableInputs Output

Am CLK D Q Q15

Am X X Q(Am) No Change

Am ↓ D Q(Am - 1) Q14

m= 0, 1, 2, 3

Design Entry MethodThis design element can be used in schematics.

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Sets the initial value of content and output of shiftregister after configuration.

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Chapter 3: About Design Elements

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Chapter 3: About Design Elements

SRLC16EPrimitive: 16-Bit Shift Register Look-Up Table (LUT) with Carry and Clock Enable

IntroductionThis design element is a shift register look-up table (LUT) with carry and clock enable. The inputs A3, A2, A1,and A0 select the output length of the shift register.

The shift register can be of a fixed, static length or it can be dynamically adjusted.

• To create a fixed-length shift register -Drive the A3 through A0 inputs with static values. The length ofthe shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.

• To change the length of the shift register dynamically -Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.

The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transition.When CE is High, during subsequent Low-to-High clock transitions, data shifts to the next highest bit positionas new data is loaded. The data appears on the Q output when the shift register length determined by theaddress inputs is reached.

Note The Q15 output is available for you in cascading to multiple shift register LUTs to create larger shiftregisters.

Logic TableInputs Output

Am CLK CE D Q Q15

Am X 0 X Q(Am) Q(15)

Am X 1 X Q(Am) Q(15)

Am ↑ 1 D Q(Am - 1) Q15

m= 0, 1, 2, 3

Design Entry MethodThis design element can be used in schematics.

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Chapter 3: About Design Elements

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexadecimal Any 16-Bit Value All zeros Sets the initial value of content and output of shiftregister after configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SRLC16E_1Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Carry, Negative-Edge Clock, and ClockEnable

IntroductionThis design element is a shift register look-up table (LUT) with carry, clock enable, and negative-edge clock. Theinputs A3, A2, A1, and A0 select the output length of the shift register.

The shift register can be of a fixed, static length or it can be dynamically adjusted.

• To create a fixed-length shift register -Drive the A3 through A0 inputs with static values. The length ofthe shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.

• To change the length of the shift register dynamically -Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.

The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

When CE is High, the data (D) is loaded into the first bit of the shift register during the High-to-Low clock (CLK)transition. During subsequent High-to-Low clock transitions data shifts to the next highest bit position as newdata is loaded when CE is High. The data appears on the Q output when the shift register length determined bythe address inputs is reached.

Note The Q15 output is available for your use in cascading multiple shift register LUTs to create larger shiftregisters.

Logic TableInputs Output

Am CE CLK D Q Q15

Am 0 X X Q(Am) No Change

Am 1 X X Q(Am) No Change

Am 1 ↓ D Q(Am -1 ) Q14

m= 0, 1, 2, 3

Design Entry MethodThis design element can be used in schematics.

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Chapter 3: About Design Elements

Available Attributes

Attribute TypeAllowedValues Default Description

INIT Hexadecimal Any 16-BitValue

All zeros Sets the initial value of content and output of shift registerafter configuration.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

SRLC32EPrimitive: 32 Clock Cycle, Variable Length Shift Register Look-Up Table (LUT) with Clock Enable

IntroductionThis design element is a variable length, 1 to 32 clock cycle shift register implemented within a single look-uptable (LUT). The shift register can be of a fixed length, static length, or it can be dynamically adjusted by changingthe address lines to the component. This element also features an active, high-clock enable and a cascadingfeature in which multiple SRLC32Es can be cascaded in order to create greater shift lengths.

Port DescriptionsPort Direction Width Function

Q Output 1 Shift register data output

Q31 Output 1 Shift register cascaded output (connect to the D inputof a subsequent SRLC32E)

D Input 1 Shift register data input

CLK Input 1 Clock

CE Input 1 Active high clock enable

A Input 5 Dynamic depth selection of the SRL

A=00000 ==> 1-bit shift length

A=11111 ==> 32-bit shift length

Design Entry MethodThis design element can be used in schematics.

If instantiated, the following connections should be made to this component:• Connect the CLK input to the desired clock source, the D input to the data source to be shifted/stored and the

Q output to either an FDCPE or an FDRSE input or other appropriate data destination.• The CE clock enable pin can be connected to a clock enable signal in the design or else tied to a logic one

if not used.• The 5-bit A bus can either be tied to a static value between 0 and 31 to signify a fixed 1 to 32 bit static shift

length, or else it can be tied to the appropriate logic to enable a varying shift depth anywhere between 1and 32 bits.

• If you want to create a longer shift length than 32, connect the Q31 output pin to the D input pin of asubsequent SRLC32E to cascade and create larger shift registers.

• It is not valid to connect the Q31 output to anything other than another SRLC32E.• The selectable Q output is still available in the cascaded mode, if needed.• An optional INIT attribute consisting of a 32-bit Hexadecimal value can be specified to indicate the initial

shift pattern of the shift register.• (INIT[0] will be the first value shifted out.)

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Chapter 3: About Design Elements

Available AttributesAttribute Type Allowed Values Default Description

INIT Hexa-decimal

Any 32-Bit Value All zeros Specifies the initial shift pattern of theSRLC32E.

For More Information• See the Spartan-6 FPGA Configurable Logic Block User Guide.

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

STARTUP_SPARTAN6Primitive: Spartan®-6 Global Set/Reset, Global 3-State and Configuration Start-Up Clock Interface

IntroductionThis design element is used to either interface device pins and logic to the Global Set/Reset (GSR) signal, or forGlobal Tristate (GTS) dedicated routing. This primitive can also be used to specify a different clock for the devicestartup sequence at the end of device configuration.

Port DescriptionsPort Type Width Function

CFGCLK Output 1 Configuration logic main clock output.

CFGMCLK Output 1 Configuration internal oscillator clock output. Fixed frequency: 50MHzat typical condition.

CLK Input 1 Input connection to the configuration startup sequence clock (StartClk)routing.

EOS Output 1 Indicates end of startup.

GSR Input 1 Input connection to the Global Set/Reset (GSR) routing.

GTS Input 1 Input connection to the Global Tristate (GTS) routing.

KEYCLEARB Input 1 Clear BBR key when it is set. Note that this signal needs to stay low for200ns (4 clock cycles) to enable KEYCLEAR function (to prevent glitches).

Design Entry MethodThis design element can be used in schematics.

To use the dedicated GSR circuitry, connect the sourcing pin or logic to the GSR pin. However, avoid using theGSR circuitry of this component unless certain precautions are taken first. Since the skew of the GSR net cannotbe guaranteed, either use general routing for the set/reset signal in which routing delays and skew can becalculated as a part of the timing analysis of the design, or to take preventative measures to ensure that possibleskew on the release of the clock cycle does not interfere with circuit operation.

Similarly, if the dedicated global 3-state is used, connect the appropriate sourcing pin or logic to the GTS inputpin of the primitive. To specify a clock for the startup sequence of configuration, connect a clock from thedesign to the CLK pin of this design element.

For More Information• See the Spartan-6 FPGA Configuration User Guide• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

SUSPEND_SYNCPrimitive: Suspend Mode Access

IntroductionThis design element extends the capabilities of the user to synchronize the design for applications using thesuspend mode. It uses a three pin interface to allow synchronization of the trigger to start the suspend mode,even when there are several clock domains requiring synchronization. SREQ outputs a request to the fabric tobegin a suspend mode. SACK acknowledges that the fabric is ready to start the suspend mode. The SACK pin issynchronous to the CLK pin.

Port DescriptionsPort Type Width Function

CLK Input 1 User clock.

SACK Input 1 SUSPEND acknowledgement; synchronous to CLK.

SREQ Output 1 Suspend request from either SUSPEND pin.

Design Entry MethodThis design element can be used in schematics.

For More Information• See the Spartan-6 FPGA Configuration User Guide

• See the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

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Chapter 3: About Design Elements

VCCPrimitive: VCC-Connection Signal Tag

IntroductionThis design element serves as a signal tag, or parameter, that forces a net or input function to a logic High level.A net tied to this element cannot have any other source.

When the placement and routing software encounters a net or input function tied to this element, it removes anylogic that is disabled by the Vcc signal, which is only implemented when the disabled logic cannot be removed.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XNOR2Primitive: 2-Input XNOR Gate with Non-Inverted Inputs

IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Logic TableInput Output

I0 ... Iz O

Odd number of 1 0

Even number of 1 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XNOR3Primitive: 3-Input XNOR Gate with Non-Inverted Inputs

IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Logic TableInput Output

I0 ... Iz O

Odd number of 1 0

Even number of 1 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 645

Chapter 3: About Design Elements

XNOR4Primitive: 4-Input XNOR Gate with Non-Inverted Inputs

IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Logic TableInput Output

I0 ... Iz O

Odd number of 1 0

Even number of 1 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XNOR5Primitive: 5-Input XNOR Gate with Non-Inverted Inputs

IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Logic TableInput Output

I0 ... Iz O

Odd number of 1 0

Even number of 1 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XNOR6Macro: 6-Input XNOR Gate with Non-Inverted Inputs

IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Logic TableInput Output

I0 ... Iz O

Odd number of 1 0

Even number of 1 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XNOR7Macro: 7-Input XNOR Gate with Non-Inverted Inputs

IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Logic TableInput Output

I0 ... Iz O

Odd number of 1 0

Even number of 1 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 649

Chapter 3: About Design Elements

XNOR8Macro: 8-Input XNOR Gate with Non-Inverted Inputs

IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Logic TableInput Output

I0 ... Iz O

Odd number of 1 0

Even number of 1 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XNOR9Macro: 9-Input XNOR Gate with Non-Inverted Inputs

IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Logic TableInput Output

I0 ... Iz O

Odd number of 1 0

Even number of 1 1

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 651

Chapter 3: About Design Elements

XOR2Primitive: 2-Input XOR Gate with Non-Inverted Inputs

IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XOR3Primitive: 3-Input XOR Gate with Non-Inverted Inputs

IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XOR4Primitive: 4-Input XOR Gate with Non-Inverted Inputs

IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XOR5Primitive: 5-Input XOR Gate with Non-Inverted Inputs

IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 655

Chapter 3: About Design Elements

XOR6Macro: 6-Input XOR Gate with Non-Inverted Inputs

IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XOR7Macro: 7-Input XOR Gate with Non-Inverted Inputs

IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 657

Chapter 3: About Design Elements

XOR8Macro: 8-Input XOR Gate with Non-Inverted Inputs

IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XOR9Macro: 9-Input XOR Gate with Non-Inverted Inputs

IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.

Design Entry MethodThis design element is only for use in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

Spartan-6 Libraries Guide for Schematic DesignsUG616 (v 11.4) December 2, 2009 www.xilinx.com 659

Chapter 3: About Design Elements

XORCYPrimitive: XOR for Carry Logic with General Output

IntroductionThis design element is a special XOR with general O output that generates faster and smaller arithmeticfunctions. The XORCY primitive is a dedicated XOR function within the carry-chain logic of the slice. It allowsfor fast and efficient creation of arithmetic (add/subtract) or wide logic functions (large AND/OR gate).

Logic TableInput Output

LI CI O

0 0 0

0 1 1

1 0 1

1 1 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XORCY_DPrimitive: XOR for Carry Logic with Dual Output

IntroductionThis design element is a special XOR that generates faster and smaller arithmetic functions.

Logic TableInput Output

LI CI O and LO

0 0 0

0 1 1

1 0 1

1 1 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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Chapter 3: About Design Elements

XORCY_LPrimitive: XOR for Carry Logic with Local Output

IntroductionThis design element is a special XOR with local LO output that generates faster and smaller arithmetic functions.

Logic TableInput Output

LI CI LO

0 0 0

0 1 1

1 0 1

1 1 0

Design Entry MethodThis design element can be used in schematics.

For More InformationSee the Spartan-6 FPGA User Documentation (User Guides and Data Sheets).

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