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Xilinx FPGA Development Environment
Tutorial
Eric MacDonald
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Basic Flow
Verilog RTL files (.v)
User’s Constraint File (.ucf) pin assignment, timing
synthesis place route
Xilinx ISE
configure
rom fpga
USB to JTAG
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Create “New Project”
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Go to directory containing existing RTL and UCF files. I prefer to have subdirectory to this for the many Intermediate files generated by Xylinx – called “xylinx”
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Select the correct device.
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Add existing source files – including UCF and simulation files. Don’t “copy to project” unless you want the files moved to the xylinx sub-folder.
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Constraints Files - *.ucf
I prefer to use text based files, but it is also possible to use the “user’s constraints” gui.
At a minimum, you need to specify pins to ports and a required speed.
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Verify the added files.
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Design Files
Implementation Process Steps
Output Log
Double click final synthesis step to start implementation
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Synthesis in process
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Synthesis complete With timing results And *.bit file for programming
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Double click the step for configure device under “Generate Programming File”
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Devices on the JTAG Boundary Scan chain self-identify. Some boards (i.e. BASYS) have proprietary software