xfel 2d pixel clock and control system train builder meeting, desy 23 april 2009 martin postranecky...

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XFEL 2D Pixel Clock and Control System XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY Train Builder Meeting, DESY 23 April 2009 23 April 2009 Martin Postranecky Martin Postranecky Matt Warren, Matthew Wing Matt Warren, Matthew Wing

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Page 1: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

XFEL 2D Pixel Clock and Control SystemXFEL 2D Pixel Clock and Control System

Train Builder Meeting, DESYTrain Builder Meeting, DESY

23 April 200923 April 2009

Martin PostraneckyMartin PostraneckyMatt Warren, Matthew WingMatt Warren, Matthew Wing

Page 2: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 2

μTCA Crate

Timing Receiver

Cra

te

Pro

cess

or

100 MHz Clock

Start/Info/Stop

Bunch Veto

FEE Status

C+C MasterFEE

C+C Fanout

C+C Fanout

C+C FanoutFEE

FEE

5MH

z C

lock

Trig

ger

+

Tel

egra

m ID

Bunch Veto

4

FEE

4C+C

FanoutSlave

XF

EL Timing

InterfaceOth

er1-

20M

Hz?

Clo

ck

Trig

/Dat

a

OverviewOverview

MINIMUM FANOUT REQUIREMENTS :

16 + Fanouts, expandable3x Outputs ( diff. LVDS, STP/UTP )1x Input ( single line, level only )

Page 3: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 3

1) TRIGGER “Telegram” from TR : same line TRIGGER, with Train ID & Pattern ID1) TRIGGER “Telegram” from TR : same line TRIGGER, with Train ID & Pattern ID

2) FEE feedback line : Status only ( e.g. Normally floating high, pulled low by FEE2) FEE feedback line : Status only ( e.g. Normally floating high, pulled low by FEE

when powered ), no other informationwhen powered ), no other information

3) External clock input at other test sites :use PLL ( to ~ 1-20 MHz range input ) 3) External clock input at other test sites :use PLL ( to ~ 1-20 MHz range input )

4) Bunch Veto signal – synchronised to the 100MHz4) Bunch Veto signal – synchronised to the 100MHz

5) Calibration Pattern distributed by LAN from RC5) Calibration Pattern distributed by LAN from RC

6) Veto Disable Pattern by LAN from RC6) Veto Disable Pattern by LAN from RC

7) 100 MHz clock output : - max. jitter to be specified by users7) 100 MHz clock output : - max. jitter to be specified by users

- programmable delay / step size to be specified - programmable delay / step size to be specified

8) Output Clock / Start/Stop pulses phase relationship : 8) Output Clock / Start/Stop pulses phase relationship :

- same cable length for all FEEs- same cable length for all FEEs

Information / Questions & Answers -Information / Questions & Answers -1-1-

Page 4: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 4

9) Connection between C+C Master and FanOuts : - on custom backplane all signals / 9) Connection between C+C Master and FanOuts : - on custom backplane all signals / FEE feedbacks only ??FEE feedbacks only ?? - use single or double FanOut layer ??- use single or double FanOut layer ?? - TBD by C&C- TBD by C&C

10) C+C FanOut cards : - separate power on backplane => not TCA-intelligent cards ??10) C+C FanOut cards : - separate power on backplane => not TCA-intelligent cards ?? - separate ‘dumb’ FanOut cards and crate ??- separate ‘dumb’ FanOut cards and crate ?? - on / near detector => fewer cables ?? - on / near detector => fewer cables ?? - TBD by C&C- TBD by C&C

11) LVDS connectors : - RJ45 – bulky, 4-pairs only, but can use 2x LEDs11) LVDS connectors : - RJ45 – bulky, 4-pairs only, but can use 2x LEDs - Double-stack RJ45 – availability / height ??- Double-stack RJ45 – availability / height ?? - HDMI - size / more signal pairs / more grounds/shielding ??- HDMI - size / more signal pairs / more grounds/shielding ??

- Double stack HDMI - size ?? - Double stack HDMI - size ?? - mini-HDMI ??- mini-HDMI ?? - TBD by C&C- TBD by C&C

12) No 12) No C&C System interface to MPS ( Machine Protection System ) C&C System interface to MPS ( Machine Protection System )

13) NO confirmation that the 5MHz PLL derived TR board clock is 13) NO confirmation that the 5MHz PLL derived TR board clock is "clean" and has no glitches ???"clean" and has no glitches ???

Information / Questions & Answers -Information / Questions & Answers -2-2-

Page 5: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 5

Connector SurveyConnector SurveyConnectorConnector ContactsContacts Bandwidth LatchBandwidth Latch Cable LengthCable Length

RJ45RJ45 8 ( 4x UTP )8 ( 4x UTP ) >100 MHz>100 MHz YY > 10 m> 10 m

HDMIHDMI 10 ( 4x STP,10 ( 4x STP, 160 / 340 MHz160 / 340 MHz N /Y(?)N /Y(?) 5 - 15 m5 - 15 m

1x UTP )1x UTP )

Mini-HDMIMini-HDMI 10 ( 4x STP,10 ( 4x STP, 340 MHz340 MHz NN 5 m5 m

1x UTP )1x UTP )

DisplayPortDisplayPort 10 ( 5x STP )10 ( 5x STP ) 340 MHz340 MHz YY 5 m5 m

USBUSB 4 4 >100 MHz>100 MHz NN 5 m5 m

Mini/Micro USBMini/Micro USB 5 5 >100 MHz>100 MHz NN 5 m5 m

Page 6: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 6

Front Panels & ConnectorsFront Panels & Connectors

73.8

0 m

m

148.

80 m

m

28.95 mm 28.95 mm

23.60 mm23.60 mm

53.8

5 m

m

135.

85 m

m

RJ45

HDMI

USB

Mini-USB

Micro-USBDisplayPort

Mini-HDMI

16.5

13.5

13.5

13.5

25.5

32

53 /

64

53 /

64

6.75

6.65

3.2

6.2 18.5

4

3

15

2520

2525

1610

8

16

8

10

10

10

4

5

5

AMC – MicroTCA

Front Panels

“Full” Size

Single

Double

?13

5.85

mm

Page 7: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 7

Front Panels & ConnectorsFront Panels & Connectors

23.60 mm

135.

85 m

m

7x RJ45

56

8x DisplayPort

80Maximum total number of contacts per card

Maximum number of connectors per card

10x Mini-HDMI

80

8x HDMI

80

Page 8: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 8

DoubleDouble

5x FanOuts

PROTOTYPE MASTER / FANOUT FANOUTSFINAL MASTER

1x Input 1x Input

5x Outputs to Fanouts

6x Fan-Outs

Max. 30 per

Master

DoubleDouble

FEE Status On Backplane

Proposal – Option A : 6x RJ45Proposal – Option A : 6x RJ45

Test Connectors/LEDs

Page 9: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 9

Double

Proposal – Option B : 7x Proposal – Option B : 7x DisplayPortDisplayPort

Double DoubleDouble

PROTOTYPE MASTER / FANOUT FINAL MASTER FANOUTS

6x FanOuts

1x Input

1x Input

6x Outputs to Fanouts

FEE Status On Backplane

7x Fan-Outs

Max. 42 per

Master

Test Connectors/LEDs

Page 10: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 1

0

BUT ( there is always a ‘but’…. )BUT ( there is always a ‘but’…. )

http://www.ttiinc.com/object/fp_tyco_stackedrj45.html

Just found…2x4, 2x6, 2x8

TYCO Stacked

RJ45s for ATCA/AMC

Page 11: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 1

1

Stacked RJ45 Modular Jacks for AdvancedTCAStacked RJ45 Modular Jacks for AdvancedTCA

Tyco Electronics Stacked RJ45 Modular Jacks for AdvancedTCATyco Electronics Stacked RJ45 Modular Jacks for AdvancedTCA

Tyco Electronics has released new stacked RJ45 modular jacks Tyco Electronics has released new stacked RJ45 modular jacks designed to meet both AdvancedTCA and AMC standards.designed to meet both AdvancedTCA and AMC standards.

The offset has been designed to fit the faceplate and board layout in The offset has been designed to fit the faceplate and board layout in AdvancedTCA and full size AMC modules, while providing the port AdvancedTCA and full size AMC modules, while providing the port density of the stacked configurationdensity of the stacked configuration

These jacks are shielded and include panel ground springs for EMI These jacks are shielded and include panel ground springs for EMI containment.containment.

• Offset designed to meet both ATCA and AMC standards Offset designed to meet both ATCA and AMC standards

• Category 5 performanceCategory 5 performance

• Press-fit termination to the boardPress-fit termination to the board

• Available in 2x1, 2x4, 2x6, and 2x8 configurationsAvailable in 2x1, 2x4, 2x6, and 2x8 configurations

• Available with various LED optionsAvailable with various LED options

Page 12: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 1

2

Modular Jacks 2x8 OFFSET STACKED W/GROUND CLIPModular Jacks 2x8 OFFSET STACKED W/GROUND CLIP

Tyco Electronics / AMP

Part No: 1888654-3

Modular Jacks 2x8 OFFSET STACKED W/GROUND CLIP

NOT YET RELEASED FOR PRODUCTION - NOT YET AVAILABLE

http://www.ttiinc.com/page/search_results.html?step=buyNow&searchTerms=%201888654-3+Tyco

Page 13: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 1

3

Possible Best Option…..:Possible Best Option…..:

Double

16x FanOuts

1x Input

COMBINED MASTER / FANOUT

?

Page 14: XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing

23 April 2009 C+C 1

4

End…..End…..