WISDOMWISDOMWP4 – Optical Processing Sub-System Development

• Start M06, finish M30• UCC lead

• Plans for next 6 months:– Begin firmware/control work– Focus on initial hybrid integrated photonic

devices– Develop driver/control boards– Incorporate 3mm long SOAs in optical modules– Start work on higher index contrast passive

waveguides

WISDOMWISDOMTwin Regenerator

Motherboard chip

Hybrid design showing SOA array in place

Silicon daughterboard

Semiconductor optical amplifier array (SOA)

Passive pigtailingarrowhead

WISDOMWISDOMOther devices

• Basic regenerator

• XOR gate – Includes time delay

structures

• 2x2 switch fabric

Integration approach is transparent to passive waveguide device structures. Long path length (cm’s to metre) possible

WISDOMWISDOMDriver Board

• Requirements:– Constant current sources for SOAs (0-1A)– Current sources for phase shifter heaters (0-

150mA)– Thermoelectric temperature control– Control algorithm for MZI bias setting

WISDOMWISDOM3mm v 2mm SOAs

• Comparison of gain recovery

• 3mm fully recovers in ~ 25ps (40Gb/s bit time)

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

-25 0 25 50 75

Time (ps)

New NL-SOA

StandardNL-SOA

WISDOMWISDOM160Gbit/s XOR gate

• Uses 3mm SOA• 2 MZI in a master MZI• Should be much

faster switch thanprevious design

WISDOMWISDOMFYI optical memory

- principle

Clock

Data

Loop (L)

Output&

Clock 1

Data 1

Loop (L)

Output 1&

&

Clock 2

Data 2Output 2

• DTI ModeMap project

Wavelength conversion

Loop length fixes memory capacity

WISDOMWISDOMFYI optical memory

- implementation

• Uses:– ≈ 1/3 of a ø150cm wafer– 6 quads

• Technology Δ = 0.75%• Will need to move to 2% Δ to reduce size