wistron akita unlocked

Download Wistron Akita Unlocked

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http://hobi-elektronika.net Akita Block Diagram4 3 2

1

SYSTEM DC/DCTPS51120INPUTS OUTPUTS5V_S5 DCBATOUT 3V_S5D

D

CLK GEN ICS9543053

Intel CPUYonah/Merom4,5

Project code : 91.4F501.001 PCB P/N : 05232 Revision : SDRGB CRT

SYSTEM DC/DCMAX8743CRT13

Host BUS 533/667MHzLVDS

INPUTSDCBATOUT

OUTPUTS1D05V_S0 1D8V_S3

LCD

14

DDRII Slot 0 533/667 11 DDRII 533/667 Slot 111

DDRII 667 Channel A

DDR II 667 Channel B

Calistoga GM6,7,8,9,10

SVIDEO PCIE x 16

TVOUT 13

MAXIM CHARGERMAX8725INPUTS OUTPUTS BT+DCBATOUT 18V 5V 3.0A 100mAC

C

139423

1394

SD/SDIO/MMC MS/MS Pro/xD 23

Ricoh R5C832CardReader22,23

DMI I/F 100MHzPCI

CAMERA30 BLUE TOOTH 30USB 2.0

CPU DC/DCMAX8736ETLINPUTSDCBATOUT

USB x 3 21

RJ45 CONN 25

10/100 NIC Intel 82562ET

OUTPUTS VCC_CORE

LCI PCIE x 1

ICH7-MSATA HDD20

0.844~1.3V 44A

PATAB

ODD

20

RJ11 CONN 25 INTERNAL ARRAY MIC MIC IN LINE OUT SPDIF

MODEM

HD Audio LPC Bus15,16,17,18

PCB LAYERL1: L2: L3: Signal 1 GND Signal 2 Signal 3 VCC Signal 4

B

AMOMWAKIKIPCIE x 1

PCIE x 1 USB 2.0 x 1

AUDIO CODECRicoh R553826

PCIE+USB 2.0

KBC ENE KB3910SF29

L4: L5: L6: Flash ROM 1MB 31

A

OP AMP APA2031

28

New Card26

Mini-Card 802.11a/b/g24

Mini-Card

Capacity Button

Touch Pad 30

Int. KB30

CIR30

Thermal & Fan G792 19

A

Wistron Corporation

2CH SPEAKER5

DOCKCRT MIC IN LINE OUT4

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

S/PDIF

TVOUT

10/100 Ethernet3

Title

CIR2

Block DiagramSize A3 Document Number Rev

AkitaSheet1

SD1 of 39

Date: Monday, February 06, 2006

A

Calistoga Strapping Signals and Configuration page 7Pin Name CFG[2:0] Strap Description FSB Frequency Select Configuration 001 = FSB533 011 = FSB667 others = Reserved

http://hobi-elektronika.netB C D

E

125CV Spread Spectrum Selectpage 3 SS3 0 0 0 SS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Spread Amount% -0.8

ICH7M Integrated Pull-up and Pull-down ResistorsACZ_BIT_CLK, DPRSLP#, EE_DIN, EE_DOUT, GNT[5]#/GPO[17],

ICH6-M EDS 14308

0.8V1

-1.0 GNT[6]#/GPO[16], LDRQ[1]/GPI[41], -1.25 LAD[3:0]#/FB[3:0]#, LDRQ[0], -1.5 PME#, PWRBTN#, TP[3] -1.75 -2.0 -2.5 ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC, LAN_RXD[2:0]

ICH6 internal 20K pull-ups

4

CFG[4:3] CFG5 CFG6

Reserved DMI x2 Select 0 = DMI x2 1 = DMI x4 0=Moby Dick 1=Calistoga CPU Strap Reserved 0 = Reserved 1 =Mobile CPU(Default) (Default)

4

0 0 0 0 0

ICH6 internal 10K pull-ups ICH6 internal 20K pull-downs

CFG7 CFG8 CFG9 CFG[11:10] CFG[13:12] CFG[15:14] CFG16 CFG17

-3.0 ACZ_SDOUT,ACZ_BITCLK, DPRSLPVR, +-0.3 SPKR, EE_CS, +-0.4 +-0.5 +-0.6 DD[7], SDDREQ ICH6 internal 11.5K pull-downs ICH6 internal 100K pull-downs +-0.8 +-1.0 +-1.25 +-1.5 LAN_CLK USB[7:0][P,N] ICH6 internal 15K pull-downs

1 PCI Express Graphics Lane Reversal Reserved 1 Reserved 1 Reserved 1 FSB Dynamic ODT Global R-comp Disable (All R-comps) VCC Select DMI Lane Reversal 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default) 1 1 0 = Reverse Lanes,15->0,14->1 ect.. 1= Normal operation(Default):Lane Numbered in order 1 1

0 = All R-comp Disable 1 = Normal Operation (Default) 0 = 1.05V (Default) 1 = 1.5V 0 = Normal operation (Default):lane Numbered in order 1 =Reverse Lane,4->0,3->1 ect...

3

CFG18 CFG19

PCI RoutingIDSEL R5C832 25 IRQ REQ/GNT 0

ICH7M IDE Integrated Series Termination ResistorsDD[15:0], DIOW#, DIOR#, DREQ, approximately 33 ohm DDACK#, IORDY, DA[2:0], DCS1#, DCS3#, IDEIRQ

3

CFG20

SDVO/PCIE Concurrent

0 = Only SDVO or PCIE x1 is operational (Default) 1 =SDVO and PCIE x1 are operating simultaneously via the PEG port

SDVOCRTL _DATA

SDVO Present

0 = No SDVO device present (Default) 1= SDVO device present

NOTE: All strap signals are sampled with respect to the leading edge of the Alviso GMCH PWORK In signal.

2

History11.18.2004: mini card not ready

ITP Debug Conn.4 XDP_TDI 4 XDP_TMS 4 XDP_TRST# 4 XDP_TCK 4 XDP_TDO 3 CLK_XDP# 3 CLK_XDP XDP_TCK 4,6 H_CPURST#

1D05V_S0

2R34 39D2R2F-L-GP CN1

1

1

R40 54D9R2F-L1-GP

R36 54D9R2F-L1-GP

1

29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30

2

2

DY

R37

1

22D6R2F-L1-GP TDO_FLEX# 2 CLK_XDP# CLK_XDP

R39

1

DY RESET_FLEX# 2 22D6R2F-L1-GP 4 XDP_BPM#5 4 XDP_BPM#4

1

R35 680R2J-3-GP

1

R38 27D4R2F-L1-GP

3D3V_S0

4 XDP_BPM#0 4 XDP_BPM#1 R41 220R2J-L2-GP 4 XDP_BPM#2 4 XDP_BPM#3

2

2

1

2

14,17 XDP_DBRESET#

1

2

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

1D05V_S0

1

DY

2

C40 SCD1U16V2ZY-2GP

DYMLX-CON28-U

Title

ITPSize A3 Document Number Rev

AkitaSheet 2 of 39

SD

Date: Friday, March 31, 2006

A

3D3V_S0

3D3V_S0

1

1

1

1

1

1

1

1

1

1

1

C401

2

2

2

2

2

2

2

2

2

2

2

SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

4

3D3V_S0

2

C221 SC4D7U10V5ZY-3GP

C220 C218 SCD1U16V2ZY-2GP SC4D7U10V5ZY-3GP

C219 SCD1U16V2ZY-2GP

C238

C400

C199

C403

C201

C402

1

1 R387

2 3D3V_APWR_S0 0R3-0-U-GP

1 R145

http://hobi-elektronika.netB C D

E

3D3V_S0

2 3D3V_48MPWR_S0 0R3-0-U-GP

1 R146

2 0R3-0-U-GP

3D3V_CLKGEN_S0

C399 SCD1U16V2ZY-2GP

4

R120 10KR2J-3-GP

H/L : CPU_ITP/SRC10 IN R123 (3D3V_S0) 10KR2J-3-GP DY HITP_EN SS_SEL

1

1

EN (6218_PGOOD) L H

OUT (VTT_PWRGD#) H Hi - Z3D3V_CLKGEN_S0

PCLK_FWH_2 PCLK_PCM_1 PCLK_KBC_1 SS_SEL 3D3V_48MPWR_S0 3D3V_APWR_S0

33R2J-2-GP 33R2J-2-GP 33R2J-2-GP

2 2 2

1 1 1

R383 R382 R380

PCLK_FWH 31 PCLK_PCM 22 PCLK_KBC 29

2

2

X

1

1

H/L: 100/96MHzR122 10KR2J-3-GP U21 CPU_SEL0 2 2K2R2J-2-GP 17 CLK48_ICH

FSA CPU_SEL2_1 1 CPU_SEL1 R546

2

CPU_SEL2

1019CLK_CPU_BCLK_1 CLK_CPU_BCLK_1# CLK_MCH_BCLK_1 CLK_MCH_BCLK_1#

R124 10KR2J-3-GP DY

PM_STPCPU# 17 CLK_EN# 33

1 R375R373 2

1 2 RN29 1 2 RN27

4 3 SRN33J-5-GP-U 4 3 SRN33J-5-GP-U

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6

2

2

41 23 45 USB_48MHZ/FSLA REF0/FSLC/TEST_SEL FSLB/TEST_MODE

30 36

VDDA VDD48 VDDREF VDDCPU

VDDPCI VDDPCI

1 33R2J-2-GP

FSA

3D3V_S0

PCICLK1 PCICLK2 PCICLK3 PCICLK4/FCTSEL1

CPU_STOP# VTT_PWRGD#/PD

VDDSRC VDDSRC VDDSRC VDDSRC

24 39

7 40 18 12

27 32 33 34

65 54 49 1

3

R143 10KR2J-3-GP 26 CONN_CLKREQ#

1 R142

CLKREQ2# 2 0R2J-2-GP

R378 R144 R126 R379 R127 R381 R121 R385 R165

1 1 1 1 1 1 1 1 1

DY DY DY DY DY DY DY DY DY

2 2 2 2 2 2 2 2 2

UMA ONLY7 7 DREFSSCLK DREFSSCLK# 7 DREFCLK 7 DREFCLK#

1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP

CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4# CLKREQ5# CLKREQ6# CLKREQ7# CLKREQ8# CLKREQ9#

46 26 28 57 29 62 38 71 72 47 48 43 44 20 19 16 17

CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4# CLKREQ5# CLKREQ6# CLKREQ7# CLKREQ8# CLKREQ9# LCD100/96/SRC0_T LCD100/96/SRCO_C DOTT_96MHZ/27MHZ_NONSPREAD DOTC_96MHZ/27MHZ_SPREAD X1 X2 CPUT_ITP/SRCT10 CPUC_ITP/SRCC10 SMBCLK SMBDAT CPUCLKC1 CPUCLKC0 CPUCLKT1 CPUCLKT0

SRCT1 SRCT2 SRCT3 SRCT4 SRCT5 SRCT6 SRCT7 SRCT8 SRCT9 SRCC1 SRCC2 SRCC3 SRCC4 SRCC5 SRCC6 SRCC7 SRCC8 SRCC9

50 52 55 58 60 63 66 70 3 51 53 56 59 61 64 67 69 2 25 37

CLK_PCIE_NEW_1 CLK_PCIE_NEW_1# CLK_PCIE_NEW_1 CLK_MCH_3GPLL_1 CLK_PCIE_SATA_1 CLK_PCIE_ICH_1 CLK_PCIE_MINI1_1 CLK_PCIE_MINI2_1

2 1 RN26 CLK_MCH_3GPLL_1 2 CLK_MCH_3GPLL_1# 1 RN32 CLK_PCIE_SATA_1 2 CLK_PCIE_SATA_1# 1 RN33 CLK_PCIE_ICH_1 2 CLK_PCIE_ICH_1# 1 RN34

3 4 SRN33J-5-GP-U 3 4 SRN33J-5-GP-U 3 4 SRN33J-5-GP-U 3 4 SRN33J-5-GP-U

CLK_PCIE_NEW 26 CLK_PCIE_NEW# 26 CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7 CLK_PCIE_SATA 16 CLK_PCIE_SATA# 16 CLK_PCIE_ICH 17 CLK_PCIE_ICH# 173

2

1

3 4 RN24 3 4 RN25

DREFSSCLK_1 2 DREFSSCLK_1# 1 SRN33J-5-GP-U DREFCLK_1 2 DREFCLK#_1 1 SRN33J-5-GP-U GEN_XTAL_IN 2 GEN_XTAL_OUT 0R2J-2-GP

CLK_PCIE_NEW_1# CLK_MCH_3GPLL_1# CLK_PCIE_SATA_1# CLK_PCIE_ICH_1# CLK_PCIE_MINI1_1# CLK_PCIE_MINI2_1#

1121

C200 1 2

CLK_PCIE_MINI1_1 2 CLK_PCIE_MINI1_1# 1 RN35 CLK_PCIE_MINI2_1 1 CLK_PCIE_MINI2_1# 2 RN36

3 CLK_PCIE_MINI1 24 4 CLK_PCIE_MINI1# 24 SRN33J-5-GP-U 4 CLK_PCIE_MINI2 24 3 CLK_PCIE_MINI2# 24 SRN33J-5-GP-U

SC27P50V2JN-2-GP X1 X-14D31818M-30GP

GEN_XTAL_O