wistron dw50 winery15 - 48.4et05.0sa 09289-sa
DESCRIPTION
Esquema SHUTTLE DW50 - Notebook Dell 3500TRANSCRIPT
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SACover Page
Custom
1 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SACover Page
Custom
1 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SACover Page
Custom
1 88Wednesday, September 09, 2009
Intel Ibex Peak-M
2009-09-09
REV : SA
Winery CALPELLA N11M-GE Schematics Mobile Arrandale
DY : Nopop ComponentUMA : Pop when schematic is UMADIS : Pop when schematic is DIS
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SABlock Diagram
Custom
2 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SABlock Diagram
Custom
2 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SABlock Diagram
Custom
2 88Wednesday, September 09, 2009
EMC2102
KBC
Thermal& Fan Int. KB
LPC Bus
256kBFlash ROM
DDRIII 1066 Channel A
DDR III 1066 Channel B
Winery CALPELLA Block Diagram
NUVOTONNPCE781BA0DX
SPI
Clock GeneratorSLG8SP585
37
7
62 68 39,58
TouchPAD 68
Project code : 91.4ET01.001Part Number : 48.4ET05.0SA PCB P/N : 09289Revision : SA
VTT_CORE
73Bluetooth
USB 2.0 x 1
PCIE
USB,ESATAMulti-Port x1
CAMERA73
USB 2.0 x 1
USB 2.0 x 1
USB 2.0
802.11a/b/g/n
64
Mini-Card
New Card
PCIE x 1
TPS2231RPower SW
ODD
S
A
T
A
59
S
P
I
HDD
RealtekRTS5138
CardReader
(8 in 1)SD/MMCMS/MS Pro/xD
USB 2.0
AzaliaCODEC
IDT92HD81
AZALIA
OP AMP
30
2CH SPEAKER
MIC IN
HP OUT
Digital Mic Array
USB 2.0 x 1
63
DDRIII1066
Slot 0
Slot 1
18
19DDRIII1066
80,81,82,83
64Mbx16x4 (512MB)VRAM(gDDR3)
484,85
Nvidia N11M-GE(40nm) PCIe x 16
(On daughter board)
(On daughter board)
OUTPUTSINPUTS
+PWR_SRC
PCB LAYER
L3: SignalL2: VCC
L5: GNDL4: Signal
L6: Bottom
L1: Top
49
60
USB 2.0 x 1
WWAN/ WiMAX
65
Mini-Card
PCIE x 1
Right Side:USB x 1
Biometric
S
A
T
A
,
U
S
B
TPM 76
63
78
100MHz/2.5Gbps
800/1066MHz
800/1066MHz
Bandwidth:8GB
33MHz
480Mbps
3
G
b
p
s
100MHz2.5Gbps
24MHz
Left Side:USB x 2USB 2.0 x 2
Capacity Board
SM Bus
400KHzSM Bus Free fall sensor
40
46
+3.3V_RTC_LDO
47,48
50
ISL62883
OUTPUTS
+VCC_CORE
INPUTS
+PWR_SRC
CPU DC/DC
+3.3V_ALW
OUTPUTS
+5V_ALW+PWR_SRC
TPS51125
INPUTS
SYSTEM DC/DC
+1.5V_SUS
SYSTEM DC/DC
OUTPUTS
+PWR_SRC
CHARGER
INPUTS
BQ24745
+DC_IN
+15V_ALW
+PBATT
86
+VCC_GFX_CORE
OUTPUTS
SYSTEM DC/DC
INPUTS
+PWR_SRC
TPS51116
+PWR_SRC
TPS51218
53
OUTPUTSINPUTS
+PWR_SRC +CPU_GFXCORE
DMIx4 FDI(UMA)
Intel CPU
8,9,10,11,12,13,14
Arrandale
Intel
14 USB 2.0/1.1 ports
PCH
High Definition AudioSATA ports (6)
LPC I/FACPI 1.1
PCI/PCI BRIDGE
ETHERNET (10/100/1000Mb)
PCIE ports (8)
20,21,22,23,24,25,26,27,28
VRAM
RGB CRT
LVDS
Switchable
RGB CRT
55
HDMI 57
CRT
LCD 54
RGB CRT
HDMI
LVDS
RGB CRT
LVDS
PCIE x 1 & USB 2.0 x 1
3510/100/1000LOMRTL8111DL
PCIE x 1 RJ45CONN 61
Touch PanelUSB 2.0 x 1
Flash ROM
4MB
+0.75V_DDR_VTT
OUTPUTSINPUTS
+V_DDR_MCH_REF
SYSTEM DC/DCADP3211
SYSTEM DC/DCTPS51218
51
OUTPUTS
APL5930LDO
INPUTS
+1.8V_RUN+3.3V_ALW
Switchable
LVDS
74
74
(On daughter board)
76
2.5 GT/s 2.7 GT/s
USB 2.0 x 1
76
(On daughter board)
(On daughter board)
87
OUTPUTS
RT9025LDO
INPUTS
+1.8V_RUN_GPU+3.3V_ALW
HDMI
75
(On daughter board)
62
(only for 15")
480Mbps
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SAPower Block Diagram
Custom
3 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SAPower Block Diagram
Custom
3 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SAPower Block Diagram
Custom
3 88Wednesday, September 09, 2009
Charger
BQ24745
+PBATT
Adapter
Battery
TPS51125
Regulator LDO Switch
+5V_ALW
+3.3V_RTC_LDO
AO4468
+5V_RUN
TPS2062AD
+5V_USB0
TPS2062AD
+5V_USB1
AO3403
+3.3V_LAN
AO4468
+3.3V_RUN+3.3V_CARDAUX
RTL8111DL
DVDD12
ISL62883
+VCC_CORE
+3.3V_CARD
G5285T11U
+LCDVDD
+PWR_SRC
+0.75V_DDR_VTT+V_DDR_MCH_REF
+1.5V_RUN
+1.5V_SUS
Power Shape
AO4407A TPS51218
+VCC_GFX_CORE
+5V_ALW
4748 86
45
45
46
Daughter BD 6342
TPS2231R
35TPS2231R
54
+15V_ALW
AO446842
42TPS2062AD
+5V_USB2
63
For USB Port1 For USB Port2,3 For ESATA
+5V_ALW2
Daughter BD
Daughter BD
APL593051
+1.8V_RUN
TPS51116PWPRG450
FDS8880
+1.05V_VTT
49TPS51218DSCR
87
+1.05V_GFX_PCIE
TPS2231R
+1.5V_CARD
Daughter BD
FDS888087
+1.5V_RUN_GPU
+3.3V_ALW
Arrandale : 1.05V
ADP3211
+CPU_GFXCORE
53
For NVIDIA GPUFor Intel GPU
RT9025
+1.8V_RUN_GPU+3.3V_RUN_GPU
FDS888087
P270352
+1.5V_CPU
87
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SASMBUS Block Diagram
C
4 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SASMBUS Block Diagram
C
4 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SASMBUS Block Diagram
C
4 88Wednesday, September 09, 2009
68
SMBus address:0A
MinicardWWANSMB_DATASMB_CLK
65
PCH_SMBDATA
PCH_SMBDATA
PCH_SMBCLK
BQ24745SCL
40
SDA
SRN10KJ-5-GP
SRN4K7J-8-GP
SRN100J-3-GP
SRN4K7J-8-GP
+3.3V_RTC_LDO
TPDATA
TPCLK
+5V_RUN
TouchPad Conn.TPDATA
TPCLK
PSCLK1
PSDAT1
PCH SMBus Block Diagram
PCHSMBCLK
SMBDATA
GPIO74/SDA2
GPIO73/SCL2
KBCNPCE781
CLK_SMB
+3.3V_RUN
SRN2K2J-1-GP
+3.3V_ALW
SRN2K2J-1-GP+3.3V_RUN
2N7002SPT
DAT_SMB
KBC_SCL1
KBC_SDA1
PCH_SMBCLKPCH_SMBDATA
ClockGeneratorSMBCLKSMBDATA
PCH_SMBCLKPCH_SMBDATA
TPDATA
TPCLK
SCL1
SDA1
BAT_SCL
ExpressCardSMB_CLK
BAT_SDA
SMB_DATA
SMBus address:D2
SMBus Address:A0
SMBus Address:A2
DIMM 1SCL
SDA
+3.3V_RTC_LDO
DIMM 2SCLSDA
SMBus address:16
SMB_CLK
SMB_DATA
PCH_SMBCLK
PCH_SMBDATA
PBAT_SMBCLK1
PBAT_SMBDAT1
KBC SMBus Block Diagram
Battery Conn.
MinicardWLANSMB_DATASMB_CLKPCH_SMBCLK
64
Free fallsensorSDA/SDI/SDOSCL/SPC
PCH_SMBDATAPCH_SMBCLK
SMB_CLK
SMB_DATA
(On daughter board)
THERM_SCL
THERM_SDA
SRN4K7J-8-GP+3.3V_RUN
Thermal
SMCLK
SMDATA
Capacity Board
SCLSDA
SMBus address:7A
THERM_SCL
THERM_SDA
39
76
22
18
19
07
45
44
+3.3V_RUN
2N7002DW-1-GP
SMBus address:12
Switchable Graphic SMBus Block Diagram
SDVO_CTRLDATA
SDVO_CTRLCLK
CRT_DDC_DATA
CRT_DDC_CLK
L_DDC_CLK
L_DDC_DATA
I2CC_SDAI2CC_SCL
I2CA_SDAI2CA_SCL
IFPC_AUX_I2CW_SDA#
IFPC_AUX_I2CW_SCL
PCH
N11M-GE
SRN2K2J-1-GP
L_DDC_DATA
L_DDC_CLK
+3.3V_RUN
LCD Conn.
LDDC_CLK_CON
LDDC_DATA_CON
+3.3V_RUN
SRN2K2J-1-GP
B1
B0GND
VCC
S
A
NC7SB3157P6X-1GP
+3.3V_RUN
54
B1
B0
GND
VCC
S
A
NC7SB3157P6X-1GP
+3.3V_RUN
B1
B0
GND
VCC
S
A
NC7SB3157P6X-1GP
+3.3V_RUN
B1
B0
GND
VCC
S
A
NC7SB3157P6X-1GP
+3.3V_RUN
B1
B0
GND
VCC
S
A
NC7SB3157P6X-1GP
+3.3V_RUN
B1
B0
GND
VCC
S
A
NC7SB3157P6X-1GP
+3.3V_RUN
LDDC_CLK
LDDC_DATA
+3.3V_RUN
SRN2K2J-1-GP
GMCH_DDCCLK
GMCH_DDCDATA
SDVO_CLK
SDVO_DAT
HDMI_SDATA_DDC
HDMI_SCLK_DDC
CRT_CLK_DDC
CRT_DAT_DDC
+3.3V_RUN
SRN2K2J-1-GP
+3.3V_RUN_GPU
2N7002DW-1-GP
CRT CONN55
DDC_CLK_CON2
DDC_DATA_CON2
+3.3V_RUN
SRN2K2J-1-GP
DDC_CLK_CON
DDC_DATA_CON
SRN2K2J-1-GP
+5V_CRT_RUN
+3.3V_RUN
2N7002DW-1-GP
HDMI55
HDMI_SCLK_CON_L
HDMI_SDATA_CON_L
+3.3V_RUN
SRN2K2J-1-GP
HDMI_SCLK_CON
HDMI_SDATA_CON
SRN2K2J-1-GP
+5V_RUN
+3.3V_RUN
+3.3V_RUN
SRN2K2J-1-GP
+3.3V_RUN
SRN2K2J-1-GP
DY
DY
-
AA
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SAThermal/Audio Block Diagram
Custom
5 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SAThermal/Audio Block Diagram
Custom
5 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SAThermal/Audio Block Diagram
Custom
5 88Wednesday, September 09, 2009
Thermal Block Diagram
ThermalEMC2102
DP1
DN1
SC470P50V3JN-2GP
DP2
DN2
DP3
DN3
Audio Block Diagram
VGA_THERMDA
VGA_THERMDC
GPUDPLUS
DMINUS54
28
CPU_THERMDA
CPU_THERMDC
SC470P50V3JN-2GPMMBT3904-3-GP
EMC2102_DN1
EMC2102_DP1
SC470P50V3JN-2GP
DigitalMICArray
DMIC_CLK/GPIO1
DMIC0/GPIO2
Codec92HD81
HPOUT
MICIN
SPEAKER
VREFOUT_A_OR_F
HP1_PORT_B_L
33R2J-2-GPAUD_DMIC_CLK
AUD_DMIC_IN033R2J-2-GP AUD_DMIC_IN0_R
AUD_DMIC_CLK_G_R
22
SPKR_PORT_D_L+
SPKR_PORT_D_L-
SPKR_PORT_D_R-
SPKR_PORT_D_R+
0R3-0-U-GPAUD_SPK_L1_R
AUD_SPK_L2_R
AUD_SPK_R2_R
AUD_SPK_R1_R
AUD_SPK_L1
AUD_SPK_L2
AUD_SPK_R2
AUD_SPK_R1
HP1_PORT_B_R
AUD_HP1_JACK_L
AUD_HP1_JACK_R
50
44
HP0_PORT_A_L
HP0_PORT_A_R
AUD_EXT_MIC_L
AUD_EXT_MIC_R
AUD_VREFOUT_B
0R3-0-U-V-GP
47
50
MMBT3904-3-GP
HW T8 sensor( CPU )
WWAN
-
AA
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SATable of Content
Custom
6 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SATable of Content
Custom
6 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SATable of Content
Custom
6 88Wednesday, September 09, 2009
PCIE Routing
New CardLANE5
LANE2
LANE3 LAN
MiniCard WLANLANE1
MiniCard WWANLANE4
Card reader
CFG[0]
CFG[7]
Processor Strapping
CFG[4] Disabled - No Physical Display Port attached toEmbedded DisplayPort.
CFG[3]
Pin Name Strap Description Configuration (Default value for each bit is 1 unless specified otherwise)
1:EmbeddedDisplayPortPresence
Calpella Schematic Checklist Rev.0_7
0: Enabled - An external Display Port device isconnected to the Embedded Display Port.
PCI-Express StaticLane Reversal
1:0: Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
DefaultValue
PCI-ExpressConfigurationSelect
1:0: Single PCI-Express Graphics Bifurcation enabled
Reserved -Temporarily usedfor earlyClarksfieldsamples.
Clarksfield (only for early samples pre-ES1) - Connect to GND with 3.01K Ohm/5% resistorNote: Only temporary for early CFD samples(rPGA/BGA) [For details please refer to the WW33MoW and sighting report].For a common motherboard design (for AUB and CFD),the pull-down resistor should be used. Does notimpact AUB functionality.
1
1
1
0
SPKRName Schematics Notes
HAD_DOCK_EN#/GPIO[33]
Low (0):High (1) :
HDA_SDO Weak internal pull-down. Do not pull high.
HDA_SYNC
Calpella Schematic Checklist Rev.0_7
INIT3_3V# Weak internal pull-down. Do not pull high.
GNT3#/GPIO55
Default Mode:Low (0) = Top Block Swap Mode
GNT0#,GNT1#/GPIO51
Weak internal pull-down. Do not pull high.
Weak internal pull-down. Do not pull high.
Weak internal pull-up. Do not pull low.
PCH Strapping
Default (SPI):
GNT2#/GPIO53
Default - Internal pull-up.Low (0)
GPIO33 Default:Disable ME in Manufacturing Mode:
SPI_MOSI
Internal weak Pull-down. Connect to Vcc3_3 with 8.2-k- 10-k weak pull-up resistor.
Enable iTPM:Disable iTPM:
NV_ALE Enable Danbury:
Disable Danbury:
NC_CLE Weak internal pull-up. Do not pull low.
GPIO15
GPIO8
Reboot option at power-upDefault Mode:No Reboot Mode with TCO Disabled:
Internal pull-up. Note: Connect to ground with 4.7-k? weak pull-down resistor. CRB uses a 1 k do not stuff resistor.
INTVRMEN High (1) = Integrated VRM is enabledLow (0) = Integrated VRM is disabled Left both GNT0# and GNT1# floating. No pull uprequired.Boot from PCI: Connect GNT1# to ground with 1-k pull-downresistor. Leave GNT0# Floating.Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-kpull-down resistor.
= Configures DMI for ESI compatible operation (for serversonly. Not for mobile/desktops).
Do not pull low. Connect to ground with 1-k pull-down resistor.
Connect to Vcc3_3 with 8.2-k weak pull-up resistor. Left floating, no pull-down required. Connect to Vcc3_3 with 8.2-k weak pull-up resistor. Connect to ground with 4.7-k weak pull-down resistor.
Flash Descriptor Security will be overridden. Flash Descriptor Security will be in effect.
GPIO27 Default = Do not connect (floating)High(1) = Enables the internal VccVRM to have a clean supply foranalog rails. No need to use on-board filter circuit.Low (0) = Disables the VccVRM. Need to use on-board filtercircuits for analog rails.
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CK_PWRGD
CLK_XTAL_IN
CLK_XTAL_OUT
CLK_CPU_BCLKCLK_CPU_BCLK#
CLKIN_DMICLKIN_DMI#
CLK_PCIE_SATACLK_PCIE_SATA#
DREFCLKDREFCLK#
CLK_XTAL_INCLK_XTAL_OUT
CK_PWRGDCPU_STOP#
FSC
CLK_27MCLK_27M_SS
FSC
TP_CPU_1#TP_CPU_1
+3.3V_RUN +3.3V_RUN_SL585 +1.05V_VTT+1.05V_RUN_SL585_IO
+1.05V_VTT
+3.3V_RUN_SL585
+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO
+3.3V_RUN
VR_CLKEN# [47]
CLKIN_DMI#[23]CLKIN_DMI[23]
CLK_CPU_BCLK[23]CLK_CPU_BCLK#[23]CLK_PCIE_SATA[23]
CLK_PCIE_SATA#[23]
DREFCLK#[23]DREFCLK[23]
CLK_PCH_14M [23]
PCH_SMBDATA [18,19,23,40,64,65]PCH_SMBCLK [18,19,23,40,64,65]
CLK_VGA_27M [81]
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00Clock Generator SLG8SP585
7 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00Clock Generator SLG8SP585
7 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00Clock Generator SLG8SP585
7 88Wednesday, September 09, 2009
FSC 0 1
133MHz100MHz
(Default)SPEED
1st Silego 71.08585.0032nd ICS 71.93197.003
68.00119.131 060368.00084.521 0805 68.00119.131
R710R706SS
NON-SS Mount DY
DY Mount
VGA 27M
1 2R709 0R3J-0-U-GPR709 0R3J-0-U-GP
1
2
C703SCD1U10V2KX-4GPC703SCD1U10V2KX-4GP
1
2
R70510KR2J-3-GPR70510KR2J-3-GP
1
2
C708SCD1U10V2KX-4GPC708SCD1U10V2KX-4GP
1
2
C711SCD1U10V2KX-4GPC711SCD1U10V2KX-4GP
1
2
C705SCD1U10V2KX-4GPC705SCD1U10V2KX-4GP
V
D
D
_
D
O
T
1
V
S
S
_
D
O
T
2
DOT_963DOT_96#4
V
D
D
_
2
7
5
27MHZ 627MHZ_SS 7
V
S
S
_
2
7
8
V
S
S
_
S
A
T
A
9
SRC_1/SATA10SRC_1/SATA#11
V
S
S
_
S
R
C
1
2
SRC_213SRC_2#14
V
D
D
_
S
R
C
_
I
O
1
5
CPU_STOP# 16
V
D
D
_
S
R
C
1
7
V
D
D
_
C
P
U
_
I
O
1
8
CPU_1#19CPU_120
V
S
S
_
C
P
U
2
1
CPU_0#22CPU_023
V
D
D
_
C
P
U
2
4
CKPWRGD/PD# 25
V
S
S
_
R
E
F
2
6
XTAL_OUT 27XTAL_IN 28
V
D
D
_
R
E
F
2
9
REF_0/CPU_SEL 30
SDA 31SCL 32
G
N
D
3
3
U701
SLG8SP585VTR-GP
U701
SLG8SP585VTR-GP1
2
R7044K7R2J-2-GP DYR7044K7R2J-2-GP DY
1 2R708 0R3J-0-U-GPR708 0R3J-0-U-GP
1
2
R70710KR2J-3-GPR70710KR2J-3-GP
12R710 33R2J-2-GPDYR710 33R2J-2-GPDY
1
2
C702SC10U10V5ZY-1GP
DY
C702SC10U10V5ZY-1GP
DY
1
2
C715SC12P50V2JN-3GPC715SC12P50V2JN-3GP
1TP701TPAD14-GP TP701TPAD14-GP
12R703 33R2J-2-GPR703 33R2J-2-GP
1TP702TPAD14-GP TP702TPAD14-GP
12R701 2K2R2J-2-GPR701 2K2R2J-2-GP
1
2
EC701SC4D7P50V2CN-1GPDY EC701SC4D7P50V2CN-1GPDY
12R706 33R2J-2-GPDYR706 33R2J-2-GPDY
1
2
C712SCD1U10V2KX-4GPC712SCD1U10V2KX-4GP
1
2
C707SCD1U10V2KX-4GPC707SCD1U10V2KX-4GP
1
2
C704SCD1U10V2KX-4GPC704SCD1U10V2KX-4GP
1 2X701
X-14D31818M-50GP
X701
X-14D31818M-50GP
1
2
C710SC10U6D3V3MX-GPC710SC10U6D3V3MX-GP
1
2
C709SC1U10V2KX-1GPDYC709SC1U10V2KX-1GPDY
G
SD
Q7012N7002A-7-GPQ7012N7002A-7-GP
1
2
C701SC1U10V2KX-1GP
DY
C701SC1U10V2KX-1GP
DY
1
2
C714SC12P50V2JN-3GPC714SC12P50V2JN-3GP
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FDI_TXN0
FDI_TXN5FDI_TXN6FDI_TXN7
FDI_TXN4
FDI_TXN1FDI_TXN2FDI_TXN3
FDI_TXP0
FDI_TXP5FDI_TXP6FDI_TXP7
FDI_TXP4
FDI_TXP1FDI_TXP2FDI_TXP3
EXP_RBIAS
PEG_IRCOMP_R
PCIE_MRX_GTX_N[0..15]
PCIE_MRX_GTX_P[0..15]
PCIE_MTX_GRX_P[0..15]
PCIE_MTX_GRX_N[0..15]
PCIE_MRX_GTX_N5PCIE_MRX_GTX_N4PCIE_MRX_GTX_N3PCIE_MRX_GTX_N2PCIE_MRX_GTX_N1PCIE_MRX_GTX_N0
PCIE_MRX_GTX_N15PCIE_MRX_GTX_N14PCIE_MRX_GTX_N13PCIE_MRX_GTX_N12PCIE_MRX_GTX_N11PCIE_MRX_GTX_N10PCIE_MRX_GTX_N9PCIE_MRX_GTX_N8PCIE_MRX_GTX_N7PCIE_MRX_GTX_N6
PCIE_MRX_GTX_P5PCIE_MRX_GTX_P4PCIE_MRX_GTX_P3PCIE_MRX_GTX_P2PCIE_MRX_GTX_P1PCIE_MRX_GTX_P0
PCIE_MRX_GTX_P15PCIE_MRX_GTX_P14PCIE_MRX_GTX_P13PCIE_MRX_GTX_P12PCIE_MRX_GTX_P11PCIE_MRX_GTX_P10PCIE_MRX_GTX_P9PCIE_MRX_GTX_P8PCIE_MRX_GTX_P7PCIE_MRX_GTX_P6
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N15
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_C_P12
PCIE_MTX_GRX_C_P7
PCIE_MTX_GRX_C_P2
PCIE_MTX_GRX_C_P14
PCIE_MTX_GRX_C_P9
PCIE_MTX_GRX_C_P4
PCIE_MTX_GRX_C_P11
PCIE_MTX_GRX_C_P6
PCIE_MTX_GRX_C_P1
PCIE_MTX_GRX_C_P13
PCIE_MTX_GRX_C_P8
PCIE_MTX_GRX_C_P3
PCIE_MTX_GRX_C_P15
PCIE_MTX_GRX_C_P10
PCIE_MTX_GRX_C_P5
PCIE_MTX_GRX_C_P0
PCIE_MTX_GRX_C_N3
PCIE_MTX_GRX_C_N15
PCIE_MTX_GRX_C_N10
PCIE_MTX_GRX_C_N5
PCIE_MTX_GRX_C_N0
PCIE_MTX_GRX_C_N12
PCIE_MTX_GRX_C_N7
PCIE_MTX_GRX_C_N2
PCIE_MTX_GRX_C_N14
PCIE_MTX_GRX_C_N9
PCIE_MTX_GRX_C_N4
PCIE_MTX_GRX_C_N11
PCIE_MTX_GRX_C_N6
PCIE_MTX_GRX_C_N1
PCIE_MTX_GRX_C_N13
PCIE_MTX_GRX_C_N8
DMI_PTX_CRXN0[22]
DMI_CTX_PRXN0[22]
DMI_PTX_CRXN1[22]DMI_PTX_CRXN2[22]DMI_PTX_CRXN3[22]DMI_PTX_CRXP0[22]DMI_PTX_CRXP1[22]DMI_PTX_CRXP2[22]DMI_PTX_CRXP3[22]
DMI_CTX_PRXN1[22]DMI_CTX_PRXN2[22]DMI_CTX_PRXN3[22]DMI_CTX_PRXP0[22]DMI_CTX_PRXP1[22]DMI_CTX_PRXP2[22]DMI_CTX_PRXP3[22]
FDI_FSYNC0[22]FDI_FSYNC1[22]FDI_INT[22]
FDI_TXN0[22]
FDI_LSYNC0[22]FDI_LSYNC1[22]
FDI_TXN1[22]FDI_TXN2[22]FDI_TXN3[22]FDI_TXN4[22]FDI_TXN5[22]FDI_TXN6[22]FDI_TXN7[22]
FDI_TXP0[22]FDI_TXP1[22]FDI_TXP2[22]FDI_TXP3[22]FDI_TXP4[22]FDI_TXP5[22]FDI_TXP6[22]FDI_TXP7[22]
PCIE_MRX_GTX_P[0..15] [80]
PCIE_MRX_GTX_N[0..15] [80]
PCIE_MTX_GRX_P[0..15] [80]
PCIE_MTX_GRX_N[0..15] [80]
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (PCIE/DMI/FDI)
8 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (PCIE/DMI/FDI)
8 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (PCIE/DMI/FDI)
8 88Wednesday, September 09, 2009
Calpella Platform Design Guide Revision 1.6
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on the Arrandale side should be tied to GND (through 1-k 5% resistors).
2.4 Arrandale Graphics Disable Guideline
Page 89
DW07/02 Added1.Added Flexible Display Interface (IntelR FDI) commentariat
It applies to Arrandale and Clarksfield discrete graphic designs.
DW07/10 Reversal1.PCI-Express Static Lane Reversal (15 -> 0, 14 -> 1, ...)
1 2C817 SCD1U10V2KX-5GPDISC817 SCD1U10V2KX-5GPDIS
1 2C828 SCD1U10V2KX-5GPDISC828 SCD1U10V2KX-5GPDIS
1 2C818 SCD1U10V2KX-5GPDISC818 SCD1U10V2KX-5GPDIS
1 2C811 SCD1U10V2KX-5GPDISC811 SCD1U10V2KX-5GPDIS
1 2R802 750R2F-GPR802 750R2F-GP
1 2C820 SCD1U10V2KX-5GPDISC820 SCD1U10V2KX-5GPDIS
1 2C819 SCD1U10V2KX-5GPDISC819 SCD1U10V2KX-5GPDIS
1 2C821 SCD1U10V2KX-5GPDISC821 SCD1U10V2KX-5GPDIS
1 2C807 SCD1U10V2KX-5GPDISC807 SCD1U10V2KX-5GPDIS
1 2C815 SCD1U10V2KX-5GPDISC815 SCD1U10V2KX-5GPDIS
1 2C809 SCD1U10V2KX-5GPDISC809 SCD1U10V2KX-5GPDIS
1 2C813 SCD1U10V2KX-5GPDISC813 SCD1U10V2KX-5GPDIS
1 2C827 SCD1U10V2KX-5GPDISC827 SCD1U10V2KX-5GPDIS
1 2C824 SCD1U10V2KX-5GPDISC824 SCD1U10V2KX-5GPDIS
1 2C825 SCD1U10V2KX-5GPDISC825 SCD1U10V2KX-5GPDIS
1 2C805 SCD1U10V2KX-5GPDISC805 SCD1U10V2KX-5GPDIS
1 2C812 SCD1U10V2KX-5GPDISC812 SCD1U10V2KX-5GPDIS
1 2C829 SCD1U10V2KX-5GPDISC829 SCD1U10V2KX-5GPDIS
1 2C808 SCD1U10V2KX-5GPDISC808 SCD1U10V2KX-5GPDIS
1 2C801 SCD1U10V2KX-5GPDISC801 SCD1U10V2KX-5GPDIS
1 2C816 SCD1U10V2KX-5GPDISC816 SCD1U10V2KX-5GPDIS
1 2C822 SCD1U10V2KX-5GPDISC822 SCD1U10V2KX-5GPDIS
1 2C804 SCD1U10V2KX-5GPDISC804 SCD1U10V2KX-5GPDIS
1 2C826 SCD1U10V2KX-5GPDISC826 SCD1U10V2KX-5GPDIS
1 2C802 SCD1U10V2KX-5GPDISC802 SCD1U10V2KX-5GPDIS
1 2C832 SCD1U10V2KX-5GPDISC832 SCD1U10V2KX-5GPDIS
1 2C810 SCD1U10V2KX-5GPDISC810 SCD1U10V2KX-5GPDIS
1 2C814 SCD1U10V2KX-5GPDISC814 SCD1U10V2KX-5GPDIS
DMI_RX#0A24DMI_RX#1C23DMI_RX#2B22DMI_RX#3A21
DMI_RX0B24DMI_RX1D23DMI_RX2B23DMI_RX3A22
DMI_TX#0D24DMI_TX#1G24DMI_TX#2F23DMI_TX#3H23
DMI_TX0D25DMI_TX1F24
DMI_TX3G23DMI_TX2E23
FDI_TX#0E22FDI_TX#1D21FDI_TX#2D19FDI_TX#3D18FDI_TX#4G21FDI_TX#5E19FDI_TX#6F21FDI_TX#7G18
FDI_TX0D22FDI_TX1C21FDI_TX2D20FDI_TX3C18FDI_TX4G22FDI_TX5E20FDI_TX6F20FDI_TX7G19
FDI_FSYNC0F17FDI_FSYNC1E17
FDI_INTC17
FDI_LSYNC0F18FDI_LSYNC1D17
PEG_ICOMPI B26PEG_ICOMPO A26
PEG_RBIAS A25PEG_RCOMPO B27
PEG_RX#0 K35PEG_RX#1 J34PEG_RX#2 J33PEG_RX#3 G35PEG_RX#4 G32PEG_RX#5 F34PEG_RX#6 F31PEG_RX#7 D35PEG_RX#8 E33PEG_RX#9 C33
PEG_RX#10 D32PEG_RX#11 B32PEG_RX#12 C31PEG_RX#13 B28PEG_RX#14 B30PEG_RX#15 A31
PEG_RX0 J35PEG_RX1 H34PEG_RX2 H33PEG_RX3 F35PEG_RX4 G33PEG_RX5 E34PEG_RX6 F32PEG_RX7 D34PEG_RX8 F33PEG_RX9 B33
PEG_RX10 D31PEG_RX11 A32PEG_RX12 C30PEG_RX13 A28PEG_RX14 B29PEG_RX15 A30
PEG_TX#0 L33PEG_TX#1 M35PEG_TX#2 M33PEG_TX#3 M30PEG_TX#4 L31PEG_TX#5 K32PEG_TX#6 M29PEG_TX#7 J31PEG_TX#8 K29PEG_TX#9 H30
PEG_TX#10 H29PEG_TX#11 F29PEG_TX#12 E28PEG_TX#13 D29PEG_TX#14 D27PEG_TX#15 C26
PEG_TX0 L34PEG_TX1 M34PEG_TX2 M32PEG_TX3 L30PEG_TX4 M31PEG_TX5 K31PEG_TX6 M28PEG_TX7 H31PEG_TX8 K28PEG_TX9 G30
PEG_TX10 G29PEG_TX11 F28PEG_TX12 E27PEG_TX13 D28PEG_TX14 C27PEG_TX15 C25
P
C
I
E
X
P
R
E
S
S
-
-
G
R
A
P
H
I
C
S
DMI
Intel(R) FDI
1 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1A
CLARKUNF
P
C
I
E
X
P
R
E
S
S
-
-
G
R
A
P
H
I
C
S
DMI
Intel(R) FDI
1 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1A
CLARKUNF
1 2C831 SCD1U10V2KX-5GPDISC831 SCD1U10V2KX-5GPDIS
1 2C806 SCD1U10V2KX-5GPDISC806 SCD1U10V2KX-5GPDIS
1 2R801 49D9R2F-GPR801 49D9R2F-GP
1 2C823 SCD1U10V2KX-5GPDISC823 SCD1U10V2KX-5GPDIS
1 2C803 SCD1U10V2KX-5GPDISC803 SCD1U10V2KX-5GPDIS
1 2C830 SCD1U10V2KX-5GPDISC830 SCD1U10V2KX-5GPDIS
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PM_DRAM_PWRGD
H_COMP3
H_COMP2
H_COMP1
H_COMP0
SKTOCC#_R
H_CATERR#
H_CATERR#
H_CPURST#
PLT_RST#_R
BCLK_ITP_PBCLK_ITP_N
SM_RCOMP_0SM_RCOMP_1SM_RCOMP_2
H_PWRGD_XDP
SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0
XDP_TDI_R
XDP_TDO_M
XDP_TDI_M
XDP_TDO_R
XDP_TDI
XDP_TDO
XDP_TRST#
XDP_TCLK
XDP_PREQ#
XDP_TDI_R
XDP_TMS
H_CPURST#
PM_DRAM_PWRGD
XDP_PRDY#XDP_PREQ#
XDP_TCLKXDP_TMS
XDP_TDI_RXDP_TDO_RXDP_TDI_MXDP_TDO_M
H_DBR#_R
XDP_TRST#
XDP_DBRESET#
XDP_OBS0XDP_OBS1
XDP_OBS3XDP_OBS2
XDP_OBS5XDP_OBS4
XDP_OBS7XDP_OBS6
XDP_OBS1
XDP_OBS5
H_CPUPWRGD_XDP
XDP_TDI
XDP_RST#_R
XDP_TDO
XDP_OBS2
XDP_TMS
BCLK_ITP_N
XDP_OBS6
H_PWRGOODPM_PWRBTN#_XDP
XDP_PRDY#
XDP_OBS3
XDP_OBS7
H_PWRGD_XDP_R
BCLK_ITP_P
XDP_TRST#
XDP_OBS0
H_PWRGD_XDP
XDP_OBS4
XDP_RST#_R
XDP_PREQ#
XDP_TCLK
VCCPWRGOOD
H_PROCHOT_R#
H_PROCHOT_R#PM_EXTTS#0_CPM_EXTTS#1_C
DPLL_REF_SSCLK#_RDPLL_REF_SSCLK_R
SM_DRAMRST#
XDP_RST#_R
VTT_PWRGD_R3 PM_DRAM_PWRGD
SM_DRAMRST#
U927_B
DPLL_REF_SSCLK_RDPLL_REF_SSCLK#_R
+1.05V_VTT
+1.05V_VTT
+1.05V_VTT
+1.5V_CPU
+1.05V_VTT
+1.05V_VTT
+1.5V_SUS
+3.3V_ALW
CLK_EXP_N [23]CLK_EXP_P [23]
H_PM_SYNC[22]
PM_DRAM_PWRGD[22]
BCLK_CPU_P [25]BCLK_CPU_N [25]
H_PECI[25]
H_PWRGOOD[25,42]
PLT_RST#[21,37,64,65,70,76,77,80]
H_VTTPWRGD[49]
PM_EXTTS#1 [19]
SML0_DATA[23]
XDP_DBRESET# [22]
PM_PWRBTN#_R[22]
PLT_RST# [21,37,64,65,70,76,77,80]
H_THRMTRIP#[25,37,42]
PM_EXTTS#0 [18]
SML0_CLK[23]
H_PROCHOT#[47]
CLK_DP_N [23]CLK_DP_P [23]
DDR3_DRAMRST# [18,19]
DDR_RST_GATE [25]
VTT_PWRGD[25,37,49,50]
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (THERMAL/CLOCK/PM )
9 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (THERMAL/CLOCK/PM )
9 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (THERMAL/CLOCK/PM )
9 88Wednesday, September 09, 2009
Processor Compensation SignalsProcessor Pullups
DDR3 Compensation Signals
0611
CPU Only
GMCH Only
Scan Chain (Default)
Stuff --> R921, R922No Stuff --> R924, R926, R925
Stuff --> R921, R924, R926No Stuff --> R922, R925
Stuff --> R926, R925No Stuff --> R921, R922, R924
JTAG MAPPING
XDP ConnectorCPU
TCK(PIN AN28)TCK(PIN 57)
+1.05V_VCCP use Decoupling Capacitor closeITP connector 100 mil ( max )
XDP Connector
Revision 0.1
Calpella Platform S3 Power Reduction PlatformS3 Power Reduction CRB Implementation Design Details
DW07/07 Added1.Added discharge circuit08/05 Changed1.Changed Q901 from 2N7002 to BSS138 MOSFET,For Vgs(th)
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_A_DQ44
M_A_DQ36
M_A_DQ47
M_A_DQ40M_A_DQ39
M_A_DQ37
M_A_DQ35M_A_DQ34
M_A_DQ59
M_A_DQ54M_A_DQ53
M_A_DQ63
M_A_DQ60M_A_DQ61
M_A_DQ58
M_A_DQ51
M_A_DQ48
M_A_DQ57
M_A_DQ55
M_A_DQ49M_A_DQ50
M_A_DQ62
M_A_DQ52
M_A_DQ56
M_A_DQ[63..0]M_A_DQ0M_A_DQ1M_A_DQ2M_A_DQ3
M_A_DQ7
M_A_DQ5M_A_DQ4
M_A_DQ6
M_A_DQ12
M_A_DQ10
M_A_DQ13
M_A_DQ9M_A_DQ8
M_A_DQ11
M_A_DQ15M_A_DQ14
M_A_DQ27
M_A_DQ25
M_A_DQ20M_A_DQ19
M_A_DQ30
M_A_DQ18
M_A_DQ16
M_A_DQ28
M_A_DQ17
M_A_DQ26
M_A_DQ31
M_A_DQ29
M_A_DQ22M_A_DQ23M_A_DQ24
M_A_DQ21
M_A_DQ46
M_A_DQ42
M_A_DQ38
M_A_DQ32
M_A_DQ45
M_A_DQ33
M_A_DQ43
M_A_DQ41
M_A_DM0M_A_DM1M_A_DM2M_A_DM3M_A_DM4M_A_DM5M_A_DM6M_A_DM7
M_A_A0
M_A_A6
M_A_A3
M_A_A5
M_A_A7
M_A_A1M_A_A2
M_A_A4
M_A_A10
M_A_A8
M_A_A13
M_A_A11
M_A_A9
M_A_A12
M_A_A14
M_B_DQ0M_B_DQ1M_B_DQ2M_B_DQ3M_B_DQ4M_B_DQ5M_B_DQ6M_B_DQ7M_B_DQ8M_B_DQ9M_B_DQ10M_B_DQ11
M_B_DQ15
M_B_DQ13M_B_DQ12
M_B_DQ14
M_B_DQ16M_B_DQ17M_B_DQ18M_B_DQ19
M_B_DQ23
M_B_DQ21M_B_DQ20
M_B_DQ22
M_B_DQ28
M_B_DQ26
M_B_DQ29
M_B_DQ25
M_B_DQ31
M_B_DQ24
M_B_DQ27
M_B_DQ30
M_B_DQ32M_B_DQ33M_B_DQ34M_B_DQ35
M_B_DQ39
M_B_DQ37M_B_DQ36
M_B_DQ38
M_B_DQ44
M_B_DQ42
M_B_DQ45
M_B_DQ41
M_B_DQ47
M_B_DQ40
M_B_DQ43
M_B_DQ46
M_B_DQ48M_B_DQ49M_B_DQ50M_B_DQ51
M_B_DQ55
M_B_DQ53M_B_DQ52
M_B_DQ54
M_B_DQ60
M_B_DQ58
M_B_DQ61
M_B_DQ57
M_B_DQ63
M_B_DQ56
M_B_DQ59
M_B_DQ62
M_B_DQ[63..0]
M_B_A12
M_B_A9
M_B_A11
M_B_A13
M_B_A8
M_B_A10
M_B_A0M_B_A1M_B_A2M_B_A3M_B_A4M_B_A5M_B_A6M_B_A7
M_B_DM0M_B_DM1M_B_DM2M_B_DM3M_B_DM4M_B_DM5M_B_DM6M_B_DM7
M_B_A14
M_A_DQS#0
M_A_DQS#3
M_A_DQS#6
M_A_DQS#4
M_A_DQS#1M_A_DQS#2
M_A_DQS#5
M_A_DQS#7
M_A_DQS5
M_A_DQS7
M_A_DQS2M_A_DQS3M_A_DQS4
M_A_DQS0M_A_DQS1
M_A_DQS6
M_B_A15
M_B_DQS#0M_B_DQS#1M_B_DQS#2M_B_DQS#3M_B_DQS#4M_B_DQS#5M_B_DQS#6M_B_DQS#7
M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7
M_A_A15
M_A_DQ[63..0][18]
M_B_DQ[63..0][19]M_CLK_DDR0 [18]M_CLK_DDR#0 [18]M_CKE0 [18]
M_CS1# [18]M_CS0# [18]
M_CLK_DDR1 [18]M_CLK_DDR#1 [18]M_CKE1 [18]
M_ODT1 [18]M_ODT0 [18]
M_CLK_DDR2 [19]M_CLK_DDR#2 [19]M_CKE2 [19]
M_CS3# [19]M_CS2# [19]
M_ODT3 [19]M_ODT2 [19]
M_CLK_DDR3 [19]M_CLK_DDR#3 [19]M_CKE3 [19]
M_A_BS0[18]M_A_BS1[18]M_A_BS2[18]
M_B_BS0[19]M_B_BS1[19]M_B_BS2[19]
M_A_CAS#[18]M_A_RAS#[18]M_A_WE#[18]
M_B_CAS#[19]M_B_RAS#[19]M_B_WE#[19]
M_A_DM[7..0] [18]M_A_DQS#[7..0] [18]
M_A_DQS[7..0] [18]M_A_A[15..0] [18]
M_B_DQS#[7..0] [19]M_B_DM[7..0] [19]
M_B_DQS[7..0] [19]M_B_A[15..0] [19]
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (DDR)
10 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (DDR)
10 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (DDR)
10 88Wednesday, September 09, 2009
SA_BS0AC3SA_BS1AB2SA_BS2U7
SA_CAS#AE1SA_RAS#AB3SA_WE#AE9
SA_CK0 AA6
SA_CK1 Y6
SA_CK#0 AA7
SA_CK#1 Y5
SA_CKE0 P7
SA_CKE1 P6
SA_CS#0 AE2SA_CS#1 AE8
SA_ODT0 AD8SA_ODT1 AF9
SA_DM0 B9SA_DM1 D7SA_DM2 H7SA_DM3 M7SA_DM4 AG6SA_DM5 AM7SA_DM6 AN10SA_DM7 AN13
SA_DQS0 C8
SA_DQS#0 C9
SA_DQS1 F9
SA_DQS#1 F8
SA_DQS2 H9
SA_DQS#2 J9
SA_DQS3 M9
SA_DQS#3 N9
SA_DQS4 AH8
SA_DQS#4 AH7
SA_DQS5 AK10
SA_DQS#5 AK9
SA_DQS6 AN11
SA_DQS#6 AP11
SA_DQS7 AR13
SA_DQS#7 AT13
SA_MA0 Y3SA_MA1 W1SA_MA2 AA8SA_MA3 AA3SA_MA4 V1SA_MA5 AA9SA_MA6 V8SA_MA7 T1SA_MA8 Y9SA_MA9 U6
SA_MA10 AD4SA_MA11 T2SA_MA12 U3SA_MA13 AG8SA_MA14 T3SA_MA15 V9
SA_DQ0A10SA_DQ1C10SA_DQ2C7SA_DQ3A7SA_DQ4B10SA_DQ5D10SA_DQ6E10SA_DQ7A8SA_DQ8D8SA_DQ9F10SA_DQ10E6SA_DQ11F7SA_DQ12E9SA_DQ13B7SA_DQ14E7SA_DQ15C6SA_DQ16H10SA_DQ17G8SA_DQ18K7SA_DQ19J8SA_DQ20G7SA_DQ21G10SA_DQ22J7SA_DQ23J10SA_DQ24L7SA_DQ25M6SA_DQ26M8SA_DQ27L9SA_DQ28L6SA_DQ29K8SA_DQ30N8SA_DQ31P9SA_DQ32AH5SA_DQ33AF5SA_DQ34AK6SA_DQ35AK7SA_DQ36AF6SA_DQ37AG5SA_DQ38AJ7SA_DQ39AJ6SA_DQ40AJ10SA_DQ41AJ9SA_DQ42AL10SA_DQ43AK12SA_DQ44AK8SA_DQ45AL7SA_DQ46AK11SA_DQ47AL8SA_DQ48AN8SA_DQ49AM10SA_DQ50AR11SA_DQ51AL11SA_DQ52AM9SA_DQ53AN9SA_DQ54AT11SA_DQ55AP12SA_DQ56AM12SA_DQ57AN12SA_DQ58AM13SA_DQ59AT14SA_DQ60AT12SA_DQ61AL13SA_DQ62AR14SA_DQ63AP14
D
D
R
S
Y
S
T
E
M
M
E
M
O
R
Y
A
3 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1C
CLARKUNF
D
D
R
S
Y
S
T
E
M
M
E
M
O
R
Y
A
3 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1C
CLARKUNF
SB_BS0AB1SB_BS1W5SB_BS2R7
SB_CAS#AC5SB_RAS#Y7SB_WE#AC6
SB_CK0 W8
SB_CK1 V7
SB_CK#0 W9
SB_CK#1 V6
SB_CKE0 M3
SB_CKE1 M2
SB_CS#0 AB8SB_CS#1 AD6
SB_ODT0 AC7SB_ODT1 AD1
SB_DM0 D4SB_DM1 E1SB_DM2 H3SB_DM3 K1SB_DM4 AH1SB_DM5 AL2SB_DM6 AR4SB_DM7 AT8
SB_DQS4 AG2
SB_DQS#4 AH2
SB_DQS5 AL5
SB_DQS#5 AL4
SB_DQS6 AP5
SB_DQS#6 AR5
SB_DQS7 AR7
SB_DQS#7 AR8
SB_DQS0 C5
SB_DQS#0 D5
SB_DQS1 E3
SB_DQS#1 F4
SB_DQS2 H4
SB_DQS#2 J4
SB_DQS3 M5
SB_DQS#3 L4
SB_MA0 U5SB_MA1 V2SB_MA2 T5SB_MA3 V3SB_MA4 R1SB_MA5 T8SB_MA6 R2SB_MA7 R6SB_MA8 R4SB_MA9 R5
SB_MA10 AB5SB_MA11 P3SB_MA12 R3SB_MA13 AF7SB_MA14 P5SB_MA15 N1
SB_DQ0B5SB_DQ1A5SB_DQ2C3SB_DQ3B3SB_DQ4E4SB_DQ5A6SB_DQ6A4SB_DQ7C4SB_DQ8D1SB_DQ9D2SB_DQ10F2SB_DQ11F1SB_DQ12C2SB_DQ13F5SB_DQ14F3SB_DQ15G4SB_DQ16H6SB_DQ17G2SB_DQ18J6SB_DQ19J3SB_DQ20G1SB_DQ21G5SB_DQ22J2SB_DQ23J1SB_DQ24J5SB_DQ25K2SB_DQ26L3SB_DQ27M1SB_DQ28K5SB_DQ29K4SB_DQ30M4SB_DQ31N5SB_DQ32AF3SB_DQ33AG1SB_DQ34AJ3SB_DQ35AK1SB_DQ36AG4SB_DQ37AG3SB_DQ38AJ4SB_DQ39AH4SB_DQ40AK3SB_DQ41AK4SB_DQ42AM6SB_DQ43AN2SB_DQ44AK5SB_DQ45AK2SB_DQ46AM4SB_DQ47AM3SB_DQ48AP3SB_DQ49AN5SB_DQ50AT4SB_DQ51AN6SB_DQ52AN4SB_DQ53AN3SB_DQ54AT5SB_DQ55AT6SB_DQ56AN7SB_DQ57AP6SB_DQ58AP8SB_DQ59AT9SB_DQ60AT7SB_DQ61AP9SB_DQ62AR10SB_DQ63AT10 D
D
R
S
Y
S
T
E
M
M
E
M
O
R
Y
-
B
4 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1D
CLARKUNF
D
D
R
S
Y
S
T
E
M
M
E
M
O
R
Y
-
B
4 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1D
CLARKUNF
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG0
CFG3CFG4
CFG0
CFG4
CFG7
CFG7
CFG3
SB_DIMM_VREF#SA_DIMM_VREF#
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (RESERVED)
11 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (RESERVED)
11 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (RESERVED)
11 88Wednesday, September 09, 2009
PCI-Express Configuration Select
CFG01:Single PEG0:Bifurcation enabled
CFG4 - Display Port Presence
CFG41:Disabled; No Physical Display Portattached to Embedded Display Port0:Enabled; An external Display Portdevice is connected to the EmbeddedDisplay Port
VSS (AP34) can be left NC isCRB implementation; EDS/DGrecommendation to GND.
CFG7(Reserved) - Temporarily used for early Clarksfield samples.
CFG7 Clarksfield (only for early samples pre-ES1) -Connect to GND with 3.01K Ohm/5% resistor.
Note: Only temporary for early CFD sample(rPGA/BGA) [For details please refer to theWW33 MoW and sighting report].For a common M/B design (for AUB and CFD),the pull-down resistor shouble be used. Doesnot impact AUB functionality.
CFG3 - PCI-Express Static Lane Reversal
CFG31 :Normal Operation0 :Lane Numbers Reversed15 -> 0, 14 -> 1, ...
DIS5%
Calpella Platform Design Guide Revision 1.6
Switchable GFX, just like integrated GFX only, to enable LVDS it is required that the OEM set the LDVS (L_DDC_DATA) strap to present (pulled up) and the eDP strap (CFG[4]) to disabled (not pulled down).
4.8.3.1 LVDS Switching
DW07/02 Added1.Added display Switchable strap commentariat
4.8.3.2 eDP SwitchingeDP for Switchable GFX can only be driven out of Port D of PCH. To configure Port D for embedded DP it is required to set the DDPD_CTRLDATA strap high to 3.3V Core rail through 2.2 k 5% resistor, LVDS (L_DDC_DATA) strap as no connect and the eDP strap CFG[4] as no connect. Page 482,486
DW07/02 Del R11041.DW50 Only support Arrandale
DW07/10 Reversal1.PCI-Express Static Lane Reversal
1TP1116TP1116
1
2
R11013KR2F-GPDYR11013KR2F-GPDY
CFG0AM30CFG1AM28CFG2AP31CFG3AL32CFG4AL30CFG5AM31CFG6AN29CFG7AM32CFG8AK32CFG9AK31CFG10AK28CFG11AJ28CFG12AN30CFG13AN32CFG14AJ32CFG15AJ29CFG16AJ30CFG17AK30
RSVD#AH25 AH25RSVD#AK26 AK26
RSVD#AJ26 AJ26RSVD#AJ27 AJ27
RSVD_TP_86H16
RSVD#AL28 AL28RSVD#AL29 AL29RSVD#AP30 AP30RSVD#AP32 AP32RSVD#AL27 AL27RSVD#AT31 AT31RSVD#AT32 AT32RSVD#AP33 AP33RSVD#AR33 AR33
RSVD#AR32 AR32
RSVD#J28J28RSVD#J29J29
RSVD#A19A19RSVD#B19B19
RSVD#A20A20RSVD#B20B20
RSVD#T9T9RSVD#U9U9
RSVD#AB9AB9RSVD#AC9AC9
SA_CK2 AA5SA_CK#2 AA4SA_CKE2 R8
SA_CK3 AA2SA_CK#3 AA1SA_CKE3 R9
SA_CS#2 AD3
SA_CS#3 AG7
SA_ODT2 AD2
SA_ODT3 AE3
SB_CK2 V4SB_CK#2 V5SB_CKE2 N2
SB_CK3 W3SB_CK#3 W2SB_CKE3 N3
SB_CS#2 AD5
SB_CS#3 AE5
SB_ODT2 AD7
SB_ODT3 AD9
RSVD#AL26 AL26RSVD_NCTF_37 AR2
RSVD#AP25AP25RSVD#AL25AL25RSVD#AL24AL24RSVD#AL22AL22RSVD#AJ33AJ33RSVD#AG9AG9RSVD#M27M27RSVD#L28L28SA_DIMM_VREFJ17SB_DIMM_VREFH17RSVD#G25G25RSVD#G17G17RSVD#E31E31RSVD#E30E30
RSVD#AJ13 AJ13RSVD#AJ12 AJ12
RSVD_TP#E15 E15RSVD_TP#F15 F15
KEY A2RSVD#D15 D15RSVD#C15 C15
RSVD#AJ15 AJ15RSVD#AH15 AH15
VSS AP34
R
E
S
E
R
V
E
D
5 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1E
CLARKUNF
R
E
S
E
R
V
E
D
5 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1E
CLARKUNF
1TP1117TP1117
1
TP1118TPAD14-GPTP1118TPAD14-GP
1
2
R11023KR2F-GPR11023KR2F-GP
1
2
R11033KR2F-GPDYR11033KR2F-GPDY
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_SENSE
CPU_VID6
VSS_SENSE
CPU_VID0CPU_VID1CPU_VID2CPU_VID3CPU_VID4CPU_VID5
TP_H_VTTVID1
TP_VSS_SENSE_VTT
+VCC_CORE
+1.05V_VTT
+1.05V_VTT
+1.05V_VTT
+VCC_CORE
+VCC_CORE
CPU_VID[6..0] [47]
VCC_SENSE [47]VSS_SENSE [47]
PSI# [47]
PM_DPRSLPVR [47]
IMVP_IMON [47]
VTT_SENSE [49]
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (VCC_CORE)
12 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (VCC_CORE)
12 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (VCC_CORE)
12 88Wednesday, September 09, 2009
PROCESSOR CORE POWER
The decoupling capacitors, filterrecommendations and sense resistors on theCPU/PCH Rails are specific to the CRBImplementation. Customers need to follow the recommendations in the Calpella PlatformDesign Guide.
Please note that the VTT RailValues are Arrandale VTT=1.05V; Clarksfield VTT=1.1V
H_VTTVID1 = Low, 1.1VH_VTTVID1 = High, 1.05V
48A
1
2
C1209
SC10U
6D3V5M
X-3G
P
C1209
SC10U
6D3V5M
X-3G
P
1
2
C1206
SC10U
6D3V5M
X-3G
P
C1206
SC10U
6D3V5M
X-3G
P
1
2
C1208
SC10U
6D3V5M
X-3G
P
C1208
SC10U
6D3V5M
X-3G
P
1
2
C1236
SC10U
6D3V5M
X-3G
P
C1236
SC10U
6D3V5M
X-3G
P
1
2
C1232
SC10U
6D3V5M
X-3G
P
C1232
SC10U
6D3V5M
X-3G
P
1
2
C1218
SC10U
10V5ZY-1G
P
C1218
SC10U
10V5ZY-1G
P
1
2
C1212
SC10U
6D3V5M
X-3G
P
C1212
SC10U
6D3V5M
X-3G
P
1
2
R1204100R2F-L1-GP-UR1204100R2F-L1-GP-U
1
2
C1217SC22U
6D3V5M
X-2G
P
C1217SC22U
6D3V5M
X-2G
P
1
2
C1201
SC10U
10V5ZY-1G
P
C1201
SC10U
10V5ZY-1G
P
1
2
C1227
SC10U
6D3V5M
X-3G
P
C1227
SC10U
6D3V5M
X-3G
P
1
2
C1237
SC10U
6D3V5M
X-3G
P
C1237
SC10U
6D3V5M
X-3G
P
1
2
C1215
SC22U
6D3V5M
X-2G
P
C1215
SC22U
6D3V5M
X-2G
P
1
2
C1241
SC22U
6D3V5M
X-2G
P
C1241
SC22U
6D3V5M
X-2G
P
1
2
C1204
SC10U
10V5ZY-1G
P
DYC1204
SC10U
10V5ZY-1G
P
DY
1 TP1202TPAD14-GPTP1202TPAD14-GP
1
2
C1211
SC10U
6D3V5M
X-3G
P
C1211
SC10U
6D3V5M
X-3G
P
1
2
C1231
SC10U
6D3V5M
X-3G
P
C1231
SC10U
6D3V5M
X-3G
P
1
2
C1226
SC10U
6D3V5M
X-3G
P
C1226
SC10U
6D3V5M
X-3G
P
1
2
C1224
SC10U
6D3V5M
X-3G
P
C1224
SC10U
6D3V5M
X-3G
P
1 TP1203 TPAD14-GPTP1203 TPAD14-GP
1
2
C1223
SC10U
6D3V5M
X-3G
P
C1223
SC10U
6D3V5M
X-3G
P
1
2
C1240
SC22U
6D3V5M
X-2G
P
C1240
SC22U
6D3V5M
X-2G
P
ISENSE AN35
VTT_SENSE B15
PSI# AN33
VID AK35VID AK33VID AK34VID AL35VID AL33VID AM33VID AM35
PROC_DPRSLPVR AM34
VTT_SELECT G15
VCC_SENSE AJ34
VSS_SENSE_VTT A15
VCCAG35VCCAG34VCCAG33VCCAG32VCCAG31VCCAG30VCCAG29VCCAG28VCCAG27VCCAG26VCCAF35VCCAF34VCCAF33VCCAF32VCCAF31VCCAF30VCCAF29VCCAF28VCCAF27VCCAF26VCCAD35VCCAD34VCCAD33VCCAD32VCCAD31VCCAD30VCCAD29VCCAD28VCCAD27VCCAD26VCCAC35VCCAC34VCCAC33VCCAC32VCCAC31VCCAC30VCCAC29VCCAC28VCCAC27VCCAC26VCCAA35VCCAA34VCCAA33VCCAA32VCCAA31VCCAA30VCCAA29VCCAA28VCCAA27VCCAA26VCCY35VCCY34VCCY33VCCY32VCCY31VCCY30VCCY29VCCY28VCCY27VCCY26VCCV35VCCV34VCCV33VCCV32VCCV31VCCV30VCCV29VCCV28VCCV27VCCV26VCCU35VCCU34VCCU33VCCU32VCCU31VCCU30VCCU29VCCU28VCCU27VCCU26VCCR35VCCR34VCCR33VCCR32VCCR31VCCR30VCCR29VCCR28VCCR27VCCR26VCCP35VCCP34VCCP33VCCP32VCCP31VCCP30VCCP29VCCP28VCCP27VCCP26
VTT0 AF10VTT0 AE10VTT0 AC10VTT0 AB10VTT0 Y10VTT0 W10VTT0 U10VTT0 T10VTT0 J12VTT0 J11
VTT0 AH14VTT0 AH12VTT0 AH11VTT0 AH10VTT0 J14VTT0 J13VTT0 H14VTT0 H12VTT0 G14VTT0 G13VTT0 G12VTT0 G11VTT0 F14VTT0 F13VTT0 F12VTT0 F11VTT0 E14VTT0 E12VTT0 D14VTT0 D13VTT0 D12VTT0 D11VTT0 C14VTT0 C13VTT0 C12VTT0 C11VTT0 B14VTT0 B12VTT0 A14VTT0 A13VTT0 A12VTT0 A11
VSS_SENSE AJ35
VTT0 J16VTT0 J15
P
O
W
E
R
CPU CORE SUPPLY
1
.
1
V
R
A
I
L
P
O
W
E
R
S
E
N
S
E
L
I
N
E
S
C
P
U
V
I
D
S
6 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1F
CLARKUNF
P
O
W
E
R
CPU CORE SUPPLY
1
.
1
V
R
A
I
L
P
O
W
E
R
S
E
N
S
E
L
I
N
E
S
C
P
U
V
I
D
S
6 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1F
CLARKUNF
1
2
C1225
SC10U
6D3V5M
X-3G
P
C1225
SC10U
6D3V5M
X-3G
P
1
2
C1233
SC10U
6D3V5M
X-3G
P
C1233
SC10U
6D3V5M
X-3G
P
1
2
C1205
SC10U
10V5ZY-1G
P
DYC1205
SC10U
10V5ZY-1G
P
DY
1
2
C1220
SC10U
6D3V5M
X-3G
P
C1220
SC10U
6D3V5M
X-3G
P
1
2
C1214
SC22U
6D3V5M
X-2G
P
C1214
SC22U
6D3V5M
X-2G
P
1
2
C1234
SC10U
6D3V5M
X-3G
P
C1234
SC10U
6D3V5M
X-3G
P
1
2
C1243
SC10U
6D3V5M
X-3G
P
DYC1243
SC10U
6D3V5M
X-3G
P
DY
1
2
C1228
SC10U
6D3V5M
X-3G
P
C1228
SC10U
6D3V5M
X-3G
P
1
2
C1238
SC10U
6D3V5M
X-3G
P
C1238
SC10U
6D3V5M
X-3G
P
1
2
C1242
SC22U
6D3V5M
X-2G
P
C1242
SC22U
6D3V5M
X-2G
P
1
2
R1201100R2F-L1-GP-UR1201100R2F-L1-GP-U
1
2
C1213
SC10U
6D3V5M
X-3G
P
C1213
SC10U
6D3V5M
X-3G
P
1
2
C1230
SC10U
6D3V5M
X-3G
P
C1230
SC10U
6D3V5M
X-3G
P
1
2
C1222
SC10U
6D3V5M
X-3G
P
C1222
SC10U
6D3V5M
X-3G
P
1
2
C1216
SC10U
10V5ZY-1G
P
C1216
SC10U
10V5ZY-1G
P
1
2
C1210
SC10U
6D3V5M
X-3G
P
C1210
SC10U
6D3V5M
X-3G
P
1
2
C1229
SC10U
6D3V5M
X-3G
P
C1229
SC10U
6D3V5M
X-3G
P
1
2
C1235
SC10U
6D3V5M
X-3G
P
C1235
SC10U
6D3V5M
X-3G
P
1
2
C1239
SC22U
6D3V5M
X-2G
P
C1239
SC22U
6D3V5M
X-2G
P
1
2
C1221
SC10U
6D3V5M
X-3G
P
C1221
SC10U
6D3V5M
X-3G
P
1
2
C1203
SC22U
6D3V5M
X-2G
P
C1203
SC22U
6D3V5M
X-2G
P
1
2
C1207
SC10U
6D3V5M
X-3G
P
C1207
SC10U
6D3V5M
X-3G
P
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TP_GFX_DPRSLPVR
+1.05V_VTT
+1.5V_CPU
+1.05V_VTT
+1.05V_VTT
+1.8V_RUN
+1.05V_VTT
+CPU_GFXCORE
+1.5V_CPU
+1.5V_SUS
+1.5V_CPU
+1.5V_SUS
+1.5V_CPU
+1.5V_SUS
+1.5V_CPU
+1.5V_SUS
GFX_VR_EN [53]
VCC_AXG_SENSE [53]VSS_AXG_SENSE [53]
GFX_IMON [53]
GFX_VID0 [53]GFX_VID1 [53]GFX_VID2 [53]GFX_VID3 [53]GFX_VID4 [53]GFX_VID5 [53]GFX_VID6 [53]
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (VCC_GFXCORE)
13 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (VCC_GFXCORE)
13 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (VCC_GFXCORE)
13 88Wednesday, September 09, 2009
18A
1.35A
3A
Please note that the VTT RailValues are Arrandale VTT=1.05V;Clarksfield VTT=1.1V
22A
VCCPLL1VCCPLL2VCCPLL3
425302_425302_Calpella_S3PowerReduction_WhitePapeRevision 0.7
1
2
C1310SC10U6D3V5MX-3GP
C1310SC10U6D3V5MX-3GP
1
2
C1309SC10U6D3V5MX-3GPC1309SC10U6D3V5MX-3GP
1
2
C1322SC10U6D3V5MX-3GPC1322SC10U6D3V5MX-3GP
1
2
C1379SCD1U10V2KX-4GP
DYC1379SCD1U10V2KX-4GP
DY
1
2
C1326
SC22U6D3V5MX
-2GP
C1326
SC22U6D3V5MX
-2GP
1
2
C1327
SC22U6D3V5MX
-2GP
C1327
SC22U6D3V5MX
-2GP
1
2
TC1301SE330U2D5VDM-2GPTC1301SE330U2D5VDM-2GP
1
2
C1314SC10U6D3V5MX
-3GP
C1314SC10U6D3V5MX
-3GP
1
2
C1302SC1U10V2KX-1G
P
C1302SC1U10V2KX-1G
P
GFX_VID AM22GFX_VID AP22GFX_VID AN22GFX_VID AP23GFX_VID AM23GFX_VID AP24GFX_VID AN24
GFX_VR_EN AR25GFX_DPRSLPVR AT25
GFX_IMON AM24
VAXG_SENSE AR22VSSAXG_SENSE AT22
VAXGAT21VAXGAT19VAXGAT18VAXGAT16VAXGAR21VAXGAR19VAXGAR18VAXGAR16VAXGAP21VAXGAP19VAXGAP18VAXGAP16VAXGAN21VAXGAN19VAXGAN18VAXGAN16VAXGAM21VAXGAM19VAXGAM18VAXGAM16VAXGAL21VAXGAL19VAXGAL18VAXGAL16VAXGAK21VAXGAK19VAXGAK18VAXGAK16VAXGAJ21VAXGAJ19VAXGAJ18VAXGAJ16VAXGAH21VAXGAH19VAXGAH18VAXGAH16
VTT1J24VTT1J23VTT1H25
VTT1K26VTT1J27VTT1J26VTT1J25VTT1H27VTT1G28VTT1G27VTT1G26VTT1F26VTT1E26VTT1E25
VDDQ AJ1VDDQ AF1VDDQ AE7VDDQ AE4VDDQ AC1VDDQ AB7VDDQ AB4VDDQ Y1VDDQ W7VDDQ W4VDDQ U1VDDQ T7VDDQ T4VDDQ P1VDDQ N7VDDQ N4VDDQ L1VDDQ H1
VTT0 P10VTT0 N10VTT0 L10VTT0 K10
VCCPLL L26VCCPLL L27VCCPLL M26
VTT1 J22VTT1 J20VTT1 J18VTT1 H21VTT1 H20VTT1 H19
P
O
W
E
R
G
R
A
P
H
I
C
S
V
I
D
s
GRAPHICS
D
D
R
3
-
1
.
5
V
R
A
I
L
S
FDI
PEG & DMI
S
E
N
S
E
L
I
N
E
S
1
.
1
V
1
.
8
V
7 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1G
CLARKUNF
P
O
W
E
R
G
R
A
P
H
I
C
S
V
I
D
s
GRAPHICS
D
D
R
3
-
1
.
5
V
R
A
I
L
S
FDI
PEG & DMI
S
E
N
S
E
L
I
N
E
S
1
.
1
V
1
.
8
V
7 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1G
CLARKUNF
1
2
C1305SC1U10V2KX-1G
P
C1305SC1U10V2KX-1G
P
1
2
C1307SC10U6D3V5MX
-3GP
C1307SC10U6D3V5MX
-3GP
1
2
C1320SC4D7U6D3V5KX
-3GP
C1320SC4D7U6D3V5KX
-3GP
1
2
C1303SC1U10V2KX-1G
P
C1303SC1U10V2KX-1G
P
1
2
C1321SC2D2U10V3KX
-1GP
C1321SC2D2U10V3KX
-1GP
1
2
C1312SC10U6D3V5MX
-3GP
C1312SC10U6D3V5MX
-3GP
1
2
C1311SC10U6D3V5MX-3GPC1311SC10U6D3V5MX-3GP
1
2
C1376SCD1U10V2KX-4GP
DYC1376SCD1U10V2KX-4GP
DY
1
2
C1304SC1U10V2KX-1G
P
C1304SC1U10V2KX-1G
P
1
2
C1301SC1U10V2KX-1G
P
C1301SC1U10V2KX-1G
P
1
2
C1316SC10U6D3V5MX-3GP
C1316SC10U6D3V5MX-3GP
1
2
C1378SCD1U10V2KX-4GP
DYC1378SCD1U10V2KX-4GP
DY
1
2
C1319SC1U25V5KX-1G
P
C1319SC1U25V5KX-1G
P
1 TP1303TPAD14-GPTP1303TPAD14-GP
1
2
C1377SCD1U10V2KX-4GP
DYC1377SCD1U10V2KX-4GP
DY
1
2
TC1303
SE330U2VDM
-L-G
P
DYTC1303
SE330U2VDM
-L-G
P
DY
1
2
C1328
SC10U6D3V5MX
-3GP
C1328
SC10U6D3V5MX
-3GP
1
2
C1318SC1U25V5KX-1G
P
C1318SC1U25V5KX-1G
P
1
2
C1306SC10U6D3V5MX
-3GP
C1306SC10U6D3V5MX
-3GP
1
2
C1315SC10U6D3V5MX
-3GP
C1315SC10U6D3V5MX
-3GP
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TP_MCP_VSS_NCTF2
TP_MCP_VSS_NCTF1TP_MCP_VSS_NCTF4TP_MCP_VSS_NCTF3
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (VSS)
14 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (VSS)
14 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00CPU (VSS)
14 88Wednesday, September 09, 2009
VSSK27VSSK9VSSK6VSSK3VSSJ32VSSJ30VSSJ21VSSJ19VSSH35VSSH32VSSH28VSSH26VSSH24VSSH22VSSH18VSSH15VSSH13VSSH11VSSH8VSSH5VSSH2VSSG34VSSG31VSSG20VSSG9VSSG6VSSG3VSSF30VSSF27VSSF25VSSF22VSSF19VSSF16VSSE35VSSE32VSSE29VSSE24VSSE21VSSE18VSSE13VSSE11VSSE8VSSE5VSSE2VSSD33VSSD30VSSD26VSSD9VSSD6VSSD3VSSC34VSSC32VSSC29VSSC28VSSC24VSSC22VSSC20VSSC19VSSC16VSSB31VSSB25VSSB21VSSB18VSSB17VSSB13VSSB11VSSB8VSSB6VSSB4VSSA29
VSS_NCTF#AT35 AT35VSS_NCTF#AT1 AT1
VSS_NCTF AR34VSS_NCTF B34VSS_NCTF B2
VSS_NCTF#B1 B1
VSS_NCTF#A35 A35
VSSA27VSSA23VSSA9
RSVD_NCTF#A3 A3RSVD_NCTF#A33 A33RSVD_NCTF#A34 A34RSVD_NCTF#AP1 AP1
RSVD_NCTF#AP35 AP35RSVD_NCTF#AR1 AR1
RSVD_NCTF#AR35 AR35RSVD_NCTF#AT2 AT2RSVD_NCTF#AT3 AT3
RSVD_NCTF#AT33 AT33RSVD_NCTF#AT34 AT34
RSVD_NCTF#C1 C1RSVD_NCTF#C35 C35RSVD_NCTF#B35 B35
VSS
N
C
T
F
9 OF 9
C
L
A
R
K
S
F
I
E
L
D
N
C
Y
F
T
E
S
T
P
I
N
:
A
3
5
,
A
T
1
,
A
T
3
5
,
B
1
,
A
3
,
A
3
3
,
A
3
4
,
A
P
1
,
A
P
3
5
,
A
R
1
,
A
R
3
5
,
A
T
2
,
A
T
3
,
A
T
3
3
,
A
T
3
4
,
C
1
,
C
3
5
,
B
3
5
CPU1I
CLARKUNF
VSS
N
C
T
F
9 OF 9
C
L
A
R
K
S
F
I
E
L
D
N
C
Y
F
T
E
S
T
P
I
N
:
A
3
5
,
A
T
1
,
A
T
3
5
,
B
1
,
A
3
,
A
3
3
,
A
3
4
,
A
P
1
,
A
P
3
5
,
A
R
1
,
A
R
3
5
,
A
T
2
,
A
T
3
,
A
T
3
3
,
A
T
3
4
,
C
1
,
C
3
5
,
B
3
5
CPU1I
CLARKUNF
VSSAT20VSSAT17VSSAR31VSSAR28VSSAR26VSSAR24VSSAR23VSSAR20VSSAR17VSSAR15VSSAR12VSSAR9VSSAR6VSSAR3VSSAP20VSSAP17VSSAP13VSSAP10VSSAP7VSSAP4VSSAP2VSSAN34VSSAN31VSSAN23VSSAN20VSSAN17VSSAM29VSSAM27VSSAM25VSSAM20VSSAM17VSSAM14VSSAM11VSSAM8VSSAM5VSSAM2VSSAL34VSSAL31VSSAL23VSSAL20VSSAL17VSSAL12VSSAL9VSSAL6VSSAL3VSSAK29VSSAK27VSSAK25VSSAK20VSSAK17VSSAJ31VSSAJ23VSSAJ20VSSAJ17VSSAJ14VSSAJ11VSSAJ8VSSAJ5VSSAJ2VSSAH35VSSAH34VSSAH33VSSAH32VSSAH31VSSAH30VSSAH29VSSAH28VSSAH27VSSAH26VSSAH20VSSAH17VSSAH13VSSAH9VSSAH6VSSAH3VSSAG10VSSAF8VSSAF4VSSAF2VSSAE35
VSS AE34VSS AE33VSS AE32VSS AE31VSS AE30VSS AE29VSS AE28VSS AE27VSS AE26VSS AE6VSS AD10VSS AC8VSS AC4VSS AC2VSS AB35VSS AB34VSS AB33VSS AB32VSS AB31VSS AB30VSS AB29VSS AB28VSS AB27VSS AB26VSS AB6VSS AA10VSS Y8VSS Y4VSS Y2VSS W35VSS W34VSS W33VSS W32VSS W31VSS W30VSS W29VSS W28VSS W27VSS W26VSS W6VSS V10VSS U8VSS U4VSS U2VSS T35VSS T34VSS T33VSS T32VSS T31VSS T30VSS T29VSS T28VSS T27VSS T26VSS T6VSS R10VSS P8VSS P4VSS P2VSS N35VSS N34VSS N33VSS N32VSS N31VSS N30VSS N29VSS N28VSS N27VSS N26VSS N6VSS M10VSS L35VSS L32VSS L29VSS L8VSS L5VSS L2VSS K34VSS K33VSS K30
VSS
8 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1H
CLARKUNF
VSS
8 OF 9
C
L
A
R
K
S
F
I
E
L
D
CPU1H
CLARKUNF
1 TP1406TP14061 TP1402TP1402
1 TP1405TP14051 TP1401TP1401
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00Reserved
A3
15 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00Reserved
A3
15 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00Reserved
A3
15 88Wednesday, September 09, 2009
(Blanking)
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00Reserved
A3
16 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00Reserved
A3
16 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00Reserved
A3
16 88Wednesday, September 09, 2009
(Blanking)
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SA(Reserve)
Custom
17 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SA(Reserve)
Custom
17 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SA(Reserve)
Custom
17 88Wednesday, September 09, 2009
(Blank)
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_A_DQ5M_A_DQ6M_A_DQ7M_A_DQ8
M_A_DQ13M_A_DQ14M_A_DQ15M_A_DQ16
M_A_DQ9M_A_DQ10M_A_DQ11M_A_DQ12
M_A_A0
M_A_DQ21M_A_DQ22M_A_DQ23M_A_DQ24
M_A_DQ29M_A_DQ30M_A_DQ31M_A_DQ32
M_A_DQ17M_A_DQ18
M_A_DQ25M_A_DQ26M_A_DQ27M_A_DQ28
M_A_DQ19M_A_DQ20
M_A_A1
M_A_DQ37M_A_DQ38M_A_DQ39M_A_DQ40
M_A_DQ45M_A_DQ46M_A_DQ47M_A_DQ48
M_A_DQ41M_A_DQ42M_A_DQ43M_A_DQ44
M_A_DQ33M_A_DQ34M_A_DQ35M_A_DQ36
M_A_A2M_A_A3
M_A_DQ53M_A_DQ54M_A_DQ55M_A_DQ56
M_A_DQ61M_A_DQ62M_A_DQ63
M_A_DQ57M_A_DQ58M_A_DQ59M_A_DQ60
M_A_A4M_A_A5
M_A_DQ49M_A_DQ50M_A_DQ51M_A_DQ52
M_A_A6M_A_A7M_A_A8M_A_A9M_A_A10M_A_A11M_A_A12M_A_A13M_A_A14
M_A_BS1
M_A_DQS#6M_A_DQS#7
M_A_DQS0M_A_DQS1
M_A_DQ0
M_A_DQS2M_A_DQS3M_A_DQS4M_A_DQS5M_A_DQS6M_A_DQS7
M_ODT0M_ODT1
M_A_DQS#0
M_A_BS2
M_A_DQS#1M_A_DQS#2
M_A_BS0
M_A_DQS#3M_A_DQS#4M_A_DQS#5
M_A_DQ1M_A_DQ2M_A_DQ3M_A_DQ4
M_A_A15M_CLK_DDR1
SA0_DM1SA1_DM1
M_A_DM4M_A_DM5M_A_DM6M_A_DM7
PCH_SMBDATAPCH_SMBCLK
M_CLK_DDR0M_CLK_DDR#0
M_A_DM0M_A_DM1M_A_DM2M_A_DM3
M_CLK_DDR#1
SA0_DM1SA1_DM1
+V_DDR_REF
+0.75V_DDR_VTT
+0.75V_DDR_VTT
+1.5V_SUS
+V_DDR_REF
+3.3V_RUN
+1.5V_SUS
+1.5V_SUS
M_A_DQS#[7..0][10]M_A_DQ[63..0][10]M_A_DM[7..0][10]M_A_DQS[7..0][10]M_A_A[15..0][10] M_A_BS2[10]
M_A_BS0[10]M_A_BS1[10]
M_ODT0[10]M_ODT1[10]
DDR3_DRAMRST#[9,19]
M_CLK_DDR#0 [10]
M_CKE1 [10]
M_CS0# [10]
M_CLK_DDR#1 [10]M_CLK_DDR1 [10]
M_CKE0 [10]
M_A_WE# [10]M_A_CAS# [10]
M_CS1# [10]
M_CLK_DDR0 [10]
M_A_RAS# [10]
PCH_SMBDATA [7,19,23,40,64,65]PCH_SMBCLK [7,19,23,40,64,65]
PM_EXTTS#0 [9]
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SADDRIII-SODIMM SLOT1
Custom
18 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SADDRIII-SODIMM SLOT1
Custom
18 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SADDRIII-SODIMM SLOT1
Custom
18 88Wednesday, September 09, 2009
Layout Note:Place near DM1
SSID = MEMORY
Height 5.2mm
SMBUS address:A0
Layout Note:Put close to VTT1,VTT2.
DW07/02 Reserve1.Added SA0_DM1 pull-up resistor07/072.Reserve pull-hi,lo resistor
DW07/10 Added1.Added Power Decoupling Cap C1822,C1823 Bason on design guide
425302_425302_Calpella_S3PowerReduction_WhitePapeRevision 0.7
1
2
C1801SC1U10V2KX-1GPC1801SC1U10V2KX-1GP
1
2
C1802SC10U6D3V5MX-3GPC1802SC10U6D3V5MX-3GP
1
2
C1872SCD1U10V2KX-4GPC1872SCD1U10V2KX-4GP
A098A197A296A395A492A591A690A786A889A985A10/AP107A1184A1283A13119A1480A1578A16/BA279
BA0109BA1108
DQ05DQ17DQ215DQ317DQ44DQ56DQ616DQ718DQ821DQ923DQ1033DQ1135DQ1222DQ1324DQ1434DQ1536DQ1639DQ1741DQ1851DQ1953DQ2040DQ2142DQ2250DQ2352DQ2457DQ2559DQ2667DQ2769DQ2856DQ2958DQ3068DQ3170DQ32129DQ33131DQ34141DQ35143DQ36130DQ37132DQ38140DQ39142DQ40147DQ41149DQ42157DQ43159DQ44146DQ45148DQ46158DQ47160DQ48163DQ49165DQ50175DQ51177DQ52164DQ53166DQ54174DQ55176DQ56181DQ57183DQ58191DQ59193DQ60180DQ61182DQ62192DQ63194
DQS0#10DQS1#27DQS2#45DQS3#62DQS4#135DQS5#152DQS6#169DQS7#186
DQS012DQS129DQS247DQS364DQS4137DQS5154DQS6171DQS7188
ODT0116ODT1120
VREF_DQ1
VSS 2
NP1 NP1NP2 NP2
RAS# 110WE# 113
CAS# 115
CS0# 114CS1# 121
CKE0 73CKE1 74
CK0 101CK0# 103
CK1 102CK1# 104
DM0 11DM1 28DM2 46DM3 63DM4 136DM5 153DM6 170DM7 187
SDA 200SCL 202
VDDSPD 199
SA0 197SA1 201
VREF_CA126
VDD18 124
NC#1 77NC#2 122
NC#/TEST 125
VDD3 81VDD4 82VDD5 87VDD6 88VDD7 93VDD8 94VDD9 99
VDD10 100
VDD13 111VDD14 112VDD15 117VDD16 118
VSS 3VSS 8VSS 9VSS 13VSS 14VSS 19VSS 20VSS 25VSS 26VSS 31VSS 32VSS 37VSS 38VSS 43VSS 44VSS 48VSS 49VSS 54VSS 55VSS 60VSS 61
VDD1 75
VSS 65VSS 66VSS 71VSS 72
VDD2 76
VDD11 105VDD12 106
VDD17 123
VSS 127VSS 128
VSS 134VSS 133
VSS 138VSS 139VSS 144VSS 145
VSS 151VSS 150
VSS 155VSS 156VSS 161VSS 162VSS 167VSS 168
VSS 173VSS 172
VSS 179VSS 178
VSS 185VSS 184
VSS 189VSS 190VSS 195VSS 196
RESET#30
EVENT# 198
VSS 205VSS 206
VTT1203VTT2204
DM1
DDR3-204P-47-GP
62.10017.P31
DM1
DDR3-204P-47-GP
62.10017.P31
1
2
C1813SC1U10V2KX-1GPC1813SC1U10V2KX-1GP
1
2
C1804SC10U6D3V5MX-3GPC1804SC10U6D3V5MX-3GP
1
2
C1823SC10U6D3V5MX-3GPC1823SC10U6D3V5MX-3GP
1
2
R180210KR2J-3-GPR180210KR2J-3-GP
1
2
C1814SC1U10V2KX-1GPC1814SC1U10V2KX-1GP
1
2
C1874SCD1U10V2KX-4GPC1874SCD1U10V2KX-4GP
1
2
C1816SC10U6D3V5MX-3GPC1816SC10U6D3V5MX-3GP
1
2
C1810SCD1U16V2KX-3GPC1810SCD1U16V2KX-3GP
1
2
C1875SCD1U10V2KX-4GPC1875SCD1U10V2KX-4GP
1
2
C1812SC10U6D3V5MX-3GPC1812SC10U6D3V5MX-3GP
1
2
C1873SCD1U10V2KX-4GPC1873SCD1U10V2KX-4GP
1
2
C1805SC2D2U10V3KX-1GPC1805SC2D2U10V3KX-1GP
1
2
R180110KR2J-3-GPR180110KR2J-3-GP
1
2
C1807SC2D2U10V3KX-1GP
DY
C1807SC2D2U10V3KX-1GP
DY
1
2
C1817SCD1U16V2KX-3GPC1817SCD1U16V2KX-3GP
1
2
C1815SC1U10V2KX-1GPC1815SC1U10V2KX-1GP
1
2
C1803SC10U6D3V5MX-3GPC1803SC10U6D3V5MX-3GP
1
2
TC1803ST330U2D5VBM-1-GPTC1803ST330U2D5VBM-1-GP
1
2
C1811SC10U6D3V5MX-3GPC1811SC10U6D3V5MX-3GP
1
2
C1806SCD1U16V2KX-3GPC1806SCD1U16V2KX-3GP
1
2
C1809SC2D2U10V3KX-1GPC1809SC2D2U10V3KX-1GP
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_B_A0M_B_A1M_B_A2M_B_A3
M_B_DQ0
M_B_A4M_B_A5M_B_A6M_B_A7
M_B_DQ1
M_B_A8M_B_A9M_B_A10M_B_A11M_B_A12M_B_A13M_B_A14
M_B_DQ2M_B_DQ3M_B_DQ4M_B_DQ5M_B_DQ6M_B_DQ7M_B_DQ8M_B_DQ9M_B_DQ10M_B_DQ11M_B_DQ12M_B_DQ13M_B_DQ14M_B_DQ15
M_B_BS2
M_B_DQ16M_B_DQ17M_B_DQ18
M_B_BS0
M_B_DQ19M_B_DQ20M_B_DQ21M_B_DQ22M_B_DQ23M_B_DQ24M_B_DQ25M_B_DQ26M_B_DQ27M_B_DQ28M_B_DQ29M_B_DQ30M_B_DQ31
M_ODT2M_ODT3
M_B_DQ32M_B_DQ33M_B_DQ34M_B_DQ35M_B_DQ36M_B_DQ37
M_B_BS1
M_B_DQ38M_B_DQ39M_B_DQ40M_B_DQ41M_B_DQ42M_B_DQ43M_B_DQ44M_B_DQ45M_B_DQ46M_B_DQ47M_B_DQ48M_B_DQ49M_B_DQ50M_B_DQ51M_B_DQ52M_B_DQ53M_B_DQ54M_B_DQ55M_B_DQ56M_B_DQ57M_B_DQ58M_B_DQ59M_B_DQ60M_B_DQ61M_B_DQ62M_B_DQ63
M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7
M_B_DQS#1M_B_DQS#2M_B_DQS#3M_B_DQS#4M_B_DQS#5M_B_DQS#6M_B_DQS#7
M_B_DQS#0
M_B_A15
PCH_SMBDATAPCH_SMBCLK
M_CLK_DDR#3M_CLK_DDR3
M_CLK_DDR2M_CLK_DDR#2
M_B_DM5M_B_DM6M_B_DM7
M_B_DM0M_B_DM1M_B_DM2M_B_DM3M_B_DM4
SA1_DM2SA0_DM2
SA0_DM2SA1_DM2
+V_DDR_REF
+V_DDR_REF
+1.5V_SUS
+3.3V_RUN
+1.5V_SUS
+0.75V_DDR_VTT
+0.75V_DDR_VTT
+3.3V_RUN
+1.5V_SUS
M_B_DQS#[7..0][10]M_B_DQ[63..0][10]M_B_DM[7..0][10]M_B_DQS[7..0][10]M_B_A[15..0][10]
M_B_BS2[10]M_B_BS0[10]M_B_BS1[10]
M_ODT2[10]M_ODT3[10]
DDR3_DRAMRST#[9,18]
M_CLK_DDR#2 [10]M_CLK_DDR2 [10]
M_CLK_DDR#3 [10]M_CLK_DDR3 [10]
M_B_WE# [10]M_B_CAS# [10]M_B_RAS# [10]
M_CKE3 [10]
M_CS2# [10]
M_CKE2 [10]M_CS3# [10]
PCH_SMBCLK [7,18,23,40,64,65]PCH_SMBDATA [7,18,23,40,64,65]
PM_EXTTS#1 [9]
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SADDRIII-SODIMM SLOT2
Custom
19 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SADDRIII-SODIMM SLOT2
Custom
19 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella SADDRIII-SODIMM SLOT2
Custom
19 88Wednesday, September 09, 2009
SSID = MEMORY
Height 9.2mm
Layout Note:Place near DM2
Change CONN 2009/06/01 2009/08/04
SMBUS address:A4
Layout Note:Put close to VTT1,VTT2.
DW07/02 Reserve1.Added SA1_DM2 pull-down resistor07/072.Reserve pull-hi,lo resistor
Note: If SA0_DIM0 = 0, SA1_DIM0 = 0SO-DIMMA SPD Address is 0xA0If SA0_DIM0 = 1, SA1_DIM0 = 0SO-DIMMA SPD Address is 0xA2If SA0_DIM0 = 0, SA1_DIM0 = 1SO-DIMMA SPD Address is 0xA4
425302_425302_Calpella_S3PowerReduction_WhitePapeRevision 0.7
1
2
C1911SC10U6D3V5MX-3GPC1911SC10U6D3V5MX-3GP
1
2
C1921SC2D2U10V3KX-1GP
DY
C1921SC2D2U10V3KX-1GP
DY
1
2
C1907SCD1U16V2KX-3GPC1907SCD1U16V2KX-3GP
1
2
C1913SC10U6D3V5MX-3GPC1913SC10U6D3V5MX-3GP
1
2
C1905SC10U6D3V5MX-3GPC1905SC10U6D3V5MX-3GP
1
2
C1978SCD1U10V2KX-4GPC1978SCD1U10V2KX-4GP
1
2
C1920SC10U6D3V5MX-3GPC1920SC10U6D3V5MX-3GP
1
2
C1977SCD1U10V2KX-4GPC1977SCD1U10V2KX-4GP
1
2
C1914SC2D2U10V3KX-1GPC1914SC2D2U10V3KX-1GP
1
2
C1979SCD1U10V2KX-4GPC1979SCD1U10V2KX-4GP
1
2
R190210KR2J-3-GPDYR190210KR2J-3-GPDY
1
2
C1912SC2D2U10V3KX-1GPC1912SC2D2U10V3KX-1GP
1
2
C1919SC10U6D3V5MX-3GPC1919SC10U6D3V5MX-3GP
1
2
C1976SCD1U10V2KX-4GPC1976SCD1U10V2KX-4GP
1
2
C1908SC1U10V2KX-1GPC1908SC1U10V2KX-1GP
1
2
R190310KR2J-3-GPDYR190310KR2J-3-GPDY
1
2
R190410KR2J-3-GPR190410KR2J-3-GP
1
2
R190110KR2J-3-GPR190110KR2J-3-GP
1
2
C1906SCD1U16V2KX-3GPC1906SCD1U16V2KX-3GP
1
2
TC1903ST330U2D5VBM-1-GPTC1903ST330U2D5VBM-1-GP
1
2
C1917SC1U10V2KX-1GPC1917SC1U10V2KX-1GP
1
2
C1910SCD1U16V2KX-3GPC1910SCD1U16V2KX-3GP
1
2
C1918SC1U10V2KX-1GPC1918SC1U10V2KX-1GP
A098A197A296A395A492A591A690A786A889A985A10/AP107A1184A1283A13119A1480A1578A16/BA279
BA0109BA1108
DQ05DQ17DQ215DQ317DQ44DQ56DQ616DQ718DQ821DQ923DQ1033DQ1135DQ1222DQ1324DQ1434DQ1536DQ1639DQ1741DQ1851DQ1953DQ2040DQ2142DQ2250DQ2352DQ2457DQ2559DQ2667DQ2769DQ2856DQ2958DQ3068DQ3170DQ32129DQ33131DQ34141DQ35143DQ36130DQ37132DQ38140DQ39142DQ40147DQ41149DQ42157DQ43159DQ44146DQ45148DQ46158DQ47160DQ48163DQ49165DQ50175DQ51177DQ52164DQ53166DQ54174DQ55176DQ56181DQ57183DQ58191DQ59193DQ60180DQ61182DQ62192DQ63194
DQS0#10DQS1#27DQS2#45DQS3#62DQS4#135DQS5#152DQS6#169DQS7#186
DQS012DQS129DQS247DQS364DQS4137DQS5154DQS6171DQS7188
ODT0116ODT1120
VREF_DQ1
VSS 2
NP1 NP1NP2 NP2
RAS# 110WE# 113
CAS# 115
CS0# 114CS1# 121
CKE0 73CKE1 74
CK0 101CK0# 103
CK1 102CK1# 104
DM0 11DM1 28DM2 46DM3 63DM4 136DM5 153DM6 170DM7 187
SDA 200SCL 202
VDDSPD 199
SA0 197SA1 201
VREF_CA126
VDD18 124
NC#1 77NC#2 122
NC#/TEST 125
VDD3 81VDD4 82VDD5 87VDD6 88VDD7 93VDD8 94VDD9 99
VDD10 100
VDD13 111VDD14 112VDD15 117VDD16 118
VSS 3VSS 8VSS 9VSS 13VSS 14VSS 19VSS 20VSS 25VSS 26VSS 31VSS 32VSS 37VSS 38VSS 43VSS 44VSS 48VSS 49VSS 54VSS 55VSS 60VSS 61
VDD1 75
VSS 65VSS 66VSS 71VSS 72
VDD2 76
VDD11 105VDD12 106
VDD17 123
VSS 127VSS 128
VSS 134VSS 133
VSS 138VSS 139VSS 144VSS 145
VSS 151VSS 150
VSS 155VSS 156VSS 161VSS 162VSS 167VSS 168
VSS 173VSS 172
VSS 179VSS 178
VSS 185VSS 184
VSS 189VSS 190VSS 195VSS 196
RESET#30
EVENT# 198
VSS 205VSS 206
VTT1203VTT2204
DM2
DDR3-204P-55-GP
62.10017.Q31
DM2
DDR3-204P-55-GP
62.10017.Q31
1
2
C1909SC1U10V2KX-1GPC1909SC1U10V2KX-1GP
1
2
C1916SC10U6D3V5MX-3GPC1916SC10U6D3V5MX-3GP
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PANEL_BKEN_PCHR
TP_LVDS_VBGLIBG
CRT_IREF
LCDVDD_EN_PCH
LCTLB_DATA
MCH_BLUE
MCH_REDMCH_GREEN
LCTLA_CLK
LCDVDD_EN_PCH
HDMI_DATA2+_CHDMI_DATA2-_C
HDMI_CLK-_C
HDMI_DATA1-_C
HDMI_CLK+_C
HDMI_DATA1+_CHDMI_DATA0-_CHDMI_DATA0+_C
+3.3V_RUN
L_DDC_CLK[54]L_DDC_DATA[54]
LBKLT_CTL_PCH[54]LCDVDD_EN_PCH[54]PANEL_BKEN_PCH[37]
MCH_BLUE[74]MCH_GREEN[74]MCH_RED[74]
MCH_LVDSA_DAT0#[74]MCH_LVDSA_DAT2#[74]MCH_LVDSA_DAT1#[74]
MCH_LVDSA_DAT1[74]MCH_LVDSA_DAT0[74]MCH_LVDSA_DAT2[74]
MCH_LVDSA_CLK[74]MCH_LVDSA_CLK#[74]
GMCH_VSYNC[74]GMCH_HSYNC[74]
GMCH_DDCDATA[55]GMCH_DDCCLK[55]
SDVO_CLK [57]SDVO_DAT [57]
HDMI_HP_DET [21,57]
HDMI_DATA2+_C [57]HDMI_DATA2-_C [57]
HDMI_CLK+_C [57]
HDMI_DATA1+_C [57]
HDMI_CLK-_C [57]
HDMI_DATA1-_C [57]
HDMI_DATA0+_C [57]HDMI_DATA0-_C [57]
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00PCH (LVDS/CRT/DDI)
20 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00PCH (LVDS/CRT/DDI)
20 88Wednesday, September 09, 2009
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.
Vostro Calpella X00PCH (LVDS/CRT/DDI)
20 88Wednesday, September 09, 2009
Place near PCH
Place near PCH
37.5 ohm trace to 150R resistor50 ohm trace to filter
DW07/05 1. LCD brightness control are separated by GPU,PCH,EC2. LCD Power Enable control are separated by GPU,PCH,EC3. LCD Backlight On/Off Status are separated by GPU,PCH,EC07/074. Dummy R2003
1 2
R20041KR2D-1-GPR20041KR2D-1-GP
1
2
R20022K37R2F-GPR20022K37R2F-GP
1
2
R2006150R2F-1-GPR2006150R2F-1-GP
1
2
R2005150R2F-1-GPR2005150R2F-1-GP
12 3
4
RN2001SRN10KJ-5-GPRN2001SRN10KJ-5-GP
1
2
R2007150R2F-1-GPR2007150R2F-1-GP
1 2
R20110R2J-2-GPR20110R2J-2-GP
L_BKLTCTLY48
L_BKLTENT48
L_CTRL_CLKAB46L_CTRL_DATAV48
L_DDC_CLKAB48L_DDC_DATAY45
L_VDD_ENT47
LVDSA_CLK#AV53LVDSA_CLKAV51
LVDSA_DATA#0BB47LVDSA_DATA#1BA52LVDSA_DATA#2AY48LVDSA_DATA#3AV47
LVDSA_DATA0BB48LVDSA_DATA1BA50LVDSA_DATA2AY49LVDSA_DATA3AV48
LVDSB_CLK#AP48LVDSB_CLKAP47
LVDSB_DATA#0AY53LVDSB_DATA#1AT49LVDSB_DATA#2AU52LVDSB_DATA#3AT53
LVDSB_DATA0AY51
DDPB_0N BD42
DDPB_1N BJ42
LVD_VREFHAT43LVD_VREFLAT42
DDPD_2N BF37
DDPD_3N BE36
DDPB_2N BB40
DDPB_3N AW38
DDPC_0N BE40
DDPC_1N BF41
DDPC_2N BD38
DDPC_3N BB36
DDPD_0N BJ40
DDPD_1N BJ38
DDPB_0P BC42
DDPB_1P BG42
DDPD_2P BH37
DDPD_3P BD36
DDPB_2P BA40
DDPB_3P BA38
LVDSB_DATA1AT48LVDSB_DATA2AU50LVDSB_DATA3AT51
LVD_IBGAP39LVD_VBGAP41
DDPC_1P BH41DDPC_0P BD40
DDPC_2P BC38
DDPC_3P BA36
DDPD_0P BG40
DDPD_1P BG38
CRT_BLUEAA52
CRT_DDC_CLKV51CRT_DDC_DATAV53
CRT_GREENAB53
CRT_HSYNCY53
CRT_IRTNAB51
CRT_REDAD53
CRT_VSYNCY51
DAC_IREFAD48
SDVO_CTRLCLK T51SDVO_CTRLDATA T53
DDPC_CTRLCLK Y49DDPC_CTRLDATA AB49
DDPD_CTRLCLK U50DDPD_CTRLDATA U52
DDPB_AUXN BG44
DDPC_AUXN BE44
DDPD_AUXN BC46
DDPB_AUXP BJ44
DDPC_AUXP BD44
DDPD_AUXP BD46
DDPB_HPD AU38
DDPC_HPD AV40
DDPD_HPD AT38
SDVO_TVCLKINP BG46SDVO_TVCLKINN BJ46
SDVO_STALLP BG48SDVO_STALLN BJ48
SDVO_INTP BH45SDVO_INTN BF45
L
V
D
S
D
i
g
i
t
a
l
D
i
s
p
l
a
y
I
n
t
e
r
f
a
c
e
C
R
T
4 OF 10U2001D
IBEXPEAK-M-GP-NF
L
V
D
S
D
i
g
i
t
a
l
D
i
s
p
l
a
y
I
n
t
e
r
f
a
c
e
C
R
T
4 OF 10U2001D
IBEXPEAK-M-GP-NF
1 2
R2003100KR2J-1-GP
DYR2003100KR2J-1-GP
DY
1TP2001TPAD14-GPTP2001TPAD14-GP
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_PCI_FB_R
PCI_DEVSEL#PCI_FRAME#
PCI_IRDY#
PCI_SERR#PCI_PERR#
PCI_TRDY#PCI_STOP#
PCI_GNT0#
PCI_PLOCK#
PLTRST#_PCH
PCI_REQ0#PCI_REQ1#
PCI_GNT3#
PCI_REQ3#
INT_PIRQB#INT_PIRQC#INT_PIRQD#
INT_PIRQA#
PCH_PME#
USB_OC#2_3
PCH_OC7#
USB_OC#0_1
USB_OC#8_9USB_OC#10_11USB_OC#12_13
USB_OC#6_7
USB_RBIAS_PN
PCI_GNT3#
TP_NV_ALETP_NV_CLE
DGPU_PWM_SELECT#
USB_OC#4_5
PCIRST#
DGPU_SELECT#
PCH_GPIO4PCH_GPIO5
INT_PIRQE#
PLTRST#_PCH
PCLK_FWH_R
PCLK_KBC_RPCLK_TPM_R
DGPU_PWM_SELECT#
TP_USB_PN6TP_USB_PP6TP_USB_PN7TP_USB_PP7
USB_OC#10_11
USB_OC#8_9USB_OC#12_13
USB_OC#0_1
USB_OC#2_3
USB_OC#6_7
USB_OC#4_5PCH_OC7#
PCI_DEVSEL#
PCI_TRDY#PCI_PLOCK#PCI_PERR#
PCI_REQ3#
TP_NV_RCOMP
PCI_REQ0#INT_PIRQB# PCI_SERR#
WWAN_RF_EN
INT_PIRQE#
PCH_GPIO5PCH_GPIO4
DGPU_SELECT#
PCI_IRDY#
INT_PIRQA#PCI_STOP# INT_PIRQD#
INT_PIRQC#
PCI_FRAME#PCI_REQ1#
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
CLK_PCI_FB[23]
USB_OC#2_3 [63]USB_OC#0_1 [76]
PLT_RST#[9,37,64,65,70,76,77,80]
PCLK_FWH[70]PCLK_KBC[37]
USB_PP0 [76]USB_PN0 [76]
USB_PP4 [63]USB_PN4 [63]
USB_PP11 [78]USB_PN11 [78]
USB_PN2 [63]USB_PP2 [63]
USB_PN10 [73]USB_PP10 [73]
USB_PN3 [63]USB_PP3 [63]
USB_PN8 [77]USB_PP8 [77]USB_PN9 [76]USB_PP9 [76]
USB_OC#4_5 [63]
PCLK_TPM[76]
HDD_FALL_INT1[40]
USB_PN12 [77]USB_PP12 [77]
DGPU