© Synopsys 2012 1

Will Everything Start To

Look Like An SoC?

Vikas Gautam, Synopsys

Verification Futures Conference 2013

Bangalore, India

March 2013

© Synopsys 2012 2

SystemVerilog Inherits the Earth

• SystemVerilog and UVM are now mainstream

– Previous languages / methodologies will persist . . .

. . . but new developments will be slow

. . . and new users will be rare.

2002 2004 2006 2008 2010

eRM

RVM

uRM

AVM

1.0/2.0/3.0

OVM

1.0/2.0

VMM

1.0

SystemC

TLM 1.0

SystemC

TLM 2.0

VMM

1.2

UVM

1.0/1.1

e

OV

SV

SC

SV VMM

1.1

2012

UVM

1.2

© Synopsys 2012 3

Methodology Deployment Ecosystem

Protocol Debug

Template Generators

Verification Planning

Verification Management

UVM-Aware Debug

Constraint Solver

Coverage & Analysis

Native UVM VIP

UVM TLM/SC Adaptors

UVM AMS Testbench

© Synopsys 2012 4

Will Everything Look Like an SoC?

Processor

High-performance

Internal Architecture

Data Processing

Software

Mobile

Low-power

External Standards

Graphics Processing

Software

Links to Analog

Performance/power Optimisation

Internal and External Standards

Links to Analog

Multiple Processors

Multiple Protocols

Software

System on Chip

Scientific Industrial Infrastructure Aerospace Military Medical Automotive

SoC-targeted Tool Developments Will Benefit ALL chip Designs

© Synopsys 2012 5

Needs Accelerated Innovation

• 10x Performance

• 10x Capacity

• 10x VIP Productivity

• 10x Constraints & Coverage

• Advanced LP solutions

• High-speed AMS Simulation

• 10x Debug Productivity

• 10x Reuse methodology

• Hw/Sw Co-Verification

Significant Challenges Remain Convergence Driving SoC Complexity

Platform

Convergence

• Increasing complexity of specs

• Shrinking time to market

• Exploding SW content

• Increasing development cost

CPU + Graphics + Modem

Multimedia + Networking

PC + Mobile Increasing

HW Functionality

1

10X Increase In

Verification Complexity

2

10X Increase Needed in

Productivity

3

Today’s Verification Complexity

• 44M+ lines of RTL & Testbench

• 168GB+ memory required

• 10+ protocols

• TB of coverage data

• 300,000+ assertions

• 200+ power domains

• Debug 35% of verification

• 2:1 verif/design engineers

• 2X CPU farm

© Synopsys 2012 6

10x Performance, 10x Capacity

• Massive Parallelism

– Many designs have repeated structures

– Many tests are run on the same DUT

– Can we automatically utilise this in order to increase performance?

• New Compute Platforms

– Are CPUs the best simulation platform?

– Can we use FPGAs for acceleration?

− SIMD, Single-Instruction-Multiple-Data

– What of other computing platforms?

− Employ GPU via OPENCL compilers?

− Cloud-based simulation?

© Synopsys 2012 7

VIP Productivity Challenge

More protocols in use per chip, each protocol evolving

© Synopsys 2012 8

VIP Productivity Challenge

A small step in for a protocol . . .

. . . can be a giant leap in complexity.

AMBA AHB

USB2.0

AMBA APB

UART

I2C SDIO

MMC-SD

PCI

USB 2.0 Traffic

AMBA4 AXI

USB2.0

AMBA4 ACE

UART

HDMI

I2C

SDIO

MMC-SD

GPIO

USB3.0

MIPI DSI

MIPI CSI

MIPI LLI SLIM Bus

HDMI

HDMI

USB OTG SATA

MIPI HSI

PCIe USB 3.0

USB 3.0 Traffic

10X Protocols Increasing complexity per protocol (20x scenarios, 10x data)

© Synopsys 2012 9

Today’s VIP Productivity Challenges

Configuration &

Test Development

• 20x increase in

scenarios

• 2-4 weeks before the

first test

Performance

• 3M+ lines of VIP code

per SOC

• Multiple layers of PLI

wrappers

Debug

• Several days to find

root cause, due to

limited visibility

• Current debug tools

not protocol-aware

Coverage Closure

• 2 man-months to

create coverage plan

per title

• 3 man-months to

implement coverage

and scenarios

Current VIP technology

running out of steam

SV Interface

Vera

UVMOVMVMM

UVMOVM

SV Interface

eRM

‘e’

VMM

SV Interface

C

OVM UVM

‘e’ and C based VIP

Vera-based VIP

© Synopsys 2012 10

Native UVM / VMM / OVM

Sequence

Collection

Configuration

Creator

Customization

Coverage

Database

User

Verification

Plan

Protocol Test Plan

Coverage

Protocol

Analyzer

VIP

Sourc

e

Vis

ibility

DVE

Debug

Testbench

Native

SystemVerilog Protocol VIP

Test

Suite

User

Tests

DUT

Monitor

Coverage Model

Sequencer

Protocol L2

Link L1

Physical Driver

Virtu

al S

eq

uencer

Configuration

AIP

• 100% SystemVerilog

• High Performance

• Ease of Use

• Native Methodology Support

• Sequence Collections

• Built-in Coverage

• Built-in Verification Plans

• Protocol Aware Debug

VIP Moves to SystemVerilog 20+ Industry Experts collaborated on Requirements and Architecture

© Synopsys 2012 11

10x Constraints and Coverage Efficiency

Plan

Analy

ze

Manage

Verification

&

Coverage

Data

• Interactive

authoring

• Annotation

• Trend analysis

• Grading

• Exclusions

• Integrated

execution

• Regression

monitoring

© Synopsys 2012 12

Advanced Low-Power Solutions

• VCS-NLP provides a unique voltage-aware

modeling engine combined with industry leading

native compiled-code simulation

• 50% faster and higher capacity than non-native

mode

– Minimal runtime impact vs. non-LP simulation

• Ease-of-use

– Supports industry-standard IEEE 1801 (UPF)

– Leverages VCS use model including testbench,

coverage, and debug

– Single compile step

– All VCS command line options supported

• Ease-of-debug

– Enhanced low power debug

© Synopsys 2012 13

Verdi Debug

10x Debug Productivity

Methodology-aware Debug Supports VMM-UVM-OVM

Windows for:

Class

Object

Resource

Factory

Phase

Sequence

Transactions Handshaking

Transcript

Protocol-aware Debug

Transaction Recording

© Synopsys 2012 14

Earliest Detection of Bugs

• Abstracted Static Equivalence Checking

• ‘X-Propagation prediction at RTL

How Can The Industry Deliver These Advances and Beyond?

© Synopsys 2012 15

Partnership with Industry Leaders

VCS customer spotlights on EE Times:

© Synopsys 2012 16

Thank You