1

Why analog microelectronics?

• Digital is taking over?– Yes, but electrical signals are fundamentally analog!

– Analog design has proven fundamental for high-quality design of complex systems

• Mixed-mode systems– Natural signals are analog

• Sound in microphone

• Photocells in cameras

• Temperature sensors

– All real world systems require interfacing to analog

TSL inf34101

TSL inf34102

Limitations of analog design

• Supply voltage limitations– Lower limit: noise

– Upper limit: headroom < supply• Aiming for active region

2

TSL inf34103

Upper signal limit

• Active region requirements– weak inversion:

– strong inversion:

– Available headroom

)( ptnGSeffDS VVVV

peratureat roomtem 26

U 5-4 T

mVU

VV

T

effDS

mVmVVeff 800100

Upper signal limit Veff from rail voltage

effsupply VVV max

Weak inversion lower saturation voltage

TSL inf34104

Upper signal limit

• Active region requirements– weak inversion:

– strong inversion:

– Available headroom

)( ptnGSeffDS VVVV

peratureat roomtem 26

U 5-4 T

mVU

VV

T

effDS

mVmVVeff 800100

Upper signal limit Veff from rail voltage

effsupply VVV max

Weak inversion lower saturation voltage

3

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Lower signal limit• Noise vs. Frequency

– Weak inversion shot noise– Strong inversion thermal noise

• Lower signal limit – Noise– Frequency dependant

• Thermal noise• Flicker noise (LF)

Flicker

W/L

log

RN

log f

ID constant

Thermal

Shot

TSL inf34106

Limitations– Ratio between largest and smallest signal

• Signal-to-noise ratio

– assuming only thermal noise

CkTR

VSNR

N

PP

42

amplitude noise

amplitudemax 2

2

2

SNR improves with the square of signal amplitude.

–Maximize signal swing

4

TSL inf34107

CMOS technology• Basic element in microelectronics

– Digital microelectronics• MOS device used as switch

– Crude and simple understanding

– Analog microelectronics• MOS device used as computational element

– Current/voltage relationship of different terminals– Limitations– Loads– Design parameters

• Exploring passive devices– Capacitors– Resistors

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CMOS technology

• Layered structure– Planar

• Plates → capacitance

• Wires → resistance

– No “pure” device• Always added parasitics

– Passive

» Resistance

» Capacitance

– Active

» Diodes

» Bipolars

• Mismatch

5

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Analog microelectronics• Mastering devices and parasitics

– Explore continuous time behavior• Example: amplifier

– Output voltage A time larger thaninput voltage

– Determine functional limits• Input voltage range• Output voltage range• Maximum error• Frequency range

• Explore physics– Available in CMOS microelectronics

– Developed for digital

inout VAV

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MOS transistor

• Most important element– 3-4 terminal device

• Depletion region

– Principal of operation• Negative gate voltage

– Accumulated channel

– capacitor

• Positive gate potential – channel between source and

drain

– Inversion

• Gate voltage for making an inverted channel

– Threshold voltagethV

pMOS -

nMOS -

tp

tn

V

V

6

TSL inf341011

nMOS transistor• Source referred potentials

– Source terminal:The one closest to bulk potential

• Substrate voltage for nMOS

– Primary characteristics• VGS – Gate-source voltage• VDS – Drain-source voltage• ID – drain current• IS – source current

– Secondary characteristics• VGD – gate-drain voltage• VBS – bulk-source voltage• IB – bulk current• IG – gate current

VGS

VGD

VBS

VDS

ID

IS

IG IB

Source and drain completely symmetric

DSBDS

BSBG

IIIII

VII

0for 0,0source

drain

gate

TSL inf341012

pMOS transistor• Source referred potentials

– Source terminal:The one closest to bulk potential

• Well voltage for pMOS

– Primary characteristics• VGS – Gate-source voltage

• VDS – Drain-source voltage

• ID – drain current

• IS – source current

– Secondary characteristics• VGD – gate-drain voltage

• VBS – bulk-source voltage

• IB – bulk current

• IG – gate current

VGS

VGD

VBS

VDS

ID

IS

IG IB

Source and drain completely symmetric

DSBDS

BSBG

IIIII

VII

0for 0,0drain

source

gate

7

TSL inf341013

MOS transistor• Definitions

– Threshold voltage• Reduced with

– feature size– Supply voltage

• Vtn - nMOS threshold voltage– Typical ≈ 0.7V

• Vtp - pMOS threshold voltage– Typical ≈ -0.9

– Effective gate voltage– Channel charge density

• Kox – relative permittivity of silicondioxide (≈3.9)

• tox – thin oxide thickness• ε0 – permittivity of free space

The gates voltage, for which the concentration of electrons under the gate is equal to the concentration of

holes in the substrate far from the gate.

)( ptnGSeff VVV

ox

oxox

effoxptnGSoxpn

t

KC

VCVVCQ

0

)()(

mF1210854.8

TSL inf341014

MOS transistor

• Gate capacitance

• Linear channel current• Impose drain-source voltage difference (VDS ≠ 0)

• Resistive, current increase with voltage difference

effox

ptnGSoxpnT

oxgs

VWLC

VVWLCQ

WLCC

)()(

areaunit pr. charge

mobility - 060 2

n

n

DSnnD

Q

Vsm.μ

VL

WQI

DSeffoxn

DStnGSoxnD

VVCL

W

VVVCL

WI

Only for VDS close to zero

8

TSL inf341015

MOS transistor

• Pinch-off

– Channel current independent of drain-source voltage• Active region

• MOS-transistor saturated

• Often desirable in analog circuits

efftnGSsatDSDS VVVVV

TSL inf341016

Activeregion

MOS transistor• Strong inversion behavior

DStnGSoxnD VVVL

WCI

2

2DS

DStnGSoxnD

VVVV

L

WCI

22 tnGS

oxnD VV

L

WCI

First order approximation

Trioderegion

ID

VDS

9

TSL inf341017

MOS transistor• Drain current vs. gate voltage

22 tnGS

oxnD VV

L

WCI

Cadence simulation of AMS 0.35μm NMOS transistorThreshold voltage

Subthreshold

Abovethreshold

0DI

TSL inf341018

MOS transistor deviations

• Channel shortening– Channel length

modulation coefficient

A

sds

effDS

ds

effDStnGSoxn

D

qN

Kk

VVL

k

VVVVL

WCI

0

0

2

2

2

12

Linearregion

Saturationregion

10

TSL inf341019

MOS transistor deviations

• Body effect• Back-gate effect, substrate effect

– Current change as VSB is different from zero

– Modeled as change in threshold voltage

– Vtn0 – zero biased threshold voltage

FFSBtntn VVV 220

potential Fermi -

2 0

F

ox

SA

C

KqN

TSL inf341020

General purpose analytical model

• Models presented in book– Aimed for strong inversion

• Above threshold

– Unusable in moderate and weak inversion• Subthreshold

• EKV model (not in book)

– Enz-Krummenacher-Vittoz model http://legwww.epfl.ch/ekv/index.html

– Handles moderate and weak inversion• Continuous transition

– Simple• Few parameters

• (BSIM parameters >65)

– Important for understanding micropower design

11

TSL inf341021

MOS transistor models

• Active region– Low frequency model

– Voltage controlled current source

– Transconductance

– Relation to drain current

gsmvg

GS

Dm V

Ig

effoxntnGSoxnGS

Dm

tnGSoxn

D

VL

WCVV

L

WC

V

Ig

VVL

WCI

2

2

DmDoxnoxn

Doxnm

oxn

DtnGS

IgIL

WC

LWC

I

L

WCg

LWC

IVV

to alproportion 22

2

TSL inf341022

MOS transistor models• Active region (cont.)

– Body effect

– Ignored for

– Output impedance

– Assuming is small

FSB

m

SB

tn

tn

D

SB

Ds

V

g

V

V

V

I

V

Ig

22

0SBV

DDS

Dds

ds

IV

Ig

r

1

12

TSL inf341023

MOSCAPs• Gate capacitance

• Fringing capacitances– Overlap

• Source-bulk capacitance (+channel cap when present)

oxgs WLCC3

2

ovoxgs

oxovov

LLWCC

CWLC

3

2

0

0'

1

SB

jchssb

V

CAAC AS – source area

Ach – channel area

Cj0 – unit depletion capacitance at 0V

0 – build in junction potential

TSL inf341024

MOSCAPs cont’d• Drain-bulk capacitance

• Gate-drain overlap• Miller capacitance

• Sidewall capacitances

• Bulk capacitances

0

0'

1

DB

jDsb

V

CAC

ovoxgd WLCC

0

0

1

DB

swjSsws

V

CPC

PS(D) – source (drain) perimeter

Cj-sw0 – unit sidewall capacitance at 0V

0

0

1

SB

swjDswD

V

CPC

swddbdbswssbsb CCCCCC ''

13

TSL inf341025

MOS transistor model• Triode region

– Gain give as slope

– Output conductance

• VDS is small and sometimes dropped

2

2DS

DStnGSoxnD

VVVV

L

WCI

DStnGSoxnDS

Dds

ds

VVVL

WC

V

Ig

r

1

tnGSoxnds VVL

WCg

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Channel inversion

Thresholdcurrent

Thresholdvoltage

Strong inversion

Weakinversion

Moderate inversion

NMOS AMS 0.35μm process

Velocity Saturation

14

TSL inf341027

Nanoelectronics• 90nm technology (ST Microelectronics)

• Minimum transistor simulated with CADENCE

– Three different threshold voltages

VelocitySaturation

VelocitySaturation

WeakInversion

Strong/moderateInversion

ALMOST NO STRONG INVERSION LEFT!!!!!

Velocity saturation in advanced technology squeeze strong inversion operation region

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Velocity saturation• Active region

– Strong inversion

• Velocity saturation– Short and small devices

– Transconductance does not increase with smaller L!

• Maximum frequency

WCvgs

cmv

VVWCvI

oxsatm

sat

tnGSoxsatD

710

effoxntnGSoxnGS

Dm

tnGSoxn

D

VL

WCVV

L

WC

V

Ig

VVL

WCI

2

2

Reduced from square to linear

L

vVV

Lnf sat

tnGST

22

3

2

12

15

TSL inf341029

• ST Microelectronics 90 nm• Minimum transistor

– Drain current

– Transconductance

linear

logVelocity saturation

TSL inf341030

The EKV MOS model• 3 parameters (simplest version)

– VT0

Zero biased threshold voltage

–

Gain factor

– nSlope factor

• Specific current

• Channel current

Vs(d) Vd(s)

Vg

IF IR

L

WCox

21n

22 TS UnI e tempraturroomat 26mVq

kTUT

RFSRFDS iiIIII

T

DSTgRF nU

nVVVi

2exp1ln )(02

)(

All potentials referred to bulk

16

TSL inf341031

EKV MOS model• Weak inversion

– If

• Strong inversion– If

T

DSTgRF nU

nVVVi )(0

)( exp

)(0 DSTg nVVV

)(0 DSTg nVVV

2)(0)( 2 DSTgRF nVVVn

I

A continuous smoothing function proposed by Oguey (swiss math-guy)

0for

0for 2

1ln2

2/2

xe

xx

f

ey

x

x

TSL inf341032

MOS saturation• Weak inversion expressions

– Transconductance

T

STG

T

S

T

TG

T

D

T

S

T

TG

nU

nVVV

SU

V

nU

VV

SD

RD

U

V

U

V

nU

VV

SRFD

eIeeII

IV

eeeIIII

00

0

00

TU 5-4 effDS VV

)(0 DSTg nVVV

0

0

TgD

TgS

VVV

VVV

DTG

D

T

GDS

T

SGD

T

TSD

T

STGSD

InUV

I

nU

VIV

nU

nVVI

nU

VII

nU

nVVVII

1g

expI0, expI

give will explet ,exp

m

0D0D

00

0

17

TSL inf341033

MOS saturation

• Strong inversion

– Transconductance

2)(02 DSTgD nVVVn

I

0

0

TgD

TgS

VVV

VVV

)(0 DSTg nVVV

)(0

)(0

2)(0

2

2

2

DSTg

D

D

DSTgg

Dm

DSTgD

nVVV

I

In

nVVVnV

Ig

nVVVn

I

TSL inf341034

Body effect

• MOS-transistor– 4-terminal device

– Back-gate

T

sbgsD

T

sbsbgsDds

sbgsgb

T

sbgbDds

nU

VnVI

nU

nVVVII

VVV

nU

nVVII

)1(expexp

exp

00

0

gate

source

drain

bulk

Body effect natural part of model• n (slope factor) denotes gate efficiency

18

TSL inf341035

Technology implications• Finer pitch - submicron

– Lower supply voltage• Reduced headroom

– Less power

• Analog circuit design– Often mixed with digital– Limited SNR– Added noise

• Weak inversion unavoidable– Even for digital circuits

• No strong inversion left!

TSL inf341036

Example: CD4007

• Lab transistors• Datasheet →MC14007.pdf

– Exact specifications not available

– Estimated parameters nMOS:• Ut=0.026

• VT0=1.6

• μn=0.067

• ε0=8.854e-12

• Kox=3.9

• L=10

• W=350

• tox=350e-10 (high voltage indicated thick dioxide)

19

TSL inf341037

Measured nMOS•CD4007 nMOS transistor •drain-current ↔ gate-voltage•Active region

•Vds=5V

Linear Y-axis Logarithmic Y-axis

Threshold voltage

Keypoints• The source terminal of nMOS → lowest voltage

• The source terminal of pMOS → highest voltage

• MOS transistors are close to linear for Vds<<Veff (triode region)

• MOS transistors with Vds>Veff have square-law current vs. voltage

• Small signal rds proportional to L/ids

• For high gain, transistors should be long and biased with low Veff

• Transistors are operation with exponential current vs voltage relationship for low gate voltages. Current is flowing even for Vds=0

• For large Veff transistor go into velocity saturation with linear current-voltage relation

• Transconductance is highest in weak inversion (linear),degrading to square root in strong inversion,fading to ‘1’ in velocity saturation

TSL inf341038

20

Layout• Chapter 2: self-study or assumed known

• Keypoints:– ALL transistors are different!

• Even with exactly the same layout, next to each other on the same die

– Systematics process variation

– Random production variations• Increase with reduced device area

• Assume 20% random variations in modern processes for small devices

– Other effects• Temperature, aging ……

TSL inf341039