week 5pami.uwaterloo.ca/~basir/ece124/week5-1.pdf · the selected signal assignment is diﬀerent...

WEEK 5.1

ECE124 Digital Circuits and Systems

Buffers vs Muxes


D0 D7

A0

A1023

D0 Device A

D0 Device B

D0 Device C

D0

D0 Device D

S0S1

Memory

Buffers vs Muxes


D0 D7

A0

A1023

2-to-4 Decoder

D0


Component instanDaDons in VHDL

  OIen we will have a VHDL DescripDon of part of a circuit that we would like to use inside of another circuit.   As an example, consider building an n‐bit ripple adder from 1‐bit full adders.

  We can use VHDL descripDons inside of other VHDL descripDons by:

  Declaring components we wish to use.   Crea1ng or instan1a1ng copies of the components.   Connec1ng together the components.


VHDL descripDon of a 1‐bit adder

-- VHDL for 1-bit full adder. library ieee; use ieee.std_logic_1164.all; entity fulladder1 is port( a,b,c : in std_logic; s,z : out std_logic); end fulladder1; architecture prototype of fulladder1 is begin s <= a xor b xor c; -- sum z <= (a and b) or (a and c) or (b and c); -- cout end prototype;


VHDL descripDon of a 4‐bit adder (built from 1‐bit adders) (1)   Before we can use the 1‐bit adder, we need to declare it inside of the declara1ve

sec1on of architecture of the 4‐bit adder:

-- VHDL for a 4-bit adder built from 1-bit adders. library ieee; use ieee.std_logic_1164.all; entity fulladder4 is port (x,y : in std_logic_vector(3 downto 0); cin : in std_logic; sum : out std_logic_vector(3 downto 0); cout : out std_logic); end fulladder4; architecture prototype of fulladder4 is -- need to declare the components (other VHDL descriptions) we will use. -- like the entity of the circuit we want to use, but notice the “component” keyword component fulladder1 port (a,b,c : in std_logic; s,z : out std_logic); end component; signal c1, c2, c3 : std_logic; -- temporary signals needed in the architecture. begin -- description will go here. end prototype;

component declaration

temporary signals


VHDL descripDon of a 4‐bit adder (built from 1‐bit adders) (2)   Once we have declared components, we can instan1ate copies in the architecture

body and connect them together:

-- VHDL for a 4-bit adder built from 1-bit adders. -- continued from previous page (architecture body only). … architecture prototype of fulladder4 is component fulladder1 port (a,b,c : in std_logic; s,z : out std_logic); end component; signal c1, c2, c3 : std_logic; -- temporary signals needed in the architecture. begin bit0: fulladder1 port map (a=>x(0),b=>y(0),c=> cin,s=> sum(0),z=> c1); bit1: fulladder1 port map (a=>x(1),b=>y(1),c=> c1,s=> sum(1),z=> c2); bit2: fulladder1 port map (a=>x(2),b=>y(2),c=> c2,s=> sum(2),z=> c3); bit3: fulladder1 port map (a=>x(3),b=>y(3),c=> c3,s=> sum(3),z=> cout); end prototype;

component declaration

temporary signals

component instantiations and wiring


Summary

  Once we declare a component (another VHDL DescripDon), we can create a copy of it using the syntax:

instance_name : component_name port map ( signal_in_component => signal_in_current_circuit, signal_in_component => signal_in_current_circuit, … signal_in_component => signal_in_current_circuit );

  The nota1on “=>” inside of the “port map” is like connec1ng or wiring the signal in

the current circuit to an input or output pin of the sub‐circuit (the component).


SimulaDon


Comments

  Note that we needed temporary signals in order to connect the 1‐bit full adders together inside of the architecture body of the 4‐bit full adder:

architecture prototype of fulladder4 is -- component declarations… signal c1, c2, c3 : std_logic; -- temporary signals needed in the architecture. begin -- cicuit description… end prototype;

  The syntax for this is:

signal signal_name : type ;

Other types of concurrent VHDL signal assignments

  The “<=“ operator is not the only means by which we can perform combinaDonal assignments in VHDL.

  There are other concurrent signal assignment operators that make wriDng VHDL a bit easier.



Concurrent signal assignments (1)

  We have the concurrent signal assignment statement “<=“ for represenDng logic equaDons in VHDL.

  Example (this is a 4‐to‐1 mulDplexer):

-- implementation of a 4-to-1 multiplexer -- version using concurrent signal assignment. library ieee; use ieee.std_logic_1164.all; entity mux4to1_version1 is port (x1, x2, x3, x4 : in std_logic; -- inputs s : in std_logic_vector(1 downto 0); -- controls f : out std_logic); -- output end entity; architecture prototype of mux4to1_version1 is begin f <= (not s(0) and not s(1) and x1) or (not s(0) and s(1) and x2) or ( s(0) and not s(1) and x3) or ( s(0) and s(1) and x4); end prototype;


CondiDonal signal assignments (1)

  A condi1onal signal assignment is another construct for assigning the value to a funcDon.

  It offers a higher level of abstrac1on that the concurrent signal assignment (which is at the gate level; e.g., AND, OR and NOT gates).

  Basic syntax is:

signal <= other_signal1 when (condi1on1) else other_signal2 when (condi1on2) else other_signal3 when (condi1on3) else … other_signaln when (condi1onn) else default_signal ;

  NoDce that we always have a default assignment in case none of the condiDons are true.



  Example (this is a 4‐to‐1 mulDplexer):

-- implementation of a 4-to-1 multiplexer -- version using conditional signal assignment. library ieee; use ieee.std_logic_1164.all; entity mux4to1_version2 is port (x1, x2, x3, x4 : in std_logic; -- inputs s : in std_logic_vector(1 downto 0); -- controls f : out std_logic); -- output end entity; architecture prototype of mux4to1_version2 is begin f <= x1 when (s = "00") else x2 when (s = "10") else x3 when (s = "01") else x4; end prototype;



  The ordering of the “when‐else” is important – they are evaluated in order.

  There is a priority implied.

  Several condiDons may be true, but the first true condiDon encountered will determine the resulDng signal assignment.


Priority encoder (1)

  IllustraDon of priority via a 8‐to‐3 priority encoder…

library ieee; use ieee.std_logic_1164.all; entity priority8 is port (x : in std_logic_vector(7 downto 0); -- input lines valid : out std_logic; -- output valid? y : out std_logic_vector(2 downto 0)); -- encoded output. end priority8; architecture prototype of priority8 is begin y <= "111" when (x(7) = '1') else -- value of lower inputs not important "110" when (x(6) = '1') else "101" when (x(5) = '1') else "100" when (x(4) = '1') else "011" when (x(3) = '1') else "010" when (x(2) = '1') else "001" when (x(1) = '1') else "000" when (x(0) = '1') else "000"; valid <= '0' when x = "00000000" else '1'; end prototype;

Priority encoder (2)



Selected signal assignment (1)

  Selected signal assignment is very similar to the condi1onal signal assignment.

  It also offers a higher level than abstrac1on compared to a concurrent assignment.

  The value to be assigned to a signal is determined by the value of a select expression, much like a case statement in a convenDonal programming language.

  It has the syntax:

with (some_signal) select other_signal <= value1 when (condi1on1) ,

value2 when (condi1on2) , … , default_value when others ;


Selected signal assignment (2)

  We can write VHDL for a 4‐to‐1 mulDplexer using selected signal assignment which is more abstract, represenDng the operaDon of a mulDplexer:

-- version using selected signal assignment. library ieee; use ieee.std_logic_1164.all; entity mux4to1_version3 is port (x1, x2, x3, x4 : in std_logic; s : in std_logic_vector(1 downto 0); f : out std_logic); end entity; architecture prototype of mux4to1_version3 is begin with s select f <= x1 when "00" , x2 when "10" , x3 when "01" , x4 when others; end prototype;


Selected vs. condiDonal signal assignment

  The selected signal assignment is different that the condiDonal signal assignment in that (1) there is no priority and (2) all choices are evaluated at once (and therefore only one choice can be true at any Dme).

  All possible choices need to be specified, but we can capture values that we are not interested in using the others keyword.

  The “others” keyword conveniently captures all the other possible values of the select signal.

  Note: we should always include the “when others;” in the selected signal assignment.


Constants

  In the explanaDon of our new condi1onal and selected signal assignment statements, we saw the assignment of constants to signals and to vectors of signals.

  To assign a constant to a signal, or to a single bit of a vector of signals, we enclose the constant inside of single Dck marks:

E.g., f <= ‘1’; ‐‐ f is std_logic E.g., y(4) <= ‘0’; ‐‐ y is std_logic_vector and y(4) is 4‐th bit.

  To assign a vector of signals all at once, we assign each bit, but enclose the bits inside of double quotaDon marks:

E.g., z <= “10011”; ‐‐ z is a 5‐bit std_logic_vector E.g., z(3 downto 0) <= “1110”; ‐‐ z is std_logic_vector and this assigns lowest 4‐bits.


Signal declaraDons inside of the architecture

  In all the examples so far, we have only seen how to declare signals in the port secDon of the enDty declaraDon.

  SomeDmes, we will have signals internal to our implementaDon. These signals get declared in the declaraDve secDon of the architecture:   (We will see more on this later)…

‐‐ no1ce en1ty declara1on skipped… architecture prototype of something is ‐‐ declara1ve sec1on

signal temp_signal : std_logic ; ‐‐ signal can be used below in the ‐‐ implementa1on sec1on. signal temp_bus : std_logic_vector(12 down 0);

begin prototype ‐‐ implementa1on sec1on

end prototype;

week 5pami.uwaterloo.ca/~basir/ece124/week5-1.pdf · the selected signal assignment is diﬀerent...

Documents