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***Microprocessor:

It is a special type of integrated circuit .A silicon chip that contains a CPU.In the world of personal computers, the terms microprocessor and CPU are used interchangeably.

A general purpose device which may be programmed and applied to wide range of applications.

It is the brains/heart of the microprocessor and microprocessor based system.

Two chief functions are processing and control, processes, data according to the program of instructions stored in the memory of the system.

Arithmetic Logic Unit (ALU) process data and Control Unit (CPU) keeps part of the system working together and in right sequences during the execution of the program.

Processor is also known as microprocessor unit (MPU) and very often it is referred to as Central Processing Unit (CPU).But CPU is slightly different from MPU,being consists of ALU, CU and Main Memory.

Microprocessor also controls the Logic of almost all digital devices.

***Three basic characters differentiate microprocessor:

∎Instruction set:

The set of instructions that the microprocessor can execute.

∎Bandwidth:

The number of bits processed is a single.

∎Clock speed:

Given in megahertz (MHz), the clock speed determines how many instructions per second the processor can execute.

For example:

A 32-bit microprocessor that runs 50MHz is more powerful than a 16-bit microprocessor that’s runs at 25MHz.The higher the value of Bandwidth and Clock Speed, the more powerful the CPU.

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***Application of microprocessor:

The main application of microprocessor is in microprocessor and in embedded system. A block diagram of typical microprocessor is given below.

Input device

Output device

Figure: Basic Microcomputer Architecture.

***Microprocessor Architecture:

It refers to the internal structure of a microprocessor .The following factors is important for selecting a microprocessor for a particular action:

Word length of microprocessor.

Directly addressable memory.

Speed of execution of instruction.

Registers available for the programmers.

Other useful registers for the microprocessor.

Range of instruction that are supported by the microprocessor.

The addressing nodes available.

***Some internals elements of the microprocessors are introduced below:


16-bit directional address bus

MP RO I/O RAM

8-bit bi-direct Data bus

Control Bus

CLK


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∎General Purpose Registers (B, C, D, E, H, L):

Each one below stores one byte of data and may be connected to the bi-directional data bus.

Can transfer data to or from the data bus.

For adding two data one of them could be kept one of these registers.

This may be 16-bit data or address.

∎Accumulator:

It is an 8bit-register connected to internal bi-directional data bus.

It works closely with ALU.

For adding two data one is hold by a while.

The results of operation appear at the output of ALU.

∎Status Register:

It is sometimes referred to as the flag register (FR) or condition code register (CCR).

This is an 8bit register and set or reset some or all bit during execution of the program.

Some of the bit may be tested by instruction in the program and decision may be taken.

These bits may be used as condition for jump, call and return instruction.

Figure :( Z80 flag register) Status Register.

H and N for BCD arithmetic and cannot be tested.

X means that the flag goes to indeterminate state.

S, Z, P/V, C are the form testable bits.

∎Instruction Register:


S Z X H X P/V N C


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It is an 8 bit –wide and connected to the internal data bus. It can only receive data.

It holds part of the current instruction known as the open form code and dictates the processor for next cycle. The output from the IR is the input to the instruction decoder.

Program Counter:

It is most essential part of microprocessor.

It holds the 16 bit address of the next instruction to be executed.

If the processor is to deal with next instruction, it must bring that instruction into itself from the memory.

In doing this PC output address of next instruction to the external data bus.

***Arithmetic Logic Unit (ALU):

Arithmetic and logical operation are done hence in ALU using the registers.

Binary multiplication and division are done by using shift and add, shift and subtract operation.

For logic operation such as ORing of two bytes ALU has in-built Logic networks constructed around registers and Logic elements.

The type of functions performed by the ALU of most microprocessors include: add, subtract, logical AND, Logical XOR, shift LEFT, shift RIGHT, Increment, Decrement and complement etc.

***Microprocessor’s Control Circuit:

It consists of instruction decoder, timing and control logic, decoder receive input from IR and control circuiting direct the fetching of instruction from the memory for execution in ALU by providing timing and control signals.

The external clock signals acts as the references for all timing operations in the microprocessor.

***Draw the internal architecture of 8086 microprocessor.

Internal Architecture of 8086 microprocessor:

The figure given below is the internal architecture of 8086 microprocessor.



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Fig: Internal Architecture of 8086 Microprocessor.

*** Write short note on the Execution Unit (EU) and the Bus Interface Unit (BIU).

8086 Microprocessor has two units; Execution Unit (EU) and Bus interface Unit (BIU).They are dependent and get worked by each other. Below is a short description of these two units.

Execution Unit:

Execution Unit (EU) receives program instruction codes and data from the BIU, executes them and stores. This unit EU has no connection with the system buses.

Arithmetic Logic Unit (ALU):

The EU contains a circuit board called the arithmetic and logic Unit. The ALU can perform arithmetic, such as, +, -, / and logic such as OR, AND, NOT operations.

Registers:



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A register is like a memory location where the exceptional is that these are denoted by name rather than numbers. It has 4 data registers, AX, BX, CX, DX and 2 pointer registers SP, BP, and 2 index registers SI, DI and 1 temporary register and 1 status registers FLAGS.AX, BX, CX and DX register has 2 8-bit registers to access the high and low byte data register. The high byte of AX is called AH and low byte is AL. Similarly, the high and low bytes of BX, CX, DX are BH and BL, CH and CL, DH and DL respectively. All the data, pointers, index, status registers are 16 bits.

Bus Interface Unit:

As the EU has no connection with the system Busses, this job is done by BIU. BIU and EU are connected with an internal bus. BIU connects EU with the memory or I/O circuits.

Registers:

BIU ha s4 segment busses, CS, DS, SS, ES. These all 4 segment registers holds the addresses of instruction and data in memory. These values are used by the processor to access memory locations. It also contain 1 pointer register IP.

Instruction Queue:

BIU also contain an instruction queue. When the EU executes instructions, the BIU gets up to 6 bytes of the next instruction and stores them in the instruction queue and this process is called instruction prefetch. This is a process to speed up the processor.

*** Purpose of having general registers(AX, BX, CX, DX,SP,BP,SI,DI) and ALU (arithmetic and logic unit) in 8086

General Registers:

All general registers of the 8086 microprocessor can be used for arithmetic and logic operations.The general registers are:

AX (Accoumulator):

This is a accumulator register. It gets used in arithmetic, logic and data transfer instructions. In manipulation and division, one of the numbers involved must be in AX or AL.\

BX (Base Register):

This is base register. BX register is an address register. It usually contain a data pointer used for based, based indexed or register indirect addressing.

CX (Count Register):

This is count register. This serves as a loop counter. Program loop constructions are facilitated by it.



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DX (Data Register):

This is data register. Data can be used as a port number in I/O operations. It is also used in multiplication and division.

SP (stack Pointer):

This is a stack pointer register pointing to program stack. It is used in conjunction with SS for accessing the stack segment.

BP (Base Pointer):

This is base pointer register pointing to data in stack segment. Unlike SP, we can use BP to access data in other segments.

SI (Source Index):

This is source index register which is used to point to memory locations in the data segment addressed by DS. By incrementing the contents of SI one can easily access consecutive memory locations addressed by ES.

ALU (Arithmetic & logic Unit):

This unit can perform various arithmetic and logic operation, in required based on the instruction to be executed. It can perform arithmetic operations, such as add, subtract, increment, decrement, convert byte/word and compare etc and logical operations, such as AND, OR, exclusive OR, shift/rotate and test etc.

*** What are the purposes of segment register in 8086

Segment Register:

Code segment ( CS) :

Code segment is a 16-bit register containing address of 64 KB segment with processor instructions. The processor users CS segment for all accesses to instructions referenced by instruction pointer (IP) register.

Stack segment (SS) :

Stack segment is a 16-bit register containing address of 64 KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) base pointer (BP) registers is located in the stack segment.

Data segment (DS):



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Data segment is a 16-bit register containing address of 64 KB segment with program data. By default, the processor assumes that all data referenced by the stack pointer (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions.

Extra Segment (ES):

Extra Segment is a 16-bit register containing address of 64 KB segment, usually with program stack. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions.

It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix.

Instruction pointer (IP):

To access instructions the 8086 uses the register s CS and IP. The CS register contains the segment number of the next instruction and the IP contains the offset.

*** Write the working principles of 8086 microprocessor.

Working Principles of 8086 Microprocessor:

Execution of instruction can be used to explain the working principles of the microprocessor. This is given below,

(1)The BIU outputs the contents of the instruction pointer register (IP) onto the address bus, causing the selected byte or word to be read into the BIU.

(2) Register IP is incremented by 1 to prepare for the next instruction fetch.

(3) Assuming that the queue is initially empty, the EU immediately draws this instruction from the queue and begins execution.

(4) While the EU is executing this instruction, the BIU proceeds to fetch a new instruction. Depending on the execution time of the first instruction, the BIU may fill the queue with several new instructions before the EU is ready to draw its next instruction.

The BIU is programmed to fetch a new instruction whenever the queue has room for two additional bytes. There are three conditions that will cause the EU to enter a “wait” mode or BIU to suspend fetching.



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(a) The first one occurs when the instruction requires access to a memory location. Here the BIU suspend fetching instruction and output the address of this memory location. Then the EU will resume execution.

(b) The second will occur when the instruction to be executed is a “jump” instruction. In this case control is to be transferred to a new non-sequential address.

(c) The third one will occur during the execution of an instruction that is slow to execute. For example, the instruction AAM (ASCII Adjust for Multiplication) requires 83 clock cycles to complete. At four cycles per instruction fetch, the queue will be completely filled during the execution of this single instruction.

*** Describe the Von Neumann Architecture or IAS architecture.

Von Neumann Architecture:

In 1947 Jhon Von Neumann developed an architecture of a new stored-programmed electronic computer which is also referred as the IAS computer as the Institute for Advanced Studies in Princeton. Key connects of that design are as follows

(a) Stored program concept.(b) Data and instruction are stored in a single read-write memory.(c) Arithmetic and Logic Unit (ALU) is capable of operating on binary data.(d) The contents of this memory are addressable by location without regarding to the type of data

contained there.(e) Control unit, which interprets and executes the instructions in memory.(f) Execution occurs in a sequential fashion from one instruction to the next, unless explicitly

modified.(g) I/O equipments are operated by the control unit.

Show below is the given structure of the Von Neumann Architecture.



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*** Draw the expanded structure of the Von Neumann Architecture or IAS computer.

Expanded Structure of Von Neumann Architecture:

The expanded structure of the Von Neumann Architecture or the IAS computer is given below: Fig: expanded structure of the Von Neumann Architecture or the IAS computer is given below.



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***Explain the conceptual organization of multilevel memory system in a computer system.

Organization of Multilevel Memory System: A CPU should have rapid, uninterrupted access to its external memories to operate at or near at its maximum a speed. But memories that operate at speed near to that of CPU are expensive. That’s why different level of memories is used in terms of performance and cost. Below is the flow –diagram of the conceptual organization of multilevel memories in a computer system.

CPU Registers: The High-speed registers in CPU are used as the temporary storage for instruction and data. They usually form a general purpose register file for storing data as it is processed. A Capacity of 32 data words is typical for a register file and each register can be accessed within a single clock cycle, that is in a few nanoseconds.

Cache Memory: Most computer now have another level of IC memory called Cache Memory which is positioned logically between register files and the main memory> Its capacity is less than main memory but access time is much lesser. That is this types of memories are much faster than the main memory.

Main or Primary memory: This is large and fairly fast external memory which stores data and programs. Storage location in this memory is directly addressing 1 by the CPU’s load and store instructions. Though the technology of this memory is same as that of register file, access time is larger in this case because of its large capacity and as it is physically separated from the CPU.

Secondary register: These type memories are giant in capacity but comparatively very slow than all the other types of memory. This stores large data files, programs and files that will not be required continuously by the CPU. It also acts as an overflow memory when the capacity of the main memory exceeded.



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*** Three Cycle are:

∎Fetch:

Fetch an instruction from memory and take the opcode for the instruction and them put it in IR.

∎Decode:

Decode the instruction; the instruction decoder which operation from the instruction, set of microprocessor is to be carried out.

∎Execute:

Perform the operation on the data as requested by programmer.

Store the result in memory if needed for each instruction these three steps are repeated until the whole program in finished.

NO

YES

Figure: Flow chart for Fetch-Decode-Execute Cycle.


Start

Fetch opcode

Decode Instruction

Fetch opcode

Last instruction?


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***Common instruction set:

Data moving instruction:

Ex: MOVE, PUSH, POP

Arithmetic: add, subtract, increment, decrement etc.

Ex: ADD, SUB etc

Logical: AND, OR, XOR, and Rotate.

Control transfer: Conditional, Unconditional, call and Subroutine.

Input/output instructions:

Ex: IN, OUT etc.

***What is the purpose of using Flag Registers?

8086 has 16 flag register among which 9 are active. The purpose of the Flag register is to indicate the status of the processor. There are two kinds of flags: Status Flags and control Flags. Status Flags reflect the result of an operation executed by the processor. The control flags enable or disable certain operation of the processor.

***The nine active flags description are given below:

Carry flag (CR):

This flags is set to 1 when there is an unsigned overflow. For example when we add bytes 255+1.When there is no overflow this flag is set to 0.

Parity flag (PG):

This flag is set to 1 when there is even number of one bits is result and to 0 when there is odd number of one bit.

Auxiliary Flag (AF):

Set to 1 when there is an unsigned overflow for low nibble (4bits).

Zero flag (ZF):

Set to 1 when result is zero. For non zero result this flag is set to 0.

Sign flag (SF):



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Set to 1 when result is negative.

Set to 0 when result is positive.

This flag takes the value of most significant bit (MSB).

Trap flag (TF):

Used for on chip debugging.

Interrupt flag (IF):

Set to 1 when CPU reacts to interrupts from external device.

Direction flag (DF):

This flag is used by some instruction to process data chains when the flag is set to o the processing is done forward when set to 1 the processing is done backward.

Overflow flag (OF):

Set to 1 when there is signed overflow. For example: when add bytes 100+50

***Assembly Language Syntax:

As assembly language program consists of statement. The syntax of an assembly language statement obeys the following rules:

Only one statement is written per line.

Each statement is either an instruction or an assembly directive.

Each statement has an opcode and possibly one or more operands.

An opcode represents a single machine instruction.

***Program Statement:

The general format for an assembly language statement is given below:

Name Opcode Operand (Destination), Operand (Source);Comment.

∎Name Field:

This field is used for:E-mail: [email protected] Twitter: Voboghurer Website: www.engineersafia.wordpress.com


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Instruction label.

Procedure names.

Variable names.

∎Opcode or operation field :

This field consists of a symbolic operation code known as opcode.

The opcode describes the operation function.

Symbolic opcodes are translated into machine language opcode.

∎Operand field:

This field specifies data to be acted on. It may have one or two or more operand.

∎Comment field:

Tsemicolon marks the begging of a comment.

Example: Here: MOV, AX, 086H; statement line with a label field.

***Assembler Directives:

Assembler directives one directed to the assembler. Assembler directives affect the generated machine code, but are not translated directly into machine code. Directives can be used to declare variables, constants, segments and procedures as well as supporting conditional assembly.

In general a directive:

Contains p.seudo-operation code.

Tells the assembler to do a specific thing.

∎Naming conventions:

A name is used to identify a label, a variable, a directive, a procedure. Here are the general rules on the use of names.

A name is between 1 to 31 characters is length.

A name may include letter, numbers and special character such as @ , . & $ # ?

A name should not begin with digit.



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A name may begin with a letter or a specific character.

Name is not case sensitive.

***Title directive:

The title directive is optional and specific the title of the program likes a comment it has no effect on the program. It is just to make the program easier to understand.

***The model directive:

The model directive specifies the total amount of memory the program would take. In other words it gives information on how much memory the assembler would allocate for the program. This depends on the size of the data and size of the program or code.

***Segment directives:

Segments are declared using directives. The following directives are used to specify.

The following segments:

Stack

Data

Code

∎Stack segments:

Used to set aside storage for the stack.

Stack addresses are computed as offsets into this segment.

USE: .Stack followed by a value that indicates the size of the stack.

∎Data segments:

Used to set aside storage for variables.

Variables addresses are computed as offsets start of this segment.

USE : .data followed by declaration of variables or definition of constants.



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∎Code segment:

The code segment contains executable instructions and calls to procedures.

USE : . code followed by sequence of program statements.

***Program data:

Number and

Characters.

∎Number:

A binary number is written as a bit string followed by the letter “B” or ‘b’.

Ex: 1010B

A decimal number is a string of decimal digits ending with an optional “D” or‘d’. Ex: 6123D

A hexadecimal umber must begin with a decimal digit and end with letter “H” or ‘h’.Ex: 1BDH

∎Characters:

Character and Character string must be enclosed in single or double quotes. Ex: ‘A’;”Hello”.

Characters are translated into their ASCII codes by the assembler, so there is no difference between using 41h and ‘A’ is a program.

***Variable:

Byte variable and

Word variable.

∎Byte variable:

Name DB Initial_value

Ex: ALPHA DB 4

∎Word variable:

Name DB Initial_value

Ex: ALPHA DW 236



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***A few Basic instructions:

MOV and

XCHG

∎MOV:

The MOV instruction is used to transfer data between a register and a memory location or to move a number directly into a register or memory location.

The syntax is:

MOV Destination, source

Ex: MOV AX, WORD1

Source Operand

General resister

Segment register

Memory location

Constant

General resister

Y Y Y N

Segment register

Y N Y N

Memory location

Y Y N N

Constant Y N Y N Fig: Logical combination of operands for MOV

∎XCHG:

The XCHG operation is used to exchange contents of two register or a register and a memory location.

The syntax is:

XCHG Destination, source

Ex: XCHG BL, AL

Source operand General register Memory location General register Y Y Memory location Y N



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∎ADD:

ADD Destination, source

∎SUB:

SUB destination, source

EXAMPLE:

ADD WORD1, AX

SUB AX, DX

ADD BL, 5

∎Increment:

INC destination

∎Decrement:

DEC destination

EXAMPLE:

INC WORD1

DEC WORD1

***Translation of high level language to assembly language:

Statement: Translation Meaning

B=A MOVAX, A ; move A into AX

MOV B, AX ; and them into B

A=5-A MOV AX, 5 ; put 5 in AX

SUB AX, A ; AX contains 5-A

MOV A, AX ; put it in A

A=B-2*A MOV AX, B ; AX=B

SUB AX, A ; AX=B-A



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SUB AX, A ; AX=B-2*A

MOV A, AX ; A=B-2*A

∎INT 21H:

INT 21H may be used to invoke a large number of DOS function a particular function is requested by placing a function number in the AH register and invoking INT 21H.

Function Routine

1 Single key input

2 Single character output

9 Character string output

Function (1):

Single key input:

Input: AH=1

Output: AL=ASCII code if character key is pressed

=0 if non-character key is pressed

Code:

MOV AH, 1

INT 21h

Function (2):

Display a character:

Input: AH=2

DL=ASCII code of display character.

Output: AL=ASCII code of display character.

Code:

MOV AH, 2

MOV DL,?



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INT 21h

PROBLEM (1):

Our first program will read a character from the keyboard and display if at the character of the next line.

.MODEL SMALL

.STACK 100h

.CODE

MAIN PROC

; display promt

MOV AH, 2 ; display character

MOV DL, ‘?’ ; display character is ‘?’

INT 21h ; display

; input a character

MOV AH, 1 ; read character function

INT 21h ; character in Al

MOV BL, AL ; save it is BL

; go to a new line;

MOV AH, 2 ; display character function

MOV DL, 0DH ; carriage return

INT 21h ; execute carriage return

MOV DL, 0AH ; line feed

INT 21h ; execute line feed

; display character

MOV DL, BL ; return character

INT 21h ; and display it



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; return to DOS

MOV AH, 4CH ; DOS exit function

INT 21h ; exit to dos

MAIN ENDP

END MAIN

***The LEA instruction:

INT 21h, function 9, expects the offset address of the character string to be in DX. To get it there we use a new instruction:

LEA destination, source

Ex: LEA DX MSG

Where destination is a general register and source is a memory location.LEA stands for “Load Effective Address”.

***Branching structures:

IF-THEN

IF AX<0

p.seudo code THEN

Replace AX by-AX

; if AX<0

CMP AX, 0

JNL END_IF

; then

NEG AX

END_IF:

IF-THEN-ELSE:

PROBLEM (2):



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Suppose AL and BL contain ASCII characters. Display the one that comes first in character sequence.

If AL<=BL

THEN

Display the character in AL

ELSE display the character in BL

END-IF

MOV AH, 2

; if AL<=BL

SCMP AL, BL ; AL<=BL?

JNBE ELSE ; No, display character in BL

; then ;Al<=BL

MOV DL, AL ; MOV character to be displayed

JMP DISPLAY ; go to display

ELSE: ; AL>BL

MOV DL, BL

DISPLAY:

INT 21h ; display it

END IF

PROBLEM (3):

CHARACTER DISPLAY

.MODEL

.STACK

.CODE



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MAIN PROC

MOV AH, 2 ; display character function

MOV CH, 256 ; number of character to display

MOV DL, ’0’ ; DL has ASCII code of null character

PRINT_LOOP:

INT 21h

INC DL

DEC CX

JNZ PRINT_LOOP

; DOS exit

MOV AH, 4CH

INT 21h

MAIN ENDP

END MAIN

PROBLEM (4):

Write a program that will display a row of 80 stars.

.MODEL

.STACK

.CODE

MAIN PROC

MOV CX, 80 ; number of stars to display

MOV AH,2 ;display character function

MOV DL,’*’ ; character to display

JCXZ SKIP ; jump if CX is zero to SKIP

TOP: ; display star



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INT 21h

Loop TOP

SKIP:

; DOS EXIT

MOV AH, 4CH

INT 21h

MAIN ENDP

END MAIN

PROBLEM (4):

Write a program that will convert a lower case letter to uppercase letter.

.MODEL

.STACK 100h

.DATA

CR EQU ODH

LF EQU OAH

MSG1 DB ‘ENTER A LOWER CASE LETTERS: $’

MSG2 DB 0DH, 0AH,’IN UPPER CASE IT IS: $’

CHAR DB ?

.CODE MAIN PROC

; initialize Ds

MOV AX,@DATA

MOV DS, AX

; PRINT USER PROMPT

LEA DX, MSG1

MOV AH, 9E-mail: [email protected] Twitter: Voboghurer Website: www.engineersafia.wordpress.com


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INT 21H

; input character and convert to upper case

MOV AH, 1

INT 21H

SUB AL, 20H

MOV CHAR, AL

; display on the next line

LEA DX, MSG2

MOV AH, 9

INT 21h

; DOS EXIT

MOV AH, 4CH

INT 21h

MAIN ENDP

END MAIN

Use of AND, OR, XOR:

One use of AND, OR and XOR is to schectively modify the bits in the destination. To do this we construct a source bit pattern know as mask. The mask bits are chosen.

To choose mask bits we will see the following properties of AND, OR and XOR:

b AND 1=b b OR 0=b b XOR 0=b

b represents a bit (0 or 1)

b AND 0=0 b OR 0=b b XOR 1= b

From these we can conclude:



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(1) The AND instruction can be used to clear specific destination bits while preserving the others. A 0 mask bits clear the corresponding destination bit; a 1 mask bit preserves the corresponding destination.

(2) The OR instruction can be used to set specific destination bits while preserving the others. A 1 mask bits set the corresponding destination bit; a 0 mask bit preserves the corresponding destination.

(3) The XOR instruction can be used to complement specific destination bits while preserving the others. A 1 mask bits clear the corresponding destination bit; a 0 mask bit preserves the corresponding destination.

Test Instruction:

The test instruction performs on AND operation with the source but does not change the destination contents. The syntax of test instruction is:

TEST destination, mask

The test instruction can be used to examine individual bits in an operand. The mask should contain 1’s in the bit position to be tested and 0’s elsewhere because

1 AND b=b; 0 AND b=0

EXAMPLE:

Jump to label below if AL contains an even number.

ANS: Even number has a 0 in bit 0 position. Thus the mask is 00000001b=1

TEST ALL, L; is AL even?

JZ BELOW; Yes, go to be low.

SHIFT Instruction:

(1)SHL (3) SAL

(2)SHR (4) SAR

∎SHL:

The SHL (Shift Left) instructions Shifts the bits in the destination to the left. The format for a single shift is:

SHL Destination, 1

A 0 is shifted into the rightmost bit position and the also msb is shifted into CF. For a Shift of N position format is:



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SHL Destination, Cl where CL contains N.

CF

EXAMPLE:

Suppose DH contains 8 Ah and CL contains 3.What are the values of DH and CF after the instruction SHA, CL is executed?

8AH=10001010

DH=o1o1oooo

CF=0

∎Multiplication by left shift:

A left Shift on a binary number multiplication it by 2. For example:

Suppose AL contains 5=00000101b. A left shift gives 00001010=10d. These doubling the value. Another left gives 00010100=20d. So , it is doubling the value again.

EXERCISE:

Write some code to multiply the value of AX by 8.

MOV CL, 3

SAL AX, CL

∎SHR:

SHR destination, 1

SHR destination, CL

A 0 is shifted into the msb position and the rightmost bit in shifted into CF.

0

7 6 5 4 3 2 1 0

∎SAR:


CF


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A right shift divide a binary number by 2.This is current for even numbers for add numbers a right shift it and rounds down to the nearest integer. For example if BL contains=00000101b=5,

Then after a right shift BL will contain 00000010=2

EXAMPLE: Divide the number 65143 by 4 and put. The answer in AX

MOV AX, 65143

MOV CL, 2

SAR AX, CL

∎Rotate:

Rotate Left:

The instruction ROL (Rotate Left) shifts bits to the left. The msb is shifted into the rightmost bit. The CF also gets the bit shifted out of the msb.

Syntax: ROL destination, 1

And

ROL destination, CL

CF

Rotate Right: The instruction ROR (Rotate Right) shifts bits to the right. The msb is shifted into the leftmost bit. The CF also gets the bit shifted out of the msb.

Syntax: ROR destination, 1

And

ROR destination, CL

7 6 5 4 3 2 1 0


CF


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∎Rotate Carry Left:

RCL (Rotate Carry Left) shifts the bits of the desatination to the left. The msb is shifted into the CF and the previous value of CF is shifted into the right most bit.

Syntax: RCR destination, 1

And

RCR destination, CL

∎Rotate Carry Right: RCR (Rotate Carry Right) shifts the bits of the destination to the left. The msb is shifted into the CF and the previous value of CF is shifted into the left most bit.


CF

CF


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Suppose DH contains 8 Ah ,CF=1 and CL=3 what are the values of DH, CF after the instruction

RCR DH, CL is executed

8Ah=1000101D

7 6 5 4 3 2 1 0

Reversing a Bit pattern: An easy way to do this is to use SHL to shifts the bits out the left end of Al into CF and then use RCR to move them in to the left end of another register BL. In this is done eight times BL will contains the reversed bit pattern and it can be copied back to AL. The cod is;

MOV CX,8;number of operations to do

REVERSE:

SHL AL, 1; get a bit into CF

RCR BL, 1; rotate it into BL

Loop REVERSE ; Loop until done


CF

1 0 0 0 1 0 1 0


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MOV AL, BL ; AL gets reserved pattern

∎STACK: A stack is one dimensional data .Items are added and removed from one end of the structure; that is it is processed in a “last –in first out “manner.

∎PUSH and PUSHF:

To a add a new word to the stack we use PUSH. The syntax is:

PUSH source

Where source is a 16-bit register or memory word. For example:

PUSH AX

Execution of PUSH causes the following to happen:

(1) SP is decreased by 2.(2) A copy specified by SS: SP the source is unchanged.(3) The instruction PUSHF has no operand, PUSHES the contents of the FLAGS register on to the

stack.

How PUSH works:

Initially, SP contains the offset address of the memory location immediately following the stack segment. The first PUSH decrease SP by 2 making it point to the last word in the stack segment, because each PUSH decreases SP, the stack grows to word the beginning of memory.


Offset

00F0

00F2 0100 SP

00F4

00F6 1234 AX

00F8

00FA 5678 BX

00FC

00FE

0100 SP

Stack (Empty)


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Fig: (a) Empty stack

Offset

00F0 00FE SP

00F2

00F4 1234 AX

00F6

00F8 5678 BX

00FA

00FC

00FE 1234 SP

0100

Fig: (b) After PUSH AH

Offset

00F0 00FE SP

00F2

00F4 1234 AX

00F6

00F8 5678 BX

00FA

00FC 5678 SP

00FE 1234

0100



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Stack

Fig: (c) After PUSH BX

∎POP & POPF:

To remove the top item from the stack we will use POP instruction. The syntax is

POP Instruction: POP Destination

Where destination is a 16-bit register or memory location for example;

POP BX

Executing POP causing to happen:

(1) The content of the top stack is moved to destination.(2) SP in increased by 2.

POPF:

The instruction POPF POPS top of the stack into the FLAG register.

Offset

00F0

00F2 00FC SP

00F4

00F6 FFFF CX

00F8

00FA 0001 DX

00FC 5678 SP

00FE 1234

0100

Fig: (a) Before POP

Offset



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00F0 00FE SP

00F2

00F4 5678 CX

00F6

00F8 0001 DX

00FA

00FC 5678

00FE 1234 SP

0100

Fig: (b) After POP CX

Offset

00F0 0100 SP

00F2

00F4 5678 CX

00F6

00F8 1234 DX

00FA

00FC 5678

00FE 1234

0100 SP

Fig: (c) After POP DX



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