Upload File

vlsi - silicon gate technology

prev
next
out of 18
Download VLSI - Silicon Gate Technology

Upload: krraguram

Post on 05-Apr-2018

239 views

Category:

Documents


0 download

Report

TRANSCRIPT

  • 7/31/2019 VLSI - Silicon Gate Technology

    1/18

    Silicon Gate Technology and

    Ion Implantati

    on

  • 7/31/2019 VLSI - Silicon Gate Technology

    2/18

    ION IMPLANTATION

    Ion Implantation is an alternative to deposition/diffusion

    and is used to produce a shallow surface region of dopant

    atoms deposited into a silicon wafer.

    In this process a beam of impurity ions is accelerated to

    kinetic energies in the range of several tens of kV and is

    directed to the surface of the silicon.

  • 7/31/2019 VLSI - Silicon Gate Technology

    3/18

    The impurity atoms enter the crystal, they give up their

    energy to the lattice in collisions and finally come to rest

    at some average penetration depth, called the projected

    range expressed in micro meters.

    Depending on the impurity and its implantation energy,

    the range in a given semiconductor may vary from a few

    hundred angstroms to about 1micro meter.

  • 7/31/2019 VLSI - Silicon Gate Technology

    4/18

    ION IMPLANTATION SYSTEM

  • 7/31/2019 VLSI - Silicon Gate Technology

    5/18

    The ions are generated and repelled from their source in

    a diverging beam that is focused before if passes through

    a mass separator that directs only the ions of the desired

    species through a narrow aperture.

    A second lens focuses this resolved beam which then

    passes through an accelerator that brings the ions to their

    required energy before they strike the target and become

    implanted in the exposed areas of the silicon wafers.

    The accelerating voltages may be from 20 kV to as much

    as 250 kV.

  • 7/31/2019 VLSI - Silicon Gate Technology

    6/18

    ADVANTAGES:

    Ion implantation provides much more precise control

    over the density of dopants deposited into the wafer, and

    hence the sheet resistance.

    Due to precise control over doping concentration, it is

    possible to have very low values of dosage so that very

    large values of sheet resistance can be obtained. These

    high sheet resistance values are useful for obtaining

    large-value resistors for ICs.

  • 7/31/2019 VLSI - Silicon Gate Technology

    7/18

    Another advantage of ion implantation is that it can be

    done at relatively low temperatures, this means that

    doped layers can be implanted without disturbing

    previously diffused regions. This means a lesser

    tendency for lateral spreading.

  • 7/31/2019 VLSI - Silicon Gate Technology

    8/18

    THE SILICON GATE TECHNOLOGY

    The Silicon Gate Technology was the worlds first

    commercial MOS self-aligned-gate process technology.

    Before this technology, the control gate of the MOS

    transistor was made with aluminum instead of

    polycrystalline silicon.

    Aluminum-gate MOS transistors were three to four

    times slower, consumed twice as much silicon area,

    had higher leakage current and lower reliability

    compared with silicon-gate transistors

  • 7/31/2019 VLSI - Silicon Gate Technology

    9/18

    Faggin created the silicon gate technology in 1968 while

    working in the R&D Laboratories of Fairchild

    Semiconductor in Palo Alto, CA.

    A transistor gate is formed wherever polysilicon crosses

    diffusion (semiconductor) with oxide between these

    layers.

  • 7/31/2019 VLSI - Silicon Gate Technology

    10/18

    PROCESS OF FABRICATION

    STEP 1:

    Si-substrate

    Pure Si single crystal

    - - - - - - - - - - - - - - - - - - - - - - - -

    - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - -

    - - - - - - - - - - - - - - - - - - - - - - - - -

    P-type impurity is lightly doped

  • 7/31/2019 VLSI - Silicon Gate Technology

    11/18

    STEP 2:

    Thick SiO2(1 m)

    - - - - - - - - - - - - - - - - - - - - - - - -

    - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - -

    - - - - - - - - - - - - - - - - - - - - - - - - -

    Fig. (4) Photoresist is depositedover SiO2 layer

    Thick SiO2(1 m)

    Photoresist

    - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - -

    - - - - - - - - - - - - - - - - - - - - - - - - -

  • 7/31/2019 VLSI - Silicon Gate Technology

    12/18

    STEP 3:

    Thick SiO2(1 m)

    UV Light

    Mask-1

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    Photoresist

  • 7/31/2019 VLSI - Silicon Gate Technology

    13/18

    Thick SiO2(1 m)

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

  • 7/31/2019 VLSI - Silicon Gate Technology

    14/18

    STEP 4:

    UV Light

    Mask-2

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

  • 7/31/2019 VLSI - Silicon Gate Technology

    15/18

    Thick SiO2(1 m)

    Thin SiO2(0.1 m)

    Polysilicon used as GATE(1 2 m)

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

  • 7/31/2019 VLSI - Silicon Gate Technology

    16/18

    STEP 5

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    Thick SiO2

    (1 m)

    Thin SiO2(0.1 m)

    GATE

    - - -- - -n+

    - - - -- -

    n+

    SOURCE DRAIN

  • 7/31/2019 VLSI - Silicon Gate Technology

    17/18

    ADVANTAGES OF SILICON GATE

    TECHNOLOGY

    FAST AND LOW POWER CONSUMING:

    the drastic reduction of the overlap

    capacitances between the gate electrode and the source

    and drain junctions.

    COST-EFFECTIVE

    RELIABLE

  • 7/31/2019 VLSI - Silicon Gate Technology

    18/18

    THANKYOU


Chapter 3 plummer SILICON VLSI TECHNOLOGY

SILICON PROCESSING FOR THE VLSI ERA

The MOS Silicon Gate Technology and the First Microprocessors€¦ · The MOS Silicon Gate Technology and the First Microprocessors ... key components necessary to build a ... volume

MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOScaxapa.ru/thumbs/905852/datasheet_en_20180601-1484094.pdfMOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 GBIT (128M × 8 BIT) CMOS

IEEE Web Hosting - Designing VLSI Interconnects …...Designing VLSI Interconnects with Monolithically Integrated Silicon-Photonics Vladimir Stojanović MIT SSCS DL series – Santa

Neuromorphic silicon neuron circuits - Digital CSICdigital.csic.es/bitstream/10261/83317/1/Neuromorphic... · 2016-02-17 · fabricated VLSI chips. Keywords: analog VLSI, subthreshold,

VLSI Fabrication Technologysmdp2vlsi.gov.in/smdp2vlsi/downloads/jun06.pdf · VLSI Fabrication Technology 1. S. K. ... Silicon and Gallium Arsenide, Second Edition, ... Wolf, Modern

VLSI Fabrication Principles, Silicon and Gallium Arsenide - 1994 Gandhi (Wiley, 2E)

Gate-Level Minimization - Welcome to VLSI …viplab.cs.nctu.edu.tw/course/DCD2017_Spring/DCD_Lecture...Gate-level minimization refers to the design task of finding an optimal gate-level

Introduction to VLSI 2020. 8. 17. · Introduction to VLSI ITI Ismailia Silicon technology roadmap low power SoC high performance MPU/SoC 2001 2004 2010 2001 2004 2010 gate length

Digital VLSI Design with Verilog - media control · 2013. 7. 18. · Digital VLSI Design with Verilog. John Williams Digital VLSI Design with Verilog A Textbook from Silicon Valley

VLSI DESIGN AND FABRICATION FOR LIQUID CRYSTAL ON SILICON

VLSI Technology - RoboSpecies VLSI Technology.pdf · Verilog HDL Programming of CMOS NOR gate, MUX, ... Concept of Ultrasound ... Why VLSI Technology Training from RoboSpecies Technologies?

Text Book: Silicon VLSI Technology Fundamentals, Practice ...zyang/Teaching/20182019SpringECE541/D… · Crystal Growth, Si Wafers- Chapter 3 Text Book: Silicon VLSI Technology Fundamentals,

3D VLSI: Next Generation 3D Integration · PDF file3D VLSI - An Emerging 3D Technology 3D VLSI SRAM Samsung (2010) Vertical via Gate 3D VLSI for general logic LETI (2011) High quality

Semiconductor Physics GATE Problems - …€¦ · Semiconductor Physics – GATE Problems 1. A P-type silicon sample has higher conductivity compared to an n-type silicon sample …

CS250 VLSI Systems Design - inst.eecs.berkeley.eduinst.eecs.berkeley.edu/~cs250/fa09/lectures/lec01.pdfCS250 VLSI Systems Design ... curriculum, research projects with silicon structures

Intel Confidential - Flash Memory Summit · SiGe Strained Silicon 2nd Gen. SiGe Strained Silicon 2nd Gen. Gate-Last High-k Metal Gate Invented Gate-Last High-k Metal Gate First to

PARALLEL LOGIC SIMULATION OF MILLION-GATE VLSI …szymansk/theses/zhu.ms.04.pdfPARALLEL LOGIC SIMULATION OF MILLION-GATE VLSI CIRCUITS By Lijuan Zhu ... FPGA/ASIC Design Flow • Gate-level

Advanced VLSI Design - csee.umbc.edutinoosh/cmpe641/slides/lect00_intro.pdf · Advanced VLSI Design Introduction CMPE 641 Gate-Array Based Design: Sea-of-Gates In a gate array, the

Introduction to CMOS VLSI Design Test. CMOS VLSI DesignTestSlide 2 Outline Testing –Logic Verification –Silicon Debug –Manufacturing Test Fault Models

Gate-All-Around Silicon Nanowire MOSFETs: Top-down

CMOS VLSI Design Harris Lab 1: Gate Design

MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Sustainable Silicon: Energy‐Efficient VLSI Interconnect …science.energy.gov/~/media/ascr/ascac/pdf/meetings/aug11/Chaing.pdf · VLSI Interconnect ... IEEE Computer Architecture

Split gate tunnel barriers in double top gated silicon

Parallel Implementation of VLSI Gate Placement in CUDApages.cs.wisc.edu/~kzhao32/projects/cs759gatePlacementCADtool.pdf · ... Project Report Parallel Implementation of VLSI Gate

VERY LARGE SCALE UCSC Silicon Valley Extension’s VLSI ... · PDF fileUCSC Silicon Valley Extension’s VLSI ... Courses in the certificate programs are subject to change based

Smart Gate Driver Design for Silicon (Si) IGBTs and

Introduction to CMOS VLSI Designkogge/courses/cse40462-VLSI-fa18/www/Public/... · CMOS VLSI Design Standard Cell Layout Layout Slide 17 Layout CMOS VLSI Design Slide 18 Gate Layout

SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ : Silicon VLSI Technology

Material and process limits in silicon VLSI technology

Ebooksclub.org VLSI Fabrication Principles Silicon and Gallium Arsenide 2nd Edition

silicon retina usin VLSI technology

Silicon nitride gate dielectrics and bandgap engineering