VLSI Power Delivery For Core, I/O, andAnalog Supplies

Claude R. Gauthier, Ph.D.,

Brian W. Amick

Sun Microsystems Inc.,

Major Electrical Interfaces Core Power Delivery

Physical and electrical view

Parasitic inductance estimation

Distribution issues, guidelines

I/O Power Delivery and Signaling Signal return current

Analog Power Delivery

Summary

Microprocessor Design Constraints Power supply impedance

Z=(∆VSPEC)/(∆IESTIMATE): Ex. 1.8-V x 5% / 10-A = 9-mΩ

Must deliver power over a broad frequency spectrum

Time (cpu clock cycles)

Po

wer

Max

Avg

Min

Architectural Power Model To Estimate ∆IClockGating

Microprocessor System Power perspective

Package types, attach strategy, board or MCM type,package/board layer assignments, decoupling capacitorrequirements.

package

capacitorvoltage regulator

capacitor

capacitor

capacitor

processor with on-chip capacitors

Decoupling Capacitor Modeling Wide range in performance and cost

Example: 3 different capacitors

Parasitics between banks must be included

SymbolWave

D0:A0:vm(1)

D0:A0:vm(4)

D0:A0:vm(7)

Volts

Mag

(log

)

1m

10m

100m

1

10

Frequency (log) (HERTZ)100k1x 10x 100x

1g

|X(f)|=1/(2πCF)|X(f)|=2πF*ESL

X(f)=ESR

1st OrderCapacitorModel

ESL

ESR

Cap

Impe

danc

e

Frequency

1mΩ

10mΩ

100mΩ

1Ω

10Ω

1MHz 10MHz 100MHz 1GHz.1MHz

Low Frequency Electrical View

Bumps,GridPCBPCBVoltage

Regulator PlanesVias and

Planes Package

BulkCaps

CeramicCaps

Package Vias,Planes, Caps

On-Chip

SwitchingLogic

Non-SwitchingLogic

Imp

ed

an

ce

Frequency

FREGULATOR FBULK FCERAMIC FPACKAGE

1/(jωCB )

1/(jωCC )

1/(jωCP )

1/(jωCDIE )

Z

Z

Qualitative Look At Frequency Domain

Cap

Inductance of Vias, Pins, Bumps Mutual inductance [1],[2]

Self inductance [1],[2]

Loop inductance of arrays is pattern dependent [3]

Muo2π------l l

s-- 1 l

2

s2

-----+

+

1 s2

l2

-----+

– sl--+ln

=

Luo2π------l 2

ld--- 1 4l

2

d2

--------+

+

1 0.25d2

l2

-----------------+

– 0.5dl---

ur4

------+ +ln

=

POOR BETTER

d

l

s

Inductance Simplification Can collapse to single inductor

Use a script/spreadsheet to construct a matrix

Lump same-type inductors in parallel and place powerand ground inductors in series

Simulate w/ spice in AC domain to determine equivalentseries inductance (V=I*jωL)

LP1

LPN

LG1

LGN

Mij1-AAC

LEFF

1-AAC

Power Plane Inductance Planes are present in the package and on the board

Loop inductance [2]:

Most planes are actually perforated

Decrease inductance for multiple pairs by 2n-1dielectrics, where n is the number of power planepairs, assuming VDD-GND-VDD-GND stack-up

Thin spacing decreases inductance

Luoπ

------ld

B C+-------------- 1.5+ln

=

d

B

Cµo

l

Low/Mid-Frequency Chip Model Estimate switching capacitance from thermal power

CSWITCH=P/(V2f)

On-die decoupling capacitance is typically about 10xthe switching capacitance (rule of thumb)

Yield issue (decoupling is ~15-20% of die area)

Scaling issue for process shrinks - leakage

Equivalent series resistance (ESR) Ratio of one type to the other is design-specific

High ESRCapacitor(Channels)

Low ESRCapacitor(Sub-blocks)

SwitchingCapacitance

Non-switchingCapacitance

Selecting and Sizing Capacitors Construct system model and determine R and L

from physical geometry

Run AC analysis with circuit simulator by sweepingload switching frequency

Different types of caps target different frequencies Board Capacitor: 1-MHz to 10-MHz

Package Capacitor: 10-MHz to 200-MHz

On-Chip Capacitor: High-Frequency

Find number & types of caps with spice simulationWhile (! full AND ! meeting_spec) Beginincrement num_caprun_ac_analysisextract_impedanceIf (impedance < target) BeginExitEndIfIf (full AND ! meeting_spec) Beginreplace_capEndIfEndWhile

Decoupling Capacitor DesignSymbolWave

D0:A3:vm(supply)

D0:A4:vm(supply)

Volts Ma

g (lin)

0

2m

4m

6m

8m

10m

12m

14m

16m

18m

20m

Frequency (log) (HERTZ)1x10x 100x

1gFrequency

Impe

danc

e

20

2

10

10MHz 100MHz

FrequencyResponse

1MHz 1GHz

With Package Capacitor

Without Package Capacitor

SymbolWave

D0:A0:fdsa

D0:A1:dfads

Result (

lin)

760m

780m

800m

820m

840m

860m

880m

900m

920m

940m

960m

980m

1

Time (lin) (TIME)05n 10n 15n 20n 25n 30n 35n 40n 45n 50n 55n 60n 65n 70n 75n 80n 85nTime

On-

Chi

p V

olta

ge

StepResponse

0nS 30nS 60nS 90nS.76xVDD

.84xVDD

.92xVDD

1xVDD

With Package Capacitor

Without Package Capacitor

On-Die Voltage Regulator Detect, and actively compensate for voltage swings

in the target frequency range:

+

-

C2

C1charge

charge

discharge

quiescent @ Vss

quiescent @ Vdd/2onchip Vdd

V inst Monitor and Charge Pump LoopVave Tracking Loop

Vdd

tdischarging charging

Vinst< Vave Vinst> Vave Vinst= VaveVinst= Vave

-

+

+

- + +--

a

b

a

b

quiescent @ Vdd

quiescent @ Vdd/2onchip Vss

quiescent@ Vdd/2

quiescent@ Vdd/2

Results

See paper for more details

1.5V

1.6V

1.7V

0 10n 20n 30n 40n 50n

Regulators ON

1.5V

1.6V

1.7V

0 20n 40n 60n 80n 100n

Regulators OFF

Regulators OFF Regulators ON0.625Tck |-----------| |-----------|

|-----------| |----------*||-----------| |----------*||-----------| |---------**||-----------| |---------**|

0.750Tck |-----------| |--------***||-----------| |--------***||-----------| |------*****||-----------| |------*****||----------*| |---********|

0.875Tck |----------*| |---********||---------**| |--*********||---------**| |***********||--------***| |***********||--------***| |***********|

1.000Tck |-------****| |***********||-------****| |***********||------*****| |***********||------*****| |***********||------*****| |***********|

1.125Tck |-----******| |***********||-----******| |***********||-----******| |***********||----*******| |***********||----*******| |***********|

1.250Tck |----*******| |***********|

1.40V 1.80V 1.40V 1.80V

Higher Frequency Models Expand plane / via examples to derive a new model,

with smaller ‘lumps’

Mid/high frequency 3-D package/chip models

Very high frequency Small localized regions

3-D chip model

Field solvers

On-Chip Decoupling Maximize on-die decoupling capacitance subject to

yield/area constraints

MOS capacitors provide on-die decoupling Effectiveness is proportional to capacitor time constant -

a long channel length will not decouple a signal risetime - a small channel length reduces area efficiency

Set a guideline based on simulations

Scaling issue for process shrinks as rise times and parasiticsscale

DecapLoadVdecap

+

-

On-Chip Power Distribution Guidelines Checkerboard bump pattern

Close to switching circuits

Watch for electromigration

Dense power-grid Alternate VDD/VSS

Explore µarchitectural fix for clock-gating Control ramp-rates of clock gating

Circuit techniques are also effective Lower the Q of the power supply network or reduce ∆I

Off-Chip Power Delivery Guidelines Pay attention to the capacitor mounting and shorten

the leads

Place capacitors close to the chip

Reduce spacing between planes

Add more VDD, VSS planes in an alternating pattern

Sockets, vias, bump arrays Use checkerboard patterns where possible

Use as many parallel paths as possible, without eatingup the entire plane with anti-pads

I/O Signaling Two separate paths to consider: power, signal return

Vdd

Vss

Signal 1

Signal 2

Package Model

Package

RX

T-Line

Supply Impedance:Use core power guidelines

T-Line

Only 1 SPICENode 0

PCB Traces

Package

Driver

Package Cross-SectionVdd

Signal 1 Signal 2

Vss

I/O ExampleSymbol

Volta

ges (

lin)

100m

150m

200m

250m

300m

350m

400m

450m

500m

550m

600m

650m

700m

750m

800m

850m

900m

950m

1

1.05

1.1

1.15

1.2

1.25

1.3

Time (lin) (TIME)8n 8.5n 9n

Vol

tage

Time0nS 1nS.1V

1.3V

.3V

.5V

.7V

.9V

1.1V

Symbol

Volta

ges (

lin)

100m

150m

200m

250m

300m

350m

400m

450m

500m

550m

600m

650m

700m

750m

800m

850m

900m

950m

1

1.05

1.1

1.15

1.2

1.25

1.3

Time (lin) (TIME)8n 8.5n 9n

Vol

tage

Time0nS 1nS.1V

1.3V

.3V

.5V

.7V

.9V

1.1V

How does signal return currentget from board (VSS only) topackage (VDD/VSS)?

Package capacitors to reducesignal return impedance?

Vdd

Vss

Vss

Package Board

Signal

Vdd

Vss

Vss

Package Board

Signal

High-Speed I/O Guidelines Power Distribution Impedance

Same guidelines as core power

Signal Return Impedance Maximize the power/ground pins in the chip, package,

and connector pin-out (under cost constraint)

Careful routing to avoid discontinuities

Minimize the effects of discontinuities by providing analternate return path (i.e. through a decouplingcapacitor)

Analog Power Noisy digital circuits & sensitive analog circuits share

the same environment Power supply coupling

Crossing supply domains

Quiet VDD

In microprocessor PLLs and DLLs power supply noisedominates jitter

SwitchingVoltage

InputSignal

∆vn

∆τ

Providing Clean Analog Supplies On chip methods: regulators and RC filters

System level approach: Use seperate trace for supply and PCB filter

Can model coupling from other traces/vias

AnalogCircuit

PCBFilter

T-LineTrace between

Gnd planesin package

C4 bump andvia impedance

Pin and viaimpedanceVoltage

at PCB

AnalogCircuit

PCBFilter

Trace betweenGnd planesin package

C4 bump andvia impedance

Pin and viaimpedanceVoltage

at PCB

Crossing Supply Domains What about noisy on-chip VSS ?

VSS isolation can be costly

Use shorted Vss as on PCB

Force VDD to track the local VSS

Reference bias lines to VDD, decoupling capacitors

R Substrate

R Power Grid

L Gnd 2L Gnd 1L Gnd

L Vdd 1 L Vdd 2

Vdd 1 Vdd 21 -> 0

0 -> 1Decap Decap

1 -> 0

Summary Several important aspects of delivering clean power

Supplying power across a broad frequency spectrum

Decoupling capacitor sizing and placement

I/O return current discontinuities and supply impedance

Solutions encompass board, package, chip

Modeling concepts Vias, bumps, pins, power planes, capacitors, and

processor

General guidelines for power distribution

References1. E. Rosa, “The Self and Mutual Inductance of Linear Conductors,” in Bureau

of Standards Bulletin 4, 1907.

2. F. W. Grover, “Inductance Calculations Working Formulas and Tables,” D.Van Nostrand Company, 1946.

3. R. Wheeler, “Modeling Simultaneous Switching Noise (SSO) in the Z-axisDirection of VLSI Packages and PCB’s”, http://www.wheeler.com,1999.

4. M. Ang, S. Taylor, R. Salem, “An On-Chip Voltage Regulator UsingSwitched Decoupling Capacitors,” in ISSCC Proceedings, Feb. 2000.

5. William J. Dally and John Poulton, “Digital Systems Engineering,”Cambridge University Press, 1997.

Acknowledgements Several functional groups contributed to this material Miriam Blatt, Sudhakar Bobba, David Greenhill, Istvan Novak, Sreemala Pannala,

Aninda Roy, Tanmoy Roy, Steve Schmidt, Bidyut Sen, GP Singh, Larry Smith,John Tam, Robert Voelker, Richard Wheeler, Ban-Pak Wong, Gin Yee.