vlsi digital design

ESSENTIALS OF

PROFESSIONAL

VLSI DIGITAL DESIGN

- AN INTRODUCTION WITH DEMOS

© 2015 Logosent Semiconductors India Pvt. Ltd.

Tony Thomas

Logosent Semiconductors India Pvt. Ltd.www.logosent.com

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Agenda

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Tony Thomas E ( [email protected] )

Digital Design Development (SOC/FPGA/IP) – An Overview.

Designs vary hugely - What are some common aspects ?

The Digital Design course contents – A complete list.

Q & A

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The Design Cycle simplified.

Functional and DFTM Specifications

Micro-architectureand detailed design development

Business justification,Requirements sign-off,Boundary Agreements

Kick-off

RTL CodeImplementation and

Quality checks

Logic Synthesis (SOC/IP/FPGA)Scan-insertion, Logic Equivalence Checks (SOC/IP)

Functional verification& Hardware Emulation

(if applicable)

Test Bench andTest-case/stimuli

development

DFTM pattern generation, Pattern Simulations,

Coverage analysis andEnhancements.

Floorplan, package design,CTS, Place and Route,

Back-end checks (SOC/IP)FPGA implementation mainly

involves partitioning and route

Final QC andHand-off

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Parasitic extraction andStatic Timing Analysis (SOC/IP).

For FPGA, STA is part of the implementation process.

FRONT-END DESIGN

PHYSICAL DESIGN

FRONT-END DESIGN

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RTL Coding, Simulation and Synthesis

• Language constructs and optimum usage SystemVerilog and VHDL

• Good coding practices for robust RTL Good readability and debug-ability DFTM considerations Timing closure friendly Synthesizable Well partitioned Portable across technologies

• Testbench development and simulations. Test environment developed based on SPEC Industry standard environments like UVM, SystemVerilog Uses tools like ModelSim (Mentor Graphics), VCS

(Synopsys) and NC-Sim (Cadence)

• Logic synthesis – Mapping to the gate-netlist. Inputs are cell-libraries, constraints and source RTL Uses tools like Design Compiler (Synopsys) and RTL

Compiler (Cadence).

Digital Design: Critical know-how.

DEMO 1Default condition

in conditional assignments

EXAMPLELAB GUIDANCE

SLIDES

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Lab Slide: Compile RTL using ModelSim

Altera-ModelSim Starter Edition is the default tool for executing all our lab simulations.– Got to the sim/ directory, execute the following commands to bring up ModelSim GUI:

• $ cd ../sim/

• $ vsim & (ModelSim simulator GUI pops-up and runs in the background)

– From the main menu, select Compile Compile. In the pop-up window, browse to the directory containing the Verilog files (i.e. ../Sandbox/) and select both shift register Verilog files.

– Now click on the 'Compile' button in the pop-up window to compile the Verilog files.

– For first time compile, the simulator will ask permission to create the 'work' library inside the sim/ directory, where all compiled output will be kept. Select ‘Yes’.

– Check for any errors/warnings

in the ‘Transcript’ pane at the

bottom of the ModelSim GUI.

– Click 'Done' to exit the

Compile pop-up window .

– Repeat the above for

re-compiling new RTL.

27 October, 2015 Tony Thomas E ( [email protected] )

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Select Verilog files

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Lab Slide: Start simulation using ModelSim

Once the RTL files are compiled with no errors, follow below steps to start simulation:

– From the main menu, select Simulate Start Simulation. In the new pop-up window, select the ‘shift_reg_tb’ module after expanding the 'work'. Click Ok. Now the design gets loaded.


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Selectthe top module

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Lab Slide: Run simulations using ModelSim

Once the design is loaded, add signals to the wave window and run simulations– Select the signals that we want to see and add them to the wave window. <Select signals in the

Objects Pane> Right Click Add Wave. Now click on ‘u_reg0’ instance, add more signals.

– Now run the simulation : From the main menu, select Simulate Run Run All. (Opt NOT to finish the simulation, if prompted). In the waveform window, right click and select ‘Zoom Full’. Check out various zoom options, add multiple cursers etc.

– Note that the waveform window can be floated using the ‘Dock/Undock’ button and then resized.


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. SelectInstance

Select signals andadd wavesbefore Run.

DEMO 1Default condition

in conditional assignments

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Critical design elements and related design considerations

• Clocking Clock-tree Clock-dividers, Clock-Multiplexers and Clock-gating. Timing Analysis – Setup, hold, input/output delays

• Synchronization. Meta-stability Vs number of synchronization stages Selective synchronization

• Resets. Synchronous and Asynchronous resets Power-On reset, Warm reset etc.

• Interface Buses and typical sideband signals. Interface protocols like AMBA, OCP, USB3.0, IIC etc. Side-band signals like interrupts, events, power mgmnt ctrl etc.

• Finite State Machine (FSM) implementations. Moore and Mealy FSM implementation styles.

• Power management functionality Power and Voltage domains Isolation cells, Level shifters, retention Flip-Flops Adaptive Body Bias, Dynamic Voltage and Frequency Scaling

• DFTM structures Scan-chains, Scan-combiners, Test-Mode-Control, BSCAN etc.

Digital Design: Critical know-how – Contd.

DEMO 2AND based and LATCH+AND based clock-gating.

EXAMPLE COURSE THEORY

SLIDES

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Theory slide: Clock-gating Overview

– The clock tree buffers and the Flip-Flops to which the clocks are fed, dissipate significant amount of power due to the switching of the clock (CV F).

– It is desirable to “gate-off” the clocks when the circuit functionality fed by the clocks are not being used (E.g. When CPU is in Idle state waiting for Interrupt).

– Clock-gating circuits form part of the Clock-Tree and require special timing closure requirements to be met.

– Typical Clock-gating methods:


2

Clock

Clock_enableGated_clock

Clock

Clock_enable

Gated_clock

Simple AND gate based gating

• Pros: Simple implementation, less power• Cons: Enable signal generated on “posedge” can cause glitches

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Theory slide : Latch based Clock-gating

– During test-mode (DFTM), all functional clocks must be controllable by the test logic. To facilitate this, the “Clock_enable” signal is OR-ed with a “Test_enable” signal before feeding to the Latch input of the clock-gate. The Test_enablesignal remains inactive (‘0’) in the normal functional mode.


Clock

Test_enable

Gated_clock

Clock

Clock_enable

Latch based gating

• Pros: Glitch free implementation.• Cons: Testability issues with the Latch, more power for clock-gating logic.

D Q

/EN

Latch_out

Latch

Latch_out

Gated_clock

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Clock_enable

DEMO 2AND based and LATCH+AND based clock-gating.

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Front-End Design Automation

• IP Packaging and IP/SOC/FPGA Integration tools IP-XACT : IP interface abstraction. GenSys (Atrenta/Synopsys), Magillem, XILINX-Vivado etc. System interconnect generators.

• Custom scripts using languages like Perl and TCL.

Digital Design: Critical know-how – Contd.

DEMO 3Usage of Perl script for RTL generation

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• The students will download and install an Oracle Virtual Box Machine on their PC which includes Ubuntu LINUX OS, the lab reference material and all tools required to execute the lab exercises. The Virtual Machine (VM) runs just like any other application on either

Windows or LINUX based PC and requires no additional licenses. The VM can be used even beyond the course completion for continued self-

learning and RTL development/simulations.

• All labs are executed in the LINUX environment, which is pretty much the standard across the industry for high-performance design development.

• As part of the LINUX based labs, the students will learn to use VIM (a powerful text editor) and Perl coding for RTL generation.

• The main RTL compilation and simulation tool is ModelSim. ModelSim is an industry standard RTL simulation tool developed by Mentor Graphics. The VM also includes the open-source tools like Icarus Verilog RTL compiler for quick compiles and

GTKWave for wave-form viewing.

• A TSMC018 standard-cell library is included for basic synthesis checks using an open-source RTL synthesis tool named YOSYS, along with a Schematic Viewer tool.

The Learning Environment

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Additional information about the course

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Contact the instructor : [email protected]

The Landing Page of the Online instructor-led course for beginners by Logosent on Edureka :

www.edureka.co/vlsi-digital-design

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Course Contents: The Knowledge packs

RTL Coding, Simulation and Synthesis– Key considerations of RTL code implementation.

– Verilog examples and warm-up exercises.

– Simulations using ModelSim.

– Synthesis using TSMC018 standard cell library and gate-netlist analysis using Schematic Viewer.

Critical design elements and related important design considerations– Clocks : Overview, setup/hold, clock-tree, clock-gating and other special considerations.

– Synchronization.

– Resets.

– Interface Buses and typical sideband signals.

– Finite State Machine (FSM).

Power Management – Overview of the driving needs and techniques.

– Basic design elements used to implement power management.

Power-Performance-Area (PPA) Trade-offs – Typical knobs

Design for Test and Manufacturability (DFTM) – Various tests and scan operation

Various ASIC Development Flows – Overview– Typical IP Development Cycle.

– Typical SOC Development Cycle.

– Gate Netlist generation Flows.

– Physical Design Implementation Flows – High level overview.

– Silicon manufacturing and packaging - High level overview.

AMBA APB and AXI4-Lite Bus Interfaces – Detailed analysis


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Course Contents: The hands-on labs.

1. LINUX environment familiarization.– Basic LINUX commands, directory structures

– ‘vi’ editor quick ramp

– Bring-up sample simulations using (a) Icarus Verilog and (b) ModelSim

2. SystemVerilog Primer labs (Details in next slide).– Thorough review of all commonly used System-Verilog constructs using 11 example codes.

– Simulation of each example and review/analysis of the waveforms.

3. Familiarization with Perl coding.– Understand the basic constructs and design-automation example using Perl.

– Experimental edits of a Perl code that generates Verilog RTL configurations.

4. Moore and Mealy FSM examples.

5. Synthesis and gate-netlist analysis of simple designs.– Quick synthesis of couple of small designs using tsmc018 standard cell library.

– Bring-up the gate netlists in an open source schematic viewer, analyze the logic mapping.

6. Instructor guided hierarchical implementation of a shift-pattern detect design, with a counter triggered on pattern detect.– The design uses multiple clock domains, synchronization and Verilog parameters.

7. Design and implementation of a PWM IP using AMBA-APB MMR interface. - The design will be implemented hierarchically so that it can be easily upgraded to other MMR

programming bus interfaces and more PWM functionality can be added for advanced learning.


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Course Contents: SystemVerilog Primer Labs

The SystemVerilog Primer Labs are provided with the intent of helping the trainees get thorough with the most commonly used language constructs and also enable the usage of lab examples as a reference during upcoming coding exercises or projects.

There are 11 specially designed examples included in the Lab, each covering the following aspects:

0. File operation, VCD waveform dump, ‘for’ loops and STD-IO.

1. Behavioral and Structural RTL.

2. Blocking and Non-Blocking assignments.

3. Signal drive strengths in SystemVerilog.

4. Usage of ‘function’, ‘case’, ‘if’ and conditional assignments.

5. An exhaustive list and functionality of SystemVerilog Operators.

6. Usage of ‘forever’, ‘repeat’ and ‘while’ loop constructs.

7. User Defined Primitives (UDP).

8. Usage of ‘task’.

9. Configurable SystemVerilog code using ‘parameters’.

10. Compiler directives.


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Tony Thomas E ( [email protected] )27 October, 2015


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Thank You&Good Luck!

27 October, 2015



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