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Introduction to Digital VLSI Design

ספרתיVLSIמבוא לתכנון

Introduction

Lecturer: Gil RahavSemester B’, EE Dept. BGU.Freescale Semiconductors Israel

24.01.2007Introduction to Digital VLSIGil Rahav

2

IC Products

� Processors� CPU, DSP, Controllers

� Memory chips� RAM, ROM, EEPROM

� Analog� Mobile communication,

audio/video processing

� Programmable� PLA, FPGA

� Embedded systems� Used in cars, factories� Network cards

� System-on-chip (SoC)


3

Why VLSI?

� Integration improves the design:� lower parasitics = higher speed;

� lower power;� physically smaller.

� Integration reduces manufacturing cost-(almost) no manual assembly.


4

Why build integrated Circuit?

� IC Technology drives the whole innovative devices and systems which effects the way we live.� ICs are much smaller.

� Consume less power than discrete component.� Easier to design and manufacture.

� More reliable than discrete system.

� Can design more complex system.

� The growth of electronic industry.


5

Example of VLSI application

� Electronic system in cars.

� Digital electronics control VCRs

� Transaction processing system, ATM

� Personal computers and Workstations

� Medical electronic systems.

� etc….


6

The advantageous of digital ICs over the discrete components (1/2)

� Size� much smaller both transistor and wires.

� leads to smaller parasitic resistances, capacitances and inductances

� Speed� communication within the chips are much faster than between a chips

on PCB (Printed Circuit Board).

� High speed of circuits on-chip due to smaller size.


7

The advantageous of digital ICs over the discrete components (2/2)

� Power Consumption

� Logic operation within the chip consumes

much less power.

� smaller size -> smaller parasitic

capacitances and resistance -> require less

power to drive the circuit.


8

Advantages of IC at System Level(1/2)

� Smaller Physical Size

� can make a small electronic appliances. ie. portableTV, handheld cellular telephone…

� Lower Power Consumption

� reduce total power consumption on a whole electronic circuit.

� Cheaper power supply which leads to a simpler cabinet for power supply. Less heat, Fan may no longer be necessary.


9

Advantages of IC at System Level(2/2)Advantages of IC at System LAdvantages of IC at System L eevelvel (2/2)(2/2)

� Reduce Cost

� Reducing in number of components.

� Power Supply requirement.

� Cabinets

� The cost of building a whole system is reduce eventhough Ics cost

more.


10

Cost factors in ICs

� For large-volume ICs:� packaging is largest cost;

� testing is second-largest cost.

� For low-volume ICs, design costs may swamp all manufacturing costs.


11

Integrated Circuit Manufacturing

Technology� Let us build a system faster, and more complex system

Economics� In 1960s,Gordon Moore said that the number of transistor would grow

exponentially. The number of transistors per chip has doubled about once a year.

� IC plant is very expensive. $2-3billion or more.� Is it worth to invest in IC business?


12

• In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months (i.e., grow exponentially with time).

• Amazing visionary – million transistor/chip barrier was crossed in the 1980’s.

– 2300 transistors, 1 MHz clock (Intel 4004) - 1971

– 42 Million, 2 GHz clock (Intel P4) - 2001

– 140 Million transistor (HP PA-8500)

Moore’s Law

Source: Intel web page (www.intel.com)


13

Die Size Growth

40048008

80808085

8086286

386486 Pentium ® proc

P6

1

10

100

1970 1980 1990 2000 2010

Year

Die

siz

e (m

m)

~7% growth per year

~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law


14

Clock Frequency

Lead microprocessors frequency doubles every 2 yearsLead microprocessors frequency doubles every 2 years

P6

Pentium ® proc486

38628680868085

8080

80084004

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Fre

quen

cy (

Mhz

)

2X every 2 years


15

Challenges in VLSI design

� Multiple levels of abstraction: transistors to CPUs.� Multiple and conflicting constraints: low cost and high

performance are often at odds.� Short design time: Late products are often irrelevant.


16

Jobs in VLSI

� Layout designers� Circuit designers� Architects� Test engineers� Fabrication engineers� System designers� CAD tool programmers


17

The VLSI design process� May be part of larger product design.� Major levels of abstraction:

� specification;� architecture;� logic design;� circuit design;� layout.


18

Design Abstraction Levels


19

VLSI Levels of Abstraction

Specification(what the chip does, inputs/outputs)

Architecturemajor resources, connections

Register-Transferlogic blocks, FSMs, connections

Circuittransistors, parasitics, connections

Layoutmask layers, polygons

Logicgates, flip-flops, latches, connections


20

Dealing with complexity

� Divide-and-conquer: limit the number of components yo u deal with at any one time.

� Group several components into larger components:� transistors form gates;

� gates form functional units;

� functional units form processing elements;� etc.


21

Hierarchical name

� Interior view of a component:� components and wires that make it up.

� Exterior view of a component = type:� body;

� pins.

Fulladder

a

bcin

sum

cout


22

Instantiating component types

� Each instance has its own name:� add1 (type full adder)

� add2 (type full adder).

� Each instance is a separate copy of the type:

Add1(Fulladder)

a

bcin

sum

cout

Add2(Fulladder)

a

bcin

sum

Add1.a Add2.a


23

A hierarchical logic design

z

box1 box2 x


24

Net lists and component lists

� Net list:net1: top.in1 in1.in

net2: i1.out xxx.B

topin1: top.n1 xxx.xin1topin2: top.n2 xxx.xin2

botin1: top.n3 xxx.xin3

net3: xxx.out i2.inoutnet: i2.out top.out

� Component list:top: in1=net1 n1=topin1 n2=topin2

n3=botin1 out=outneti1: in=net1 out=net2

xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3

i2: in=net3 out=outnet


25

Component hierarchy

top

i1 xxx i2


26

Hierarchical names

� Typical hierarchical name:� top/i1.foo

component pin


27

Transistor schematic

D Q'

φ

φ'

+


28

Mixed schematic

D Q'

φ

φ'

inverter


29

Levels of abstraction

� Specification: function, cost, etc.� Architecture: large blocks.� Logic: gates + registers.� Circuits: transistor sizes for speed, power.� Layout: determines parasitics.


30

Circuit abstraction

� Continuous voltages and time:

+

t

v

t

v


31

Digital abstraction

� Discrete levels, discrete time:

fulladder

cout

cin

sum

a

b

fulladder

cout

cin

sum

a

b

t

a

t

b

t

a

t

b

t

sum

t

sum


32

Register-transfer abstraction

� Abstract components, abstract data types:

+

+

0010

0001

0100

0011


33

Register-transfer abstraction

� Abstract components, abstract data types:

+

+

0010

0001

0100

0111


34

Top-down vs. bottom-up design

� Top-down design adds functional detail.� Create lower levels of abstraction from upper levels.

� Bottom-up design creates abstractions from low-level behavior.

� Good design needs both top-down and bottom-up effort s.


35

Design abstractions

specification

behavior

register-transfer

logic

circuit

layout

English

Executableprogram

Sequentialmachines

Logic gates

transistors

rectangles

Throughput,design time

Function units,clock cycles

Literals, logic depth

nanoseconds

microns


36

Design validation� Must check at every step that errors haven’t been intro duced-

the longer an error remains, the more expensive it becom es to remove it.

� Forward checking: compare results of less- and more-abstract stages.

� Back annotation: copy performance numbers to earlier stages.


37

Manufacturing test

� Not the same as design validation: just because the design is right doesn’t mean that every chip coming off the li ne will be right.

� Must quickly check whether manufacturing defects dest roy function of chip.

� Must also speed-grade.

38

VLSI Design Cycle


39

IC Design Steps

SpecificationsSpecifications High-levelDescription

High-levelDescription

FunctionalDescription


BehavioralHDL, C

StructuralHDL


40

PackagingPackagingPackagingPackaging FabriFabriFabriFabri----cationcationcationcation

PhysicalPhysicalPhysicalPhysicalDesignDesignDesignDesign

TechnologyTechnologyTechnologyTechnologyMappingMappingMappingMapping

SynthesisSynthesisSynthesisSynthesis

IC Design Steps (cont.)

SpecificationsSpecifications High-levelDescription

High-levelDescription



Placed& RoutedDesign

Placed& RoutedDesign

X=(AB*CD)+(A+D)+(A(B+C))

Y = (A(B+C)+AC+D+A(BC+D))

Figs. [©Sherwani]

Gate-levelDesign

Gate-levelDesign

LogicDescription

LogicDescription


41

VLSI Design Cycle (2/9)

System Specification – Specification of the size, speed, power and functionality of the VLSI system.

Architectural Design – Decisions on the architecture, e.g., RISC/CISC, # of ALU’s, pipeline structure, cache size , etc. Such decisions can provide an accurate estimation of the system performance, die size, power consumption, etc.


42


Functional Design – Identify main functional units and their interconnections. No details of implementation.


43


Logic Design – Design the logic, e.g., boolean expressions, control flow, word width, register allocati on, etc. The outcome is called an RTL ( Register Transfer Level) description. RTL is expressed in a HDL ( Hardware Description Language), e.g., VHDL and Verilog.

X = (AB+CD)(E+F)Y= (A(B+C) + Z + D)


44


Circuit Design – Design the circuit including gates, transistors, interconnections, etc. The outcome is called a netlist.


45


� Net list:net1: top.in1 in1.in

net2: i1.out xxx.B

topin1: top.n1 xxx.xin1topin2: top.n2 xxx.xin2

botin1: top.n3 xxx.xin3

net3: xxx.out i2.inoutnet: i2.out top.out

� Component list:top: in1=net1 n1=topin1 n2=topin2

n3=botin1 out=outneti1: in=net1 out=net2

xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3

i2: in=net3 out=outnet


46


top

i1 xxx i2

Component hierarchy


47


Physical Design – Convert the netlist into a geometric representation. The outcome is called a layout.


48


Fabrication – Process includes lithography, polishing, deposition, diffusion, etc., to produce a chip.

Packaging – Put together the chips on a PCB ( Printed Circuit Board) or an MCM ( Multi-Chip Module)


49

VLSI Design Cycle

System Specification

ArchitecturalSpecification

RTL in HDL

Netlist

Layout

Timing & relationshipbetween functional units

Chips

Packaged andtested chips

ArchitecturalDesign

FunctionalDesign

LogicDesign

PhysicalDesign

Fabrication

Packaging

Circuit Designor

Logic Synthesis


50

Physical Design Cycle (1/6)

Circuit Partitioning

Floorplanning & Placement

Routing

Layout Compaction

Extraction and Verification

Clock Tree


51


Circuit Partitioning – Partition a large circuit into sub-circuits (called blocks). Factors like #blocks, block sizes, interconnection between blocks, etc., are considered.

�

�

�


52


Floorplanning – Set up a plan for a good layout. Place the modules (modules can be blocks, functional units, e tc.) at an early stage when details like shape, area, I/O pin pos itions of the modules, …, are not yet fixed.

Deadspace


53


Placement – Exact placement of the modules (modules can be gates, standard cells, etc.) when details of the mod ule design are known. The goal is to minimize the delay, total area and interconnect cost.

v

Feedthrough

Standard cell type 1

Standard cell type 2


54


Routing – Complete the interconnections between modules. Factors like critical path, clock skew, wire spacing, etc., are considered. Include global routing and detailed routing.

v

Feedthrough

Type 1 standard cel1

Type 2 standard cell


55


Compaction – Compress the layout from all directions to minimize the total chip area.

Verification – Check the correctness of the layout. Include DRC (Design Rule Checking), circuit extraction (generate a circuit from the layout to compare with the original netlist), performance verification (extract geometric information to compute resistance, capacitance, delay, etc.)


56

Design Styles

� Full-Custom ASICs� Some (possibly all) logic cells are customized and

all mask layers are customized

� Semicustom ASICs� All logic cells are predesigned (defined in cell library) and some

(possibly all) of the mask layers are customized� Types:

Standard-cell based and Gate-array-based ASICs� Programmable ASICs

� All logic cells are predesigned and none of the mask layers are customized

� Types: PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array)


57

Full-custom ASICs (1/3)

� Engineers design some or all of the logic cells, circu its, or layout specifically for one ASIC� Full-custom ICs are the most expensive

to manufacture and to design� Manufacturing lead time (the time it takes just to make an IC – not

including design time) is typically 8 weeks


58

Full-custom ASICs (2/3)

� When does it make sense?� there are no suitable existing cell libraries available

� existing logic cells are not fast enough

� logic cells are not small enough� logic cells consume too much power

� ASIC is so specialized that some circuits must be custom designed

� Trends: fewer and fewer full-custom ICs are being d esigned (excluding mixed analog/digital ASICs)


59

Full Custom Design (3/3)


60

Standard-Cell-Based ASICs (1/5)

� Cell-Based ASIC (CBIC) uses pre-designed cells (AND, OR gates, multiplexers, flip-flops, ...)

� Standard-cell areas are built of rows of standard c ells� Standard-cell areas can be used in combination with larger pre-

designed cells (microcontrollers, or even microproc essors), known as megacells

A cell-based ASIC (CBIC) die with a single standard-cell area combined with 4 fixed blocks


61

Standard-Cell-Based ASICs(2/5)

� Characteristics� custom blocks can be embedded;

ASIC designer defines only the placement of the standard cells and the interconnect in a CBIC

� standard cells can be placed anywhere on a silicon =>all mask layers of a CBIC are customized

� manufacturing lead time is 8 weeks


62


� Advantages� designers save time, money, and reduce risks using a predesigned,

pretested, and precharacterized standard-cell library� standard cells in the library are constructed using full-custom;

each standard cell can be optimized individually(for example, to maximize speed, minimize area, etc);

� Disadvantages� time or expense of designing or buying the standard-cell library� time needed to fabricate all layers of the ASIC for each new design


63

Standard-Cell-Based ASICs(4/5)

� Standard-cells are designed to fit horizontally together to form rows

� Internal construction of a cell

- 25 microns wide (lambda is 0.25)- AB: abutment box - BB: bounding box- Power supplies: VDD, GND- Each different shaded and labeled pattern represents a different layer- Connections: A1, B1, Z


64


� Routing the CBIC

- Interconnections between cells use spaces (called channels) between rows - 2 separate layers of metal interconnect (metal1 and metal2) running at right angles to each other- Feedthrough: refers either to the piece of metal that is used to pass a signal through a cell or to a space in a cell waiting to be used as a feedthrough


65

Programmable Logic Devices(1/2)

� PLDs� standard ICs, available in standard configurations

� sold in high volume to many different customers� PLDs may be configured or programmed to create

a part customized to specific application

� Characteristics� no customized mask layers or logic cells� fast design turnaround

� a single large block of programmable interconnect

� a matrix of logic macrocells that usually consists of programmable array logic followed by a flip-flop or latch


66

Programmable Logic Devices(2/2)

� Types of PLDs� PROM: uses metal fuse that can be blown permanently)� EPROM: used programmable MOS transistors whose characteristics are altering by

applying a high voltage

� PAL – Programmable Array Logic • programmable AND logic array or AND plane,

and fixed OR plane� PLA – Programmable Logic Array

• programmable AND plane followed by programmable OR plane

� Depending on how the PLD is programmed� erasable PLD (EPLD)� mask-programmed PLD


67

Field-Programmable Gate Arrays (FPGA)

� FPGA� a step above the PLD in complexity;

it is usually larger and more complex than a PLD� rapidly growing in importance

� Characteristics� none of mask layers are customized� a method for programming basic cells

and the interconnect� the core is regular array

of programmable basic logic cells (combinational + sequential)

� a matrix of programmable interconnectthat surrounds the basic cells

� programmable I/O cells around the core� design turnaround is a few hours


68

Digital Logic Circuit Definitions

PLDProgrammable Logic Devices

SPLD HCPLD

FPGACPLD

PLA PAL

Simple PLD High Capacity PLD

Programmable Logic Array Programmable Array Logic

Complex PLD Field Programmable Gate Array


69

Cell development (Analog/digital)

� Schematic entry (transistor symbols)� Analog simulation (SPICE models)� Layout (layer definitions)� Design Rule Checking, DRC ( design rules)� Extraction (extraction rules and parameters)� Electrical Rule Checking, ERC (ERC rules)� Layout Versus Schematic, LVS ( LVS rules)� Analog simulation.� Characterization: delay, setup, hold, loading sensiti vity,etc.� Generation of digital simulation model with back anno tation.� Generation of synthesis model� Generation of “black-box” for place & route


70

Digital design

� Behavioral simulation� Synthesis (synthesis models)� Gate level simulation (gate models)� Floor planning� Loading estimation (loading estimation model)� Simulation/timing verification with estimated back-a nnotation� Place and route (place and route rules)� Design Rule Check, DRC (DRC rules)� Loading extraction (rules and parameters)� Simulation/ timing verification with real back-annotation� Design export� Testing: Test generation, Fault simulation, Vector translation


71

Design entry

� Layout� Drawing geometrical shapes: Defines layout hierarchy

Defines layer masksRequires detailed knowledge about CMOS technologyRequires detailed knowledge about design rules (hundreds of rules)Requires detailed knowledge about circuit designSlow and tediousOptimum performance can be obtained


72

� Schematic� Drawing electrical circuit: Defines electrical hierarchy

Defines electrical connectionsDefines circuit: transistors, resistors,,,

Requires good circuit design knowledge for analog designRequires good logic design knowledge for digital design (boolean logic, state machines)Gives good overview of design hierarchySignificant amount of time used for manual optimization

Transistor level Gate level Module level


73

� Behavioral + Synthesis� Writing behavior (text): Defines behavioral hierarchy

Defines algorithmDefines architecture

� Synthesis tool required to map into gates

� Often integrated with graphical block diagram tool.

always @(posedge clk)beginif (set) coarse <= #(test.ff_delay) offset;else if (coarse == count_roll_over)

coarse <= #(test.ff_delay) 0;else coarse <= #(test.ff_delay) coarse + 1;end

module add_and_mult( a,b,c, out)input[31:0] a,b,c;output[31:0] out;wire[31:0] internal_add;

adder32 add1(a,b, internal_add);multiplier32 mult1( internal_add, c, out);endmodule

assign #(test.logic_delay)bsr_clk = ~(m_extest | m_sample | m_intest) | clk_dr, bsr_shift = (m_extest | m_sample | m_intest) & shift_dr,;


74

Verification

� Design Rule Check (DRC):Checks geometrical shapes: width, length, spacing, overlap, etc.

� Electrical rule check (ERC):Checks electrical circuit: unconnected inputs

shorted outputscorrect power and ground connection

� Extraction:Extracts electrical circuit: transistors, connections, capacitance,

resistance

� Layout versus schematic (LVS):Compares electrical circuits: transistors: parallel or serial(schematic and extracted layout)

a

b

IN Out

Vdd

Gnd

10 10 10 10 10 10 40

EXT LVS

?


75

Simulation

� Simulates behavior of designed circuit� Input: Models (transistor, gates, macro)

Textual netlist (schematic, extracted layout, behavioral) User defined stimulus

� Output: Circuit response (waveforms, patterns), Warnings

� Transistor level simulation using analog simulator ( SPICE)� Time domain� Frequency domain� Noise

� Gate level simulation using digital simulator� Logic functionality� Timing: Operating frequency, delay, setup & hold violations

Timing calculator needed to calculate delays from extracted parameters

� Behavioral simulation� System and IC definition ( algorithm, architecture )� Partitioning� Complexity estimation

Normally samesimulator


76

Gate level models

� Border between transistor domain (analog) and digital domain

� Digital gate level models introduced to speed up digital simulation.

� Gate level model contains:� Logic behavior� Delays depending on: operating conditions, process, loading,

signal slew rates� Setup and hold timing violation checks

� Gate level model parameters extracted from transistor level simulations and characterization of real gates.


77

Place and Route

� Generates final chip from gate level netlist� Goals: Minimum chip size

Maximum chip speed.

� Placement:� Placing all gates to minimize distance between connected gates

• Floor planning tool using design hierarchy

• Specialized algorithms ( min cut, simulated annealing, etc.)• Timing driven

• Manual intervention

� Very compute intensiveHierarchy based floor planning

Simulated annealing

High temperature:move gates randomly

Low temperature:Move gates locally

Min cut

Keep cutting designinto equal sized pieces

For each cut:Move gates arounduntil minimum connectionacross cut


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� Routing:� Channel based: Routing only in channels between gates

(few metal layers: 2)

� Channel less: Routing over gates(many metal layers: 3 - 6)

� Often split in two steps:• Global route: Find a coarse route depending on local routing

density• Detailed route: Generate routing layout

Channel based Channel less


79

� Performance of sub-micron CMOS IC’s are to a large exte nt determined by place & route.� Loading delays bigger than intrinsic gate delays

� Wire R-C delays becomes important in sub-micron� Clock distribution over complete chip gets critical at operating

frequencies above 100Mhz.Number of wires

Wire length

Local connections

Global connections

Delay

Technology1.0u 0.5u 0.25u 0.1u

25ps

50ps

100ps

200ps

Gate delay

Wire load delay


80

Design tool framework

� Design tools from one vendor normally integrated into a framework which enables tools to exchange data.� Common data base

� Automatic translation from one type to another� (Allows third part tools to be integrated into framework)

� Few standards to allow transport of designs between tools from different vendors.� VHDL and Verilog behavioral models and netlists

� EDIF netlist, SPICE netlist for analog simulation

� GDSII layout� Standard Delay Format (SDF) for gate delays.

� Small vendors must be compatible with large vendors.

Transporting designs between tools from different vendors may cause problems


81

Hardware describing languages (HDL)

� Describe behavior not implementation� Make model independent of technology� Model complete systems� Specification of sub-module functions� Speed up simulation of large systems� Standardized text format� CAE tool independent


82

� VHDL� Very High speed integrated circuit Description Language

� Initiated by American department of defense as a specification language.

� Standardized by IEEE

� Verilog� First real commercial HDL language from gateway automation (now

Cadence)

� Default standard among chip designers for many years

� Until a few years ago, proprietary language of Cadence.� Now also a IEEE standard because of severe competition from

VHDL. Result: multiple vendors


83

� Compiled/Interpreted � Compiled:

• Description compiled into C and then into binary or directly into binary

• Fast execution• Slow compilation

� Interpreted:• Description interpreted at run time

• Slow execution• Fast “compilation”

• Many interactive features

� VHDL normally compiled� Verilog exists in both interpreted and compiled versions


84

HDL design entry

� Text:� Tool independent

� Good for describing algorithms

� Bad for getting an overview of a large design


85

� Add-on tools� Block diagrams to get overview of hierarchy� Graphical description of final state machines (FSM)

• Generates synthesizable HDL code� Flowcharts� Language sensitive editors� Waveform display tools

From Visual HDL, Summit design


86

Synthesis and Technology dependence

Algorithm

Architecture

Register level

Gate level

Logic synthesis

Behavioral synthesis

For i = 0 ; i = 15sum = sum + data[I]

Data[0]

Data[15]

i

Sum

Data[0] Data[15]

Sum

MEM

Clock

Clearaddress

Clearsum

0% technology dependent





87

Logic synthesis

� HDL compilation (from VHDL or Verilog)� Registers: Where storage is required

� Logic: Boolean equations, if-then-else, case, etc.

� Logic optimization� Logic minimization (similar to Karnaugh maps)� Finds logic sharing between equations

� Maps into gates available in given technology

� Uses local optimization rules6 basic CMOS gates

3 basic CMOS gates

3 logic gates


88

� Timing optimization� Estimate loading of wires

� Defined timing constraints (clock frequency, delay, etc.)� Perform transformations until all constraints fulfilled

Arriving lateArriving late

Arriving late

Complexlogic

Complexlogic

Complexlogic

0

1

Arriving late

0

1


89

Synthesis goals

� Combined timing - size optimization� Smallest circuit complying to all timing constraints

Size

Delay

Design space

Requirements

� Best solution found as a combination of special optimization algorithms and evaluation of many alternative solutions(Similar to simulated annealing)


90

� Problems in synthesis� Dealing with “single late signal”

� Mapping into complex library elements(special directives required)

� Regular data path structures:• Adders: ripple carry, carry look ahead, carry select,etc.

• Multipliers, etc.

Use special guidance to select special adders, multipliers, etc..

Performance of sub-micron technologies are dominated by wiring delays (wire capacitance + R-C delays)

� Synthesis in many cases does a better job than a man ually optimized logic design.

(in much shorter time)


91

Timing estimation in synthesis

� Wire loadingTiming optimization is based on a wire loading model.

Loading of gate = input capacitance of following gates + wire capacitance

Gate loading known by synthesizer

Wire loading must be estimatedR-C delay calculation very complicated

Wire capacitance

Relative number

Large chipSmall chip

Average Average

Delay

Technology1.0u 0.5u 0.25u 0.1u

25ps

50ps

100ps

200ps

Gate delay

Wire load delay


92

� Estimate wire capacitance from number of gates connec ted to wire.

Small chip

Large chip

Number of gates per wire

Wire capacitance

Advantage: Simple modelDisadvantage: Bad estimate of long wires

(which limits circuit performance)


93

� Estimate using floor plan

Inside local region:Estimate as function of numberof gates and size of region

Between regions:Use estimate of physical distancebetween routing regions.

Region 1

Region 2

Region 3

Advantage: Realistic estimateDisadvantage: Synthesizer most work with complete design

In sub-micro CMOS technologies Synthesis and Place & Route must work hand in hand


94

Trends in synthesis

� Integration of synthesis and P&R� Synthesizable standard modules (Processor, PCI

interface, Digital filters, etc.)� Automatic insertion of scan path for production

testing.� Synthesis for low power� Synthesis of self-timed circuits (asynchronous)� Behavioral synthesis� Formal verification


95

Technology Trends

� Processor� Logic capacity increases ~ 30% per year

� Clock frequency increases ~ 20% per year� Cost per function decreases ~20% per year

� Memory� DRAM capacity: increases ~ 60% per year

(4x every 3 years)

� Speed: increases ~ 10% per year� Cost per bit: decreases ~25% per year


96

These trends have brought many changes and new challenges to circuit design.


97

Complicated Design

� Too many transistors and no way to handle them manual ly.� Solutions:

� CAD� Hierarchical design� Design re-use


98

Power and Noise

� Huge power consumption and heat dissipation becomes a problem

� Noise and cross talk.� Solutions:

� Better physical design


99

Interconnect Area

� Too many interconnects� Solutions:

� More interconnect layers (made possible by Chemical-Mechanical Polishing)

� CAD tools for 3-D routing


100

Interconnect Delay

� Interconnect delay becomes a dominating factor in circ uit performance

� Solutions:� Use copper wire� Interconnect optimization in physical design, e.g., wire sizing,

buffer insertion, buffer sizing.


101

The Process of Design

DesignInitial concept: what is the function performed by the object?Constraints: How fast? How much area? How much co st?Refine abstract functional blocks into more concret e realizations

Implementation

Assemble primitives into more complex building bloc ksComposition via wiringChoose among alternatives to improve the design

DebugFaulty systems: design flaws, composition flaws, co mponent flawsDesign to make debugging easierHypothesis formation and troubleshooting skills

Implementation

Design

Debug

introduction to digital vlsi design - bgudigivlsi/slides/introduction_1_1.pdf · 1 introduction to...

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