vlsi design lab phase noise in phase-locked loop circuits ashok srivastava department of electrical...

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PHASE NOISE IN PHASE-LOCKED LOOP CIRCUITS

Ashok Srivastava

Department of Electrical and Computer EngineeringSchool of Electrical Engineering & Computer Science

Louisiana State University, Baton Rouge, LA

Email: [email protected]: http://www.ece.lsu.edu/ashok/index.html

2012 Southeast Symposium on Contemporary Engineering Topics The 3rd SSCET, 31 August 2012 New Orleans, Louisiana

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Outline of Presentation Introduction

• Phase-Locked Loop (PLL) building blocks

• Phase noise and jitter

• Goals and objectives

Experimental study of phase noise in CMOS PLL

• Circuit design

• Phase noise superposition

Switchable PLL design with phase noise and jitter tests

• Design

• Analysis

• Experimental results

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Outline of Presentation Low power phase-locked loop with LC voltage-controlled oscillator

• Design

• Layout and simulation

• Experiment Results

Conclusion

References

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P F D /C PL o o pF ilte r

V C O

D iv id e r

Input O utput

+-

F e e dba c k

Phase/Frequency Detector (PFD)

Charge Pump (CP)

Loop Filter (LF)

Voltage-Controlled Oscillator (VCO)

Frequency Divider (FD)

Introduction – PLL Building Blocks

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PFD

The PFD built by two D-flip-flops and one NAND gate


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PFD outputs with same frequency inputs

PFD outputs different frequency inputs


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Charge Pump & Loop Filter

C 1

V C TR L

C 2

R

IC P

IC P

S 1

S 2

V D D

L o o p F ilte r

C P

R is to improve the stability.

C2 is to prevent the voltage jumps on the control voltage.

Transfer function: 1

1)(

sC

ssF

1RC neglecting C2

Resulting in a first order loop filter


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REF leading–UP high–Charge C1–VCTRL increase


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•VCO Feedback leading–DN high–Discharge C1–VCTRL decrease


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Current Starved Single-ended Voltage Control Oscillator

DDL

D

frO VCn

I

ttnf

)(

1


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Phase noise (frequency domain) - A signal’s short-term instabilities are usually characterized in terms of the single sideband noise spectral density. It is expressed in decibel below the carrier per hertz (dBc/Hz) and is defined as

carrier

noisetotal P

HzffPfL

)1,(log10 0

)1,( 0 HzffPnoise is the sideband noise power at offset frequency, ffrom the carrier frequency .0f

Introduction – Phase Noise and Jitter

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f

f0 f0 f

Oscillator power spectrum with phase noise

Phase noise - the ratio of the area of the rectangle with 1-Hz bandwidth at offset Δf to the total area, approximately the difference in the height


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Jitter and phase noise are different ways to express the same phenomenon. Phase noise is the uncertainty of the waveform in the frequency domain and jitter is characterization in time domain of the PLL output. Jitter is the deviation of a waveform transition from its ideal position.

(1) The cycle jitter: TTT ncn

Tn is the time of the nth cycle of the output waveform, and is the average period.

T

(2) The cycle-to-cycle jitter: nnccn TTT 1

(3) The accumulated jitter:

N

nnacc TTT

1

)(


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where N is the N th cycle of the waveform. This accumulated jitter is characterized and increased by time interval, ΔT, which is the time difference between the reference and the observed transitions during the measurement.

The RMS (root mean-squared) jitter, which is the value of one standard deviation of the normal distribution, is more useful because this value changes not much as the number of samples increases.

3rd 3rd


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Introduction – Goals and Objectives

Develop a comprehensive phase noise model of PLL

Compare the modeled phase noise results with the corresponding experimentally measured results on a phase-locked loop chip fabricated in 0.5 m n-well CMOS process.

Design a programmable PLL frequency synthesizer. The frequency synthesizer is implemented by LC VCO and a low power dual-modulus prescaler.

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PHASE NOISE STUDY IN CMOS PLL

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P F (s )

1 /N

o u t(s )K V

s

nv co(s )

nd(s )

npfdcp(s ) n lf(s )n in pu t(s )

Phase Noise in PLL

Each of the noise sources is shaped by the loop transfer function from the corresponding noise voltage source to the output phase. The PLL open loop transfer function is . The PLL closed loop transfer function is

21221

1 )1()(

sCRCsCsC

sRCsF

( ) ( ) /CP vG s I F s K s ( )

( )1 ( ) /

G sH s

G s N

Noise sources in a second order PLL

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VCO: The closed loop transfer function of the VCO phase noise can be calculated using the noise transfer function from to , which is given by,

The power spectral density of the output phase noise can be obtained as follows,

Phase Noise in PLL

)(snvco )(sout

( ) 1 1

( ) 1 ( ) ( ) 1 (2 / ) (1/ ) ( )out

vco vco vco v p

s

n s G s H s K s N K F s

2

2

)(

)()()(

jn

jSS

vco

out

inVCOoutVCO

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Input Reference: Assuming a noisy input signal, the response of the loop to the phase variations in the input can be evaluated using a similar method. For the PLL under consideration, the input noise transfer function is given by,

The closed loop phase noise power spectrum of input reference phase noise is given by,

Phase Noise in PLL

(2 / ) ( )( ) ( )

( ) 1 ( ) ( ) 1 (2 / ) (1/ ) ( )v pout in

input in in v p

K s K F ss G s


2

2

)(

)()()(

jn

jSS

input

out

inINPUToutINPUT

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Divider: The additive noise is injected at the input of the PFD and share the same transfer function as the noise at the input terminal. Similarly, the noise transfer function for divider can be described as follows,

and,

Phase Noise in PLL

(2 / ) ( )( ) ( )

( ) 1 ( ) ( ) 1 (2 / ) (1/ ) ( )v pout d

d d d v p

K s K F ss G s


2

2

)(

)()()(

jn

jSS

d

out

inDoutD

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PFD: noise model for PFD can be expressed by the following equations,

and,

Loop filter: Noise model for the loop filter can also be described by the following equations,

Phase Noise in PLL

( )( ) (2 / ) ( )

( ) 1 ( ) ( ) 1 (2 / ) (1/ ) ( )pfdcpout v

pfdcp pfdcp pfdcp v p

G sI s K s F s


2

2

)(

)()()(

jn

jSS

pfdcp

out

inPFDCPoutPFDCP

( )( ) (2 / )

( ) 1 ( ) ( ) 1 (2 / ) (1/ ) ( )lfout v

lf lf lf v p

G sV s K s


2

2

)(

)()()(

jn

jSS

lf

out

inLFoutLF

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Total PLL Phase Noise (Superposition)

Phase Noise in PLL

• Phase noise caused by components are evaluated separately.

• Total phase noise is the sum of them.

• There is a peak in the spectrum at loop bandwidth frequency.

• Phase noise at low offset is dominated by input noise.

• Phase noise at high offset is dominated by VCO noise.

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EXPERIMENTAL STUDY OF PHASE NOISE IN CMOS PLL

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PLL Experimental Study – Circuit Design

8N

AICP 30

kR 5.41

pFC 3.431

fFC 1002

C 1

V C TR L

C 2

R

IC P

IC P

S 1

S 2

U P

D N

V D D = 5 V

L o o p F ilte r

P F D

in

f e e dba ck

C P

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PFD circuit, layout and simulation result:

Buffers

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Charge Pump circuit, layout:

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1/8 Frequency Divider circuit and layout:

Transmission gate D-flip-flop

A very small and simple design

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The differential VCO circuit and layout with biasing:

V D D

V B i as

In_ a In_ bM 1 M 2

M 3 M 4

O utput_ aO utput_ b

2.1/1 .2 2.1/1 .2

9.6/1 .2 9.6/1 .2

80/2

O utput_ a

O utput_ b

In_ a

In_ b

+

- +

- +

- +

- +

- +

- +

- +

-

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The PLL chip layout with differential VCO.

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RF test board with mounted PLL chip

SMA connecting cables which provide repeatable electrical performance with low noise injection to the chip are used in this measurement.

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PLL Experimental Study – Phase Noise Superposition

PLL with Differential VCO Phase Noise Study

The gain of the VCO is 30 MHz/V measured at 80 MHz. The free running frequency of the VCO is .

0.5 1 1.5 2 2.5 3 3.5 4 4.5 540

50

60

70

80

90

100

110

120

130

140

Bias Voltage (V)

Osc

illat

ion

Fre

quen

cy (

MH

z)The tuning range of differential VCO.

ctrlVVKff 0

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The open loop VCO has two pins: bias voltage and VCO output. Bias voltage pin is connected to a dc 1.9V and the output frequency is 80 MHz. The open loop means that only the VCO is working in this case and it is outside the PLL.



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Experimental results of input reference clock phase noise at 80 MHz PLL output frequency. The experimentally measured phase noise is between -70 to -103 dBc/Hz from 10 kHz to 10 MHz offset frequency at 10 MHz center frequency.



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The experimentally measured divider open loop SSB phase noise at 80 MHz PLL output frequency.

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The experimentally measured PFD/CP open loop SSB phase noise at 80 MHz PLL output frequency.

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The experimentally measured loop filter open loop SSB phase noise at 80 MHz PLL output frequency.

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The PLL output phase noise is obtained by the superposition of the noises spectra from VCO, input reference, divider, PFD and loop filter. There is a peak observed in VCO closed loop phase noise when the offset frequency is near the predicted loop bandwidth, 800 kHz. The phase noise of PLL follows the closed loop VCO phase noise beyond the PLL bandwidth. At low offset frequencies, noise is dominated by the input reference clock since the loop gain tries to make the phase of VCO stable.

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The experimentally measured phase noise of the fabricated CMOS PLL circuit follows the calculated frequency dependence phase noise behavior and is in good agreement.

104

105

106

107

-70

-65

-60

-55

-50

-45

-40

-35

-30

Frequency (Hz)

Pha

se N

oise

(dB

c/H

z)

Calculated PLL output

Expermental PLL output

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PLL Experimental Study – Summary

PLL based on differential VCO structures is designed and fabricated in 0.5 μm CMOS technology.

Simulation and experimental results on VCO phase noise are shown which are used for PLL phase noise prediction.

Predicted and measurement results of PLL phase noise are compared which verify the phase noise prediction method.

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PHASE NOISE AND JITTER STUDY IN CMOS SWITCHABLE PHASE-LOCKED LOOP (PLL)

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P F D L o o p filte r H _ V C O

D iv id e r

inp ut

H ig h F re que c y P L L (6 4 0 M H z-8 0 0 M H z)

P F D L o o p filte r L _ V C O

D iv id e r

L o w F re que nc y P L L (3 2 0 M H z-6 4 0 M H z)

M U Xoutp ut

L ocalO s cillator

F D

Switchable PLL – Design

Building blocks of a switchable PLL architecture

The switch includes a local oscillator, frequency detector (FD) and a two input multiplexer (MUX). The FD compares it with the input signal.

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Switchable PLL – Analysis

Switchable PLL outputs at different frequencies

The output of the switchable PLL at different frequencies where 320 MHz waveform is the low frequency PLL (L_PLL) output and 1.12 GHz waveform is the high frequency PLL (H_PLL) output. (L_PLL starts to oscillate after 60ns and H_PLL starts to oscillate after 5ns).

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Switchable PLL – Analysis

Frequency detector output

The function of RC in the frequency detector is to translate the PFD output pulses into dc voltages

If the input frequency is less than the reference frequency, which is output of the local oscillator defined as 80 MHz, the output is at low level; while if the input frequency is higher than the reference frequency, the output is at high level. But if the input frequency is closer to the reference frequency it will take more time to get the dc output.

Stabilizing time versus offset frequency

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Switchable PLL – Experimental Results

Cadence/Virtuoso layout and microphotograph of the fabricated switchable PLL chip

The switchable PLL described in the present work was fabricated in 0.5 μm n-well CMOS process.

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Phase noise performance of VCO at 1GHz

The experimental results which are from open loop VCO circuit on the chip are in good agreement with the modeled phase noises which are calculated.

PLL phase noise at 700MHz carrier frequency

PLL phase noise before stress is -61dBc/Hz at 10 kHz offset frequency and is around -104dBc/Hz at 1 MHz offset frequency. The PLL phase noise increases by about 1-2 dB relative to carrier power per Hertz after four hours of hot carriers stress. .

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Experimental results of PLL jitter

The experimental results of device degradation on RMS jitter performance under different PLL output frequencies due to hot carrier effects. A 40 ps increase is observed after 4 hours of stress.

Photograph of PLL jitter

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Switchable PLL – Summary

A new design is proposed to expand PLL tuning range without sacrificing its speed and jitter and phase noise performances.

Cadence/Spectre has been used for post-layout simulations for jitter, phase noise and switchable frequency range.

The chip is experimentally tested for jitter, phase noise and switchable frequency range.

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LOW POWER PHASE-LOCKED LOOP WITH LC VOLTAGE-CONTROLLED

OSCILLATOR

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P F D L o o p filte r V C OX O

N

PP /)1(B

A

M a in C o unte r P re s c a le r

M o de C o ntro l

S w a llo w C o unte r

M

P F D fo u t

fo u t

LC VCO PLL – Design

Building blocks of a LC VCO PLL architecture

The programmable PLL includes a general PLL block and a dual modulus prescaler. The output frequency can reach to 1.2GHz in this design. In the design, the main counter is an 11-bit counter and the divider ratio can reach 2047 and the Swallow Counter is a 7-bit counter with divider ratio 127. Thus, the maximum divider ratio N = PB + A = 131135 where P=64, B=2047 and A=127 for 64/65 prescaler or N = 262143 where P=128, B=2047 and A=127 for 128/129 prescaler.

N = (P+1)A+P(B-A) = PB + A

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LC VCO architecture

LC VCO frequency range is 900MHz-1.2GHz.

V D D

V C TR L

C C

L L

4/4 4/4

5/1 .5 5/1 .5

5 0/5 05 nH 5 nH

1 0/1 5/1

V D D

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LC VCO architecture

Crystal oscillator circuit

X O S C _ IN V

O S C IN O S C O U T

X O S C _ IN VF O S C

R = 1.8k

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The 3rd order low pass loop filter schematic.

The transfer function of the loop filter is

)1()1(

1)(

31

2

TsTsCs

TssZ

tot

333

1221

321

222

CRT

C

CCRT

CCCC

CRT

tot

tot

F ro m C harge P u m p

C 1= 4.7 nF

R 2= 4.2 k

C 2= 47 nF

C 3= 4.7 nF

R 3= 9.1 kTo V C O

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LC VCO PLL – Layout and Simulation

L C _ V C O

P F D _ C PP re s c a le r

Lo o p F ilte r

C o unte r

Layout of the PLL frequency synthesizer.

The programmable PLL is implemented in 0.5 μm double poly triple metal CMOS technology.

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LC VCO PLL – Layout and Simulation

1.2 GHz PLL differential output waveforms

The voltage swing of the PLL output is from 1.36V to 1.72V.

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LC VCO PLL – Experiment Results

The spectrum measurement setup

PLL output is connected to a power splitter to fulfill the impedance match.

P F D L o o p filte r V C OR e f

N P o w e rS plitte r

S p e c tru mA n a lyze r

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LC VCO PLL – Experimental Results

Power spectrum density measurement

The carrier power is -29 dBm which is 0.001mW.

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LC VCO PLL – Experimental Results

PLL output phase noise

The in-band phase noise is -66.67 dBc/Hz at 10kHz offset frequency and phase noise reaches -120dBc/Hz at 1MHz offset frequency.

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LC VCO PLL – Summary

The low power design of a 3V 30mW PLL frequency synthesizer designed in 0.5 μm CMOS process is presented.

The divider has a main counter, a swallow counter and control logic. The on-chip inductor and n-MOSFET varactors are used in the LC VCO design.

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Conclusion• A 3rd order PLL circuit is designed and an attempt has been made to model

phase noise based on superposition of phase noises from its following circuit building blocks: the input reference, VCO, frequency divider, PFD and the loop filter.

• A new design is proposed to expand PLL tuning range without sacrificing its speed and jitter and phase noise performances.

• A low power design of a frequency synthesizer designed in 0.5 μm CMOS process is presented.

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References1. Y. Liu, A. Srivastava and Y. Xu, “Switchable PLL frequency synthesizer and hot carrier effects,” Journal of Circuits and

Systems, Vol. 2, No. 1, pp.45-52, Jan. 2011.

2. Y. Liu, A. Srivastava and Y. Xu, “A switchable PLL frequency synthesizer and hot carrier effects,” Proc. ACM Great Lakes Symposium on VLSI, pp. 481-486, May 10-12, 2009, (Boston, MA).

3. Y. Liu and A. Srivastava, “Reliability considerations in switchable PLL frequency synthesizers for wireless sensor networks,” Proc. SPIE Nano-, Bio-, Info-Tech Sensors and Systems, vol. 7646, pp. 7646-28, March 7-9, 2010, (San Diego, CA).

4. Y. Liu and A. Srivastava, “Hot carrier effects on CMOS phase-locked loop frequency synthesizers,” Proc. International Symposium on Quality Electronic Design (ISQED), pp. 92-98, March 22-24, 2010, (San Jose, CA).

5. Y. Liu and A. Srivastava, “Effect of hot carrier injection and negative bias temperature instability on the performance of CMOS phase-locked loops,” Proc. 2010 ASEE-GSW Annual conference, Mar. 24-26, 2010, (Lake Charles, LA).

6. A. Srivastava, Y. Xu, Y. Liu, A. K. Sharma, and C. Mayberry, “CMOS LC voltage-controlled oscillator design using carbon nanotube wire inductor,” Proc. 5th IASTED International Symposium on Circuits and Systems, pp. 171-176, August 23 – 25, 2010, (Maui, Hawaii).

7. A. Srivastava, Y. Xu, Y. Liu, A. K. Sharma, and C. Mayberry, “CMOS LC voltage-controlled oscillator design using multiwalled carbon nanotube wire inductor,” Proc. IEEE International Symposium on Electronic System Design (ISED), December 20-22, 2010, (Bhubaneswar, India).

8. A. Srivastava, Y. Xu, Y. Liu, A.K. Sharma, and C. Mayberry, ‘‘CMOS LC voltage controlled oscillator design using carbon nanotube wire inductors,” ACM Journal on Emerging Technologies in Computing Systems, in Production (2012).

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vlsi design lab phase noise in phase-locked loop circuits ashok srivastava department of electrical...

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