phase locked loop design kyoungtae kang, kyusun choi electrical engineering computer science and...
TRANSCRIPT
![Page 1: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/1.jpg)
Phase Locked LoopDesign
KyoungTae Kang, Kyusun Choi
Electrical Engineering
Computer Science and Engineering
CSE598A/EE597G Spring 2006
![Page 2: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/2.jpg)
Frequency Synthesizer
![Page 3: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/3.jpg)
General Synthesizer Issues
![Page 4: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/4.jpg)
Frequency Spectrum
![Page 5: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/5.jpg)
Settling Time (Lock Time)
![Page 6: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/6.jpg)
PLL Components Circuits
![Page 7: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/7.jpg)
PLL Components Circuits
![Page 8: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/8.jpg)
Reference Circuit
![Page 9: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/9.jpg)
PLL Components Circuits
![Page 10: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/10.jpg)
PFD and Charge Pump
Spur!!
![Page 11: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/11.jpg)
Phase Frequency Detector(1)
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Phase Frequency Detector(2)
![Page 13: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/13.jpg)
PFD and modified flip-flop
B.park, “A 1GHz, Low-Phase-Noise CMOS Frequency Synthesizer with Integrate LC VCO for Wireless Communications“, CICC 1998
Park, Byungha? GIT PhD. Samsung LSI, RF/Analog IC Group
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New Modified flip-flop by KT
•Reduce signal path
•High speed
•10 Transistors
•Negative reset
•No oscillation
•Customized
![Page 15: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/15.jpg)
D Flip-Flop
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DFF Simulation Comparison
•Modifed FF by KT
•DFF
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PFD Simulation(1)
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PFD Simulation(2)
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PFD Simulation(3)
![Page 20: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/20.jpg)
PFD Output Stage-Charge Pump
Programmable
![Page 21: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/21.jpg)
Charge Pump (Drain–s/w)
•My first Charge pump.
•Easy to design and understand how to work
•Spike Noise from net76 when U2 turn on
•High noise contribution!
•If you designed CP like this, you got fired!
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Charge Pump (Source-s/w)
•Low charge sharing
•Low noise
•Suppression the Spur
Level?
Why? Cascode?
>High impedence
>Pole!!!
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Charge Pump Simulation
CP_Drain
CP_Source
V(U/D)
I(U)
I(D)
![Page 24: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/24.jpg)
Charge Pumps
Rhee, W., "Design of high performance CMOS charge pumps in phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548
J. S. Lee, M. S. Keel, S. I. Lim, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,” Electronics Letters, Vol. 36, No. 23, pp. 1907-1908, November 2000.
![Page 25: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/25.jpg)
Loop Filter(1)
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Loop Filter(2)
![Page 27: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/27.jpg)
PLL Components Circuits
![Page 28: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/28.jpg)
Differential Delay Cell-Single pass
Chan-Hong Park, Solid-State Circuits, 1999.
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Differential Delay Cell-Multiple pass
Yalcin Alper Eken, Solid-State Circuits, 2004
Negative Skewed Delay Scheme:
Seog-Jun, Lee, ISSC, 1997
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Single pass Ring OSC.
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Multiple pass Ring OSC.
Which one is faster?
1. 3 stage single pass Ring OSC.
2. 5 stage multiple pass Ring OSC.
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3 Stage-Single pass Ring OSC.
•220MHz~825MHz @ V(Ctrl)=1.65V~3.3V
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3 Stage-Single pass Ring OSC.
![Page 34: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/34.jpg)
5 Stage-Multiple pass Ring OSC.
•1.65GHz~2.5GHz @ V(Ctrl) 1.65V~3.3V
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How to simulate Oscillator in Hspice?
.Option
Transient Step
Start-up time
Triggered Signal
Frequency Measure Tool: Cscope
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PLL Components Circuits
![Page 37: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/37.jpg)
Frequency Divider
•Input stage-high speed, low power, Following stages-High speed
•Differential type-Suppression Noise
•Input buffer is required
![Page 38: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/38.jpg)
N=64 Divider Simulation
![Page 39: Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006](https://reader035.vdocuments.site/reader035/viewer/2022081501/56649dbf5503460f94ab2fec/html5/thumbnails/39.jpg)
Input buffer
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PLL Simulation
V(VCO)
V(Ref)
V(DiV)
V(Up)
V(Dn)
V(Ctrl)