syllabus · vlsi design and embedded systems p.e.s. college of engineering, mandya - 571 401,...

SYLLABUS�(With effect from 2015-2016)�Out Come Based Education

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I to IV Semester

Master of Technology In

VLSI Design and Embedded Systems

P.E.S. College of Engineering, Mandya - 571 401, Karnataka(An Autonomous Institution Affiliated to VTU, Belagavi)

Grant -in- Aid Institution

(Government of Karnataka)

Accredited by NBA, New Delhi

Approved by AICTE, New Delhi.

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PrefacePES College of Engineering, Mandya, started in the year 1962, has become autonomous in the

academic year 2008-09. Since, then it has been doing the academic and examination activities

successfully. The college is running 8 Postgraduate programs. It consists of 6 M.Tech programs,

which are affiliated to VTU. Other postgraduate programs are MBA and MCA.

India has recently become a Permanent Member by signing the Washington Accord. The accord

was signed by the National Board of Ac-creditation (NBA) on behalf of India on 13th June 2014.

It enables not only the mobility of our degree globally but also establishes equivalence to our

degrees with that of the member nations such as Taiwan, Hong Kong, Ire-land, Korea, Malaysia,

New Zealand, Russia, Singapore, South Africa, Turkey, Australia, Canada and Japan are among

16 signatories to the international agreement besides the US and the UK. Implementation of

Outcome Based Education (OBE), has been the core issue for enabling the equivalence and of

Indian degrees and their mobility across the countries.

Our higher educational institution has adopted Credit Based semester structure with OBE scheme

and grading system.

The credit based OBE semester system provides flexibility in designing curriculum and assigning

credits based on the course content and hours of teaching.

The OBE, emphasize setting clear standards for observable, measurable outcomes of programs in

stages. There lies a is shift in thinking, teaching and learning processes moving towards Students

Centric from Teacher Centric education. OBE standards focusing on mathematics, language,

science, attitudes, social skills, and moral values.

The key features which may be used to judge if a system has implemented an outcomes-based

education systems is mainly Standards-based assessments that determines whether students have

achieved the stated standard. Assessments may take any form, so long as the process actually

measure whether the student knows the required information or can perform the required task.

Outcome based education is a commitment that all students of all groups will ultimately reach the

same minimum standards. Outcome Based Education is a method or means which begins with the

end in mind and constantly emphasizes continuous improvement.

In order to increase the Industry/Corporate readiness, many Soft Skills and Personality

Development modules have been added to the existing curriculum of 2015-16. Lab components

are added with each course.

(Dr.H.V.RAVINDRA)

Dean (Academic)

Professor

Dept. of Mechanical Engg.

B.DINESH PRABHU)

Deputy Dean (Academic)

Associate Professor

Dept. of Automobile Engg.

P.E.S.COLLEGE OF ENGINEERING, MANDYA-571401

(KARNATAKA)

(An Autonomous Institution under VTU, Belagavi)

Vision“An institution of high repute, imparting quality education to develop innovative and

Humane engineers”

Mission“Committed to develop students potential through high quality teaching- learning processes and

state of the art infrastructure”

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

About the DepartmentIn the department, the B.E degree was started in 1972 and the M.Tech degree in 2006 , the

Ph.D and M.Sc (by research) programmes in 2004. Currently the strength of teaching faculty is 20

and that of non teaching staff is 14. The present intake of B.E course is 120 and that of M.Tech

course is 49. The teacher - student ratio is 1:16. The department has a research centre under VTU,

with 4 research guides and 17 research students. During the last five years, the department has

published 15 technical papers in international journals and 10 technical papers in national journals.

So far, the department has organized one international and one national conference.

Vision

Developing high quality engineers with sound technical knowledge, skills and ethics in

order to meet the global technological and societal demands in the area of Electronics and

Communication engineering.

Mission

• Developing high quality graduates and post-graduates of Electronics and communication Engineering with modern technical knowledge, professional skills and attitudes in order to

meet industry and society demands.

• Developing graduates with an ability to work productively in a team with professional

ethics and social responsibility.

• Developing highly employable graduates and post graduates who can meet industrial

requirements and bring innovations.

• Moulding the students with foundation knowledge and skills to enable them to take up post-graduate programmes and research programmes at the premier institutes.

• Providing students with an excellent academic ambience to instil leadership qualities, character moulding and life-long learning necessary for a successful professional career.

P.E.S. COLLEGE OF ENGINEERING, MANDYA

Scheme of Teaching and Examination

First semester

Sl. No.

Course code Course title Teaching Dept.

Hrs/Week L:T:P:H

Total Credits

Marks Allotted Total Marks CIE SEE

1. P15MECE11 CMOS VLSI Design E & C 4:0:0:4 04 50 50 100

2. P15MECE 12 Advanced Embedded System

E & C 4:0:0:4 04 50 50 100

3. P15MECE13 SOC Design E & C 4:0:0:4 04 50 50 100

4. P15MECE 14 Elective – I E & C 4:0:0:4 04 50 50 100

5. P15MECE 15 Elective – II E & C 4:0:0:4 04 50 50 100

6. P15MECE16 Seminar-I E & C 0:0:4:4 02 50 --- 50 7 P15MECE L** VLSI design Lab E & C 0:0:4:4 02 50 50 100

Total 24 350 300 650

Sl. No. Course code Elective – I Hrs/Week L:T:P:H

1 P15MECE141 VLSI Process Technology 4:0:0:4

2 P15MECE142 Hardware - Software Co-Design 4:0:0:4

3 P15MECE143 Digital system design using Verilog 4:0:0:4

Elective – II

4 P15MECE151 ASIC Design 4:0:0:4

5 P15MECE152 VLSI Design Automation 4:0:0:4

6 P15MECE153 Nanotechnology 4:0:0:4

Second semester Sl. No. Course code Course title

Teaching Dept.

Hrs/Week L:T:P:H

Total Credits


1. P15MECE21 Design of Analog and Mixed mode VLSI Circuits

E & C 4:0:0:4 04 50 50 100

2. P15MECE22 Low power VLSI design E & C 4:0:0:4 04 50 50 100

3. P15MECE23 Real Time Operating System

E & C 4:0:0:4 04 50 50 100

4. P15MECE 24 Elective – III E & C 4:0:0:4 04 50 50 100 5. P15MECE 25 Elective – IV E & C 4:0:0:4 04 50 50 100 6. P15MECE26 Seminar II E & C 0:0:4:4 02 50 --- 50 7 P15MECE L** Embedded System Lab E & C 0:0:4:4 02 50 50 100

Total 24 350 300 650

Sl. No. Course code Elective – III Hrs/Week L:T:P:H

1 P15MECE241 Advanced Microcontrollers 4:0:0:4

2 P15MECE242 Interfacing of Mixed Signal Embedded System

4:0:0:4

3 P15MECE243 Embedded System design with FPGA 4:0:0:4 Elective – IV

4 P15MECE251 System Verilog 4:0:0:4 5 P15MECE252 Design of VLSI system 4:0:0:4 6 P15MECE253 Advanced Computer Architecture 4:0:0:4


Third semester

Sl. No.

Course code Course title Teaching Dept. Hrs/Week L:T:P:H

Total Credits

Marks Allotted Total

Marks CIE SEE

1. P15MECE31 VLSI Testing and Verification

E & C 4:0:0:4 04 50 50 100

2. P15MECE32 Elective – V E & C 4:0:0:4 04 50 50 100 3. P15MECE33 Elective – VI- E & C 4:0:0:4 04 50 50 100 4. P15MECE34 Industrial Training1 E & C 06 50 50 100

5. P15MHSM35 Pedagogy/Research Methodology

Humanities, Social Science & Management 0:2:2:4 02 100 -- 100

5. P15MECE35 Project –Phase - I E & C 0:0:8:8 04 50 50 100 Total 24 350 250 600

Sl. No. Course code Elective – V Hrs/Week( L:T:P:H) 1 P15MECE321 CMOS RF Circuit Design 4:0:0:4

2 P15MECE322 Synthesis and Optimization of Digital Circuits 4:0:0:4

3 P15MECE323 Automotive Electronics 4:0:0:4

Elective – VI

4 P15MECE331 MEMS 4:0:0:4

5 P15MECE332 Advances in VLSI design 4:0:0:4

6 P15MECE333 High Speed VLSI Design 4:0:0:4

Fourth semester Sl. No.

Course code Course title Teaching

Dept. Hrs/Week L:T:P:H

Total Credits


1. P15MECE41 Project –Phase-II E & C 0:0:8:8 04 50 50 100

2. P15MECE42 Project –Phase-III E & C 0:0:8:8

04 50 50 100

3. P15MECE43 Project work Thesis Evaluation

E & C -- 12 -- 100 100

4. P15MECE44 Project Work Viva-Voce E & C -- 08 -- 100 100

Total 28 100 300 400

Note: 1. Eight weeks of compulsory Industrial Training to be undergone by the students during their third semester. A report on Industrial Training to be submitted by the student. The report will be jointly evaluated by guides at Industry and Institute for CIE of 50 marks. The student must give seminar based on Industrial Training before a committee constituted by the Department for SEE of 50 marks. 2. The laboratories are CIE with report submission and seminar presentation/viva voce of 50 marks each. 3. Pedagogy/Research methodology has only CIE for 100 marks with object type questions for evaluation. 4. The Seminar I & II will be presentation on Miniprojects carried out during semester I and II along with project report evaluation. 5. Project work Phase-1, 2 and 3 to be awarded by Department committee constituted for the purpose

a) The Project Phase-I is based on Report Submission consisting of Title, Introduction, Literature, Survey, Summary of Literature Survey, Objectives and Methodology as CIE and Presentation as SEE 50 marks each.

b) The Project Phase-II is based on Report Submission consisting of Experimentation, Theoretical analysis approach and discussion (if completed) as CIE and Presentation as SEE for 50 marks each.

c) The project Phase-III is based on Thesis manuscript as CIE and Presentation as SEE for 50 marks each. 6. The project thesis evaluation has to be done separately by internal and external examiners. 7. The project viva- voce has to be done jointly by internal and external examiners.


M.Tech. - VLSI Design and Embedded System Syllabus of 2015-16 Academic Year Page 3

FIRST SEMESTER

Course Title : CMOS VLSI DESIGN

Course Code: P15MECE11 Semester : I L:T:P:H: 4:0:0:4

Contact Period : Lecture :52 Hr, Exam: 3Hr Weightage :CIE:50% SEE:50%

Prerequisites: The student should have undergone the course on basic CMOS VLSI Design.

Course Learning Objectives (CLOs)

At the end of the course the students should be able to:

1. Provide the basic knowledge of MOSFETs. 2. Explain the MOS Transistor threshold voltage equation. 3. Describe the second order effects. 4. Provides the knowledge of lamda based design rule. 5. Outline the concepts of Basics of Digital CMOS Design. 6. Illustrate the concepts of CMOS Analog Design. 7. Discuss the concepts of clocking in digital CMOS design

Course Content Unit I:

MOS Transistor Theory: n MOS / p MOS transistor, threshold voltage equation, body effect, MOS device design equation, sub threshold region, Channel length modulation. mobility variation, Tunneling, punch through, hot electron effect MOS models, small signal AC Characteristics, CMOS inverter, βn / βp ratio, noise margin, static load MOS inverters, differential inverter, transmission gate, tri-state inverter, Bi-CMOS inverter. 10 Hrs

Unit II: CMOS Process Technology: Lambda Based Design rules, scaling factor, semiconductor Technology overview, basic CMOS technology, p well / n well / twin well process. Current CMOS enhancement (oxide isolation, LDD. refractory gate, multilayer inter connect), Circuit elements, resistor, capacitor, interconnects, sheet resistance & standard unit capacitance concepts delay unit time, inverter delays, driving capacitive loads, propagate delays, MOS mask layer, stick diagram, design rules and layout, symbolic diagram, mask feints, scaling of MOS circuits. 11Hrs

Unit III: Basics of Digital CMOS Design: Combinational MOS Logic circuits-Introduction, CMOS logic circuits with a MOS load, CMOS logic circuits, complex logic circuits, Transmission Gate. Sequential MOS logic Circuits - Introduction, Behavior of hi stable elements, SR latch Circuit, clocked latch and Flip Flop Circuits, CMOS D latch and triggered Flip Flop. Dynamic Logic Circuits - Introduction, principles of pass transistor circuits, Voltage boot strapping synchronous dynamic circuit’s techniques, Dynamic CMOS circuit techniques. 11Hrs Unit IV: CMOS Analog Design: Introduction, Single Amplifier. Differential Amplifier, Current mirrors, Band gap references, basis of cross operational amplifier. 10 Hrs



Unit V: Dynamic CMOS and clocking: Introduction, advantages of CMOS over NMOS, CMOS\SOS technology, CMOS\bulk technology, latch up in bulk CMOS., static CMOS design, Domino CMOS structure and design, Charge sharing, Clocking- clock generation, clock distribution, clocked storage elements. 10Hrs TEXT BOOKS 1. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design: A System Perspective,” 2nd edition, Pearson Education (Asia) Pvt. Ltd. 2000. 2. Wayne, Wolf, “Modern VLSI design: System on Silicon” Pearson Education”, 2nd Edition. 3. Douglas A Pucknell & Kamran Eshragian , “Basic VLSI Design” PHI 3rd Edition (original Edition – 1994). 4. Sung Mo Kang & Yosuf Lederabic Law, “CMOS Digital Integrated Circuits: Analysis and Design”, McGraw-Hill (Third Edition).

Course Outcome (CO) After learning all the units of the course, the student is able to

1. Explain the behaviour of enhancement and depletion mode MOSFET in different region.- L2(Unit-I)

2. Discuss the second order effects in MOSFETS.-L2 (Unit-I) 3. Describe the various types of MOS inverters.-L1(Unit-I) 4. Explain the concepts of Lamda based design rules.-L2(Unit-II) 5. Outline the various delay concepts.-L4(Unit-II) 6. Describe the CMOS logic circuits with a MOS load.-L1(Unit-III) 7. Illustrate the various Sequential MOS logic Circuits.-L3(Unit-III) 8. Explain the various concepts of CMOS analog design.-L2(Unit-IV) 9. Explain the various concepts of MOS design technology.-L2(Unit-V) 10. Outline the concepts clock generation and clock distribution.-L4(Unit-V)



Course Title : Advanced Embedded systems

Course Code: P15 MECE12 Semester : I (L:T:P:H : 4:0:0:4)

Contact Period : Lecture :52 Hr, Exam: 3Hr Weightage :CIE:50%SEE:50%

Prerequisites: The student should have undergone the course on basic embedded systems and microcontrollers architecture and programming Course Learning Objectives (CLOs)

At the end of the course the students should be able to: 1. Explain the need for embedded systems 2. Explain the basic hardware components in embedded systems. 3. Design of certain basic applications using microcontrollers 4. Choose appropriate controllers for a particular applications. 5. Compare the performance of applications built using different microcontrollers. 6. Get exposure to both software and hardware. Design of embedded systems.

b) Relevance of the Course Advanced embedded systems is a foundation course for M.Tech in VLSI Design and Embedded Systems programme. It deals with the study and implementation of specific microcontrollers and their applications in general and the hardware and software design principles in particular. The course aims at developing the understanding of concepts like the use of Memory, interfacing I/O devices, Timers and their applications, RTOS principles, semaphore, etc. It helps in the design of basic embedded systems for particular applications like mobile phone, camera, heating systems, domestic appliances which are being used in everyday life.

Course Content

Unit I: Typical Embedded System: Core of the Embedded System, Memory, Sensors and Actuators, Communication Interface, Embedded Firmware, Other System Components. Characteristics and Quality Attributes of Embedded Systems: Characteristics of an embedded system, Quality attributes of embedded systems. 10 Hrs

Unit II: Hardware Software Co-Design and Program Modeling: Fundamental Issues in Hardware Software Co-Design, Computational Models in Embedded Design, Introduction to Unified Modeling Language, Hardware Software Trade-offs. Embedded Firmware Design and Development: Embedded Firmware Design Approaches, Embedded Firmware Development Languages 11 Hrs

Unit III: Real-Time Operating System (RTOS) based Embedded System Design: Operating System Basics, Types of OS, Tasks, Process and Threads, Multiprocessing and Multitasking, Task Scheduling, Threads, Processes and Scheduling: Putting them altogether, Task Communication, Task Synchronization, Device Drivers, How to Choose an RTOS 11 Hrs



Unit IV: The Embedded System Development Environment: The Integrated Development Environment (IDE), Types of Files Generated on Cross compilation, Disassembler/Decompiler, Simulators, Emulators and Debugging, Target Hardware Debugging, Boundary Scan. 10 Hrs

Unit V: Trends in the Embedded Industry: Processor Trends in Embedded System, Embedded OS Trends, Development Language Trends, Open Standards, Frameworks and Alliances, Bottlenecks. 10 Hrs TEXT BOOKS 1.Introduction to Embedded Systems, Shibu K V, Tata McGraw Hill Education Private Limited, 2009 2.Embedded Systems – A contemporary Design Tool, James K Peckol, John Weily, 2008. Course Outcome (CO) The student should be able to

1. Describe the architecture of a microcontroller .(L1) 2. Describe the purpose of an embedded system. (L1) 3. Explain the concepts of memory, sensors, actuators, interfaces etc..(L2) 4. Use the watchdog timers and programming concepts.( L2) 5. Use instructions /programs to perform specific tasks. ( L3) 6. Compare accessing data through pointers and arrays (L4) 7. Use the hardware interfacing chips for specific applications (L3) 8. Explain how a controller is programmed (L2) 9. Implementation of RTOS for specific applications.(L3) 10. Explain the concept of semaphores(L2) 11. Use of IDE for a system design and debugging .(L3) 12. Explain the concept of industrial applications .(L4)



Course Title : SOC design


Contact Period : Lecture :52 Hr, Exam:3Hr Weightage :CIE:50%SEE:50%


At the end of the course the students should be able to: 1. Compare the performance, advantage, and disadvantage of system on board, system on chip, and

system in package. 2. Provide the knowledge of embedded processors with different architectures and embedded

memories with scratchpad and cache concepts. 3. Describe the hardware accelerations for graphics and image processing as well as DMA

controller and USB controller. 4. Outline the interfacing procedure to form D/A converter with the microcomputer. 5. Focus on the vital issues of ESL design flow for MPSoCs.

Course Content

Unit 1: Motivation for SoC Design - Review of Moore’s law and CMOS scaling, benefits of system-on-chip integration in terms of cost, power, and performance. Comparison on System-on-Board, System-on-Chip, and System-in-Package. Typical goals in SoC design – cost reduction, power reduction, design effort reduction, performance maximization. Productivity gap issues and the ways to improve the gap – IP based design and design reuse. 11 Hrs

Unit 2: Embedded Processors – microprocessors, microcontrollers, DSP and their selection criteria. Review of RISC and CISC instruction sets, Von-Neumann and Harvard architectures, and interrupt architectures. Embedded Memories – scratchpad memories, cache memories, flash memories, embedded DRAM. Topics related to cache memories. Cache coherence. MESI protocol and Directory-based coherence. 11 Hrs

Unit 3: Hardware Accelerators in an SOC – comparison on hardware accelerators and general-purpose CPU. Accelerators for graphics and image processing. Typical peripherals in an SoC – DMA controller, USB controller. Interconnect architectures for SoC. Bus architecture and its limitations. Network on Chip (NOC) topologies. Mesh-based NoC. Routing in an NoC. Packet switching and wormhole routing. 10 Hrs

Unit 4: Mixed Signal and RF components in an SoC. Sensors, Amplifiers, Data Converters, Power management circuits, RF transmitter and receiver circuits. 10 Hrs

Unit 5: SoC Design Flow. IP design, verification and integration, hardware-software codesign, power management problems, and packaging related problems. 10 Hrs



TEXT BOOKS 1. Sudeep Pasricha and Nikil Dutt,”On-Chip Communication Architectures: System on Chip Interconnect”, Morgan Kaufmann Publishers © 2008 2.Henry Chang et al., “Surviving the SOC revolution: a guide to platform-based design”, Kluwer (Springer), 1999 3.Frank Ghenassia,”Transaction Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems”, Springer © 2005 (281 pages), ISBN:9780387262321 4.Luca Benini and Giovanni De Micheli,”Networks on Chips: Technology and Tools”, Morgan Kaufmann Publishers © 2006(408 pages), ISBN:9780123705211, 5. Michael J. Flynn & Wayne Luk, “Computer System Design – System -On-Chip”, John Wiley, 2011

Course Outcome(CO) After learning all the units of the course, the student is able to

1. Mention the best design practices which are important to achieve the minituration at optimized cost-L1 2. Describe with neat sketches the two mechanisms of data programming and erasing the flash memory

cell-L1 3. Explain the role of CPU accelerators in multi processor design-L2 4. Sketch the diagrams for three types of physical structures of shared bus implementation-L3 5. Analyze the Hartley image reject receiver graphically-L4 6. Explain the Adoptive performance management by voltage control-L2



ELECTIVE I

Course Title : VLSI Process Technology



Course Learning Objectives (CLO) :

At the end of the course the students should be able to: 1. Provide the overview of crystal growth technique and thin film technologies. 2. Explain the different lithographic process, plasma formation and etching techniques, 3. Describe the deposition process of polysilicon, oxide, nitride and other materials. 4. Highlight the ion implantation techniques with shallow and deep profiles. 5. Discuss the metallization process and VLSI NMOS and PMOS fabrication processes. 6. Provide the steps of IC memory fabrication technology and packaging schemes.

b) Relevance of the Course The VLSI technology course is very much relevant from the view point of understanding the device fabrication using diffusion, ion implantation, thin film growth, crystal growth, thin film deposition, epitaxial growth, lithography, etching, metallization, annealing, assembly and packaging. Using these processes nmos, pmos bicoms devices are fabricated on the substrates. The oxide and nitride layer growth is also very much essential in defining the configuration of the devices. Highly sophisticated and accurate machines and equipments are adopted to produce the devices using IC technology, in order to achieve the desired characteristics and performance for the devices. All these aspects must be thoroughly understood by the design engineer to design and fabricate the devices on suitable substrates. This course provides the knowledge of all these more clearly and in detail.

Course Content Unit 1:

Crystal Growth and Wafer Preparation: Introduction, Electronic-Grade Silicon, Czochralski Crystal Growing, Silicon Shaping, Process Considerations. Epitaxy: Introduction, Vapour-Phase Epitaxy, Molecular Beam Epitaxy, Silicon on Insulators, Epitaxial Evaluation. 10 Hrs

Unit 2: Lithography : Introduction, Optical Lithography, Electron Lithography, X-ray Lithography, Ion Lithography. Reactive Plasma Etching: Introduction, Plasma Properties, Feature-Size Control and Anisotropic Etch Mechanisms, Other Properties of Etch Processes, Reactive Plasma-Etching Techniques and Equipment, Specific Etch Processes. 11 Hrs

Unit 3: Dielectric and Polysilicon Film Deposition: Introduction, Deposition Processes, Polysilicon, Silicon Dioxide, Silicon Nitride, Plasma-Assisted Depositions, Other Materials. Ion Implantation: Introduction, Range Theory, Implantation Equipment, Annealing, Shallow Junctions, High-Energy Implantation. 11 Hrs

Unit 4: Metallization: Introduction, Metallization Applications, Metallization Choices, Physical Vapor Deposition, Patterning, Metallization Problems, New Role of Metallization.



VLSI Process Integration: Introduction, Fundamental Considerations for IC Processing, NMOS IC technology, CMOS IC Technology 10 Hrs

Unit 5: MOS Memory IC Technology, Bipolar IC Technology, IC Fabrication. Packaging of VLSI Devices: Introduction, Package Types, Packaging Design Considerations. 10 Hrs

Reference Books: 1. S. M. Sze, “VLSI Technology”, McGraw-Hill, Second Edition. 2. S.K. Ghandhi, "VLSI Fabrication Principles", John Wiley Inc., New York, 1994, Second Edition.

Course Outcome After learning all the units of the course, the student is able to

1. Explain Wet cleaning and dry cleaning of silicon wafers. 2. Describe optical lithography, electron lithography, X-ray Lithography, Ion Lithography. 3. Discuss the Polysilicon, Silicon Dioxide and Silicon Nitride depositions as well as Plasma-

Assisted Depositions. 4. Outline the Metallization Problems and solutions. 5. Describe the VLSI Process Integration and Important Considerations for IC Processing. 6. Describe the steps in MOS memory and bipolar IC fabrication processes.



Course Title : Hardware-Software CO-Design

Course Code: P15MECE142 Semester : I (L:T:P:H: 4:0:0:4)

Contact Period : Lecture :52 Hr,Exam: 3Hr Weightage:CIE:50% SEE:50%

Prerequisites: The student should have undergone the course on basic VLSI Design and computer architecture /microcontrollers Course Learning Objectives (CLO)

At the end of the course the students should be able to: 1. Explain the need for Hardware software co design 2. Explain the basic hardware and software components in VLSI system design 3. Explain the concept on system communication and emulation 4. Choose appropriate controllers for certain system applications. 5. Compare the performance and applications of target architecture like ADSP 21060/ TMS 32060 6. Get exposure to both software and hardware Design of VLSI system.

Relevance of the Course This course is so designed that it gives exposure to the students regard to the hardware and software aspects to be considered in any VLSI system design. The system architecture are studied in depth and the concepts on high performance data systems are also exposed. Compilation techniques and tools for embedded system architecture are also exposed. Further the design specifications and verification are also explained at later units.

Course Content

UNIT I: Co- Design Issues:Co- Design Models, Architectures, Languages, A Generic Co-design Methodology. Co- Synthesis Algorithms: Hardware software synthesis algorithms: hardware – software partitioning distributed system co synthesis. 10 Hrs

UNIT II: Prototyping and Emulation:Prototyping and emulation techniques, prototyping and emulation environments, future developments in emulation and prototyping architecture specialization techniques, system communication infrastructure Target Architectures:Architecture Specialization techniques, System Communication infrastructure, Target Architecture and Application System classes, Architecture for control dominated systems (8051-Architectures for High performance control), Architecture for Data dominated systems (ADSP21060, TMS320C60), Mixed Systems. 11 Hrs

UNIT III: Compilation Techniques and Tools for Embedded Processor Architectures:Modern embedded architectures, embedded software development needs, compilation technologies, practical consideration in a compiler development environment. 10 Hrs

UNIT IV: Design Specification and Verification:Design, co-design, the co-design computational model, concurrency coordinating concurrent computations, interfacing components, design verification, implementation verification, verification tools, interface verification 10 Hrs



UNIT V: Languages for System – Level Specification and Design-I:System – level specification, design representation for system level synthesis, system level specification languages, Languages for System – Level Specification and Design-II: Heterogeneous specifications and multi language co-simulation, the cosyma system and lycos system. 11 Hrs TEXT BOOKS: 1. Hardware / Software Co- Design Principles and Practice – Jorgen Staunstrup, Wayne Wolf –2009, Springer. 2. Hardware / Software Co- Design - Giovanni De Micheli, Mariagiovanna Sami, 2002, Kluwer Academic Publishers REFERENCE BOOKS: 1. A Practical Introduction to Hardware/Software Co-design -Patrick R. Schaumont - 2010 –Springer

Course Outcome The student should be able to

1. Describe the architecture models with respect to co designmethodology.(L1) 2. Describe the purpose of hardware and software codesign.(L2) 3. Explain the concepts of prototype emulation techniques(L2) 1. 4.Describe the specialization in target architecture.(L2) 2. 5. Use the high performance control architecture.(L3) 7. Narrate the instructions /programs to perform specific tasks. ( L3) 8. Learn about compilation techniques for tools for embedded systems.(l3) 9. Work about the use of verification tools.(L4) 10. Use the language for system level specification and design(L4) 11. learn about the interfacing chips for specific applications (L3)



Course Title : DIGITAL SYSTEM DESIGN USING VERILOG Course Code: P15MECE143 Semester : I L:T:P:H : 4:0:0:4 Contact Period : Lecture :52 Hr, Exam:3Hr Weightage :CIE:50%SEE:50%

Course Learning Objectives (CLOs) At the end of the course the students should be able to: 1. Provide the understanding of Digital Systems and Embedded Systems. 2. Outline the concepts of Real world circuits, Models and Design methodology. 3. Explain Combinational Circuits and its Verification. 4. Describe the concepts of Number Systems. 5. Illustrate and explain the concepts of Sequential Circuits. 6. Outline the concept of clocked Synchronous Timing Methodology. 7. Illustrate the knowledge of Memories. 8. Describe Interconnection, packaging and circuit boards. 9. Provide the understanding of processor basics and I/O interfacing. 10. Explain and verify the concepts of Accelerators.

Course Content Unit I

Introduction and Methodology:Digital Systems and Embedded Systems, Binary representation and Circuit Elements, Real-World Circuits, Models, Design Methodology. Combinational Basics:Boolean Functions and Boolean Algebra, Binary Coding, Combinational Components and Circuits, Verification of Combinational Circuits. 11 Hrs

Unit II Number Basics:Unsigned and Signed Integers, Fixed and Floating-point Numbers. Sequential Basics: Storage elements, Counters, Sequential Datapaths and Control, Clocked Synchronous Timing Methodology. 11 Hrs

Unit III Memories: Concepts, Memory Types, Error Detection and Correction. Implementation Fabrics: ICs, PLDs, Packaging and Circuit Boards, Interconnection and Signal Integrity. 10 Hrs

Unit IV Processor Basics: Embedded Computer Organization, Instruction and Data, Interfacing with memory. I/O interfacing: I/O devices, I/O controllers, Parallel Buses, Serial Transmission, I/O software. 10 Hrs

Unit V Accelerators: Concepts, case study, Verification of accelerators. Design Methodology: Design flow, Design optimization, Design for test. 10 Hrs TEXT BOOK “Digital Design: An Embedded Ssytems Approach Using VERILOG”, Peter J. Ashenden, Elesvier, 2010. Course Outcomes (CO) After learning all the units of the course, the student is able to

1. Describe the knowledge of Digital Systems and Embedded Systems.-L1(Unit-I) 2. Outline the concepts of Combinational Circuits and its Verification.-L4(Unit-I) 3. Discuss the concepts of Number Systems.-L2(Unit-II) 4. Illustrate and explain the concepts of Sequential Circuits.-L4(Unit-II) 5. Describe the knowledge of Memories.-L1(Unit-III) 6. Outline the concept of processor basics and I/O interfacing.-L4(Unit-IV) 7. Explain and verify the concepts of Accelerators.-L5(Unit-V) 8. Illustrate the concept of Design methodology.-L4(Unit-V)



ELECTIVE II

Course Learning Objectives (CLOs) At the end of the course the students should be able to:

1. Provide the basic knowledge of ASIC Design and VHDL. 2. Explain the Full custom, Semi custom and standard cell based ASIC. 3. Describe the Programmable logic device and FPGA Design flow. 4. Provide the understanding of Data Logic cells and ASIC Library Design. 5. Explain the Low-level Design entry. 6. Describe the various concepts of Programmable ASIC Design. 7. Outline the concept of Low Level Design Language. 8. Describe the various ASIC Construction Floor Planning. 9. Outline the concepts of Placement and Routing of ASIC Design.

Course Content

Unit I: Introduction: Full Custom with ASIC, Semi custom ASICS, Standard Cell based ASIC, Gate array based ASIC, Channeled gate array, Channel less gate array, structured get array, Programmable logic device, FPGA design flow, ASIC cell libraries. 10 Hrs

Unit II:

Data Logic Cells: Data Path Elements, Adders, Multiplier, Arithmetic Operator, I/O cell, Cell Compilers ASIC Library Design: Logical effort: practicing delay, logical area and logical efficiency logical paths, multi stage cells, optimum delay, optimum no. of stages, library cell design. 10 Hrs

Unit III: Low-Level Design Entry: Schematic Entry: Hierarchical design. The cell library, Names, Schematic, Icons & Symbols, Nets, schematic entry for ASIC’S, connections, vectored instances and buses, Edit in place attributes, Netlist, screener, Back annotation. 10 Hrs

Unit IV: Programmable ASIC: programmable ASIC logic cell, ASIC I/O cell A Brief Introduction to Low Level Design Language: an introduction to EDIF, PLA Tools, an introduction to CFI designs representation. Half gate ASIC. Introduction to Synthesis and Simulation.

11 Hrs Unit V:

ASIC Construction Floor Planning and Placement and Routing: Physical Design, CAD Tools, System Partitioning, Estimating ASIC size, partitioning methods. Floor planning tools, I/O and power planning, clock planning, placement algorithms, iterative placement improvement, Time driven placement methods. Physical Design flow global Routing, Local Routing, Detail Routing, Special Routing, Circuit Extraction and DRC. 11 Hrs

Course Title : ASIC Design

Course Code: P15MECE151 Semester : I (L:T:P:H : 4:0:0:4)




TEXT BOOKS 1.M.J.S .Smith, - “Application - Specific Integrated Circuits” – Pearson Education,2003. 2. Jose E.France, Yannis Tsividis, “Design of Analog-Digital VLSI Circuits for Telecommunication and signal processing”, Prentice Hall, 1994. 3.Malcolm R.Haskard; Lan. C. May, “Analog VLSI Design – NMOS and CMOS”, Prentice Hall, 1998. 4.Mohammed Ismail and Terri Fiez, “Analog VLSI Signal and Information Processing”, McGraw Hill, 1994.


1.Describe the Full custom and Semi custom ASIC.-L1(Unit-I) 2.Explain the Standard Cell based and Gate array based ASIC.-L2(Unit-I) 3.Describe the various concept of Data Logic cells.-L1(Unit-II) 4.Explain the concept of ASIC Library Design.-L2(Unit-II) 5.Illustrate the various concepts of Low-level Design entry.-L3(Unit-III) 6.Explain the various types of Programmable ASIC.-L2(Unit-IV) 7.Outline the concept of Low Level Design Language.-L4(Unit-IV) 8.Describe the CFI designs representation and Half gate ASIC.-L1(Unit-IV) 9.Explain the various concepts ASIC Construction Floor Planning.-L2(Unit-V) 10.Outline the concepts of Placement and Routing of ASIC Design.-L4(UnitV)



Course Learning Objectives (CLOs) After learning all the units of the course, the student is able to

1. Provide the basic knowledge of Automation. 2. Explain the Logic Synthesis & Verification 3. Provide the understanding of VLSI Automation Algorithms. 4. Illustrate and explain various classification of partitioning algorithms 5. Describe the various placement algorithms. 6. Outline the concepts of Floor Planning & Pin Assignment 7. Describe the various global routing algorithms. 8. Explain the concepts of Detailed routing 9. Outline the concepts of Over The Cell Routing & Via Minimization. 10. Illustrate the concepts of Compaction.

Course Content Unit I Logic Synthesis & Verification: Introduction to combinational logic synthesis, Binary Decision Diagram, Hardware models for High-level synthesis. VLSI Automation Algorithms : Partitioning: problem formulation, classification of partitioning algorithms, Group migration algorithms, simulated annealing & evolution, other partitioning algorithms. 11 Hrs Unit II Placement, Floor Planning & Pin Assignment: problem formulation, simulation base placement algorithms, other placement algorithms, constraint based floor planning, floor planning algorithms for mixed block & cell design. General & channel pin assignment. 10 Hrs Unit III Global Routing: Problem formulation, classification of global routing algorithms, Maze routing algorithm, line probe algorithm, Steiner Tree based algorithms, ILP based approaches. 10 Hrs Unit IV Detailed Routing: problem formulation, classification of routing algorithms, single layer routing algorithms, two layer channel routing algorithms, three layer channel routing algorithms, and switchbox routing algorithms. 10 Hrs Unit V Over The Cell Routing & Via Minimization : two layers over the cell routers, constrained & unconstrained via minimization Compaction: problem formulation, one-dimensional compaction, two dimension based compaction, hierarchical compaction. 11 Hrs

Course Title : VLSI DESIGN AUTOMATION

Course Code: P15MECE152 Semester : I L:T:P:H : 4:0:0:4




TEXT BOOKS : 1. Naveed Shervani, “Algorithms for VLSI physical design Automation”, Kluwer Academic Publisher, Second edition. 2.Christophn Meinel & Thorsten Theobold, “Algorithm and Data Structures for VLSI Design”, KAP, 2002. 3.Rolf Drechsheler : “Evolutionary Algorithm for VLSI ”, Second edition. 4.Trimburger, “Introduction to CAD for VLSI ”, Kluwer Academic publisher, 2002. Course Outcome (CO) After learning all the units of the course, the student is able to

1. Describe the concept of Logic Synthesis & Verification.-L1(Unit-I) 2. Illustrate VLSI Automation Algorithms.-L4(Unit-I) 3. Explain various classification of partitioning algorithms.-L5(Unit-I) 4. Outline the concepts of various placement algorithms.-L4(Unit-II) 5. Describe the concepts of Floor Planning & Pin Assignment.-L1(Unit-II) 6. Explain various global routing algorithms.-L5(Unit-III) 7. Illustrate the concepts of Detailed routing.-L4(Unit-IV) 8. Outline the concepts of Over The Cell Routing & Via Minimization.-L4(Unit-V) 9. Explain the concepts of Compaction.-L5(Unit-V)



Course Title : NANOTECHNOLOGY

Course Code: P15MECE153 Semester : I (L:T:P:H : 4:0:0:4)

Contact Period:Lecture :52Hr,Exam: 3Hr Weightage:CIE:50%SEE:50%


After learning all the units of the course, the student is able to 1.Provide the understanding of nanoscience and engineering. 2.Outline the concepts of Electronic properties of atoms and solids. 3.Explain different fabrication methods. 4.Describe the concepts of Characterization. 5.Illustrate and explain the concepts of techniques for property measurement. 6.Outline the concept of Inorganic semiconductor nanostructures. 7.Describe different techniques of fabrication. 8.Describe Interconnection, packaging and circuit boards. 9.Provide the understanding of different physical processes with respect to nano technology. 10.Discuss the concept of characterization of semiconductor nanostructures. 11. Explain different properties of nanoparticles. 12.Illustrate carbon nanostructures with its application. 13.Discuss various applications of nano electronics.

Course Content

Unit I Introduction: Overview of nanoscience and engineering, Development milestones in microfabrication and electronic industry, Moores law and continued miniaturization, Classification of Nano structures, Electronic properties of atoms and solids: Isolated atom, Bonding between atoms, Giant molecular solids, Free electron models and energy bands, crystalline solids, Periodicity of crystal lattices, Electronic conduction, effects of nanometer length scale, Fabrication methods: Top down processes, Bottom up processes methods for templating the growth of nanomaterials, ordering of nanosystems. 11 Hrs Unit II Characterization: Classification, Microscopic techniques, Field ion microscopy, scanning probe techniques, diffraction techniques: bulk, surface, spectroscopy techniques: photon, radiofrequency, electron, surface analysis and dept profiling: electron, mass, Ion beam, Reflectrometry, Techniques for property measurement: mechanical, electron, magnetic, thermal properties. Inorganic semiconductor nanostructures: overview of semiconductor physics, Quantum confinement in semiconductor nanostructures: quantum wells ,quantum wires, quantum dots, super-lattices, band offsets, electronic density of states. 10 Hrs Unit III Fabrication techniques: requirements of ideal semiconductor, epitaxial growth of quantum wells, lithography and etching, cleaved edge overgrowth, growth of vicinal substrates, strain induced dots and wires, electrostatically induced dots and wires, Quantum well width fluctuations, thermally annealed quantum wells, semiconductor nanocrystals, collidal quantum dots, self-assembly techniques. 10 Hrs Unit IV Physical processes: modulation doping, quantum hall effect, resonant tunneling, charging effects, ballistic carrier transport, Inter band absorption, intraband absorption, Light emission processes, phonon



bottleneck, quantum confined stark effect, nonlinear effects, coherence and dephasing, characterization of semiconductor nanostructures: optical electrical and structural. 10 Hrs Unit V Methods of measuring properties: structure: atomic, crystallography, microscopy, spectroscopy. Properties of nanoparticles: metal nano clusters, semiconducting nanoparticles, rare gas and molecular clusters, methods of synthesis(RF, chemical, thermolysis, pulsed laser methods) Carbon nanostructures and its applications(field emission and shielding, computers, fuel cells, sensors, catalysis).Self assembling nanostructured molecular materials and devices: building blocks,principles of self assembly, methods to prepare and pattern nanoparticles ,template nanostructures, liquid crystal mesophases. Nanomagnetic materials and devices: magnetism, materials, magneto resistance, nanomagnetism in technology, challenges facing nano magnetism. Applications: Injection lasers, quantum cascade lasers, singe photon sources, biological tagging, optical memories, coulomb blocade devices, photonic structures, QWIP’s, NEMS, MEMS. 11 Hrs TEXT BOOKS 1. Ed Robert Kelsall,Ian Hamley,Mark Geoghegan, “ Nanoscale science and technology” ,John wiley and sons,2007. 2. Charles P Poole,Jr,Frank J owens “Introduction to Nanotechnology” ,John wiley,copyright 2006,Reprint 2011. 3. Ed William A Goddard III,Donald W Brenner,Sergey Edward Lyshevski,Gerald J Lafrate, “ Hand Book of Nanoscience Engineering and Technology” ,CRC press,2003. Course Outcomes (CO) After learning all the units of the course, the student is able to

1. Describe the knowledge of nanoscience and engineering.-L2(Unit-I) 2. Explain the electronic properties of atoms and solids.-L5(Unit-I) 3. Illustrate and explain the concepts of Characterization.-L4(Unit-II) 4. Describe the knowledge of Inorganic semiconductor nanostructures.-L1(Unit-II) 5. Outline the concept of Fabrication techniques.-L4(Unit-III) 6. Explain the concepts of Physical Processes.-L5(Unit-IV) 7. Illustrate the Methods of measuring properties.-L4(Unit-V) 8. Discuss the application nano electronics.-L2(Unit-V)



Course Title : VLSI DESIGN LABORATORY

Course Code: P15MECEL** Semester : I (L:T:P:H : 0:0:4:4)

Contact Period:Lecture :42 hrs,Exam: 3hrs Weightage : CIE:50% SEE:50%

Course Learning Objectives (CLOs) After learning all the units of the course, the student is able to 1. Provide the basic knowledge of how to use CADENCE Tool for VLSI concepts. 2. Analyze the ASIC Design flow. 3. Design and Verify an inverter, Buffer ,Transmission gate and Basic/universal gates using verilog

code. 4. Design and Verify an Flip flops(RS, D, JK, MS, T) and Serial & Parallel adder using Verilog code. 5. Design and Verify an 4-bit counter [Synchronous & Asynchronous counter] using verilog code. 6. Analyze the FPGA Digital Design. 7. Develop 8-bit Carry Ripple Adder, Carry LookAhead adder and Carry Skip Adder using Verilog

code. 8. Design BCD Adder & Subtracter using Verilog code. 9. Develop 8-bit Array Multiplication (Signed and Unsigned) and Booth Multiplication (Radix-4) using

Verilog code. 10. Design 4/8-bit Magnitude Comparator, LFSR, Parity Generator and Universal Shift Register using

Verilog code. 11. Develop a Verilog Code for 3-bit Arbitary Counter to generate 0,1,2,3,6,5,7 and repeats. 12. Design a Mealy and Moore Sequence Detector using Verilog to detect Sequence. 13. Design and verify a FIFO and LIFO buffers using Verilog code. 14. Develop Mealy FSM model for a coin operated public Telephone unit for the specified operations. 15. Analyze the Analog Design flow. 16. Construct the schematic for an inverter and analyze DC and Transient Behaviour. 17. Construct the layout for an inverter and verify DRC and ERC. 18. Construct the schematic for a given circuit and analyze DC,AC and Transient Behaviour. 19. Construct the layout for a given circuit and verify DRC and ERC. 20. Develop a simple 8-bit ADC converter and simple NAND/NOR gate.

Course Content A.VLSI Digital Design (i) ASIC-Digital Design Flow 1. Write Verilog Code for the following circuits and their Test Bench for verification,

� An inverter, Buffer and Transmission gate � Basic/universal gates � Flip flop -RS, D, JK, MS, T � Serial & Parallel adder � 5.4-bit counter [Synchronous & Asynchronous counter]

(ii) FPGA DIGITAL DESIGN VLSI Front End Design programs: 1. Write Verilog code for the design of 8-bit

� Carry Ripple Adder � Carry LookAhead adder



� Carry Skip Adder � BCD Adder & Subtracter

2. Write Verilog Code for 8-bit � Array Multiplication (Signed and Unsigned) � Booth Multiplication (Radix-4)

3. Write Verilog code for 4/8-bit � Magnitude Comparator � LFSR � Parity Generator � Universal Shift Register

4. Write Verilog Code for 3-bit Arbitary Counter to generate 0,1,2,3,6,5,7 and repeats. 5. Design a Mealy and Moore Sequence Detector using Verilog to detect Sequence. 6. Design a FIFO and LIFO buffers in Verilog and Verify its Operation. 7. Design a coin operated public Telephone unit using Mealy FSM model with specified operations Note: Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits B. ANALOG DESIGN Analog Design Flow: 1. Design an Inverter with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following

� DC Analysis � Transient Analysis

b. Draw the Layout and verify the DRC, ERC c. Check for XX d. Extract RC and back annotate the same and verify the Design e. Verify & Optimize for Time, Power and Area to the given constraint*** 2. Design the following circuits with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following

� DC Analysis � AC Analysis � Transient Analysis

b. Draw the Layout and verify the DRC, ERC c. Check for XX d. Extract RC and back annotate the same and verify the Design. i) A Single Stage differential amplifier

* Appropriate specification should be given. ** Applicable Library should be added & information should be given to the Designer.



*** An appropriate constraint should be given 6. Design a simple 8-bit ADC converter using any one of the tools given above. 7. Design a simple NAND/NOR gate using any one of the tools given above.(Any other experiments may be added in supportive of the course) Course Outcome After conducting all the experiments the student is able to

1. Illustrates the basic knowledge of how to use CADENCE Tool for VLSI concepts.(L3) 2. Analyze the ASIC Design flow.(L4) 3. Construct and Verify an inverter, Buffer ,Transmission gate and Basic/universal gates using

verilog code.(L5) 4. Design and Verify an Flip flops(RS, D, JK, MS, T) and Serial & Parallel adder using verilog

code.(L5) 5. Develop and Verify an 4-bit counter [Synchronous & Asynchronous counter] using verilog

code.(L5) 6. Analyze the FPGA Digital Design.(L4) 7. Develop 8-bit Carry Ripple Adder,Carry LookAhead adder and Carry Skip Adder using Verilog

code.(L5) 8. Design BCD Adder & Subtractor using Verilog code.(L5) 9. Develop 8-bit Array Multiplication (Signed and Unsigned) and Booth Multiplication (Radix-4)

using Verilog code.(L5) 10. Design 4/8-bit Magnitude Comparator, LFSR, Parity Generator and Universal Shift Register

using Verilog code.(L5) 11. Develop a Verilog Code for 3-bit Arbitary Counter to generate 0,1,2,3,6,5,7 and repeats.(L5) 12. Construct a Mealy and Moore Sequence Detector using Verilog to detect Sequence.(L5) 13. Design and verify a FIFO and LIFO buffers using Verilog code.(L5) 14. Implement Mealy FSM model for a coin operated public Telephone unit for the specified

operations.(L4) 15. Analyze the Analog Design flow.(L4) 16. Construct the schematic for an inverter and analyze DC and Transient Behaviour.(L5) 17. Develop the layout for an inverter and verify DRC and ERC.(L5) 18. Construct the schematic for a specified circuit and analyze DC,AC and Transient Behaviour.(L5) 19. Design the layout for a specified circuit and verify DRC and ERC.(L5) 20. Develop a simple 8-bit ADC converter and simple NAND/NOR gate.(L5)



SECOND SEMESTER Course Title : DESIGN OF ANALOG and MIXED MODE VLSI CIRCUITS

Course Code: P15MECE21 Semester : II L:T:P:H : 4:0:0:4



At the end of the course the students should be able to: 1. Analyze the analog CMOS circuits. 2. Describe the basic MOS device physics and more advanced properties and fabrication details. 3. Describe the small signal and large signal analysis of amplifiers. 4. Explain the working of various single stage MOS amplifiers. 5. Describe the operation of differential amplifier and different types of Current mirrors and their

applications. 6. Provide the understanding of the concept of band gap references and discuss the speed and noise

issues. 7. Discuss the elementary switched capacitor circuit and effect of non–linearity and miss–match. 8. Explain the condition for oscillation and design of different types of oscillators. 9. Design the Phase Locked Loops and its applications.

Unit 1: Basic MOS Device Physics: General considerations, MOS I/V Characteristics, second order effects, MOS device models. Single stage Amplifier: CS stage with resistance load, divide connected load, current source load, triode load, CS stage with source degeneration, source follower, common-gate stage, cascade stage, choice of device models. 11 Hrs

Unit 2: Differential Amplifiers: Basic difference pair, common mode response, Differential pair with MOS loads, Gilbert cell. Passive and active Current mirrors: Basic current mirrors, Cascade mirrors, active current mirrors. 11 Hrs

Unit 3: Frequency response of CS stage: source follower, Common gate stage, Cascade stage and Difference pair. Noise in CS stage, C- G stage, source follower, cascade stage, differential pair. 10 Hrs

Unit 4: Operational Amplifiers: One Stage OP-Amp. Two Stage OP-Amp, Gain boosting, Coommon Mode Feedback, Slew rate, PSRR. Compenastion of 2stage OP-Amp, Other compensation techniques. 10 Hrs

Unit 5: Oscillators: Ring Oscillators, LC Oscillators, VCO, Mathematical Model of VCO. PLL: Simple PLL, Charge pump PLL, Non-ideal effects in PLL, Delay locked loops and applications. Bandgap References and Switched capacitor filters. 10 Hrs



TEXT BOOKS : 1.“Design of Analog CMOS Integrated Circuits”, Behzad Razavi, TMH, 2007. Course Outcome (CO) After learning all the units of the course, the student is able to: 1. Describe the physics of MOSFETs that is necessary for basic analog design & low frequency

behaviour of single stage amplifiers and analysis of different parameters using small signal and large signal analysis. L1 (Unit – I).

2. Explain the importance of current sources in single stage and differential amplifiers and design of current mirrors, differential amplifier design and analysis and Gilbert cell operation. – L2 (Unit – II)

3. Explain the common class of discrete time system called switched capacitor circuits. L2 (Unit – III) 4. Design the CMOS oscillators such as VCOs. – L5 (Unit – IV) 5. Design the PLLs using CMOS technology. – L5 (Unit – V) 6. .Classify the different types of PLLs. – L2 (Unit – V)



Course Title : LOW POWER VLSI DESIGN

Course Code: P15MECE22 Semester : II (L:T:P:H : 4:0:0:4)

Contact Period :Lecture :52 Hr, Exam: 3Hr Weightage :CIE:50%SEE:50%

Course Learning Objectives (CLO): At the end of the course the students should be able to:

1. Provide the basic knowledge of power dissipation in CMOS devices. 2. Explain the Technology Impact on Low Power. 3. Describe the Power estimation and Simulation Power analysis. 4. Provides the knowledge of Probabilistic power analysis. 5. Outline the concepts of Low Power Design in Circuit level. 6. Illustrate the concepts of Low power Architecture & Systems. 7. Discuss the concepts of Low power Clock Distribution. 8. Discuss the various Algorithm & Architectural Level Methodologies.

Course Content

Unit 1: Introduction: Need for low power VLSI chips, Sources of power dissipation on Digital Integrated circuits. Emerging Low power approaches, Physics of power dissipation in CMOS devices. Device & Technology Impact on Low Power: Dynamic dissipation in CMOS, Transistor sizing & gate oxide thickness, Impact of technology Scaling, Technology & Device innovation. 11 Hrs Unit 2: Power estimation, Simulation Power analysis: SPICE circuit simulators, gate level logic simulation, capacitive power estimation, static state power, gate level capacitance estimation, architecture level analysis, data correlation analysis in DSP systems, Monte Carlo simulation. 10 Hrs Unit 3: Probabilistic power analysis: Random logic signals, probability & frequency, probabilistic power analysis techniques, signal entropy. Low Power Design Circuit level: Power consumption in circuits. Flip Flops & Latches design, high capacitance nodes, low power digital cells library. 10 Hrs Unit 4: Logic level: Gate reorganization, signal gating, logic encoding, state machine encoding, pre-computation logic Low power Architecture & Systems: Power & performance management, switching activity reduction, parallel architecture with voltage reduction, flow graph transformation, low power arithmetic components, low power memory design. 10 Hrs Unit 5: Low power Clock Distribution: Power dissipation in clock distribution, single driver Vs distributed buffers, Zero skew Vs tolerable skew, chip & package co design of clock network Algorithm & Architectural Level Methodologies: Introduction, design flow, Algorithmic level analysis & optimization, Architectural level estimation & synthesis. 11 Hrs



TEXT BOOKS: 1.Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit Design” Wiley, 2000 2. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP, 2002 3. Rabaey, Pedram, “Low Power Design Methodologies” Kluwer Academic, 1997 Course Outcome (CO) After learning all the units of the course, the student is able to

1. Explain the Sources of power dissipation on Digital Integrated circuits.- L2(Unit-I) 2. Discuss the Transistor sizing & gate oxide thickness.-L2(Unit-I) 3. Describe the Impact of technology Scaling.-L1 (Unit-I) 4. Analyze the concepts gate level logic simulation.-L4(Unit-II) 5. Illustrate the data correlation analysis in DSP systems.-L4(Unit-II) 6. Describe the probabilistic power analysis techniques.-L1(Unit-III) 7. Outline the Power consumption in circuits.-L2(Unit-III) 8. Explain the various concepts of Gate reorganization.-L3(Unit-IV) 9. Discuss the various concepts of Power & performance management.-L2(Unit-IV) 10. Explain the various concepts of Power dissipation in clock distribution.-L2(Unit-V) 11. Analyze the circuit in its Algorithmic level and circuit optimization.-L4(Unit-V)



Course Title : REAL TIME OPERATING SYSTEMS


Contact Period : Lecture :52 Hr,Exam: 3Hr Weightage :CIE:50%SEE:50%

Course Learning Objectives (CLOs) After learning all the units of the course, the student is able to 1. Provide the basic knowledge of Real-Time Embedded Systems 2. Explain the concept of Resource Analysis, Real-Time Service Utility, and Scheduling Classes. 3. Provide the understanding of Preemptive Fixed-Priority Policy. 4. Highlight the nature of memory, Capacity and allocation, Shared Memory, ECC Memory, Flash file systems. 5. Outline the concepts of Deadlock and livestock, Critical sections. 6. Provide the knowledge of RTOS system software mechanisms, Software application components. 7. Illustrate the procedure for calculation of High availability and Reliability Design.


Introduction to Real-Time Embedded Systems: Brief history of Real Time Systems, A brief history of Embedded Systems. System Resources: Resource Analysis, Real-Time Service Utility, Scheduling Classes, The Cyclic Esecutive, Scheduler Concepts, Preemptive Fixed Priority Scheduling Policies, Real-Time OS, Thread Safe Reentrant Functions. 10 Hrs

Unit 2: Processing: Preemptive Fixed-Priority Policy, Feasibility, Rate Montonic least upper bound, Necessary and Sufficient feasibility, Deadline – Monotonic Policy, Dynamic priority policies. I/O Resources: Worst-case Execution time, Intermediate I/O, Execution efficiency, I/O Architecture. Memory: Physical hierarchy, Capacity and allocation, Shared Memory, ECC Memory, Flash file systems. 11 Hrs

Unit 3: Multi-resource Services: Blocking, Deadlock and livestock, Critical sections to protect shared resources, priority inversion. Soft Real-Time Services: Missed Deadlines, QoS, Alternatives to rate monotonic policy, Mixed hard and soft real-time services. 10 Hrs

Unit 4: Embedded System Components: Firmware components, RTOS system software mechanisms, Software application components. Debugging Components: Execptions assert, Checking return codes, Single-step debugging, kernel scheduler traces, Test access ports, Trace ports, Power-On self test and diagnostics, External test equipment, Application-level debugging. 10 Hrs



Unit 5: Performance Tuning: Basic concepts of drill-down tuning, hardware – supported profiling and tracing, Building performance monitoring into software, Path length, Efficiency, and Call frequency, Fundamental optimizations. High availability and Reliability Design: Reliability and Availability, Similarities and differences, Reliability, Reliable software, Available software, Design trade offs, Hierarchical applications for Fail-safe design. Design of RTOS – PIC microcontroller. (Chap 13 of book MykePredko) 11 Hrs TEXT BOOK: 1. “Real-Time Embedded Systems and Components” ,Sam Siewert, Cengage Learning India Edition, 2007. 2. “Programming and Customizing the PIC microcontroller” ,MykePredko, 3rd Ed, TMH, 2008. 3. “Programming for Embedded Systems”, Dreamtech Software Team, Jhon Wiley, India Pvt. Ltd., 2008. Course outcomes After learning all the units of the course, the student is able to

1. Explain the basics of Real-Time Embedded Systems-L2(unit 1) 2. Discuss the various concepts of I/O resources ,memory and processing -L2(unit 2) 3. Analyze Deadlock and livestock, Critical sections to protect shared resources, priority inversion,

Mixed hard and soft real-time services-L4(unit 3) 4. Summarize the Firmware components, RTOS system software mechanisms, Software application

components,, Single-step debugging, kernel scheduler traces, -L2(unit 4) 5. Explain the basic concepts of drill-down tuning, hardware – supported profiling, Building

performance monitoring into software and Fundamental optimizations. -L2(unit 5) 6. Discuss the Reliability, Reliable software, Available software, Design trade offs, Hierarchical

applications for Fail-safe design.-L2(unit 5)



ELECTIVE III

Course Title : ADVANCED MICROCONTROLLER



Course Learning Objectives (CLOs) After learning all the units of the course, the student is able to 1. Provide the basic knowledge of advanced microcontrollers. 2. Explain the concept of MSP430 – 16-bit Microcontroller family. 3. Provide the understanding of basic Timer, Real Time Clock (RTC), ADC, DAC, Digital I/O. 4. Highlight the nature of low-power features of MSP430. 5. Outline the concepts of 32 bit Microcontroller family. Architecture and ARM Cortex M3. 6. Provide the knowledge of Advanced Programming Features and Memory Protection. 7. Illustrate the procedure for Low-Power RF circuits.


Motivation for advanced microcontrollers – Low Power embedded systems, On-chip peripherals, low-power RF capabilities. Examples of applications. 10 Hrs

Unit 2:

MSP430 – 16-bit Microcontroller family. CPU architecture, Instruction set, Interrupt mechanism, Clock system, Memory subsystem, bus –architecture. The assembly language and ‘C’ programming for MSP-430 microcontrollers.On-chip peripherals. WDT, 11 Hrs

Unit 3:

Comparator,Op-Amp, Timer, Basic Timer, Real Time Clock (RTC), ADC, DAC, Digital I/O. Using the low-power features of MSP430. Clock system, low-power modes, Clock request feature, Low-power programming and interrupts. 10 Hrs

Unit 4: ARM -32 bit Microcontroller family. Architecture of ARM Cortex M3 – General Purpose Registers, Stack Pointer, Link Register, Program Counter, Special Register,. Nested Vector Interrupt Controller. Interrupt behavior of ARM Cortex M3. 10 Hrs

Unit 5:

Exceptions Programming.Advanced Programming Features.Memory Protection. Debug Architecture. Applications – Wireless Sensor Networking with MSP430 and Low-Power RF circuits; Pulse Width Modulation(PWM) in Power Supplies. 11 Hrs



TEXT BOOKS: 1.JosephYiu “ The Definitive Guide to the ARM Cortex-M3, , Newnes, (Elsevier), 2008. 2.John Davies, “ MSP430 Microcontorller Basics”, Newnes (Elsevier Science), 2008.

Course outcomes

After learning all the units of the course, the studentis able to 1. Explain the basics of 16-bit microcontrollers-L2(unit 1) 2. Discuss the various concepts of MSP430 -L2(unit 2) 3. Write the assembly language and ‘C’ programming for MSP-430 microcontrollers-L2 (unit 2) 4. Summarize the Basic Timer, Real Time Clock (RTC), ADC, DAC, Digital I/O -L2(unit 3) 5. Discuss theArchitecture of ARM Cortex M3 family. -L2(unit 4) 6. Explain the Advanced Programming Features and applications of Low-Power RF circuits.-L2(unit 5)




This course aims to 1. 1 Provide the basic knowledge of designing system in terms of throughput, speed and other

system considerations. 2. Explain various ADC and DAC converters. 3. Design of high speed ADC for radar application. 4. Design of high speed DAC using mixed signal for radar application. 5. Explain frequency synthesizer in the design of PLL. 6. Design of PLL synthesizer using oscillator. 7. Describe various sensor types related to mixed signal. 8. Illustrate the interfacing of transducers for temperature, pressure, displacement. 9. Explain the different types of LCD panels and infrared detection. 10. Discuss measuring period versus frequency and voltage to frequency converters.


INTRODUCTION TO SYSTEM DESIGN: Dynamic Range, Calibration, Bandwidth, Processor Throughput, Avoiding Excess Speed Other System Considerations, Sample Rate and Aliasing 10 Hrs

Unit 2: DAC & ADC Introduction: Converters - High speed ADC design, High speed DAC design and Mixed signal design for radar application - ADC and DAC modules used for LIGO 10 Hrs

Unit 3: PLL: Introduction - Frequency Synthesizers - Design of PLL and Frequency Synthesizers – PLL with voltage driven oscillator- PLL with current driven oscillator- ETPLL – PLL synthesizer oscillator by MC14046B 11 Hrs

Unit 4: SENSOR INTERFACING: Sensors, Sensor Types, Amplifier Design, Interfacing of Temperature, Pressure, Displacement Transducer in Embedded System Environment. LCD AND INFRA RED: LCD Fundamentals, Response Time, Temperature Effects, Connection Methods, Different types of LCD Panels, Static Waveforms, Infra Red Detection and Transmission 11 Hrs

Unit 5: TIME-BASED MEASUREMENTS: Measuring Period versus Frequency, Mixing, Voltage-to-Frequency Converters, Clock Resolution and Range, Extending Accuracy with Limited Resolution 10 Hrs

Course Title: Interfacing of Mixed signal Embedded system.

Course Code:P15MECE242 Semester : II (L:T:P:H : 4:0:0:4)




TEXT BOOKS:

1. Analog Interfacing to Embedded Microprocessors Real World Design, Stuart Ball. 2. Breems, “Continuous-Time Sigma Delta Modulations for A/D Conversion”, Kluwer, 2002. 3. Allen, “CMOS Analog Circuit Design”, Oxford, 2005. 4. Behzad Razavi, “Design of Analog CMOS integrated circuit”, Tata McGraw Hill.

Course Outcome (CO) After learning all the units of the course, the student is able to 1. Define dynamic range, calibration, throughput and bandwidth in context to mixed signal system

design.-L1(Unit-I). 2. Explain sample rate and aliasing in system design.-l2(Unit-I). 3. Illustrate the ADC and DAC modules used for LIGO.-L3(Unit-II) 4. Explain different ADC and DAC converters for radar applications.-L2(Unit-II) 5. Design of PLL and frequency synthesizers.-L5(Unit-III) 6. Explain different sensor types in context to interfacing.-L2(Unit-I(Unit-IV) 7. Define response time related to LCD and temperature effects.-L1(Unit-IV) 8. Explain different types of LCD panels and infrared detection-L2(Unit-IV) 9. Discuss measuring period versus frequency –L2(Unit-V) 10. Explain the voltage to frequency converters-L2 (Unit-V)



Course Title : EMBEDDED SYSTEM DESIGN WITH FPGA




After learning all the units of the course, the student is able to 1. Provides basic knowledge of embedded system. 2. Explain the computer hardware and software. 3. Illustrate the concept of the SAYEH Design and Test. 4. Describe the concept of Field Programmable gate arrays . 5. Explain the embedded system design tools and design protyping. 6. Describe the various concept of design of utility hardware cores. 7. Explain the concepts of embedded design steps. 8. Estimate the concept of FIR Filter Hardware Implementation. 9. Outline the concept of design of embedded system.

10. Explain the Building Calculator Software and Calculator Program,.

Course Content Unit I

COMPUTER HARDWARE AND SOFTWARE: Computer System, Computer Software, Machine Language, Assembly Language, High-Level Language, C Programming Language, Instruction Set Architecture, SMPL-CPU Design, CPU Specification, Single-Cycle Implementation, Multi-Cycle Implementation, SAYEH Design and Test, Details of Processor Functionality, SAYEH Datapath, SAYEH Verilog Description, SAYEH Top-Level Testbench / Assembler,SAYEH Hardware Realization 10 Hrs

Unit II FIELD PROGRAMMABLE DEVICES : Read Only Memory, Basic ROM Structure, NOR Implementation, Distributed Gates, Array Programmability, Memory View, ROM Variations, Programmable Logic Arrays, PAL Logic Structure, Product Term Expansion, Three-State Outputs, Registered Outputs, Commercial Parts, Complex Programmable Logic Devices, Altera's MAX 7000S CPLD, Field Programmable gate arrays, Altera's FLEX 10K DOGMA, Altera's cyclone DOGMA. 10 Hrs

Unit III TOOLS FOR DESIGN AND PROTOTYPING: Hardware Design Flow, Datapath of Serial Adder, Serial Adder Controller, HDL Simulation and Synthesis, Pre-Synthesis Simulation, Module Synthesis, Post-Synthesis Simulation, Mixed-Level Design with Quartus II, Project Specification, Block Diagram Design File, Creating and Inserting Design Components, Wiring Design Component, Design Compilation, Design Simulation, Synthesis Results, Design Prototyping, UP3 Board Specification, DE2 Board Specification, Programming DE2 Cyclone II.

10 Hrs Unit IV

DESIGN OF UTILITY HARDWARE CORES: Library Management, Basic IO Device Handling, Debouncer, Single Stepper, Utilizing UPS Basic IO, Utilizing DE2 Basic IO, Frequency Dividers, Seven Segment Displays, SSD Driver, Testing DE2 SSD



Driver, LCD Display Adapter, Writing into LCD, LCD Initialization, Display Driver with Initialization, Testing the LCD Driver (UPS), Testing the LCD Driver (DE2), Keyboard Interface Logic, Serial Data Communication, Power-On Routine, Codes and Commands, Keyboard Interface Design, VGA Interface Logic, VGA Driver Operation, Monitor Synchronization Hardware, Character Display, VGA Driver for Text Data, VGA Driver Prototyping (UPS), VGA Driver Prototyping (DE2) . DESIGN WITH EMBEDDED PROCESSORS: Embedded Design Steps, Processor Selection, Processor Interfacing, Developing Software, Filter Design, Filter Concepts, FIR Filter Hardware Implementation, FIR Embedded Implementation, Building the FIR Filter, Design of a Microcontroller, System Platform, Microcontroller Architecture. 11 Hrs

Unit V DESIGN OF AN EMBEDDED SYSTEM: Designing an Embedded System, Nios II Processor, Configurability Features of Nios II, Processor Architecture, Instruction Set,Nios II Alternative Cores, Avalon Switch Fabric, Avalon Specification, Address Decoding Logic, Data-path Multiplexing, Wait-state Insertion, Pipelining, Endian Conversion, Native Address Alignment and Dynamic Bus Sizing, Arbitration for Multi-Master Systems, Burst Management, Clock Domain Crossing, Interrupt Controller, Reset Distribution, SOPC Builder Overview, Architecture of SOPC Builder Systems, Functions of SOPC Builder, IDE Integrated Development Environment, IDE Project Manager, Source Code Editor, C/C++ Compiler, Debugger , Flash Programmer, An Embedded System Design: Calculator, System Specification, Calculating Engine, Calculator IO interface, Design of Calculating Engine, Building Calculator Software, Calculator Program, Completing the Calculator System. 11 Hrs TEXT BOOK 1. “Digital Design: An Embedded Ssytems Approach Using VERILOG”, Peter J. Ashenden, Elesvier, 2010. Course Outcomes (CO) After learning all the units of the course, the student is able to

1. Explain the concept of Machine Language, Assembly Language, High-LeveI Language.-L2(Unit-I) 2. Illustrate the concept of SAYEH Top-Level Testbench / Assembler.-L3(Unit-I) 3. Describe the structure of PLA and PAL arrays.-L2(Unit-II) 4. Explain the concept of Altera's MAX 7000S CPLD.-L2(Unit-II) 5. Estimate the HDL Simulation and Synthesis.-L2(Unit-III) 6. Outline the concept of UP3 Board Specification.-L1(Unit-IV) 7. Write a short note on LCD Initialization.-L3(Unit-IV) 8. Explain the FIR Filter Hardware Implementation.-L2(Unit-IV) 9. Write a note on Data-path Multiplexing.-L3 (Unit-V) 10. Describe the concept of IDE Integrated Development Environment.-L2 (Unit-V)



ELECTIVE IV

Course Learning Objectives (CLOs) After learning all the units of the course, the student is able to 1. Provide the basic knowledge of C, C++ and Verilog. 2. Describe the Verification basics, Testbenches, Layered Organization of Testbenches. 3. Explain the System Verilog data types and typedefs 4. Provide the basic understanding of System Verilog operators, loops, jumps, functions 5. Explain the system Verilog Class and Randomization. 6. Describe the various types of Interfaces. 7. Outline the concepts of Program block. 8. Describe the various types of verilog clocking.. 9. Outline the concepts of System Verilog assertions.

Course Content

Unit I Basics of Verification: Difference between ASIC verification and ASIC testing, Verification basics, Testbenches, Layered Organization of Testbenches. Importance of hardware verification languages and methodologies. System Verilog data types and typedefs: System Verilog data types enhanced literal numbers syntax, 4-state and 2-state types, typedefs, enum, struct data type, Type parameters, $unit and $root. Packages, strings, static and dynamic type casting, Random number generation. 10 Hrs

Unit II

System Verilog operators, loops, jumps, functions: loops and jumps in system verilog, introduction to different always blocks, system verilog enhancements to tasks and functions, system verilog priority and unique modifiers for case and if statements, ‘time scale, system verilog time unit and time precision. Structs, Unions, Packed and Unpacked Arrays, Semaphores and Mailboxes: Structs and its assignments, packed and unpacked arrays, array indexing, structs and packed structs, Unions and packed unions, dynamic arrays and methods, for each loop, associative arrays and methods, queues and concatenation operations, queue methods, semaphores and methods, mailboxes and methods, bounded and unbounded mailboxes. 11 Hrs

Unit III

Class and Randomization: System verilog class basics, class declaration, class members and methods, class handles, class object construction, super and this keywords, object handles, user defined constructors, class extension and inheritance, chaining new() constructors, overriding class methods, extending class methods, local and protected keywords, constrained random variables, directed vs random testing, rand and randc class data types, randomize-randomizing class variables, random case, built-in-randomization methods, random sequence and examples.

Course Title : System Verilog





Interfaces: Interface overview, generic interfaces, interfaces vs records, how interfaces work, requirements of good interface, interface constructs, interface mode ports. 11 Hrs

Unit IV Program block: Fundamental testbench construction, program blocks, program block interaction with modules, final blocks, Testbench stimulus/Verification vector timing strategies. Constrained Random variables, Coverage, Methods and interfaces: Randomization constraints, simple and multi-statement constraints, constraint distribution and set membership, constraint distribution operators, external constraints, covergroups, coverpoints, coverpoint bins and labels, cross coverage, covergroup options, coverage capabilities. Virtualclass, why to use virtual class, virtual class methods and restrictions, polymorphism using virtual methods, pure virtual methods, pure constraints, passing type parameters, virtual interfaces. 10 Hrs

Unit V Clocking: Clocking blocks, clocking skews, clocking block scheduling, fork-join processes. System Verilog assertions :Assertion definition, assertion benefits, system Verilog assertion types, immediate assertions, concurrent assertions, assert and cover properties and labels, overlapping and non-overlapping implications, edge testing functions, sequences, Vacuous success, property styles, System Verilog assertion system functions, Assertion severity tasks, assertion and coverage example of an FSM design. 10 Hrs Text Books: 1. Christian B Spear, “ SystemVerilog for Verification: A guide to learning the Testbench language features”, Springer publications, 3 rd edition. 2. VijayaRaghavan, “SystemVerilog Assertions”, Springer publications, 2005 3. Sutherland, “ Systemverilog for Design”, Springer publications


1. Describe the Verification basics, and Importance of hardware verification languages and methodologies.-L1 (Unit-I)

2. Illustrate the various concepts of System Verilog data types and typedefs.-L4 (Unit-I) 3. Explain theSystem Verilog operators, loops, jumps, functions.-L2 (Unit-II) 4. Describe the Structs, Unions, Packed and Unpacked Arrays, Semaphores and Mailboxes.-L1

(Unit-II) 5. Explain the system verilog classes and randomization.-L2 (Unit-III) 6. Illustrate the various concepts of verilog interfaces.-L4 (Unit-III) 7. Explain the various types of Program blocks.-L2 (Unit-IV) 8. Describe the Constrained Random variables, Coverage, Methods and interfaces.-L1 (Unit-IV) 9. Illustrate the various types of Clocking.-L4 (Unit-V) 10. Explain the System Verilog assertion system functions.-L2 (Unit-V)



Course Title : DESIGN OF VLSI SYSTEMS


Contact Period : Lecture:52Hr,Exam:3Hr Weightage:CIE:50%SEE:50%

Course Learning Objectives (CLOs) After learning all the units of the course, the student is able to 1. Provide the basic knowledge of VLSI system design 2. Explain the concept of VLSI System Design Methodology and Chip Design Methods. 3. Provide the understanding of Design Capture Tools. 4. Highlight the concept of Data Path Sub System Design and Array Subsystem Design 5. Outline the concepts of Control Unit Design and Special Purpose Subsystems. 6. Provide the knowledge of Design Economics,VLSI System Testing & Verification 7. Outline the concepts of VLSI Applications.

Course contents Unit 1:

VLSI System Design Methodology: Structure Design, Strategy, Hierarchy, Regularity, Modularity, and Locality. System on Chip Design options: Programmable logic and structures, Programmable interconnect, programmable gate arrays, Sea of gate and gate array design, standard cell design, full custom mask design. Chip Design Methods: Behavioral synthesis, RTL synthesis, Logic optimization and structural tools layout synthesis, layout synthesis, EDA Tools for System 11 Hrs

Unit 2: Design Capture Tools: HDL Design, Schematic Design, Layout Design, Floor planning and Chip Composition. Design Verification Tools: Simulation Timing Verifiers, Net List Comparison Layout Extraction, Design Rule Verification. 10 Hrs

Unit 3: Data Path Sub System Design: Introduction, Addition, Subtraction, Comparators, Counters, Boolean logical operations, coding, shifters, Multiplication, Parallel Prefix computations. Array Subsystem Design: SRAM, Special purpose RAMs, DRAM, Read only memory, Content Addressable memory, Programmable logic arrays. 10 Hrs

Unit 4: Control Unit Design: Finite State Machine (FSM) Design, Control Logic Implementation: PLA control implementation, ROM control implementation. Special Purpose Subsystems: Packaging, power distribution, I/O, Clock, Transconductance amplifier, follower integrated circuits, etc. 10 Hrs

Unit 5:

Design Economics: Nonrecurring and recurring engineering Costs, Fixed Costs, Schedule, Person power, example VLSI System Testing & Verification: Introduction, A walk through the Test Process, Reliability, Logic Verification Principles, Silicon Debug Principles, Manufacturing Test Principles, Design for Testability, Boundary Scan VLSI Applications: Case Study: RISC microcontroller, ATM Switch, etc. 11 Hrs



TEXT BOOKS: 1. Neil H.E. Weste, Davir Harris, “CMOS VLSI Design: A Circuits and System Perspectives”

Addison Wesley - Pearson Education, 3rd Edition, 2004. 2. Wayne, Wolf, “Modern VLSI Design: System on Silicon” Prentice Hall PTR/P

syllabus · vlsi design and embedded systems p.e.s. college of engineering, mandya - 571 401,...

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