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Vivekananda College of Engineering and TechnologyPuttur (D.K)

Analog and Digital Electronics Laboratory Manual

15CSL 37

Author

Prof. Mahesh Prasanna K

Assoc. Professor & Head, CSE

[email protected]

© Vivekananda College of Engineering & Technology, Puttur (D.K)

Directions to use PSPICE:Go to: Start → Programs → Cadence → OrCAD Capture CIS

Select: File → New → Project → (Enter the Project name, and select Analog or Mixed

A/D)

Select: Place → Part ( select the required components)

Select: Place → Wire ( connect the components using wire)

Select: Place → Ground (to ground the circuit)

Select: PSPice → New simulation ( create a new simulation profile)

Set the 'Run to time' as t= 1/ f (f= frequency of input waveform)

Set the 'Maximum step size' as: 0.0001m

Check the 'Skip the Initial Transients bias point calculation' box

Select: PSPice → Run

Introduction to Xilinx

Xilinx is one of most popular software tool used to synthesize VHDL/Verilog code. This toolincludes many steps. To make user feel comfortable with the tool the steps are given below:-

• Double click on Project navigator. (Assumed icon is present on desktop).

• Select NEW PROJECT in FILE MENU.

• Enter following details in New Project Wizard – Create New Project window –

Project name : PANNA

Project location : C:\Xilinx\PANNA

Top-Level source type : HDL

• Click Next.

• Enter following details in New Project Wizard – Device Properties window –

Product Category : All

Device family : Spartan3

Device : XC3S200

Package : FT256

Speed : - 4

Top-Level Source Type : HDL

Synthesis Tool : XST (VHDL/Verilog)

Simulator : ISE Simulator (VHDL/Verilog)

Preferred Language : Verilog

• Enable Enhanced Design Summary and Click Next for three times and finally Click Finish.

• In Sources window Right Click on xc3s200-4ft256, select New Source…

Enter the following details in New Source Wizard – Select Source Type window –

File name : and_gate


Location : C:\Xilinx\PANNA

Select Verilog Module

• Enable Add to project and Click Next.

• Enter the following details in New Source Wizard – Define Module window –

a select as ‘in’

b select as ‘in’

c select as ‘out’

• Click Next. Check the Summary and Click Finish.

• Now, and_gate.vhd file is created. Enter the code as c <= a and b;

• Click on Save all.

• Go to Sources for > Synthesis/Implementation. Select and_gate in Sources window.

• Go to Processes window: Click on ‘+’ against Synthesize – XST. Double click on “CheckSyntax”.

• Double click on “View Technology Schematic” to see Truth-Table & k-map; and close thatwindow.

• Double click on “View RTL Schematic” to see the Gate; and close that window.

• In Sources window, Right Click on and_gate.vhd, select New Source…

Enter the following details in New Source Wizard – Select Source Type window –Select Test Bench Waveform

File name : and_gate_bench

Location: C :\Xilinx\PANNA

• Enable Add to project and Click Next.

• In New Source Wizard – Associate Source window, - associate and_gate file and ClickNext; and finally Click Finish.

• Enter the following in Initial Timing and Clock Wizard – Initialize Time window –

Select Global Signal as (GSR) FPGA – High for initial 100 ns.

Clock Information: Select Combinational (or internal clock)

Check outputs 50 ns After Inputs are Assigned.

Assign Inputs 50 ns After Outputs are Checked.

Initial Length of Test Bench: 1000 ns

Time Scale: ns

Click Finish.

• Set input waveforms and Save all.

• Go to Sources for > Behavioral Simulation. Verify that and_gate_bench.tbw is selected inthe Sources window.

• Go to Processes window: Click on ‘+’ against Xilinx ISE Simulator and Double Click“Simulator Behavioral Model”.

• Check the output waveform.


7. CONTENTS:ExptNo.

Title of the Experiments

1a) Design and construct a Schmitt trigger using Op-Amp for given UTP and LTP values anddemonstrate its working.b) Design and implement a Schmitt trigger using Op-Amp using a simulation package for twosets of UTP and LTP values and demonstrate its working.

2

a) Design and construct a rectangular waveform generator (Op-Amp relaxation oscillator) forgiven frequency and demonstrate its working.b) Design and implement a rectangular waveform generator (Op-Amp relaxation oscillator)using a simulation package and demonstrate the change in frequency when all resistor valuesare doubled.

3Design and implement an Astable multivibrator circuit using 555 timer for a given frequencyand duty cycle.

4Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using basicgates.

5

a)Given a 4-variable logic expression, simplify it using Entered Variable Map and realize thesimplified logic expression using 8:1 multiplexer IC.b) Design and develop the Verilog /VHDL code for an 8:1 multiplexer. Simulate and verify itsworking.

6Design and implement code converter I)Binary to Gray II) Gray to Binary Code using basicgates.

7Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker usingbasic Logic Gates with an even parity bit.

8a) Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table.b) Design and develop the Verilog / VHDL code for D Flip-Flop with positive-edge triggering.Simulate and verify its working.

9

a) Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs anddemonstrate its working.b) Design and develop the Verilog / VHDL code for mod-8 up counter. Simulate and verify itsworking.

10Design and implement an asynchronous counter using decade counter IC to count up from 0 ton (n<=9) and demonstrate on 7-segment display (using IC-7447).

11Generate a Ramp output waveform using DAC0800 (Inputs are given to DAC throughIC74393 dual 4-bit binary counter).

12 Open ended experiment – 1: To study 4-bit ALU using IC-74181.

EXPERIMENTS1. EXPERIMENT NO: 012. TITLE: SCHMITT TRIGGER 3. LEARNING OBJECTIVES:

• To learn about the Op-Amp based Schmitt trigger circuit and understand its working. • To learn simulation of Op-Amp based Schmitt trigger circuit.

4. AIM:• To design and implement an inverting Schmitt trigger using Op-Amp for a given UTP and

LTP values. .• To implement a Schmitt trigger using Op-amp using a simulation package for two sets of

UTP and LTP values. 5. MATERIAL / EQUIPMENT REQUIRED:

S. No Components/Equipments Specification/No Quantity

1 Op-Amp uA741 1

2 Resistor 10K 1


1K 2

3 DC Regulated Power Supply - 1

4 Signal Generator - 1

5 CRO - 1

6. THEORY / HYPOTHESIS:Schmitt Trigger converts an irregular shaped waveform to a square wave or pulse. Here, theinput voltage triggers the output voltage every time it exceeds certain voltage levels calledthe upper threshold voltage VUTP and lower threshold voltage VLTP. The input voltage isapplied to the inverting input. Because the feedback voltage is aiding the input voltage, thefeedback is positive. A comparator using positive feedback is usually called a SchmittTrigger. Schmitt Trigger is used as a squaring circuit, in digital circuitry, amplitudecomparator, etc.

7. PROCEDURE / PROGRAMME / ACTIVITY: 1. Test all the components.2. Rig up the circuit according to the circuit diagram.3. Apply VCC =12V, VEE = -12V.

4. Apply a sinusoidal signal of peak voltage say 5V, with a frequency of 500Hz.5. Observe the rectangular output on the CRO, measure the UTP and LTP values, comparethem with the design values.6. Keep the CRO in X-Y mode (Vin to X-channel, Vout to Y-channel). Observe the transfercurve which is called the Hysteresis curve.

8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:• a) Hardware Implementation


b) SimulationCase 1: UTP =_____V, LTP = ______V

Case 2: UTP =_____V, LTP = ______V

9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: a)

1. Vin-p =_________ V

2. Input period T =________ mS3. UTP = _________ V


4. LTP =__________ V5. +Vsat =___________V

6. –Vsat =_________ V

b) Case 1: UTP= ___________V, LTP= V

Case 2: UTP = V , LTP = 10. FORMULA / CALCULATIONS:

UTP(Upper Trip Point) is the point in the raising part of input waveform, at which theoutput voltage changes state . LTP (Lower Trip Point) is the point in the falling part of theinput waveform, at which the output changes state. The above state change of output occurswhen the input voltage crosses Vref

UTP = BVsatLTP = -BVsat

Where B is called the feedback fraction. It is the part of the output voltage fed back to theinput (pin 3)

B = R2/ (R1+R2)(by potential divider principle)

+Vsat : It is the output voltage. Ideally it is either +Vcc or –VEE respectively. (Practically it

will be a little less than this value)

Let us design an inverting Schmitt trigger for a UTP =+1V and LTP = -1VLet VCC = +12V (= +Vsat)

VEE= -12V (= -Vsat) , R2 =1K

We know UTP = +BVsat , ie 1V= (R2 /(R1 + R2))12V

ie 1 = 1K/ (R1 + 1K )* 12

R1 + 1K =12K

R1=12K -1K = 11K

The above design will set an LTP = -1V11. GRAPHS / OUTPUTS:

12. RESULTS & CONCLUSIONS:a)The difference between UTP and LTP is defined as Hysteresis is:H=UTP – LTP =_______V - V = __________V

13. LEARNING OUTCOMES :• Hence from this experiment we can conclude that Opamp Schmitt trigger circuit converts

sine wave to square wave for a given threshold voltage.• Simulation results of Op Amp Schmitt trigger circuit matches with practical values.

14. APPLICATION AREAS:• Function Generator.• Noise immunity and Oscillator.


15. REMARKS:•••

-1. EXPERIMENT NO: 22. TITLE: RELAXATION OSCILLATOR3. LEARNING OBJECTIVES:

• To learn about the rectangular waveform generator circuit and understand its working. • To learn to implement a rectangular waveform generator using a simulation package.

4. AIM:• To design and implement a rectangular waveform generator(op-amp relaxation oscillator)

for a given frequency.• To implement a rectangular waveform generator (Op-amp relaxation oscillator) using a

simulation package, and observe the change in frequency when all the resistors values aredoubled

5. MATERIAL / EQUIPMENT REQUIRED:


1 Op-Amp uA741 1

2 Resistor 1K,10K, 1.8K 1 each

3 Capacitor 0.1u 1

4 Regulated Power Supply - 2

5 CRO - 1

6. THEORY / HYPOTHESIS:As the name indicates, here there is no input signal, but circuit produces a square waveoutput that swings between +Vsat and –Vsat. The capacitor charges through the feedbackresistor R, exponentially towards +Vsat. But capacitor voltage never reaches +Vsat becausethe voltage crosses the UTP. When this happens the output wave switches to –Vsat. Withthe output now in negative saturation, the capacitor discharges. When the capacitor voltagecrosses through zero, the capacitor starts charging negatively toward –Vsat.When thecapacitor voltage crosses the LTP, output switches back to +Vsat. The above events repeat,resulting in rectangular output.

7. PROCEDURE / PROGRAMME / ACTIVITY: 1. Check all the components2. Rig-up the circuit according to the circuit diagram.3. Apply +Vcc of say 15V and –VEE of -15V.

4. Connect the CRO channel-1 across the capacitor and channel-2 across the output.5. Observe the output rectangular waveform and capacitor waveform.6.Calculate the period of the waveform, T.7. Note down the out put voltage (+Vsat and –Vsat) and UTP and LTP voltages.(Observed Vsat will be < +Vcc and | - Vsat | < | -VEE |)

8. Draw the graph of the output waveform and the capacitor voltage waveform.


8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:

a) Hardware Implementation

b) SimulationCase 1: for the original circuit

Case 2: Circuit with all resistors doubled


9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:a)

i) Period, T = msii) +Vsat = V iii) -Vsat = - Viv) UTP = + Vv) LTP = - V

b)

Case 1: Period of the output waveform = ___________ms Frequency f = ___________Hz

Case 2: With all resistors doubled: Period of the output waveform =____________ms

Frequency f = ___________Hz

10. FORMULA / CALCULATIONS:


11. The output is a rectangular wave with a duty cycle of 50 %. (i.e., high duration = low duration). The period of the output wave is given by,

Let us choose R1= 1.8KΩ.

The maximum voltage across the capacitor is the UTP and minimum voltage across the capacitor is the LTP.UTP = +BVsat and LTP = -BVsatThe output waveform swings between +Vsat and –Vsat)

11. GRAPHS / OUTPUTS:

12. RESULTS & CONCLUSIONS:• Frequency of output waveform =1/T = Hz • Frequency of output waveform in simulation=1/T = Hz

13. LEARNING OUTCOMES :• From this experiment we can conclude that relaxation oscillator can be used to generate

rectangular waveforms of desired frequency.• Relaxation oscillator circuit can be simulated using PSPICE simulator and the results are

matching with the practical values.14. APPLICATION AREAS:

• Voltage controlled oscillators (VCOs)


https://en.wikipedia.org/wiki/Voltage_controlled_oscillator

• Switching power supplies.• Dual-slope analog to digital converters.• function generators.


-1. EXPERIMENT NO: 032. TITLE: ASTABLE MULTIVIBRATOR3. LEARNING OBJECTIVES:

• To learn about the astable multivibrator circuit using 555 timer for a given frequency andduty cycle.

4. AIM:• To design and implement an Astable multivibrator using 555 timer, for a given frequency

and duty cycle.5. MATERIAL / EQUIPMENT REQUIRED:


1 Timer NE 555 1

2 Resistor 3.3K, 6.8K 1 each

3 Capacitor 0.1u, 0.01u 1 each

4 DC Regulated Power Supply - 1

5 CRO - 1

6. THEORY / HYPOTHESIS:• Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output

waveform is rectangular. When 555 timer is used as astable multivibrator, it has nostable states, which means it cannot remain indefinitely in either state. This results inrectangular output.

• The multivibrators are classified as: • Astable or free running Multivibrator: It alternates automatically between two states

(low and high for a rectangular output) and remains in each state for a timedependent upon the circuit constants. It is just an oscillator as it requires no externalpulse for its operation.

• Monostable or one shot Multivibrator: It has one stable state and one quasi stablestate. The application of an input pulse triggers the circuit time constants. After aperiod of time determined by the time constant, the circuit returns to its initial stablestate. The process is repeated upon the application of each trigger pulse.

• Bistable Multivibrators on other hand have both stable states. It requires theapplication of an external triggering pulse to change the output from one state toother. After the output has changed its state, it remains in that state until theapplication of next trigger pulse.

7. PROCEDURE / PROGRAMME / ACTIVITY: 1. All the components are tested.2. Circuit is rigged up according to the circuit diagram.3. Connect CRO-CH1 to pin no.6 (or 2) and CH2 to pin no.3 (Vout) of the 555.4. Apply a Vcc of +10V.5. Observe the capacitor voltage waveform at pin no.6. Observe the output waveform at pin no.3.6. Note down the period, pulse width, UTP, LTP and VH values.


https://en.wikipedia.org/wiki/Function_generator

https://en.wikipedia.org/wiki/Dual-slope_ADC

https://en.wikipedia.org/wiki/Switching_power_supply

7. Plot the graph of output waveform and capacitor voltage waveform. (UTP= 2/3 Vcc, LTP = 1/3 Vcc, as per theory)


9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:

1. Period,T = _________ms 2. Therefore frequency, f =_________Hz3. Pulse width, W =___________ms3. Duty cycle, D = W/T = ________%4. UTP =_________V5. LTP=_________V6. High level of output, VH =__________Volts. (Low level is zero volts).

10. FORMULA / CALCULATIONS:When 555 timer IC is connected to run as an Astable multivibrator, it gives rectangularoutput. Let T be the period of the output waveform. Then duration of T during which outputis high,



12. RESULTS & CONCLUSIONS:• The various values are as expected. Frequency of output waveform = Hz.• Duty cycle = ___________%

13. LEARNING OUTCOMES :• From this experiment we can conclude that square waveforms of desired frequency can be

generated using 555 timer based astable multivibrator.

14. APPLICATION AREAS:• Multivibrator.• Embedded Applications.


-1. EXPERIMENT NO: 042. TITLE: ADDERS AND SUBTRACTORS3. LEARNING OBJECTIVES:

• To realize the half adder circuits using basic gates. • To realize the half substractor circuits using basic gates.


• To realize the full adder circuits using basic gates. • To realize the full substractor circuits using basic gates.

4. AIM:• To realize Half Adder and Full Adder using Basic gates. • To realize Half Substractor and Full Substractor using Basic gates.

5. MATERIAL / EQUIPMENT REQUIRED: • IC7404,7408,7432.• Patch Cords, IC Trainer Kit.

6. THEORY / HYPOTHESIS:• Adder circuit is a combinational digital circuit that is used for adding two numbers. A

typical adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as theoutput. Adder circuits are of two types: Half adder ad Full adder.

• Half-Adder: A combinational logic circuit that performs the addition of two data bits, A andB, is called a half-adder. Addition will result in two output bits; one of which is the sum bit,S, and the other is the carry bit, C.

• Full-Adder: The half-adder does not take the carry bit from its previous stage into account.This carry bit from its previous stage is called carry-in bit. A combinational logic circuit thatadds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder.

• Subtractor is the one which used to subtract two binary number(digit) and providesDifference and Borrow as a output.In digital electronics we have two types of subtractor. Half Subtractor and Full Subtractor.

• Half Subtractor :Half Subtractor is used for subtracting one single bit binary digit fromanother single bit binary digit.

• Full Subtractor : A logic Circuit Which is used for Subtracting Three Single bit Binary digitis known as Full Subtractor.Adder circuit is a combinational digital circuit that is used foradding two numbers. A typical adder circuit produces a sum bit (denoted by S) and a carrybit (denoted by C) as the output. Adder circuits are of two types: Half adder ad Full adder.

• Half-Adder: A combinational logic circuit that performs the addition of two data bits, A andB, is called a half-adder. Addition will result in two output bits; one of which is the sum bit,S, and the other is the carry bit, C.

• Full-Adder: The half-adder does not take the carry bit from its previous stage into account.This carry bit from its previous stage is called carry-in bit. A combinational logic circuit thatadds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder.

• Subtractor is the one which used to subtract two binary number(digit) and providesDifference and Borrow as a output.In digital electronics we have two types of subtractor. Half Subtractor and Full Subtractor.

• Half Subtractor :Half Subtractor is used for subtracting one single bit binary digit fromanother single bit binary digit.

• Full Subtractor : A logic Circuit Which is used for Subtracting Three Single bit Binary digitis known as Full Subtractor.

7. PROCEDURE / PROGRAMME / ACTIVITY: • Make connections as shown in the circuit diagram.• Verify the Truth Table and observe the outputs.


IC 7404 PIN DIAGRAM


IC 7408 PIN DIAGRAM

IC 7432 PIN DIAGRAM IC 7411 PIN DIAGRAM

Half Adder Half subtractor

Full Adder Full Subtractor



Difference=ab+ab

Borrow = ab

Sum = a b c + a b c + a b c + a b c Carry = A·B + A·C + B·C


Difference = a b c + a b c + a b c + a b c Borrow = a c + a b + b c

10. FORMULA / CALCULATIONS:• N/A

11. GRAPHS / OUTPUTS:• N/A

12. RESULTS & CONCLUSIONS:• The truth table of half adder, half subtractor, full adder and full subtractor is verified.

13. LEARNING OUTCOMES :• Students will be able to design half adder, half subtractor, full adder and full subtractor

using basic gates. 14. APPLICATION AREAS:

• Used in the design of ripple counters.• Half adders can be used to design full adders.


-1. EXPERIMENT NO: 052. TITLE: EVM & 8:1 MUX3. LEARNING OBJECTIVES:

• To learn about various applications of multiplexer.• To learn and understand the working of IC 74151.• To learn to realize any function using Multiplexer.• To develop a Verilog code for an 8:1 Multiplexer using dataflow modeling in Xilinx

simulator.4. AIM:

• To simplify 4 variable logic expression, simplify it using Entered Variable Map and realizethe simplified logic expression using 8:1 Multiplexer IC.

• To develop the Verilog / VHDL code for an 8:1 multiplexer, simulate and verify itsworking.

5. MATERIAL / EQUIPMENT REQUIRED: • IC 74151, IC 7404 • Patch Cords & IC Trainer Kit• PC with Windows XP, XILINX software.

6. THEORY / HYPOTHESIS:


• Multiplexer means many into one. A ‘multiplexer’ is a circuit with many inputs, but only one output. By using control signals, we can connect any input to the output. Hence, it is also known as Data Selector.

• Map Entered VariableRules for entering values in a MEV K-map:

7. PROCEDURE / PROGRAMME / ACTIVITY:

• Assume that the following 4-variable Boolean function is to be implemented using 8:1multiplexer IC 74151. Y = F(A,B,C,D) = ∑ (0,1,2,4,5,6,8,9,12,13,14).

• Entered Variable Map Simplification and the simplified expression is shown below:

The Entered Variable Map Truth-Table corresponding to the above expression is shown below:


Rule MEV f Entry in MEV Comments

No. Map

1 0 0 If function equals 0 for both values of MEV, enter

0 in appropriate cell of MEV Map. 1 0 0

2 0 1

If function equals 1 for both values of MEV, enter 1. 1 1 1

3 0 0 If function equals MEV enter MEV 1 1 MEV

4 0 1 ------

If the function is compliment of MEV, enter MEV. 1 0 MEV

5 0 -

If function equals don't care for both values of MEV, enter –. 1 - –

6 0 - 0

Iff = 0 for MEV= 0 and f=0 for MEV=1, enter 0. 1 0

7 0 0 0

Iff = 0 for MEV= 0 and f=- for MEV=l, enter 0. 1 -

8. 0 - 1

Iff = – for MEV= 0 and f=1 for MEV=1, enter 1. 1 1

9 0 1 1

Iff = 1 for MEV= 0 and f=- for MEV= –, enter –. 1 -

• IC 74151 is an 8-channel digital multiplexer having 8- data inputs D0…D7, three selectlines (MSB)ABC(LSB) and two complementary outputs designated as Y and Y’. IC 7404contains 6-inverters. IC 74151 and IC 7404 are inserted into the separate sockets in thedigital trainer. In IC 74151 Pin 16 is Vcc and Pin 8 is Ground. In IC 7404 in 14 is Vcc andPin 7 is Ground. Vcc pins of both the ICs are connected to +5V dc power source pin.Ground pins of both the ICs are connected the Ground points in the trainer.

• The circuit is rigged up as shown in the following diagram.• Inputs D0 through D7 are connected as shown in the diagram and as required by the

function to be implemented. Output Y (Pin 5) is connected to LED. To enable the IC 74151,Pin 7 (Enable Pin) which is active low is connected to GND. Additional input D (LSB)derived from a switch is connected to Pin 1 of IC 7404. Pin 2 (output) of IC 7404 is D’ andhence connected to Pin 3, Pin 1 and Pin 12 of IC 74151constituting D1, D3, and D7respectively. Pin 14 (D5) of IC 74151 is grounded remaining D input pins to the Vcc.

• Inputs ABCD are varied by making the corresponding switches ON or OFF, according tothe truth table below and the output observed in the LED (ON =1; OFF = 0) is verified forcorrectness.8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:a) Hardware Implementation

• Pin Diagram:

IC 74151 (8:1 MUX) IC 7404(NOT Gate)

Circuit Diagram:


b) Simulationmodule

MUX8to1(A,B,C,D0,D1,D2,D3,D4,D5,D6,D7, Y); input A,B,C,D0,D1,D2,D3,D4,D5,D6,D7;

output Y;

reg Y;

always @ (A or B or C or D0 or D1 or D2 or D3 or D4 or D5 or D7)

case ({A, B, C})

0: Y = D0;

1: Y = D1;

2: Y = D2;

3: Y = D3;

4: Y = D4;

5: Y = D5;

6: Y = D6;

7: Y = D7;

endcase

endmodule9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:

a)




12. RESULTS & CONCLUSIONS:• A four-variable logic expression is simplified using entered variable map and is verified

using 8:1 multiplexer.13. LEARNING OUTCOMES :

• We can conclude that using an Entered variable map a four variable logic expression can besimplified so that it can be implemented using an 8:1 Multiplexer.

• Thus it can also be concluded that a multiplexer sometimes works as an universal logiccircuit because a 2n–to–1 multiplexer can be used as a design solution for any n variabletruth table.

14. APPLICATION AREAS:• Programmable Logic Devices.• Multiplexing.• Digital Subscriber Line Access Multiplexer.


-1. EXPERIMENT NO: 062. TITLE: Code Converters3. LEARNING OBJECTIVES:

• To learn the importance of non-weighted code.• To learn to generate gray code.

4. AIM:• Design and implement code converter I)Binary to Gray II)Gray to Binary Code using basic

gates.5. MATERIAL / EQUIPMENT REQUIRED:

• IC 7404 1, IC 7432 2, IC 7411 2 or IC 7486 2 • Patch Cords & IC Trainer Kit

6. THEORY / HYPOTHESIS:• Binary Codes: A symbolic representation of data/ information is called code. The base or

radix of the binary number is 2. Hence, it has two independent symbols. The symbols usedare 0 and 1. A binary digit is called as a bit. A binary number consists of sequence of bits,each of which is either a 0 or 1. Each bit carries a weight based on its position relative to thebinary point. The weight of each bit position is one power of 2 greater than the weight of theposition to its immediate right. e. g. of binary number is 100011 which is equivalent todecimal number 35.

• Gray Codes: It is a non-weighted code; therefore, it is not a suitable for arithmeticoperations. It is a cyclic code because successive code words in this code differ in one bitposition only i.e. it is a unit distance code.


Applications of Gray Code:In instrumentation and data acquisition system where linear or angular displacement ismeasured.In shaft encoders, input-output devices, A/D converters and the other peripheral equipment.

• Code Converters: The availability of a large variety of codes for the same discrete elementsof information results in the use of different codes by different digital systems. It is sometime necessary to use the output of one system as the input to the other. The conversioncircuit must be inserted between the two systems if each uses different codes for the sameinformation. Thus a code converter is a circuit that makes the two systems compatible eventhough each uses the different code.

7. PROCEDURE / PROGRAMME / ACTIVITY: • Check all the components for their working.• Insert the appropriate IC into the IC base.• Make connections as shown in the circuit diagram.• Verify the Truth Table and observe the outputs

8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:IC 7411 Pin Diagram

IC 7486 Pin Diagram

Binary to Gray code converter

BOOLEAN EXPRESSIONS:G3=B3G2=B3 B2 = B3⊕ B2 + B3B2G1=B1 B2 = B1⊕ B2 + B1B2G0=B1 B0 = B1⊕ B0 + B1B0

Gray to binary code converter


or

BOOLEAN EXPRESSIONS:B3 = G3B2 = G3 G2 = G3⊕ G2 + G3G2B1 = G3 G2 G1 = G3 (G2⊕ ⊕ ⊕ G1 + G2G1)= G3(G2G1 + G2G1)' + G3(G2G1 + G2G1)= G3(G2 G1 + G2G1) + G3(G2G1 + G2G1)= G3G2 G1+ G3G2G1+ G3G2G1+G3 G2G1B0=G3 G2 G1 G0⊕ ⊕ ⊕




12. RESULTS & CONCLUSIONS:• Binary to gray code conversion and vice versa is realized using basic gates.

13. LEARNING OUTCOMES :• Binary to gray code conversion and vice versa is implemented using basic gates.

14. APPLICATION AREAS:• Code conversion.• Encoding and decoding.



-1. EXPERIMENT NO: 072. TITLE: PARITY GENERATOR AND CHECKER3. LEARNING OBJECTIVES:

• To implement parity generator and parity checker using basic gates.4. AIM:

• Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker using basic Logic Gates with an even parity bit.

5. MATERIAL / EQUIPMENT REQUIRED: • IC7404 1, IC7411 2, IC7432 2 or• IC7486 1• Trainer kit, patch cords.

6. THEORY / HYPOTHESIS:• Parity Generator: It is combinational circuit that accepts an n-1 bit stream data and generates

the additional bit that is to be transmitted with the bit stream. This additional or extra bit istermed as a parity bit.In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the datastream and the parity bit is ‘1’ if there are odd number of 1s in the data stream.In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the datastream and the parity bit is ‘0’ if there are odd number of 1s in the data stream. Let usdiscuss both even and odd parity generators.

• Parity Check: It is a logic circuit that checks for possible errors in the transmission. Thiscircuit can be an even parity checker or odd parity checker depending on the type of paritygenerated at the transmission end. When this circuit is used as even parity checker, thenumber of input bits must always be even.When a parity error occurs, the ‘sum even’ output goes low and ‘sum odd’ output goes high.If this logic circuit is used as an odd parity checker, the number of input bits should be odd,but if an error occurs the ‘sum odd’ output goes low and ‘sum even’ output goes high.

7. PROCEDURE / PROGRAMME / ACTIVITY: • Make the connections according to the design and verify the truth table.

8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:Parity Generator with even parity bit:

Parity Checker with even parity bit:

Parity Checker with even parity bit using XOR gates:





12. RESULTS & CONCLUSIONS:• 3-bit Parity generater and 4-bit parity checker using even parity is implemented using basic

gates. And truth table is verified.13. LEARNING OUTCOMES :

• Able to implement parity generator and parity checker using basic gates.14. APPLICATION AREAS:

• Error detection and correction. 15. REMARKS:

•••

-1. EXPERIMENT NO: 082. TITLE: MASTER-SLAVE JK FLIP-FLOP3. LEARNING OBJECTIVES:

• To learn about various applications of flip flops.• To learn and understand the working of IC 7410.• To learn and understand the working of J-K Master Slave Flip flop.• To develop Verilog/VHDL code for positive edge triggered D Flip-Flop using behavioral

modeling in Xlinx simulator.4. AIM:

• To study the truth table of J-K Master Slave flip flop and verify the same.• To develop Verilog/VHDL code for positive edge triggered D Flip-Flop and simulate its

working.5. MATERIAL / EQUIPMENT REQUIRED:


• IC 7410 2• IC 7400 2• Patch Cords & IC Trainer Kit• PC with Windows XP, XILINX software.

6. THEORY / HYPOTHESIS:• A flip-flop is a circuit that can maintain a binary state until directed by an input signal to

switch states. JK flip-flop is the most generally used flip-flop, which is edge triggered andhas got two data inputs J & K, and a clock input.

• Normal data inputs to a flip-flop are referred to as synchronous inputs, because they effectthe output in steps synchronous with the clock signal.

• Preset and Clear are asynchronous inputs, because they can set / reset the flip-flopregardless of the status of clock. When Preset is activated, the flip-flop will be set and whenClear is activated, the flip-flop will be reset. Preset and Clear find use when multiple flip-flops are ganged together to perform a function.

• In Master-Slave JK flip-flop, two flip-flops are arranged such that, when the clock pulseenables the first (the Master) latch, it disables the second (the Slave) latch. When the clockchanges the state again (on its falling edge), the output of the Master latch is transferred tothe Slave latch.

• The output of MS JK flip-flop is: Qnext = JQ’ + K’Q

NOTE: A group of flip-flops sensitive to pulse duration is a latch. E.g.: 7475, a 4-bit latch.A group of flip-flops sensitive to pulse transition is a register. E.g.: 74175, a 4-bit register.

7. PROCEDURE / PROGRAMME / ACTIVITY: • Flip-flop is a sequential circuit used as memory element in other sequential circuits as it is

capable of storing a single bit of information. Every flip-flop has two complementaryoutputs (Q and Q’). Numbers of inputs to a JK flip-flop is 2 and are usually designated as Jand K. The circuit does not respond to the change in the inputs unless an additional inputcalled the clock input is applied.

• NAND gates of both the 3-input and 2-input ICs are connected as shown below. It isensured that the Vcc and GNDs of both the ICs are connected to +5V dc power source andGround points respectively in the trainer. Outputs Q and Q’ are connected to the LEDs.• Inputs J and K are connected to the switches and the CP input is connected to the

monopulser slot in the trainer.• Initially J=0 and K = 0. Observe the Q. If it is 0, apply the clock pulse. Otherwise make

clear LOW (to make Q=0) and again HIGH (for normal operation) and then apply theclock pulse. Observe the output listed in the column captioned Q(t+1).

• If Q=1 is to be established, make preset LOW (to make Q=1) and again HIGH (fornormal operation).

• Likewise obtain all the input combinations according the sequence in the table andverify corresponding outputs.

8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:a) Hardware Implementation

Pin Diagram: IC 7400(2-input NAND Gate) IC 7410 (3-input NAND)


Circuit Diagram:

b) Simulationmodule DFF(Clock, D, Q);

input Clock, D;

output Q;

reg Q;

always @ (posedge Clock)

Q = D;

endmodule 9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:a)




12. RESULTS & CONCLUSIONS:• The J-K Master / Slave Flip Flop is designed using NAND gates and its truth table is

verified.13. LEARNING OUTCOMES :

• The master slave flip flop is used as a solution to the race around problem in flip flops. 14. APPLICATION AREAS:

• Data Storage• Data Transfer• Counter, Registers• Frequency Division.


-1. EXPERIMENT NO: 09

2. TITLE: SYNCHRONOUS UP-COUNTER3. LEARNING OBJECTIVES:

• To learn about synchronous Counter and its application.• To learn and understand the working of IC 7476.• To learn the design and the working of synchronous counter.• To develop Verilog/VHDL code for mod-8 up counter using behavioral modeling in Xilinx

simulator.4. AIM:

• To Design and implement mod n (n<8) synchronous up-counter using J-K Flip Flop.• To develop Verilog/VHDL code for mod-8 up counter and simulate its working.

5. MATERIAL / EQUIPMENT REQUIRED: • IC 7476 2• IC 7408 1• Patch Cords & IC Trainer Kit, • PC with Windows XP, XILINX software.

6. THEORY / HYPOTHESIS:• A Counter is a sequential circuit that goes through a prescribed sequence of states up on

application of input pulse. Counter are in two categories – • Ripple Counter (Asynchronous Counter) – consists of a series connection of

complementing flip-flops (T / JK type), with the output of each flip-flop connected tothe clock pulse input of the next higher order flip-flop. The flip-flop holding the LSBreceives the clock pulses.

• Synchronous Counter – the input pulses / clock pulses are applied to all clock pulseinputs of all the flip-flops simultaneously.

• The ripple counter requires a finite amount of time for each flip flop to change state. Thisproblem can be solved by using a synchronous parallel counter where every flip flop istriggered in synchronism with the clock, and all the output which are scheduled to changedo so simultaneously.

• The counter progresses counting upwards in a natural binary sequence from count 000 tocount 100 advancing count with every negative clock transition and get back to 000 after


this cycle.7. PROCEDURE / PROGRAMME / ACTIVITY:

• The counter with n flip-flops has maximum mod number 2n. For example, 3-bit binarycounter is a mod 8 counter. This basic counter can be modified to produce MOD numbersless than 2n by allowing the counter to skip states those are not normally part of countingsequence.

• MOD-5 synchronous counter is designed below using JK flip-flops and the circuit isimplemented as shown in the circuit diagram. A timing diagram is also constructed below.

• Number of Flip-flops required = 3 as 3 is the minimum number for which 5<8. Let theinputs of the three Flip-flops be JA, KA JB, KB, JC, KC. Let the normal outputs be QA,QB, QC and the complementary outputs be QA’, QB’, QC’.

• Preset and Clear are the active low direct inputs (asynchronous inputs) to set or reset thecounter (means to set or reset all the flip-flops contained in the counter) before to theapplication of the clock pulse to obtain the next state of the counter.

• The Characteristic table is useful for analysis and defining operation of flip-flops. Thecharacteristic table of JK flip-flop is given below.

• But during design, we normally know the transition from the present state to the next state,called Transition table. The transition table is derived using the truth table. Truth table isconstructed using the given counter.

• Here, given counter is mod-5. i.e., the given sequence is: 0, 1, 2, 3, 4, 0, . . .

• First draw the State Diagram:

Then construct the expected Truth table: Expected Truth table

From the truth table, construct Transition table.


Transition table of Mod-5 Counter

Now, construct the Excitation table of JK flip-flop using the State diagram / Characteristic table ofJK flip flop. A table that lists the required inputs for a given change of state is called ‘Excitationtable’.

Now by using the excitation table and the transition table, evaluate the flip-flop inputs as shownbelow.

Go for K-Map simplification, and after K-Map simplification, expressions for the flip-flop inputsare as shown below:


• Having obtained the combinational expressions for the flip-flop inputs to ensure the desirednext state transitions at the corresponding outputs, the following circuit diagram is riggedup.

• Two 7476 JK Flip-flop ICs are required as one IC contains only two JK flip-flops. Vcc andGND of both the ICs are connected. Outputs QA(LSB), QB, and QC(MSB) are connected toLEDs. Preset and Clear are the direct inputs connected to the switches. All the flip-flopsdriven by the same clock pulse, establishes the concept of synchronous counter. Clock inputmay be supplied with monopulser or continuous clock generator.

8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:a) Hardware ImplementationPin Diagram:

IC 7476 (J K Flip Flop) IC 7408(2-input AND Gate)

Circuit Diagram:


b)module Mod8UpCounter(Clock, Rst, Q); input Clock, Rst;

output [2:0] Q;

reg [2:0] Q;

always @ (negedge Clock or negedge Rst)

if (~Rst)

Q = 3'b0;

else

Q = Q + 1;

endmodule 9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:

• N/A10. FORMULA / CALCULATIONS:

• N/A11. GRAPHS / OUTPUTS:a)

b)


12. RESULTS & CONCLUSIONS:• The mod-n synchronous counter is successfully implemented by using the JK Flip Flop.

13. LEARNING OUTCOMES :• Using the JK Flipflops a mod-n synchronous counter can be implemented thereby allowing

to generate a count sequence that is desired.14. APPLICATION AREAS:

• Data Storage• Data Transfer• Frequency Division.


-1. EXPERIMENT NO: 102. TITLE: ASYNCHRONOUS COUNTER3. LEARNING OBJECTIVES:

• To learn about asynchronous counter and decade counter.• To learn and understand the working of IC 7490.• To understand the working of mod-n asynchronous counter using decade counter.

4. AIM:• Design and implement an asynchronous counter using decade counter IC to count up from 0

to n (n<=9) and demonstrate on 7-segment display (using IC-7447). 5. MATERIAL / EQUIPMENT REQUIRED:

• IC 7490 1• IC 7411 1• IC 7447 1• Patch Cords & IC Trainer Kit

6. THEORY / HYPOTHESIS:• A Counter is a sequential circuit that goes through a prescribed sequence of states up on

application of input pulse. Counter are in two categories – • Ripple Counter (Asynchronous Counter) – consists of a series connection of

complementing flip-flops (T / JK type), with the output of each flip-flop connected tothe clock pulse input of the next higher order flip-flop. The flip-flop holding the LSBreceives the clock pulses.

• Synchronous Counter – the input pulses / clock pulses are applied to all clock pulseinputs of all the flip-flops simultaneously.

• A counter is a device which stores (and sometimes displays) the number of times aparticular event or process has occurred, often in relationship to a clock signal. Inasynchronous counter a clock signal is provided for one flip-flop and its output is providedas clock source for next flip-flop. The output of asynchronous counter is not synchronizedwith clock signal.

• A decade counter follows a sequence of 10 states and returns to zero after the count of nine.Such a counter must have at least 4 flip flops to represent each decimal digit since a decimaldigit is represented by a binary code with at least 4 bits.


7. PROCEDURE / PROGRAMME / ACTIVITY: • Explained along with the circuit diagram.

8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:• Pin Diagram:

IC 7490 (Decade counter) Internal Diagram of 7490

IC 7447

Function Table of 7490

IC 7411 (3-input AND Gate)


Circuit Diagram:The examples of different MODs are self-explanatory with the corresponding circuit diagrams.


For mod-6 (divide-by-6) and onwards the clk input is INPUT-A, and not the INPUT-B. INPUT-B isconnected to QA.

Divide-by-8: QD to R1 and R2.

Divide-by-9: QAQD to AND Gate, then ANG Gate output to R1 and R2 / QAQD to R1R2.


9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:• Given along with the circuit diagram.



12. RESULTS & CONCLUSIONS:• An asynchronous counter using a decade counter is designed and the truth table is verified

for the same.13. LEARNING OUTCOMES :

• By using a decade counter we can obtain an appropriate decimal number14. APPLICATION AREAS:

• Binary Coded Decimal.• Finite State Machines.



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