VIRGO+ 1st Review Document

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Virgo+ 1st review document

Title:

New Control and DAQ Electronics (“Part I”)

Name: Letendre Nicolas Name: Masserot Alain Email letendre@lapp.in2p3.fr Email: masserot@lapp.in2p3.fr

Coordinator(s):

Institution: LAPP/IN2P3/CNRS Institution: LAPP/IN2P3/CNRS

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Index Index.....................................................................................................................................................2 List of tables.........................................................................................................................................2 Abstract ................................................................................................................................................3 Motivations ..........................................................................................................................................3

Obsolete components: ..................................................................................................................3 Electromagnetic noise:.................................................................................................................3 Absolute GPS time stamp: ...........................................................................................................3 Control Loop................................................................................................................................4

Reference documentation.....................................................................................................................5 Production activities status...................................................................................................................6

Production Task 1: Atomic GPS receiver ........................................................................................6 Short description ..........................................................................................................................6 Status of the task: .........................................................................................................................6

Production Task 2: Timing distribution board.................................................................................6 Short description ..........................................................................................................................6 Status of the task: .........................................................................................................................8

Production Task 3: MUX/DeMUX board........................................................................................9 Short description ..........................................................................................................................9 Status of the task: .........................................................................................................................9

Production Task 4: ADC board........................................................................................................9 Short description ..........................................................................................................................9 Status of the task: .........................................................................................................................9

Production Task 5: TOLM.............................................................................................................10 Short description ........................................................................................................................10 Status of the task: .......................................................................................................................10

Deliverables .......................................................................................................................................11 Collaborators involved in the production tasks..................................................................................11 Expenditures and future budget .........................................................................................................11 Production and Installation Planning .................................................................................................12 Automatic information fields .............................................................................................................14

List of tables Table 1 - Reference documentation .....................................................................................................5 Table 2 - Collaborators involved in the production tasks ..................................................................11 Table 3 – Expenditures ......................................................................................................................11 Table 4 - Foreseen budget..................................................................................................................11

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Abstract The goal is to upgrade the current control and DAQ system by a new one. The mains motivations are:

• Replace the old obsolete components • Reduce the electromagnetic noise. • Provide a fast access to an absolute GPS time stamp to all the front end electronics • Reduce the jitter at the sensing or acting level(ADC, DAC) • Reduce the noise level of the ADC readout • Provide faster readout (ADC readout up to 800kHz, main Loop at least running at 20kHz) • Increase the control loop phase margin and the computing power

This document does not described the new DSP or the new DAC developed by EGO/Pisa.

Motivations Obsolete components: As a typical example, the current GPS board is GPS bc635VME/bc350VXI. This board is a ten year old board and we raise some problems due to a local battery which damage some wire on the printed circuit. This board is based on a 10MHz VCXO oscillator. We use this opportunity to upgrade the oscillator and to have a more stabilized oscillator.

Electromagnetic noise: The timing system is again a typical example: it is based on four signals propagated using fibers between each building and coaxial cable (BNC) between the building distributor crate and each Timing board. The GPS VME board and the translator board are located on VME crate with switched-mode power supply. The new timing system will based on:

• 2 signals: 1PPS IRIGB frame and a fast clock • Optical distribution between all the building distributor boxes • Optical distribution between a building distributor box and a rack distributor box • Differential LVDS distribution between the rack distribution box and the TOLM Timing • Short single ended distribution between the TOML Timing and the sensing/acting

driver(ADC/DAC, …) • A GPS receiver and a timing distribution box with linear power supplies

Absolute GPS time stamp: Today the frame building is based on a 16 bits frame counter and the GPS time stamp is frozen at each frame signal on the VME GPS board. It’s also difficult to measure precisely the time between two loop components at less that the sampling period (50us). To simplify the GPS time stamp and to allow to measure precisely the time between all the loop components, the time available on all the TOLM timing will be a GPS time stamp with a precision of few 100ns.

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Control Loop Due to the technical choices done ten years ago, the control loop is based today on 3 pipeline elements running synchronously at 10 KHz. To reduce the control noise into the loop, there is the needed of complex filtering algorithms which required more computing power and enough phase margin. Today to deal with this challenge, the computation is distributed over the 3 components and the filtering algorithms complexity reduced to fulfil the phase margin constraint. To increase the control loop phase margin and to provide more power computation, we propose:

• to reduce the number of elements involved in the control loop(two or one elements) • to use more powerful CPU/DSP (PC server @ 2GHz/DSP @300MHz) • to improve the data access path (MUX/DEMUX board) • and to run at higher frequency the control loop

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Reference documentation Table 1 - Reference documentation

1. The Virgo DAQ System ; RTAI proceedings, May 2003 (Overview of the control/DAQ system)

2. Consequence of the jitter noise on ADC readout; D. Tombolato; VIR-NOT-LAP-1390-274 (3/08/04)

3. Control System Upgrade of the VIRGO interferometer. Timing Interface & Optical Links; O. Chautemps, et al. VIR-NOT-LAP-1390-278 (11/08/04)

4. Proposal for the Timing & Optical Links Mezzanine (TOLM); O. Chautemps, et al. VIR-NOT-LAP-1390-279 (11/08/04)

5. Preliminary Timing system interface requirements; O. Chautemps, et al. VIR-NOT-LAP-1390-280 (11/08/04)

6. Connectors pin-out of the TOLM ver1.0 prototype; N. Letendre, O. Chautemps; VIR-NOT-LAP-1390-281 (14/09/04)

7. MUX/DEMUX optical card specifications; N. Letendre, VIR-NOT-LAP-1390-321 (15/03/06)

8. TOLM Boundary Scan Board specifications, N. Letendre VIR-NOT-LAP-1390-322 (05/04/06)

9. New timing distribution system for Virgo: prospect for a full system from the market; S. Karkar. June 9, 2006, VIR-NOT-LAP-1390-323

10. EGO R&D program R&D, Final report for the Electronic Upgrade; Part I (Timing; TOLM, ADC; Analog Electronic) June 2006

11. ADC tests for the general purpose acquisition board, VIR-NOT-LAP-1390-329 (October 25, 2006)

12. EGO R&D program; Final report. R&D for the Electronic Upgrade; Part I (Timing; TOLM, ADC; Analogue Electronic) LAPP Annecy (June 2006)

13. R&D for the Electronic Upgrade; Part I; Presentation during the STAC June 2006 meeting.

14. New control and DAQ electronic Architecture and cost estimate, November 2007 15. ADC Board: Analogue input stage; Presentation during the Advanced Virgo WG4

meeting, November 21, 2006 16. ADC Board; ADC choice; Presentation during the Advanced Virgo WG4 meeting,

November 21, 2006 17. Characterization of RTAI/ Linux real-time performance on i386 hardware for the Virgo

control loops, VIR-NOT-LAP-1390-335, (Jan 16, 2007) 18. PC server Realtime Performances with RTAI-Linux , Presentation during the Advanced

Virgo WG4 meeting, January 24, 2007 19. Proposal for the Online architecture based on the new digital electronics with PC and

DSP; Presentation during the Advanced Virgo WG4 meeting, January 24, 2007 20. News from Annecy Virgo+ electronic developments; Presentation during the Advanced

Virgo WG4 meeting, January 24, 2007

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Production activities status General remarks: All following tasks require the development of associated software for the test and also regular use in Virgo. This part is not described in this section.

Production Task 1: Atomic GPS receiver

Short description We have selected the Signal generator SW1050-R-10 from MicroSystems based on:

• a GPS Motorola M12T receiver • and a Rubidium clock

We have qualified the Atomic GPS receiver by performing the following tests: • Check the 1PPS accuracy • Check the GPS time stamp and the status bits

Status of the task: All the tests have been performed over several weeks. After an upgrade of the firmware to fix some GPS time stamp errors and to improve the status bits report, the status is the following:

• No more GPS time stamp errors • It remains up to 2 jumps of 130ns over one week on the 1PPS position in the IRIGB frame

It remains to order two additional Atomic GPS receiver

Production Task 2: Timing distribution board

Short description The goal of this box is to propagate the 2 timing signals, 1PPS and the fast clock, over all the building to each TOLM timing part. It has been designed to be compliant with the current timing system and to allow the propagation of the current 4 timing signals.

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The timing distribution box characteristics are:

• 3 input signal types driven by a input selector: o 4 TTL inputs o 4 LVDS inputs o 2 optical receiver(1300mn,multimode, length < 5Km)

• 2 output configurations o Type A:

2 TTL outputs(1PPS – Fast Clock) 32 LVDS outputs with variable delay line(10.5-255ns) 32 LVDS outputs

o Type B: 2 TTL outputs(1PPS – Fast Clock) 64 LVDS outputs 12 optical transmitter(1300mn,multimode, length < 5Km)

• Linear power supply 220VAC/1.6A The scheme of a timing distribution box channel is showed in the following picture:

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The timing distribution box front and rear face:

Figure 1 Timing distribution box faces

Status of the task: The phase jitter measures between two timing distribution boxes according their connections have been done with a 10MHz signal.

The results are reported in the following table:

MEASURE with 10 MHz signal TDBox n°1 Long. TDBox n°2 Measures Input Output Câble Input Output Delay Jitter Range BNC BNC 1 m 14,86 ns 17,77 ps 116 ps BNC RJ-45 1 m RJ-45 BNC 44,56 ns 18,33 ps 125 ps BNC Optic 5 m Optic BNC 69,09 ns 19,34 ps 156 ps BNC Optic 3 Km Optic BNC 15,84 µs 58,32 ps 508 ps

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The Timing distribution box is fully tested and basically ready for the production. It remains to define the number of box of the different types according the new online architecture (spring 2007), and do minor fixes to the PCB before starting the production.

Production Task 3: MUX/DeMUX board

Short description This board is a router for the optical links between TOLM and ADC boards.

Status of the task:

A prototype exists and has fulfilled the basic electrical test. The Writing of the VHDL code is in progress as well as the TOLM test software needed for a full test of the board. When the board will pass this full test then the production could start.

Production Task 4: ADC board

Short description This is a 16 ADC channel board to be used for photodiode readout and monitoring of the various Virgo components. It has an optical fiber output.

Status of the task: The different elements have been selected and the schematic of the board made. The design of the PCB for the first prototype is in progress. Then once the prototype will be received, test will be performed. Given the complexity of the board a second prototype may be needed before starting the production.

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Production Task 5: TOLM

Short description The following showed the TOLM block diagram, in yellow the part related to the timing, in blue the part for the data transmission.

IRIG B Decoding

Local Clock control

User Signals Generation

Configuration Registers

Data Packet Receiver

Local

Data Packet Emitter From/ToPC

From/To DSP boars

BUS PCI

Link ports

User SignalsOutput

IRIG B

2 optical Outputs

2 Optical Inputs

1PPS

GPS Ti

1.6 Gbit/s 64-bit @66MHz

100 Mo/s

We have implemented and tested on the TOLM board the following items:

• User’s signal configuration from PCI • the TCXO oscillator servo loop driven by the 1PPS IRIGB frame

Status of the task: The phase jitter on 20MHz signal generated by the TOLM board timing part is 15ps. The phase jitter between two TOLM board timing part locked on the same 1PPS IRIGB propagated through 2 timing distribution boxes separated by a 3km optical fibber is +/-30ns. The data transfer has been successfully tested, including the link with the DSP. The different part of the VHDL code, developed to test the various TOLM part need to be integrated. TOLM configuration protocol remains also to be implemented and tested. The speed of the optical link will be upgraded to 1.2Gbits/S to 1.6 Gbits/s (also an upgrade of the VHDL code). A new version of the TOLM board is foreseen to support a 64 bits PCI running at 66 Mhz. This version will not have the PMC format in order to directly plug it in a PC. The TOLM version 1 will be used for the DSP communications.

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Deliverables See the reference [14] for the list of the main components to provide. The other references give information about the specification of the different components. The delivery schedule of the various components is described in the following planning section.

Collaborators involved in the production tasks Table 2 - Collaborators involved in the production tasks Name Institution Activities/role Bouedo Thierry LAPP Software Engineer Nappa Jean-Marc LAPP Electronic Engineer Letendre Nicolas LAPP Electronic Engineer Masserot Alain LAPP Software Engineer Mours Benoit LAPP Physicist Pacaud Emmanuel LAPP Software Engineer Vilalte Sébastien LAPP Electronic Engineer XX LAPP Electronic Support (requested to LAPP)

Expenditures and future budget Table 3 – Expenditures The expenditures have been supported by the EGO R&D program. For details up to May 2006, see the reference [12]. Since then an additional 39610 Euros for expenditures have been spend on this program and the fellowship program completed Table 4 - Foreseen budget The foreseen budget is estimate in reference [14], section 3. Notice that this estimate does not include the taxes, the network upgrade or the DAQ main workstations (olservers) upgrades. Some parts could be order directly by EGO under the guidance of LAPP like the PCs (40kE + network + workstations, to be ordered in 2008), but the production of boards that required multiples orders needed to be directly handled by LAPP with a convention between EGO and LAPP as usual (estimate to 285kEuros without taxes in 2007).

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Production and Installation Planning

Remarks:

• This planning is focus on the construction of the real time components of the system. Other “satellite task” like the upgrade of the DAQ workstations are needed but not included in this planning, since it is not on the critical path.

• The first installation of some timing components will be in parallel of the existing system. Therefore it should be “transparent” for the user.

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• The second installation phase ADC+ TOLM+ … means a full stop of all the controls. Only the hardware installation is quoted here. Additional time (at least several weeks) will be needed to deploy the software and debug the full system.

• Support from EGO people doing the DAQ support will be welcome during the tests of the production and also during the installation at the site.

.

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