vhdl tutorial 3 - university of waterloosshahir/ · outline • vhdl quick look • entity •...
TRANSCRIPT
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Outline• VHDL Quick Look• Entity• Architecture• Component• HalfAdder• FullAdd• Generate if Statement• Selected Signal Assignment• Generics• How to develop VHDL code using Xilinx Project
Navigator
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VHDL Quick Look
�� Entity�� Architecture
All the available signal types and functions can be imported by adding :
Library ieee;��������������� �������
In C:
#include <stdio.h>
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Entityentity < entity_identifier>is
Port(<signal identifier> : <mode> <type>;<signal identifier> : <mode> <type>;
…<signal identifier> : <mode> <type>);
end < entity_identifier >;
Example:
entity QuarterAdder is
port(
i_a : in std_logic;
i_b : in std_logic;
o_s : out std_logic);
end QuarterAdder ;
buffer
Inout
Out
In
mode
character
String
Integer
Boolean
Std_logic
type
Z (High impedance)
H (Weak High)
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L (Week Low)
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- (Don’t Care)
X(Unknown)
U(Uninitialized)
W(Week Unknown)
STD_logicBoolean
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Architecturearchitecture <architecture_name> of <entity_identifier> is
[ architecture_declarative_part]begin
<architecture_statement> ;<architecture_statement> ;…<architecture_statement> ;
end <architecture_name>;
Example:architecture main of QuarterAdder is
begino_s <= i_a xor i_b;
end main;
Concurrent statements
Int main (void)
{
Printf(“Hello World”);
}
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ComponentComponent < entity_identifier>
Port(<signal identifier> : <mode> <type>;<signal identifier> : <mode> <type>;
…<signal identifier> : <mode> <type>);
end Component;
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VHDL Code For HalfAdderentity HalfAdder is
port(
i_a : in std_logic;
i_b : in std_logic;
o_s : out std_logic;
o_c : out std_logic);
end HalfAdder ;
architecture main of HalfAdder is
component QuarterAdder port(
i_a : in std_logic;
i_b : in std_logic;
o_s : out std_logic);
end component;
begino_c <= i_a and i_b;
�� �QuarterAdder port map( i_a, i_b, o_s);end main;
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FullAddLibrary iieee;Use ieee�����������������Entity FullAdd is
port (i_a, i_b,i_c : in std_logic;o_s,o_c : out std_logic);
End FullAdd;
Architecture main of FullAdd isBeging
o_s<=i_c xor i_a xor i_b;o_c<=(i_c and ( i_a or i_b)) or (i_a and i_b);
End main;
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Generate-If StatementLibrary ieee;Use ieee�����������������Entity adder is
Port ( ������� !���������"#���$����downto ����� ��%����������"#���$����downto ��o_c: out std_logic);
End adder;Architecture main of adder is
Component fulladdPort(
i_a, i_b, i_c : in std_logic;o_s,o_c : out std_logic);
End component;Component halfadd
Port(i_a,i_b :in std_logic;o_s,o_c : out std_logic);
End component;
&!�����$$' ���������"#���$����downto �:=“ ”;
&!����������� ���������"#���$����downto ):=“ ”; Signal initialization
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Generate-If Statement (con’t)Begin
(�$��!����downto �#!#$��#�)� *�+ �#!#$��#
���*��� � �halfadd --Label,�$��-�.��� ����� ����� �����$$'� ���
End generate;)�� �*�+���#!#$��#
(%�������� �fulladd,�$��-�.�����������������$$'������������������
End generate;)�� �*�/+ ��!��/+���#!#$��#
Fulladdi : fulladdPort map(a(i), b(i), carry(i-����������$$'����
End generate;End generate;
a<=i_a;o_s<=s;
End main;
Generate with if
Concurrent statements
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Selected Signal AssignmentWith <expression> select
<target> <= <waveform> when <choice>; < waveform > when <choice>;< waveform > when others;
Example:Library ieee;0�#�###������������������
Entity muxone is,�$��� ����������� �!���������
�� �!���������"#���$����downto ��o_q:out std_logic);
End muxone;Architecture main of muxone isBeginWith i_c select
��1�2+�� ���#!�“ ”;�����#!�“ �”;�����#!�“� ”;�����#!����#$��
End main;
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Generics
345657�$#��6&
��������������� ��������� �������� �!������!��� ��
port(clk,r: IN std_logic;� 64���������"#���$�� ����width - ��);1 805���������"#���$�� ����width - �));#!��$#��
9:;�653;50:3�!*#$��*�$#��6&
...*��$�+<�<����#!�12+��others => ‘’);…End infer
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LIBRARY IEEE;
������������� �����������
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port(clk,r: IN std_logic;
��������� ��������� downto !"�
#��$������� ��������� downto !""�
�%��������
�&'(���'��&����������)����������
��*+�%�%���� �
generic(width:positive;
reset_value : positive);
port(
clk,r: IN std_logic;
d:IN std_logic_vector(width-� downto !"�
q:OUT std_logic_vector(width-� downto !"
);
end component;
begin
,���� ��generic map (reset_value -.���/�width -.�"�+����*,+
(clk/�/�/#�"�
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How To Develop VHDL Code Using Xilinx Project Navigator
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• This brief tutorial will help you on how to start a VHDL project on Xilinx ,$�=#���4�"���$�������#.��'���#.�
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• new project• Select a Name for the project• Select Schematic as the project type • Click Next
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• Select the device properties• Click Next
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• Click on New Source • Select a name for your VHDL code• Choose VHDL module• Click Next and click next• Click finish
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• Click next• Click next• Click finish
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