Validation of LPDDR2/3 Validation of LPDDR2/3 Package on Package (PoP) Package on Package (PoP)

Memory ChannelsMemory Channels

Perry KellerPerry KellerProgram LeadProgram Lead

Digital Applications and StandardsDigital Applications and StandardsAgilent TechnologiesAgilent Technologies

Mobile Memory Forum 2012

LPDDR2/3 PoP Measurement LPDDR2/3 PoP Measurement ChallengesChallenges

• Physical access to the interface

• Package “parasitics” dominate

• Extreme sensitivity to loading• Extreme sensitivity to loading

• High signal count in crowded space

• Rework is virtually impossible

• Proliferation of pinouts/packages

• Measurement/instrument diversity

PoP MechanicsPoP Mechanics

CPU

DRAM

• Package length/width from 7-14mm

• Two/Three rows of balls

• Ball pitch 0.65, 0.5, 0.4mm

• Ball counts from 79 – 240 (and more for LPDDR3)

• Up to Two 32 bit channels or Flash/DRAM >> 100 signals

How can all these signals be measured?

Reaching the Memory SignalsReaching the Memory Signals

CPU

PoP DRAM

Solderdown DRAM options

SoftTouch

connectorless

midbus

DRAM BGA

Interposer

!

• Traditional probing works only for MCM/solderdown

• Only an interposer can reach PoP signals

CPU MCM DRAM

Backside via

Interposer

Standards are Great, That’s Standards are Great, That’s why….why….

• Seven standard ballouts in JESD209-2D

• More variants being proposed

• Even similar footprints may be incompatible

Many of these are essentially one-off

DUT / Measurement DUT / Measurement CConfigurationsonfigurations

Probe

DRAM

DRAM Probe

DRAM

CPU CPU CPU

• SoC, probe, DRAM and instrument might need to be configured in many different ways for different tests

• PoP ball pitch and size makes rework impractable

PoP Stack Sockets and Standard PoP Stack Sockets and Standard Instrument I/F WorksInstrument I/F Works

Standard Test

Footprint

Logic

Analyzer

• SoC, probe, or DRAM can be socketed as desired

• Stack reconfigurable within minutes

• Standard footprint for multiple instruments

PoP BGA

Interposer

PoP stack

socket

Scope

Probes

Simplified Probe ArchitectureSimplified Probe Architecture

Buried isolation resistor

Package

Tx

Rx

InterconnectEscape

Package

Escape

Electrical Effects of PoP:Electrical Effects of PoP:The Package The Package ISIS The ChannelThe Channel

PoP DRAM

CPU MCM DRAM

CPU

• Package designs are closely guarded

• Pennies and fractions of a mil height are critical

• Single layer routing and no GND plane create High Z channel

Package

Tx

RxPackage

LPDDR2/3 Load SensitivityLPDDR2/3 Load Sensitivity

DRAM

• High Z channel > load sensitivity

• Tight margin in LDDR2, tighter in lpddr3

Probe

CPU CPU

DRAM

How the Probe Impacts ThingsHow the Probe Impacts Things

DRAM

Jitter/Noise added at DRAM

Load Isolation / Probe BW

Probe Bandwidth

Instrument

Controller

Schematic for each probed signal

July 2011PagBGA Probing

Design and

Optimizing Probe DesignOptimizing Probe Design

12

Signal

Loading

BandwidthConflicting Requirements

July 2011BGA Probing

Design and

If Low Loading is Paramount..If Low Loading is Paramount..

13 July 2011BGA Probing

Design and

Measured signal will be BW limited

DeDe--Embedding: BW Normalization Embedding: BW Normalization and Moreand More

Scope optimized BGA probe

Channel 1: Probing at VIA (under the

DRAM)

Channel 2: Probing at scope pad point

Channel 1: Probing at VIA

Channel 2: Probing at scope pad point on adapter

boardDecrease in

amplitude

Flex wing BGA probe with adapter board

Skew caused by

delay

Skew

caused by

delay

Good for SI check:

High bandwidth probe allows for

Measurement distorted for SI

check:

Signal performance is affected using

the BGA probe for SI check. How do I

simulate an ideal probe?

Overall DUT ModelOverall DUT ModelPhysical layout of a board

Memory Controller DRAMBGA probe

DUT Topology modelMemory

ControllerDRAM

Simulation

Delay

Scope probe

BGA probe

S parameter

file

probe head

loading

model

Measurement

SubSub--circuit Modeling of DDR BGA circuit Modeling of DDR BGA probeprobe

True Signal After DeTrue Signal After De--embeddingembedding

Channel 1: Probing at VIA (DQS strobe)

Channel 2: Probing at scope pad point

Channel 1: At VIA (DQS strobe)

Channel 2: At scope adapter board

Turn on Bandwidth Limit to 4G on the

channel to reduce the ringing effect

due to high frequency content.

Signal at BGA probe is identical to signal probing at via.

Measurement result is not compromised by the probing

effect.

Triggering on LPDDR Rd/Wr BurstsTriggering on LPDDR Rd/Wr Bursts

DQS

Two distinctive read and write burst patterns

LPDDR2 Read and Write Burst (DQS) with Data (DQ)

DQ Eye diagram

DQ0

Read and Write data

Read and Write eye overlapping

Idle state

Zone Qualified Triggers Isolate Zone Qualified Triggers Isolate BurstsBursts

DQS

Zone 1

Zone 2

Zone 1 – Must not Intersect to eliminate Idle StateZone 2 – Must Intersect to trigger on Read DQS to get read Data

DQ0

Read DQS is edge aligned with Read DQ

Eye Diagram Test after Eye Diagram Test after Read/Write SeparationRead/Write Separation

Eye Diagram Test

• Allows measurement of eye

height and width to measure

Data eye height and width

• User can also define own

mask as per device

specification

Automated AC/DC ParametricsAutomated AC/DC Parametrics

Protocol and Full Channel SIProtocol and Full Channel SI

LPDDR2 Data Eyes Potential LPDDR3 Data Eyes

Data Sample Position EyeScan: Overlaying clock delayed copies of 4 or 8 bursts on top of each other.

(example of burst of 4)

+

Using Logic Analysis to Capture Using Logic Analysis to Capture All Channel Eyes All Channel Eyes ConsurrentlyConsurrently

Pag

Data Signal Trace EyeScan: Overlaying identically clocked copies of 4 or 8 bursts on top of

each other (pattern lock repetitive mode)(example of burst of 4)

+

Case Study Case Study –– DQ Signal QualityDQ Signal Quality

Clean open eyes

for most Data

Read lines.

Closed or

Signal activity vs. time snapshots entire bus

2

4

Closed or

small DQ Eyes

LA Threshold?

Probing issue?

Design issue?

(Small eyes OK

for LA as long

as somewindow exists)

ConclusionConclusion

• LPDDR2/3 PoP measurement is difficult but practical– Electromechanical access to a lot of hidden, densely packed

signals mandates interposers with advanced design rules

– LPDDR2/3 optimization of measurement performance vs. probe loading requires careful optimization of probe design, de-embedding and potential Ctrlr adjustments

– Diverse DUT and tool configurations virtually mandate use of sockets for SoC, Probe and memory.sockets for SoC, Probe and memory.

• Concept borrowing from DDR simplifies learning curve for AC/DC/Protocol measurements

– Advanced instrument capabilities developed for DDR are therefore used in LPDDR2/3

– However, they still may be new to mobile memory engineers.

• Knowing what you can put in your toolbox is key