V01 – Verilog Part 1

Chapter 3. Section 3.9. pp. 108 - 118

Rev. 10/06/2013

Verilog I 2

Hardware Description Language

• A Hardware description language (HDL) is a formal language that describes the hardware of a digital system.

• Describes hardware components and their interconnections– Can also use truth tables– Can also use Boolean expressions

• Used with logical simulation, can show the behavior of the system.• Used with logic synthesis, can lay out a circuit board or silicon chip.

– (We won’t do this)

Two dominant HDLs:• Verilog

– Began as proprietary, now maintained by Open Verilog International– an IEEE standard– What this course uses

• VHDL– US DoD standard– Also an IEEE standard

Verilog I 3

HelloWorld.vl

• See QUICK_START.txt in the samples subdirectory of the iverilogdirectory.

• Create a source file (text file) using notePad++ or other programming editor: helloWorld.vl

• C:\iverilog\MyFiles is a convenient place to do this in.

module main;initialbegin$display("Hello, World");$finish ;

endendmodule

Verilog I 4

Running Verilog

You will need to install Icarus Verilog and set the path name for the C:/iverilog/bin in your computer's list of environment variables.

Start a command prompt window ("DOS window"):Start Button/ Run/ Open cmd

C:\iverilog\MyFiles>iverilog -o hello helloWorld.vlcompiles the source, creates object file hello

C:\iverilog\MyFiles>vvp hello runs the object, does the logic simulation

Hello, World

C:\iverilog\MyFiles>

Verilog I 5

Several Files

Often it is convenient to have the Verilog model of a circuit in one file,and the source file that tests the model (the test bench) in another file.

Do this:

C:\iverilog\MyFiles>iverilog -o myFile model.vl test.vlcompiles the sources, creates runnable file myFile

C:\iverilog\MyFiles>vvp myFileruns myFile, does the logic simulation

Verilog I 6

Syntax

• Verilog is organized into modules (somewhat like functions in C)• Verilog is case sensitive • There are many keywords• Modules start with module and end with endmodule• Semicolons separate statements (but are not part of statements)• Blocks start with begin and end with end• Comments start with // and continue to end of line.• Multiline comments start with /* and end with */• Identifiers are similar to C identifiers

Two parts to a Verilog program:• Modeling the circuit• Describing the simulation

Verilog I 7

Single AND Gatemodule test_module;reg A, B; // 1-bit registers A, Bwire C; // output wire

// Modeling the circuitand( C, A, B ); // AND gate; C is the output

// SimulationinitialbeginA = 1'b0; // initialize A to 1 bit with value 0B = 1'b1; // initialize B to 1 bit with value 1 #1 ; // wait 1 tick for gate to settle$display("Input: ", A, " ", B, " Output: ", C) ;$finish ;

end

endmodule

Verilog I 8

Simulation

C:\iverilog\MyFiles>iverilog -o test test.vlC:\iverilog\MyFiles>vvp testInput: 0 1 Output: 0C:\iverilog\MyFiles>

• Modeling:• Statements are declarative: describe a

Circuit, not a procedure• and is a keyword that asks for an AND gate. • First identifier in the port list, C, is the output.

• Simulation:• Values are put in registers.• initial means start here at start of simulation.• May be several initial statements: each one starts at same time.• Statements are run in sequence.• need to wait for AND gate to settle down.

• #1 means wait one tick

Verilog I 9

Values

<width in bits>'<base letter><number>

1’b0 -- one bit wide, value 02’b01 -- two bits wide, value 01

b -- binaryd -- decimalo -- octalh -- hex

4’b1010 -- 4 bits, value 10104’ha -- same thing4’d10 -- same thing

16’b0101_1101 -- 16 bits, groups of 4 separated with _

Verilog I 10

Two-Gate Simulation

module truthTable;reg x, y ; // 1-bit registerswire wire1, wire2;

or ( wire1, x, y ); // OR gate; output is wire1not( wire2, wire1); // NOT gate; output is wire2, input is wire1

initialbegin

$display("xy x+y (x+y)'");x = 1'b0; // initialize A to 1 bit with value 0y = 1'b0; // initialize B to 1 bit with value 0 #1 ; // wait 1 tick for gate to settle $display( x, y, " ", wire1, wire2) ;

x = 1'b0; y = 1'b1; #1 ; $display( x, y, " ", wire1, wire2) ;

x = 1'b1; y = 1'b0;#1 ; $display( x, y, " ", wire1, wire2) ;

x = 1'b1; y = 1'b1;#1 ; $display( x, y, " ", wire1, wire2) ;

$finish ;end

endmodule

Verilog I 11

Output

Writes out:

C:\iverilog\MyFiles>vvp tablexy x+y (x+y)'00 0 101 1 010 1 011 1 0

If you don’t put in the delays, #1, everything happens at once and you get strange output.

Sometimes a value will print as “x” which means “unknown.”

Sometimes a value will print as “z” which means “high impedance” (i.e., not connected.)

Verilog I 12

Book’s Example

Gates have optional names, G1, G2, G3Can be any identifier, but not a keywordInternal connections are wires, like w1

Verilog I 13

Book’s Example

The module Simple_Circuit is declared without being instantiated.(Like a class in Java.)

The module has a port list (looks like a parameter list.)

A test bench instantiates the circuit and tests it on some values.(Like main in Java.)

// Verilog model from chapter 3//module Simple_Circuit(A, B, C, D, E );output D,E;input A,B,C;wire w1;and G1(w1, A, B);not G2(E, C);or G3(D, w1, E);

endmodule

Verilog I 14

Test Bench for Example

module t_Simple_Circuit;wire D, E; // outputsreg A, B, C; // inputsSimple_Circuit M1(A, B, C, D, E);

initialbeginA = 1'b0; B = 1'b1; C = 1'b0;#1$display("First : %b %b %b %b %b", A, B, C, D, E);#50A = 1'b1; B = 1'b1; C = 1'b1;#1$display("Second: %b %b %b %b %b", A, B, C, D, E);

#200$finish;

end

endmodule

Verilog I 15

Result

C:\iverilog\MyFiles>vvp manoFirst : 0 1 0 1 1Second: 1 1 1 1 0

Declaration (in this context) means describing hardware and connections , without creating it yet. The module Simple_Circuit merely declares a circuit type and gives it a name.

Instantiation means creating (in simulation) a circuit previously declared. The test bench t_Simple_Circuit instantiated Simple_Circuit.

Several modules can be in the same source file.

In a test bench, registers are inputs to the circuit, wires are outputs from the circuit.

Verilog I 16

Port List

Correspondence between registers in the test bench and ports of the circuit is made in the port list in the test bench.

Ports in port list of declaration can be in any order.

input and output describe their roles.

Same declared module can be instantiated many times using different registers and wires.

(Think of port names in the declaration as having “block scope” .. ie are formal names for use only within the declaration.)

Verilog I 17

Gate Delays

• All gates take time to react to new input values• “propagation delay” – time it takes for a change in input to reach

the output of a circuit

• For us, measure delays in “ticks”• Think of it as a nanosecond

• #30 means a delay of 30 ticks

• Gates can be declared to have delays• and #(30) G1 (w1, A, B)• An AND gate named G1, output w1, • Propagation delay of 30 ticks.

Verilog I 18

Example with Delays

// Verilog model from chapter 3//module Simple_Circuit(A, B, C, D, E );

output D,E;input A,B,C;wire w1;and #(30)G1(w1, A, B);not #(10)G2(E, C);or #(20)G3(D, w1, E);

endmodule

#(30)

#(10)

#(20)

Verilog I 19

How to Figure out what it Does

#(30)

#(10)

#(20)

Start by writing the initial logic value on A, B, C.Everything else gets x for undefined.Write the logic value on each wire or port for every 10 ticks.Do this whether or not it has changed.

Write new values left to right like the t axis of a graph.For each gate, look in its input backwards the number

of ticks of its delay.Eg, gate G1, look 3 values behind.

0000 00

0000 00

0000 00

xxx0 00

x111 11

xxx1 11

x111 11

Verilog I 20

How to Figure (cont.)

#(30)

#(10)

#(20)

To start from a steady state, write down the ss logic values.Label the next input with the changed values.Propagate through the circuit as before.

0 1111 11

0 1111 11

0 1111 11

0 0001 11

1 1000 00

1 1110 01

1 1000 00

Verilog I 21

Test Benchmodule t_Simple_Circuit;wire D, E;reg A, B, C;Simple_Circuit M1(A, B, C, D, E);

initialbegin$display("tick A B C D E");$monitor("%5d %b %b %b %b %b", $time, A, B, C, D, E);end

initialbeginA = 1'b0; B = 1'b0; C = 1'b0;#100A = 1'b1; B = 1'b1; C = 1'b1;end

initial#200$finish;

endmodule

Verilog I 22

Result of SimulationC:\iverilog\MyFiles>vvp mano

tick A B C D E0 0 0 0 x z10 0 0 0 x 130 0 0 0 1 1

100 1 1 1 1 1110 1 1 1 1 0130 1 1 1 0 0150 1 1 1 1 0

Each initial starts at the same time, like a parallel process.

monitor fires each time one of the values it is monitoring changes.

$finish terminates the simulation.

#(30)

#(10)

#(20)

Digital Design: With an Introduction to the Verilog HDL, 5eM. Morris Mano • Michael D. Ciletti

Copyright ©2013 by Pearson Education, Inc.All rights reserved.

FIGURE 3.36 Simulation output of HDL Example 3.3

Verilog I 24

Race Conditions

The order of execution isn't guaranteed within Verilog.

initial a = 0; initial b = a; initial begin #1; $display("Value a=%a Value of b=%b",a, b); end

What will be printed out for the values of a and b?

Depending on the order of execution of the initial blocks, it could be zero and zero, or alternately zero and some other arbitrary uninitialized value.

The $display statement will always execute after both assignment blocks have completed, due to the #1 delay.

Verilog I 25

Boolean Expressions

• continuous assignment statement

• keyword assign followed by Boolean equation

• symbols && -- AND|| -- OR (note typo in book)! -- NOT

• assign D = (A && B) || (!C)

• The simulation maintains the truth of the equation at all times.

• D is always equal to the expression to the right of the = evaluated with the current values of A, B, and C.

Verilog I 26

Example

// HDL example 3.4

module Circuit_Boolean_CA( E, F, A, B, C, D);output E, F;input A, B, C, D;

// E = A + BC + B'Dassign E = A || (B&&C) || ((!B)&&D) ;

// F = B'C + BC'D'assign F = ((!B)&&C) || (B&&(!C)&&(!D)) ;

endmodule

Verilog I 27

Example Test Benchmodule t_Circuit;wire out1, out2;reg w, x, y, z;

Circuit_Boolean_CA circ01 ( out1, out2, w, x, y, z );

initial$monitor("%b %b %b %b %b %b", out1, out2, w, x, y, z );

initialbegin$display("E F A B C D");

w = 1'b0; x = 1'b0; y = 1'b1; z = 1'b0;#1 w = 1'b1; x = 1'b1; y = 1'b1; z = 1'b0;#1 w = 1'b0; x = 1'b0; y = 1'b0; z = 1'b1;#1 $finish;end

endmodule

Verilog I 28

Example Simulation Run

C:\iverilog\MyFiles>vvp manoE F A B C D0 1 0 0 1 01 0 1 1 1 01 0 0 0 0 1

Note that in the test bench the “local variables” have different names thanthe “parameters” of the module for the circuit.

The wires and registers of the test bench are “bound” to the formal names in the circuit module when the circuit is instantiated.

A circuit can be instantiated many times (like a class in Java that is instantiated many times. )

Verilog I 29

User-Defined Primitives (UDP)

• A primitive is a building block, like and, or, not.

• User can define their own primitive

• Keyword pair primitive ... endprimitive

• Only one output• Output is listed first in the port list• Declared with keyword output

• Any number of inputs• Declared with keyword input

• Keyword pair table ... endtable• Table has 2^N rows.• Each table row lists inputs in order of port list,

: before output value ; at end of row

Verilog I 30

Example UDP

// HDL example 3.5

primitive UDP02467 ( d, a, b, c );output d;input a, b, c;

// Truth table. minterms 0,2,4,6,7

table// a b c : d

0 0 0 : 1;0 0 1 : 0;0 1 0 : 1;0 1 1 : 0;1 0 0 : 1;1 0 1 : 0;1 1 0 : 1;1 1 1 : 1;

endtableendprimitive

Verilog I 31

Circuit that uses UDP

module CircuitWithUDP( e, f, a, b, c, d);output e, f;input a, b, c, d;

UDP02467 #(10) U1(e, a, b, c ); // note delayand #(10) G1(f, e, d); // output e of UDP connected to input

endmodule

Verilog I 32

Test Bench for Circuit

module t_bench;wire E, F;reg A, B, C, D;

CircuitWithUDP circ01 ( E, F, A, B, C, D);

initial$monitor("%4d: %b %b %b %b %b %b",

$time, A, B, C, D, E, F );initialbegin$display(" A B C D E F");A = 1'b0; B = 1'b0; C = 1'b1; D = 1'b0;#100A = 1'b1; B = 1'b1; C = 1'b1; D = 1'b0;# 1$finish;end

endmodule

Verilog I 33

Result of Simulation Run

C:\iverilog\MyFiles>vvp manoA B C D E F

0: 0 0 1 0 z z10: 0 0 1 0 0 0

100: 1 1 1 0 0 0110: 1 1 1 0 1 0

Remember that “z” means “high impedance” .