updated interconnect proposal bob ross, teraspeed labs epeps 2015 ibis summit san jose, ca, october...
DESCRIPTION
Goals Update the Interconnect proposal Terminal section based on existing IBIS keyword Illustrate locations for Buffer, Pad, Pin Illustrate pin_name, signal_name, and bus_label qualifiers Illustrate buffer terminals Buffer_I/O, Puref, Pdref, (and not shown) Pcref, Gcref, Extref Illustrate rail locations: Buffer_rail (not shown), Pad_rail, Pin_rail Show chart of connections rules including Aggressor 3 Copyright 2015 Teraspeed LabsTRANSCRIPT
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Updated Interconnect Proposal
Bob Ross, Teraspeed [email protected]
EPEPS 2015 IBIS SummitSan Jose, CA, October 28, 2015
Draft Presented September 9, 2015 at the Interconnect Working Group
Copyright 2015 Teraspeed Labs
2Copyright 2015 Teraspeed Labs
Background• Simplified from earlier presentations from Randy
Wolff, Walter Katz, and Interconnect Task Group chair Michael Mirmak:o http://www.eda.org/ibis/summits/may15/wolff2.pdfo http://www.eda.org/ibis/summits/jan15/katz.pdfo http://www.eda.org/ibis/summits/jun14/katz1.pdfo http://www.eda.org/ibis/summits/may14/wolff.pdfo http://www.eda.org/ibis/summits/jan14/katz.pdfo http://www.eda.org/ibis/summits/may13/wolff.pdfo http://www.eda.org/ibis/summits/jan13/mirmak2.pdfo http://www.eda.org/ibis/summits/jan13/katz.pdf
• Terminology simplificationo No Model_name supporto No pre-layout distinctiono Simpler I/O buffer that uses existing IBIS syntax
• Note, “I/O” here is generic for all 21 IBIS [Model] Model_types
3Copyright 2015 Teraspeed Labs
Goals• Update the Interconnect proposal Terminal
section based on existing IBIS keyword• Illustrate locations for Buffer, Pad, Pin• Illustrate pin_name, signal_name, and
bus_label qualifiers• Illustrate buffer terminals Buffer_I/O, Puref,
Pdref, (and not shown) Pcref, Gcref, Extref• Illustrate rail locations: Buffer_rail (not
shown), Pad_rail, Pin_rail• Show chart of connections rules including
Aggressor
4Copyright 2015 Teraspeed Labs
Definition Example[Pin] signal_name model_name R_pin L_pin C_pin A1 DQ1 DQ A2 DQ2 DQ A3 DQ3 DQ D1 DQS+ DQS D2 DQS- DQS P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER P5 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND G5 VSS GND
[Pin Mapping] pulldown_ref pullup_ref gnd_clamp_ref power_clamp_ref ext_ref A1 VSS VDD NC NC A2 VSS VDD NC NC A3 VSS VDD NC NC D1 VSS VDD NC NC D2 VSS VDD NC NC P1 NC VDD P2 NC VDD P3 NC VDD P4 NC VDD P5 NC VDD G1 VSS NC G2 VSS NC G3 VSS NC G4 VSS NC G5 VSS NC
pin_names
signal_names for POWER/GND pins
bus_labels for implicitly shorted pins or on-die shorted connections for POWER/GND pins
POWER bus_labels = signal_names
GND bus_labels = signal_names
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Partial Reference Diagram [Pin, Pad, Buffer] (A3, D1, D2
Omitted)Physical Buffer, its Model and On-Die Interconnect
Pads Pins
A1P1P2P3P4P5G1G2G3G4G5A2
Die
A1
A2
Pdref(A2)
Puref(A2)
Pdref(A1)
Puref(A1)
IBIS buffer model
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Terminal Syntax[Begin Interconnect Model]… | Other syntax
Number_of_terminals = <number> | List follows<term_number> <terminal_type> <qualifier> <name> <Aggressor>*… | More lines…[End Interconnect Model]______________________________________________________
<qualifier>: pin_name, signal_name from [Pin] keyword, or bus_label from [Pin Mapping] keyword,*Optional <Aggressor> for Buffer_I/O
Convention: “shorted” connectionelectrical connection
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Legal InterconnectionsTerminal_Type / Qualifier pin_name signal_name bus_label AggressorBuffer_I/O X APuref X Pdref X Pcref X Gcref X Extref X Buffer_rail Y Y Pad_I/O X Pad_rail Y Y Pin_I/O X Pin_rail Y Y
X: I/O pin_names, Y: POWER/GND names,A: Optional Aggressor column to assign one or more aggressor buffers
8Copyright 2015 Teraspeed Labs
Reference Example[Pin] signal_name model_name R_pin L_pin C_pin A1 DQ1 DQ A2 DQ2 DQ A3 DQ3 DQ D1 DQS+ DQS D2 DQS- DQS P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER P5 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND G5 VSS GND
[Pin Mapping] pulldown_ref pullup_ref gnd_clamp_ref power_clamp_ref ext_ref A1 VSS VDD NC NC A2 VSS VDD NC NC A3 VSS VDD NC NC D1 VSS VDD NC NC D2 VSS VDD NC NC P1 NC VDD P2 NC VDD P3 NC VDD P4 NC VDD P5 NC VDD G1 VSS NC G2 VSS NC G3 VSS NC G4 VSS NC G5 VSS NC
pin_names
signal_names for POWER/GND pins
bus_labels for implicitly shorted pins or on-die shorted connections for POWER/GND pins
POWER bus_labels = signal_names
GND bus_labels = signal_names
9Copyright 2015 Teraspeed Labs
With bus_label = signal_name[Pin] signal_name model_name R_pin L_pin C_pin A1 DQ1 DQ A2 DQ2 DQ A3 DQ3 DQ D1 DQS+ DQS D2 DQS- DQS P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER P5 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND G5 VSS GND
pin_names
signal_names for POWER/GND pins
bus_labels for implicitly shorted pins or on-die shorted connections for POWER/GND pins
New optional Bus_signal_name subparameter indicates that POWER/GND signal_name pins are assumed and do not have to be listed
[Pin Mapping] pulldown_ref pullup_ref gnd_clamp_ref power_clamp_ref ext_ref Bus_signal_name A1 VSS VDD NC NC A2 VSS VDD NC NC A3 VSS VDD NC NC D1 VSS VDD NC NC D2 VSS VDD NC NC
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Pin-to-Buffer Interconnect Example using pin_names
[Pin Mapping] not needed, all connections are pin-to-buffer
(Similar to [Package] model direct connection to I/O buffer)
Number_of_Terminals = 12 1 Pin_I/O pin_name A1 | I/O Pin 2 Buffer_I/O pin_name A1 | Buffer Model Nodes 3 Puref pin_name A1 4 Pdref pin_name A1 5 Pin_rail pin_name P1 | POWER Pin 6 Pin_rail pin_name G1 | GND Pin | 7 Pin_I/O pin_name A2 | I/O Pin 8 Buffer_I/O pin_name A2 | Buffer Model Nodes 9 Puref pin_name A2 10 Pdref pin_name A2 11 Pin_rail pin_name P2 | POWER Pin 12 Pin_rail pin_name G2 | GND Pin [End Interconnect Model]
11Copyright 2015 Teraspeed Labs
Pin-to-Buffer Interconnect Example
Physical Buffer, its Model and On-Die Interconnect
Pads Pins
A1P1P2P3P4P5G1G2G3G4G5A2
Die
A1
A2
Pdref(A2)
Puref(A2)
Pdref(A1)
Puref(A1)
12Copyright 2015 Teraspeed Labs
Pin-to-Pad-to-Buffer Exampleusing pin_names
[Pin Mapping] not needed, all connections are pin-to-buffer
(Similar to [Package] model direct connection to I/O buffer)
Number_of_Terminals = 14 1 Pin_I/O pin_name A1 | I/O Pin 2 Pad_I/0 pin_name A1 | Pad I/O Pin 3 Buffer_I/O pin_name A1 | Buffer Model Nodes 4 Puref pin_name A1 5 Pdref pin_name A1 6 Pin_rail pin_name P1 | POWER Pin 7 Pin_rail pin_name G1 | GND Pin | 8 Pin_I/O pin_name A2 | I/O Pin 9 Pad_I/0 pin_name A1 | Pad I/O Pin 10 Buffer_I/O pin_name A2 | Buffer Model Nodes 11 Puref pin_name A2 12 Pdref pin_name A2 13 Pin_rail pin_name P2 | POWER Pin 14 Pin_rail pin_name G2 | GND Pin [End Interconnect Model]
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Pin-to-Pad-to-BufferInterconnect Example
Physical Buffer, its Model and On-Die Interconnect
Pads Pins
A1P1P2P3P4P5G1G2G3G4G5A2
Die
A1
A2
Pdref(A2)
Puref(A2)
Pdref(A1)
Puref(A1)
14Copyright 2015 Teraspeed Labs
Power Rail Interconnect Example using signal_name
[Pin Mapping] optional if bus_labels are signal_names
Number_of_Terminals = 10 1 Pin_I/O pin_name A1 | I/O Pin 2 Buffer_I/O pin_name A1 | Buffer Model Nodes 3 Puref pin_name A1 4 Pdref pin_name A1 5 Pin_rail signal_name VDD | "shorted" POWER Pins 6 Pin_rail signal_name VSS | "shorted" GND Pin | 7 Pin_I/O pin_name A2 | I/O Pin 8 Buffer_I/O pin_name A2 | Buffer Model Nodes 9 Puref pin_name A2 10 Pdref pin_name A2 [End Interconnect Model]
15Copyright 2015 Teraspeed Labs
Pin-to-Buffer Interconnect Example using signal_name
for RailsPhysical Buffer, its Model and On-Die Interconnect
Pads Pins
A1P1P2P3P4P5G1G2G3G4G5A2
Die
A1
A2
Pdref(A2)
Puref(A2)
Pdref(A1)
Puref(A1)
VDD
VSS
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Example with bus_label Groups[Pin] signal_name model_name R_pin L_pin C_pin
A1 DQ1 DQ A2 DQ2 DQ A3 DQ3 DQ D1 DQS+ DQS D2 DQS- DQS P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER P5 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND G5 VSS GND
pin_names
signal_names for POWER/GND pins
bus_labels for implicitly shorted pins or on-die shorted connections for POWER/GND pins
[Pin Mapping] pulldown_ref pullup_ref gnd_clamp_ref power_clamp_ref ext_ref A1 VSS1 VDD1 NC NC A2 VSS1 VDD1 NC NC A3 VSS2 VDD2 NC NC D1 VSS3 VDD3 NC NC D2 VSS3 VDD3 NC NC P1 NC VDD1 P2 NC VDD1 P3 NC VDD2 P4 NC VDD2 P5 NC VDD3 G1 VSS1 NC G2 VSS1 NC G3 VSS2 NC G4 VSS2 NC G5 VSS3 NC [End Interconnect Model]
POWER bus_labels
GND bus_labels
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Power Rail Interconnect Example using signal_names
and bus_labelsNumber_of_Terminals = 12 1 Pin_I/O pin_name A1 | I/O Pin 2 Buffer_I/O pin_name A1 | Buffer Model Nodes 3 Puref pin_name A1 4 Pdref pin_name A1 5 Pin_rail signal_name VDD | "shorted" POWER Pins 6 Pin_rail signal_name VSS | "shorted" GND Pin 7 Pad_rail bus_label VDD1 | "shorted" POWER Bus Groups 8 Pad_rail bus_label VSS1 | "shorted" GND Bus Groups | 9 Pin_I/O pin_name A2 | I/O Pin 10 Buffer_I/O pin_name A2 | Buffer Model Nodes 11 Puref pin_name A2 12 Pdref pin_name A2 [End Interconnect Model]
18Copyright 2015 Teraspeed Labs
Pin-to-Buffer Interconnect Example with signal_names
and bus_labelsPhysical Buffer, its Model and On-Die Interconnect
Pads Pins
A1P1P2P3P4P5G1G2G3G4G5A2
Die
A1
A2
Pdref(A2)
Puref(A2)
Pdref(A1)
Puref(A1)
VDD
VSS
VDD1 VDD2 VDD3
VSS1 VSS2 VSS3
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Default “shorted” Connectionfrom [Pin Mapping]
Physical Buffer, its Model and On-Die Interconnect
Pads Pins
A1P1P2P3P4P5G1G2G3G4G5A2
Die
A1
A2
Pdref(A2)
Puref(A2)
Pdref(A1)
Puref(A1)
VDD
VSS
VDD1 VDD2 VDD3
VSS1 VSS2 VSS3
20Copyright 2015 Teraspeed Labs
Bus_labels used for Pad names for Package to Pad
InterconnectPhysical Buffer, its Model and On-Die Interconnect
Pads Pins
A1P1P2P3P4P5G1G2G3G4G5A2
Die
A1
A2
Pdref(A2)
Puref(A2)
Pdref(A1)
Puref(A1)
21Copyright 2015 Teraspeed Labs
Conclusions• Revised syntax
o Makes use of existing [Pin Mapping] for bus labels and defaults, [Diff Pin], [Series Pin Mapping] for two-node models
o Supports directly all 21 IBIS [Model] Model_typeso Overrides all [Package] model syntax including [Define Package
Model]o Supports IBIS-ISS (an HSPICE subset) and Touchstone electrical
modelso Supports electrical models from pin-to-buffer, pin-to-bus-to-
buffer, and pin-to-bus and default short from bus to buffero I/O buffer 1-to-1 connection assumed, but not so for POWER
and GND interconnections• Issues
o Can two or more [Begin Interconnect Model]s be used together? (E.g., a pin-to-bus simplified package model and a bus-to-buffer interconnect model)