unit vi vlsi

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UNIT VI

ARRAY SUBSYSTEMS: SRAM, DRAM,

ROM, Serial Access Memories,Content Addressable Memory


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Introduction to Array Subsystems


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General concepts

Data storage capacity available on a single integratedcircuit grows exponentially being doubledapproximately every two years.

Capacity of the dynamic read/write memory (DRAM)

chip exceeds now 1 Gigabit. Data transfer speed of a standard DRAM is at the

level of 200Mb/sec/pin.

Static and dynamic power consumption is of the

order of Semiconductor Memories are classifiedaccording to the type of data storage and the type ofdata access mechanism into the following two maingroups:


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Non-volatile Memory (NVM) also known as Read-Only Memory (ROM)which retains information when the power supply voltage is off. Withrespect to the data storage echanism NVM are divided into the followinggroups:

Mask programmed ROM. The required contents of the memory isprogrammed during fabrication,

Programmable ROM (PROM). The required contents is written in apermanent way by burning out internal interconnections (fuses). It is aone-off procedure.

Erasable PROM (EPROM). Data is stored as a charge on an isolated gatecapacitor (floating gate). Data is remove by exposing the PROM to theultraviolet light.

Electrically Erasable PROM (EEPROM) also known as Flash Memory. It isalso base on the concept of the floating gate. The contents can be re-programmed by applying a suitable voltages to the EEPROM pins. TheFlash Memories are very important data storage devices for mobileapplications.


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Read/Write (R/W) memory, also known as

Random Access Memory (RAM). From the

point of view of the data storage mechanism

RAM are divided into two main groups:

Static RAM, where data is retained as long

as there is power supply on.

Dynamic RAM, where data is stored on

capacitors and requires a periodic freshment.


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Fig: Typical Memory Organization


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The memory consists of the following basicblocks:

The array of 1-bit memory cells,

The row decoder which selects a single wordline for a given n-bit row address a[1:n],

The column decoder which selects a single bit

line for a given m-bit column address b[1:m],and routs a 1-bit data to or from a selectedmemory cell.


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Static Random Access Memory - SRAM

Static Read/Write (or Random Access)memory (SRAM) is able to read and write datainto its memory cells and retain the memory

contents as long as the power supply voltageis provided.

Currently SRAM are manufactured in theCMOS technology which offers very low staticpower dissipation, superior noise margin andswitching speed.


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The cells of the CMOS SRAM are based on a simple latch circuit

as shown in Figure


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The two-inverter latch is able to store one bitdata. In order to access the cell the word line isactivated with high-level signal S, which closesaccess switches on both sides of the cell.

The state of the cell (and its complement) is nowavailable on two complemented bit lines and theread operation can be performed.

In order to perform write operation the data and

its complement is supplied through the bit line.We consider some details of the cell operationlater.


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SRAM 6T CELL


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Principles of operations

In order to consider operation of the static

read/write memory we have to take into

account:

relatively large parasitic column

Capacitances, Cc and Cd ,

column pull-up pMOS transistors, as shown

in Figure


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Operation of SRAM Cell

When none of the word lines is selected, that is, all Ssignals are 0, the pass transistors n3, n4 are turned offand the data is retained in all memory cells. Thecolumn capacitances are charged by the drain currents

of the pull-up pMOS transistors, p3, p4. The column voltages Vc and Vd both reach the level just

below VDD VTp, say 3.5V for VDD = 5V and thethreshold voltage VTp = 1V.

For the read or write operations we select the cell

asserting the word line signal S=1. For the write operation we apply a low voltage to one

of the bit line, holding the other one high.


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To write 0 in the cell, the column voltage VC is forced to low (C =0). This low voltage acts through a related pass transistor (n3) onthe gates of the corresponding inverter (n2, p2) so that its inputgoes high. This sets the signal at the other inverter Q = 0.

Similarly, to write 1 in the cell, the opposite column voltage V C

is forced to low ( C = 0) which sets the signal Q = 1.

During the read 1 operation, when the stored bit is Q = 1,transistors n3, p1 and n4, n2 are turned on. This maintains thecolumn voltage VC at its steady-state high level (say 3.5V) while theopposite column voltage V C is being pulled down discharging the

column capacitance C C through transistors n4, n2 so that VC > V C.

Similarly, during the read 0 operation we have VC < V C.


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SRAM Write Circuitry


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Dynamic Read-Write Memory

(DRAM) SRAM drawbacks

large area: 4-6 transistors/bit + 4 lines connections

static power issipation (exception CMOS SRAM)

Nee for high ensity RAM arrays DRAM

binary ata is store as charge in a capacitor

requires perioic refreshing of the store ata

no static power issipation

In the static CMOS read-write memory data is stored in six-transistor cells. Such amemory is fast and consumed small amount of static power. The only problem isthat a SRAM cell occupies a significant amount of silicon space. This problem isaddressed in the dynamic read-write memory (DRAM).

In a dynamic RAM binary data is stored as charge in a capacitor. The memory cellconsists of a storage capacitor and an access transistor as shown in Figure


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Data stored as charge in a capacitor can be retained only for a limited time

due to the leakage current which eventually removes or modifies the

charge.

Therefore, all dynamic memory cells require a periodic refreshing of the

stored data before unwanted stored charge modifications occur.

Typical storage capacitance has a value of 20 to 50 fF.

Assuming that the voltage on the fully charged storage capacitor is V =

2.5V, and that the leakage current is I = 40pA, then the time to discharge

the capacitor C = 20fF to the half of the initial voltage can be estimated as

t= 1(C.V)/2I =20*10-15

*2.5/(40*10-12

) = 0.625ms Hence ever memory cell must be refreshed approximately every half

millisecond.


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To consider read/write operations we have to take into account a

significant parasitic capacitance Cc associated with each column, as shown

in Figure

Typically, before any operation is performed each column capacitance is

precharged high. The cell is selected for a read/write operation by asserting its word line

high (S = 1). This connects the storage capacitance to the bit line.

The write operation is performed by applying either high or low voltage

to the bit line thus charging (write 1) or ischarging (write 0) the storage

capacitance through the access transistor. During read operation there is a flow of charges between the storage

capacitance C1 and the column capacitance, Cc. As a result the column

voltage either increases (rea 1) or ecreases (rea 0) slightly. This

difference can then be amplified by the sense amplifier.


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One-Transistor DRAM Cell


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Dynamic Random Access Memories - DRAM


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READ ONLY MEMEORY-ROM

Mask programmed ROM

Programmable ROM (PROM)

Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM

(EEPROM)

In this section we consider memory cells of Read-Only

Memories programmed by application of specific masks

during the fabrication process. Two basic types of the ROM

cells are based on NOR and NAND gates.


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Mask programmable read-only memories (ROMs) are the least expensive

type of solid state memory.

They are primarily used for storing video game software and fixed data for

electronic equipment, such as fonts for laser printers, dictionary data in

word processors, and sound data in electronic musical instruments.

ROM programming is performed during IC fabrication. Several process

methods can be used to program a ROM. These include

Metal contact to connect a transistor to the bit line.

Channel implant to create either an enhancement-mode transistor or a

depletion-mode transistor. Thin or thick gate oxie, which creates either a stanar transistor or a

high threshold transistor, respectively.


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Mask programmed (ROM) memory circuits


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Unlike in a standard CMOS gate, the pMOS pull-up circuitry is

replaced by a single pMOS with its gate tied up to GND, hence

being permanently on acting as a load resistor.

If none of the nMOS transistors is activated (all Ri being low)

then the output signal C is high.

If any of the nMOS transistors is activated (Ri being high) then

the output signal C is low.

To reduce the power consumption the gate of the pMOS pull-

up transistor is connected to a clock signal. The power is

consumed only during low period of the clock.


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Each memory cell is represented by one nMOS transistor and

a binary information is stored by connecting or not the drain

terminal of such a transistor to the bit line.

For every row address only one word line is activated by

applying a high signal to the gates of nMOS transistors in arow.

If a selected transistor in the i-th column is connected to a bit

line then the logic 0 is stored in this memory cell. if the

transistor is not connected, then the logic 1 is stored.


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NAND-based ROM


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EPROM

EPROM (UV Erasable Programmable Read Only Memory) is a special typeof ROM that is programmed electrically and yet is erasable under UV light.

The EPROM device is programmed by forcing an electrical charge on a

small piece of polysilicon material (called the floating gate) located in the

memory cell.

When this charge is present on this gate, the cell is programme, usuallya logic 0, an when this charge is not present, it is a logic 1.

The floating gate is where the electrical charge is stored.

Prior to being programmed, an EPROM has to be erased.

To erase the EPROM, it is exposed to an ultraviolet light for approximately

20 minutes through a quartz window in its ceramic package.

After erasure, new information can be programmed to the EPROM. After

writing the data to the EPROM, an opaque label has to be placed over the

quartz window to prevent accidental erasure.


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Programming is accomplished through a phenomenon called hot electron

injection.

High voltages are applied to the select gate and drain connections of the

cell transistor.

The select gate of the transistor is pulse on causing a large rain

current to flow.

The large bias voltage on the gate connection attracts electrons that

penetrate the thin gate oxide and are stored on the floating gate.


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EEPROM

EEPROM (Electrically Erasable Programmable ROM) offer users excellent

capabilities and performance.

Only one external power supply is required since the high voltage for

program/erase is internally generated.

Write and erase operations are performed on a byte per byte basis.

The EEPROM uses the same principle as the UV-EPROM. Electrons trapped in afloating gate will moify the characteristics of the cell, an so a logic 0 or a logic

1 will be store.

The EEPROM is the memory device that implements the fewest standards in cell

design. The more common cell is composed of two transistors. The storage

transistor has a floating gate (similar to the EPROM storage transistor) that will

trap electrons.

In addition, there is an access transistor, which is required for operations. Figure 9-

10 shows the voltages applied on the memory cell to program/erase a cell.


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Note that an EPROM cell is erased when electrons are removed from the

floating gate and that the EEPROM cell is erased when the electrons are

trapped in the floating cell.

To have products electrically compatible, the logic path of both types of

prouct will give a 1 for erase state an a 0 for a programme state.

Figure 9-11 shows the electrical differences between EPROM and EEPROM

cells.

EPROM programming: Hot electron

High VPP Current

High ISUB

VPP must be an external supply

No VBB generator

EEPROM programming: Tunneling

VPP is generated by an internal pump.

Figure 9-11. VPP EPROM Versus VPP EEPROM


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Serial Access Memories

Serial access memories do not use an address

Shift Registers

Serial In Parallel Out (SIPO)

Parallel In Serial Out (PISO)

Queues (FIFO, LIFO)


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FIFOs are commonly used in electronic circuits for buffering and flow

control which is from hardware to software.

In its hardware form, a FIFO primarily consists of a set of read and write

pointers, storage and control logic.

Storage may be SRAM, flip-flops, latches or any other suitable form of

storage. For FIFOs of non-trivial size, a dual-port SRAM is usually used,

where one port is dedicated to writing and the other to reading.

A synchronous FIFO is a FIFO where the same clock is used for both

reading and writing. An asynchronous FIFO uses different clocks for

reading and writing.

FIFO full/empty

A hardware FIFO is used for synchronization purposes. It is often

implemented as a circular queue, and thus has two pointers:

Read Pointer/Read Address Register

Write Pointer/Write Address Register
http://en.wikipedia.org/wiki/Electronicshttp://en.wikipedia.org/wiki/Static_random_access_memoryhttp://en.wikipedia.org/wiki/Circular_queuehttp://en.wikipedia.org/wiki/Circular_queuehttp://en.wikipedia.org/wiki/Static_random_access_memoryhttp://en.wikipedia.org/wiki/Electronics


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FIFO Empty

When the read address register reaches the write address register, the FIFO

triggers the Empty signal.

FIFO FULL

When the write address register reaches the read address register, the FIFO

triggers the FULL signal. FIFO Empty

When the read address register equals the write address register, the FIFO is

empty.

FIFO FULL

When the read address LSBs equal the write address LSBs and the extra MSBs aredifferent, the FIFO is full.


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