unit v peripheral interfacing

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UNIT 5

PERIPHERAL INTERFACING

5.1 Introduction

The microprocessor achieves its aim or applies its potential only when it is usedfor data processing or problem solving. The microprocessor has to accept thedata through input devices process them using the Arithmetic and Logic Unit anddisplays the result in a human readable form. In other words we can say themicroprocessor is to be interfaced with input and output devices to provide acomputing environment. Frequently used input devices are Analog to Digital(A/D) converters and keyboard and the output devices are Light Emitting Diodes(LEDs), printers and monitors. These input and output devices are calledperipherals. Since the speed at which the processor and the peripherals operateis different, suitable logic circuits (hardware) and writing instructions (software)

should be used to enable the microprocessor to communicate with theseperipherals. This is called interfacing. The logic circuits are called I/O ports orinterfacing devices. In this unit you will study about the various programmableinterfacing devices. This unit also discusses about the coprocessors that areused to enhance the performance of the microprocessors.

5.2 Learning Objectives

To understand the various issues involved in interfacing peripherals to the

microprocessor

To study about the various modes and formats of I/O communication

To learn the basics of programmable interfacing devices To study about the principles of matrix keyboard operation

To study about the architecture and programming of Intel 8279

To learn the fundamentals and principles of Cathode Ray Tube

To understand the architecture and programming of 8275 CRT controller

To know the basics of coprocessors

To study about the architecture of 8087 coprocessor

5.3 Basics of I/O Operation

The microprocessor communicates with the peripherals in either of the twoformats: asynchronous or synchronous. In synchronous mode the sender and thereceiver are synchronized with the same clock. In asynchronous mode, thecommunication takes place at irregular intervals. The communication betweenthe microprocessor and the peripherals is by and large asynchronous.

The microprocessor receives or sends the data in either of the two modes:parallel and serial. In parallel mode entire word is transferred at a time.

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Keyboards, data converters, LEDs etc are interfaced with the microprocessor inparallel mode. In serial mode, one bit is transferred at a time over a single linebetween the microprocessor and the peripheral. Teletypes (TTY), Cathode RayTube (CRT) terminals etc operate in serial mode.

The microprocessor uses two types of mappings to identify the I/O devices. Themicroprocessor uses a common bus to transfer information between theprocessor and the memory as well as the I/O devices. The distinction between amemory transfer and an I/O transfer is made through the control signals. In suchcases, the processor uses specialized instructions like IN and OUT for I/Otransfers. Moreover the I/O devices and the memory use separate addressspaces. Such a mapping is called I/O mappedI/O.The other type of mapping used by the microprocessors is Memory-Mapped I/Oin which the I/O devices are treated alike memory. Same address space isshared between the memory and I/O devices and a common set of controlsignals are used. In this arrangement an address will refer to memory, if amemory device is connected there; it will refer to an I/O location, if an I/O deviceis connected there. In memory-mapped I/O no separate instructions are neededto differentiate between the memory and I/O devices.

Data transfer between the microprocessor and the peripherals can be controlledeither by the microprocessor or by the peripherals. Most peripherals are slowerthan the microprocessor and hence the conditions for the data transfer are to beset up. In this case, conditions are set up by the microprocessor and this type oftransfer is called microprocessor controlled data transfer. If the peripheral isfaster than the microprocessor then the conditions are set up by the peripheral

and this type of data transfer is called peripheral controlled data transfer. DirectMemory Access Controller (DMAC) is a typical example for the second case.

Have you understood?

1. What are the two formats for I/O operation?2. What are the two modes of I/O operation?3. What is the difference between parallel transfer and serial transfer?4. What are the two types of mappings to identify the I/O devices?5. When does the transfer between the microprocessor and the I/O devices arecontrolled by the I/O devices?

5.4 Programmable Interfacing Devices

I/O functions can be done with the help of either simple integrated circuits orprogrammable devices. Latches and tri-state buffers are simple integratedcircuits whose capabilities are limited. The major limitation of these devices isthey are hard-wired and hence each device can perform only one function. Onthe other hand, a programmable interfacing device is capable of performing

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various input/output functions according to the way in which we program thedevice. This type of device can be set up to perform specific functions by writingan instruction (or instructions) in its internal register. The internal register is calledcontrol register. The particular function the device will perform depends on theinstruction we write into the control register. Hence it is possible to change the

function at any time. In general, programmable interfacing devices are flexible,versatile and economical. They are widely used in microprocessor basedproducts.

A programmable device should include input and output registers, tri-statebuffers, capability for bidirectional data flow, handshake and interrupt signals,control logic, chip select logic and interrupt control logic. Very often, theprogrammable devices include another register by name status register thatmonitors the data lines of the data register. A hypothetical programmable deviceis shown in figure 5.1.

Figure 5.1 Hypothetical programmable Interfacing DeviceHave you understood?

1. What are the advantages of programmable interfacing devices over

buffers and latches?2. Mention the major internal components of a programmable interfacing

device.

5.5 Matrix Keyboard and Multiplexed Display Interface

A matrix keyboard is a commonly used input device when more than eight keysare necessary. A matrix keyboard reduces the number of connections and hence

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reduces the number of interfacing devices. The rows and columns do not haveany connection and the connection occurs when a key is pressed. In otherwords, we can say that pressing a key shorts one row and column. Theinterfacing of a matrix keyboard requires one input port and one output port.Rows are connected to the output port and columns are connected to the input

port. The schematic of the interface is as shown in figure 5.2.

Figure 5.2 Schematic of the Keyboard Interface

In a matrix keyboard, the major task is to identify a key that is pressed anddecode the key in terms of its binary value. This task can be accomplishedthrough either software or hardware. The keyboard has 4 rows and 4 columnsand hence the number of keys is 20. The 6 keys in a sequence represent data 0to F in Hex. The rows are connected to port C and columns are connected to portB of the programmable peripheral interface 8255. Columns and rows makecontact only when a key is pressed, otherwise they remain high. The majorfunction required here is to identify the row and column of the pressed key. Interms of the hardware the intersection of the row and column of the pressed keyshould change from high state (default state) to low state. This is achieved bygrounding all the rows by sending logic 0 through the output port. The interfacingarrangement checks the columns by reading the input port. If any key is pressedthen a change is identified and the key press is decoded. The steps involved inthis process are

1. Check whether all keys are open2. Check a key closure

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3. Identify the key4. Find the binary key code for the key

Various steps like detection, debouncing and encoding is shown in figure 5.3.

Figure 5.3 Reading of a keypress in a matrix keyboard

The matrix keyboard routine is shown as follows with appropriate comments.

KEYBOARD: PUSH B ; Save registersPUSH D

XRA A ; Clear accumulator MOV E,A ; Set up register E as binary code

; counter starting with code forkey 0

OUT PORT C ; Ground all rowsKEYRELS: IN PORT B ; Read columns

ANI 00001111B ; Mask data lines D7-D4CPI 0FH ; Check for key releaseJNZ KEYRELS ; If previous key is not released,

waitin a loop

CALL DEBOUNCE ; Wait for 10 ms when key isReleased

KEYCHECK: IN PORTB ; Read columnsANI 00001111B ; Mask data lines D7-D4CPI 0FH ; Is any key closed?JZ KEYCHECK ; If not, wait in a loopCALL DBOUNCE ; Wait for a key debounce

NEXTROW: RLC ; Move zero in one of the rows

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MOV D,A ; Save data byte to ground nextrow

OUT PORTC ; Ground one of the rowsIN PORTB ; Read columns

ANI 00001111B ; Mask D7-D4

MVI C,04H ; Set column counter NEXTCOLUMN: RAR ; Move D0 in CYJNC CODE ; Key closure is found if zero is in

CYINR E ; Increment binary code for next

keyDCR C ; No key closure found yet,

; decrement column counterJNZ NEXTCOLUMN ; Check for key closure in

nextColumn

MOV A,D ; Load data byte to ground nextrowDCR B ; No key closure found in

columns,; get ready to ground next row

JNZ NEXTROW ; No key closure yet, go back to; ground the next row

JMP KEYCHECK ; No key closure found, it was an; error

MOV A,E ; Load accumulator with binarycode

from code counterPOP D ; Retrieve registersPOP B ;RET ; Return to main program

DBOUNCE: ; This is a 10 ms delay routine, does not destroy any register; content; Input : None; Output : NonePUSH B ; Save registersPUSH PSWLXI B, COUNT ; Load 10ms delay count

LOOP: DCX B ; Repeat loop for delayMOV A,CORA B ; Set zero flag if BC = 0JNZ LOOPPOP PSWPOP BRET

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A display and a keyboard are the two popular peripheral devices used inmicroprocessor based systems. A display and a keyboard are often combined toform a single peripheral device. If we use the scanned-display with the software-driven matrix keyboard, the keyboard subroutine must be coupled with thescanned display. In this case, the program must alternate between refreshing the

display and checking a keyboard to find a key pressed. The time needed for thekeyboard subroutine to check a key is relatively short and hence it does notaffect the display. Another approach is to interface the keyboard using theinterrupt technique. In the interrupt approach, the program continues to scan thedisplay until the interrupt signal is received. Once the interrupt signal is received,the program checks the keyboard, processes the key and goes back to thescanning display.


1. What are the advantages of a matrix keyboard?

2. What are the steps required in identifying a key press in a matrix keyboard.3. What is the necessity to debounce a key press?4. Why a keyboard and a display are combined together to form a single I/Odevice?

5.6 Intel 8279 Keyboard/Display Controller

Intel 8279 is the keyboard/display controller that is used to interface the keyboardand the display of a system to the microprocessor. The advantage of 8279 is thatit is able to drive the signals for both the keyboard and display and hence it ispossible for the microprocessor to concentrate in its routine tasks. The 8279 has

two sections: keyboard and display. The 8279 chip provides a set of four scanlines and eight return lines for interfacing keyboards and a set of eight outputlines for interfacing display. The keyboard section can interface to regular type-writer style keyboards or random toggle or thumb switches. The display sectiondrives alphanumeric displays or a bank of indicator lights. Thus the CPU isrelieved from scanning the keyboard or refreshing the display. The keyboardportion can provide a scanned interface to a 64-contact key matrix. The keyboardportion interfaces an array of sensors or a strobed interface keyboard. Keyboarddepressions can be 2-key lockout or N-key rollover. Keyboard entries aredebounced and strobed in an 8-charcter FIFO. If more than 8 characters areentered, overrun status is set. Key entries set the interrupt output line to theCPU. The display portion provides a scanned display interface for LED,incandescent and other popular display technologies. Both numeric andalphanumeric segment displays may be used as well as simple indicators. The8279 has 16*8 display RAM which can be organized into dual 16*4. The RAMcan be loaded or interrogated by the CPU. Both right entry, calculator and leftentry typewriter display formats are possible. Both read and write of the displayRAM can be done with auto-increment of the display RAM address.

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Since the 8279 is directly connected to the microprocessor, the microprocessorcan program all operating modes of 8279. The various input modes of the 8279are scanned keyboard, scanned sensor matrix and strobed input. In scannedkeyboard mode, a key depression generates a 6-bit encoding of the key position.Position and shift control status are stored in the FIFO. Keys are automatically

debounced with 2-key lockout or N-key rollover. In the scanned sensor matrix,key status is stored in RAM addressable by the microprocessor. Data on returnlines during control line strobe is transferred to FIFO in strobed input. In oneoutput mode, 8 or 16 character multiplexed displays are organized as dual 4-bitor single 8-bit and another output mode deals with right entry or left entry displayformats.

The keyboard interface part of 8279 continuously scans the keyboard to check ifany key has been pressed. If it finds that a particular key has been pressed itsends the code of the corresponding key to the microprocessor. Themicroprocessor uses 8279 to send the result to the display device. In other

words, we can say that 8279 controller transmits the data received from the CPUto the display device. The major advantage of using 8279 is that both of theseactivities are done without the intervention of the microprocessor. The keyboardcan be interfaced to the microprocessor either in the polled mode or in theinterrupt mode. In the polled mode the microprocessor reads an internal flag of8279 to check if any key has been pressed. In the interrupt mode, the processoris requested service only if a key is pressed otherwise the microprocessor canproceed with its routine activities. 8279 permits a maximum of 64 keys to bepresent in the keyboard. This keyboard/display controller maintains an 8-byteFirst in First out Random Access Memory (FIFO RAM). If the FIFO contains avalid key entry, the CPU is interrupted (in interrupt mode) or the CPU checks the

status (in polling mode) to read the entry. Once the CPU reads the key, thecorresponding entry is deleted from the queue to generate space for the futurekeys that may be pressed. The 8279 normally provides a maximum of sixteen 7segment display interface with CPU. It contains a 16-byte display RAM that canbe used either as an integrated block of 16*8 bits or two 16*4 bit blocks of RAM.The data entry to RAM block is controlled by CPU using the command words ofthe 8279.

Figure 5.4 shows the functional block diagram of 8279.

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Figure 5.4 Block diagram of Intel 8279

The I/O control section controls the flow of data to/from the 8279. The databuffers interface the external bus of the system with internal bus of 8279. The I/O

section is enabled only if D (Active Low) is low. The pins A0, Rd (Active Low),WR (Active Low) select the command, status or data read/write operationscarried out by the microprocessor with 8279.

Timing control registers store the keyboard and display modes and otheroperating conditions programmed by the processor. The registers are written with

A0=1 and WR (Active Low) = 0. The timing and control unit controls the basictimings for the operation of the circuit.

Scan counter divide down the operating frequency of 8279 to derive scankeyboard and scan display frequencies. The scan counter has two modes to

scan the key matrix and refresh the display. In the encoded mode, the counterprovides a binary count that is to be externally decoded to provide the scan linesfor keyboard and display. In the decoded scan mode, the counter internallydecodes the least significant 2 bits and provides a decoded 1 out of 4 scan onSL0-SL3. The keyboard and the display both are in the same mode at a time.

Another set of functional components is return buffers and keyboard debounceand control. These components scan for a key closure row wise. If it is detected,

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the keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). Afterthe debounce period, if the key continues to be detected the code of the key isdirectly transferred to the sensor RAM along with SHIFT and CONTROL keystatus.

One more block present in 8279 is the FIFO sensor RAM and Status Logic. FIFOis used to handle the quick pressings of the key. Each key code of the pressedkey is entered in the order of the key, and in the meantime, read by the CPU, tillthe RAM becomes empty. The status logic generates an interrupt request aftereach FIFO read operation till the FIFO is empty. In scanned sensor matrix mode,this unit acts as the sensor RAM. Each row of the sensor RAM is loaded with thestatus of the corresponding row of sensors in the matrix. If a sensor changes itsstate, the IRQ line goes high to interrupt the CPU.

The display address registers hold the address of the word currently beingwritten or read by the CPU to or from the display RAM. The contents of the

registers are automatically updated by 8279 to accept the next data entry byCPU. The 16-byte display RAM contains the 16-bytes of data to be displayed onthe sixteen 7-segment displays in the encoded scan mode.

5.6.1 Signal description 8279 pins

The pin diagram and signal description of 8279 is depicted in figure 5.5. Thesignal descriptions of each of the pins of 8279 are presented below in brief:

DB0-DB7 These are bidirectional data bus lines. The data and commandwords to and from the CPU are transferred on these lines.

CLK This is a clock input used to generate internal timings required by 8279.

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Figure 5.5 Pin diagram and Signal description of 8279

RESET This pin is used to reset 8279. A high on this line resets 8279. Afterresetting 8279, its in sixteen 8-bit display, left entry encoded scan, 2 key lock outmode. The clock prescalar is set to 31.

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CS (Active Low) Chip select. A low on this line enables 8279 for normal read orwrite operations. Otherwise this pin should remain high.

A0 A high on the A0 line indicates the transfer of a command or status

information. Alow on this line indicates the transfer of data. This is used to selectone of the internal registers of 8279.

RD (Active Low) WR (Active Low) READ/WRITE input pins enable the databuffers to receive or send data over the data bus

IRQ The interrupt output line goes high when there is data in the FIFO sensorRAM. The interrupt line goes low with each FIFO RAM read operation. However,if the FIFO RAM further contains any key-code entry to be read by the CPU, thispin again goes high to generate an interrupt to the CPU

Vss and Vcc these are the ground and power supply lines for the circuit

SL0-SL3 Scan Lines These lines are used to scan the keyboard matrix anddisplay digits. These lines can be programmed as encoded or decoded, using themode control register

RL0-RL7 Return Lines These are the input lines which are connected to oneterminal of keys, while the other terminal of the keys are connected to thedecoded scan lines. These are normally high, but pulled low when a key ispressed.

SHIFT The status of the shift input line is stored along with each key code inFIFO in the scanned keyboard board. Till it is pulled low, with the key closure it ispulled up internally to keep it high.

CNTL/STB-CONTROL/STROBED I/P mode In the keyboard mode, this line isused as a control input and stored in FIFO on a key closure. The line is a strobedline that enters the data into FIFO RAM in the strobed input mode. It has aninternal pull up. The line is pulled down with the key closure.

BD Blank Display This output pin is used to blank the display during digitswitching or by a blanking comment.

OUTA0 OUTA3 and OUTB0 OUTB3 These are the output ports for two 16*4(or one 16*8) internal display refresh registers. The data from these lines issynchronized with the scan lines to scan the display and keyboard. The two fourbit ports may also be used as one eight bit port.

5.6.2 Modes of Operation

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In scanned keyboard mode with 2 key lockout, when a key is pressed, adebounce logic comes into operation. During the next two scans, the other keysare checked for closure and if no other is pressed the first pressed key isidentified. The key code of the identified key is entered into the FIFO with SHIFTand CNTL status, provided that FIFO is not full, that is it has at least one byte

free. If the FIFO does not have any free byte, naturally the key data will not beentered and the error flag is set. If the FIFO has at least one byte free, the abovecode is entered into it and the 8279 generates an interrupt (on IRQ line) to theCPU to inform about the previous key closures. If another key is found closedduring the subsequent two sacns, no entry to FIFO is made. If all the other keysare released before the first key, the key code is entered into FIFO. If the firstpressed key is released before the others, the first will be ignored. A key code isentered to FIFO only once for each valid depression, independent of other keyspressed along with it, or released before it. If two keys are pressed within adebounce cycle (simultaneously) no key is recognized till one of them remainsclosed, and the other is released. The last key that remains depressed is

considered as single valid key depression.

In scanned keyboard with N-key rollover each key depression is treatedindependently. When a key is pressed the debounce circuit waits for twokeyboard scans and then checks whether the key is still depressed. If it is stilldepressed, the code is entered in FIFO RAM. Any number of keys can bepressed simultaneously and recognized in the order, the keyboard scan recordedthem. All the codes of such keys are entered into FIFO. Note that, in this mode,the first pressed key need not be released before the second is pressed. All thekeys are sensed in the order of their depression, rather in the order the keyboardscan senses them, and independent of the order of their release.

The scanned keyboard special error mode is valid only under the N-key rollovermode. This mode is programmed using end interrupt/error mode set command. Ifduring a single debounce period (two keyboard scans) two keys are foundpressed, this is considered a simultaneous depression and an error flag is set.This flag, if set, prevents for the writing in FIFO, but allows generation of furtherinterrupts to the CPU for FIFO read. The error flag can be read by reading theFIFO status word. The error flag is set by sending normal clear command withCF = 1.

In the sensor matrix mode, the debounce logic is inherited. The 8-byte FIFORAM now acts as 8*8 bit memory matrix. The status of the sensor switch matrixis fed directly to sensor RAM matrix. Thus the sensor RAM bits contain the rowwise and column wise status of the sensors in the sensor matrix. The IRQ linegoes high, if any change in sensor value is detected at the end of a sensor matrixscan or the sensor RAM has a preivous entry to be read by the CPU. The IRQline is reset by the first data read option, if AI = 0, otherwise, by issuing the endinterrupt command. AI is a bit in read sensor RAM word.

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There are various options of data display. For example, the command number ofcharacters can be 8 or 16, with each character organized as single 8-bit or dual4-bit codes. Similarly, there are two display formats. The first one is known as leftentry mode or type writer mode, since in a type writer the first character typedappears at the left most position, while the subsequent characters appear

successively to the right of the first one. The other display format is known as theright entry mode, or calculator mode, since in a calculator the first characterentered appears at the rightmost position and this character is shifted oneposition left when the next character is entered. Thus all the previously enteredcharacters are shifted left by one position when a new character is entered.

In the left entry mode, the data is entered from the left side of the display unit.Address 0 of the display RAM contains the leftmost display character andaddress 15 of the RAM contains the right most display character. It is just likewriting in our note books, i.e., from left to right. If the 8279 is in auto incrementmode, the display on the leftmost display and the sixteenth entry on the rightmost

display. The seventeenth entry is again displayed at the leftmost display position.

In the right entry mode, the first entry to be displayed is entered on the rightmostdisplay. The next entry is also placed in the right most display but after theprevious display is shifted left by one display position. The leftmost character isshifted out of that display at the seventeenth entry and is lost; it is pushed out ofthe display RAM.

5.6.3 Software Operation

The following commands program the 8279 operating modes. The commands

are sent on the data bus with CS (Active Low) and A0 high and are loaded to the8279 on the rising edge of WR (Active Write).

Keyboard/Display Mode Set

Where DD is the display mode and KKK is the keyboard mode. For display modethe various combinations are

For keyboard mode the various combinations are

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Programmable Clock

The clock for operation of 8279 is obtained by dividing the external clock inputsignal by a programmable constant called prescalar.

PPPPP is a 5-bit binary constant. The input frequency is divided by a decimalconstant ranging from 3 to 31, decided by the bits of an internal prescalarPPPPP.

Read FIFO/Sensor RAM

X Dont CareAI Auto Increment flagAAA Address pointer to 8-bit FIFO RAM

This command is used to set the 8279 for a read of the FIFO/Sensor RAM by firstwriting this command. In the scan keyboard mode, the Auto Increment flag andthe RAM address bits (AAA) are irrelevant. The 8279 will automatically drive thedata bus for each subsequent read in the same sequence in which the data first

entered the FIFO. All subsequent reads will be from FIFO until another commandis issued. In the sensor matrix mode, the bits AAA select one of the 8 rows of theRAM. If AI flag is set, each successive read will be from the subsequent row ofthe sensor RAM.

Read Display RAM

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This command enables a programmer to read the display RAM data. The CPUwrites this command word to 8279 to prepare it for display RAM read operation.

AI is auto increment flag and AAAA, the 4-bit address, points to the 16-bytedisplay RAM that is to be read. If AI=1, the address will be automatically,

incremented after each read or write to the display RAM. The same addresscounter is used for reading and writing.

Write Display RAM

The microprocessor uses this command to set up the 8279 for a write to thedisplay RAM. The addressing and auto-increment functions are identical to thosefor the Read Display RAM. However, this command does not affect the sourceof subsequent data read. The CPU will read from whichever RAM (Display or

FIFO/Sensor) which was last specified.

Display Write inhibit/Blanking

The Inhibit Write (IW) bits are used to mask the individual nibble in applicationsrequiring separate 4-bit display ports. Once a nibble is masked by setting thecorresponding IW bit to 1, the entry to display RAM does not affect the nibbleeven though it may change the unmasked nibble. The Blank display (BL) flagsare used for blanking A and B nibbles. If the user wishes to blank the display, theBL flags are available for each nibble.

Clear Display RAM

The CD2, CD1 and CD0 is a selectable blanking code to clear all the rows of thedisplay RAM as given below. The characters A and B represent the outputnibbles.

1 0 X All zeros (X dont care) AB = 001 1 0 A1-A2 = 2 (0010) and B3-B0 = 00 (0000)1 1 1 All ones (AB=FF), i.e. clear RAM

End Interrupt/Error Mode Set

For the sensor matrix mode, this command lowers the IRQ line and enablesfurther writing into the RAM. Otherwise, if a change in sensor value is detected,

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IRQ goes high that inhibits writing in the sensor RAM. For N-key rollover mode, ifthe E bit is programmed to be 1, the 8279 operates in special error mode.

Status Word, data Read and Data Write

The status word contains the FIFO status, error and display unavailable signals.This word is read by the CPU when A0 is high and CS (Active Low) and RD(Active Low) are low. Data is read when A0, CS (Active Low) and RD(ActiveLow) are all low. The source of the data is specified by the READ FIFO or READDisplay commands. The trailing edge of RD (Active Low) will cause the addressof the RAM being read to be incremented if the Auto-Increment flag is set. FIFOreads always increment independent of AI. Data that is written with A0, CS(Active Low) and WR (Active Low) low is always written to the Display RAM. Theaddress is specified by the latest Read Display or Write Display command. Auto-Incrementing on the rising edge of WR (Active Low) occurs if AI is set by thelatest display command.

Typical configuration of an 8-bit processor, 8279 keyboard/display controller andthe peripherals is shown in figure 5.6.

Figure 5.6 Interfacing Keyboard/Display to the Microprocessor Using Intel 8279


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1. What are the functional components of 8279 keyboard display controller?2. Differentiate between 2-key lockout and N-key rollovers of the key depression.3. How do the items in the queue are processed in polling and interrupt mode?4. What is the information available in the status word of Intel 8279?

5. What is the difference between the typewriter mode and the calculator mode indisplay?

5.7 CRT Fundamentals

Early computers communicated with the user with either indicator lamps or hardcopy printers, but today, the primary output device is the electronic display. Thisis usually the CRT display, although other technologies are available. The CRTdisplay uses the same technology as the television.

It is the oldest and most popular display technology. Advantages of CRT are as

follows. Low cost because of volume of production.

Speed of updating and the retention of image is good.

Colour display is available.

Text and graphics display modes.

Disadvantages of CRT are as follows.

Large size and weight: Typical CRT displays are at least as deep as they

are wide

High voltage and power consumption.

Also generate a lot of heat.

CRT displays are glass vacuum tubes, and are therefore relatively fragile.

The microprocessor interface is relatively complex.

Figure 5.7 shows the basic components of the CRT. The vacuum glass tube hasat the end of its neck a heated filament. The electrons emitted are attractedtowards the face of the screen by the electric field created by the high tension(HT) voltage applied between the cathode and the anode. For a 12-inch monitor,this voltage is about 1200V. The beam of electrons passes through the focusingand deflection electrostatic plates or coils along the way. The screen is coated

with a thin phosphor layer which emits light when impacted by an electron at thatpoint. The voltage applied to the control grid regulates the intensity of theelectron beam. Since the brightness of the screen is dependent on the number ofelectrons hitting the phosphor, the display brightness is a function of the controlvoltage applied to the grid. For monochrome displays, the colour of the display isdependent on the type of phosphor used. The focusing anode, sometimes calledan electrostatic lens, forms the emitted electrons into a thin circular beam (alongthe Z direction), so that the image created on the screen is a sharp well-defined

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spot. Magnetic focusing coils are common and can produce a narrower beam ofelectrons, that is, a sharper focus.

The electron beam is aimed at a particular point on the screen by passing itthrough an electromagnetic field generated by the set of deflection coils in the

yoke assembly. Two vertical deflection coils generate a field perpendicular in Xdirection of the electrons, allowing the electron beam to be scanned vertically.And two horizontal deflection coils do the same in the horizontal direction, thusenabling the beam to be positioned anywhere on the face of the tube. The CRTused in oscilloscopes which require faster, more precise and linear positioning ofthe beam uses electrostatic deflection plates in the tube rather than deflectioncoils.

Figure 5.7 Basic Components of the CRT

CRT INTERFACE SIGNALS

The circuit that interfaces the microprocessor buses to the CRT monitor is calledthe CRT controller. The three basic signals that must be provided to the CRTmonitor are the video information, horizontal sync, and vertical sync. Each timehorizontal sync is asserted, the electron beam retraces to the left edge of thescreen. Each time vertical sync is asserted, the beam retraces to the top of thescreen. These signals are usually provided by the CRT controller to synchronizethe sweep oscillators in the monitor to the video information. For special

applications, such as overlaying of computer generated video on televisionimages, the CRT controller may accept the sync signals as inputs andsynchronize the computer-generated video to them. The major interface signalsare shown in figure 5.8.

Some CRT monitors use signals called horizontal driveand vertical drive insteadof the sync signals described above as shown in figure 5.8. These signals havethe same period as sync signals but different pulse widths and polarity.

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Figure 5.8 Major Interface Signals

Figure 5.9 Horizontal and Vertical sync Pulses

Horizontal sync: Retraces beam to the left edge of the screen.

Horizontal oscillator: Saw-tooth signal that sweeps the beam horizontally

across the screen.

Vertical sync: Causes beam to retrace to the top of the screen.

Vertical oscillator:Saw-tooth signal applied to the vertical deflection

amplifier to move the beam down the screen.

Video signal: Determines the intensity of the beam that will strike thescreen. The signal is amplified and applied as the accelerating voltage inthe CRT.

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1. What are the advantages of CRT?2. What are the major components of a CRT?3. What is a CRT controller?

5.8 CRT CONTROLLER 8275

A CRT controller generates all the signals and coordinates the supportingactivities for interfacing and controlling a CRT display with a microprocessor.Intels 8275 is a programmable CRT controller designed to interface raster scandisplays with Intel microcomputer systems. This device refreshes the displaybesides storing the display data obtained from the CPU, in a display buffer(RAM). This also keeps a track of the current display position pointer (cursor) ofthe screen and offers different formats and styles to the display.

5.8.1 Internal Architecture of 8275

The internal architecture of 8275 is shown in figure 5.10. The functionaldescription of each block is presented in this section.

Figure 5.10 Functional block diagram of 8275

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Data Bus Buffer: this tri-bidirectional 8-bit buffer interfaces the internal circuit of8275 with the external system data bus, used to read or write the internalregisters of 8275 or to send data to the display RAM.

Read /Write Control Logic: the definitions of all the input signals accepted by this

block will be explained later in the signal description section. This block decodesthe lines A0, RD, WR and CS as shown below.

CS A0 RD WR Operations

0 0 0 1 Read 8275 parameter Reg

0 0 1 0 Write 8275 parameter Reg

0 1 0 1 Read 8275 status Reg

0 1 1 0 Write 8275 command Reg

Character Counter: This is a programmable counter used to determine thenumber of characters to be displayed per row and the length of the horizontalretrace interval. This driven by CCLK ( Character Clock) input that is derived fromthe dot clock. The dot clock decides for how much time a smallest dot on thescreen which may form a character should be displayed on the screen.

Line Counter: This is a programmable counter used to decide the number of rowsto be displayed per frame and the length of vertical retrace interval.

Light Pen Registers: These are the two registers that store the contents of thecharacter counter and row counter whenever a rising edge is detected at the

LPEN input pin.

Raster Timing and Video Control: The raster timing circuit controls the timing ofthe HRTC and VRTC outputs. The video control circuit controls the generation ofLA0-LA1 (Line Attribute), HGLT (High Light), RVV ( Reserve Video), LTEN (LightEnable), VSP (Video Suppress) and GPA0-GPA1 (General Purpose Attribute )outputs.

Row BuffersThese two 80 characters row buffers are filled from the microcomputer systemmemory with the character codes to be displayed. While a buffer is displaying a

row of characters, the other is being filled with the next row of characters to bedisplayed.

FIFOsThese two sixteen-character FIFOs in the 8275 are used to provide extra rowbuffer length in the transparent attribute mode.

Buffer Input/Output Controllers

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These buffer input/output controllers decode the character information beingplaced in the row buffers. If the character is a character attribute, field attribute ora special code, the controllers decide the appropriate action. For example, endof screen-stop DMA special code will cause the input buffer controller to stopfurther DMA requests. Then a highlight attribute code causes the Buffer Output

Controller to activate the HGLT output.

5.8.2 Signal descriptions of 8275

The pin configuration of 8275 is shown in figure 5.11. .

Figure 5.11 Pin diagram of 8275

The signal descriptions are as follows.

Line Counter Outputs (LC0-LC1)These are outputs of the line counter, used to address the character generatorfor the current line position on the screen.

DMA Request (DRQ)This is a DMA request output pin that is used to request for a service of one ofthe DMA channels of 8257 DMA controller, in DMA mode.

DMA Acknowledge (DACK)

This is an input pin that accepts the acknowledge signal from a DMA controller ,to indicate to the CRT controller that it has been offered a DMA cycle as aresponse to its DMA request.

Horizontal Retrace (HRTC)This output is active during the programmed horizontal retrace interval. Duringthe active HRTC, the VSP output is high and the LTEN is low.

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Vertical Retrace (VRTC)This output signal is active during the programmed vertical retrace interval.During this period, the VSP output is high and the LTEN is low.

Read Signal (RD)

This is an input control signal used by the CPU to read the internal registers of8275

Write Signal (WR)This is an input control signal used to write the data into the control registers of8275 or to write it into the display RAM via row buffers.

Light Pen (LPEN)This is an input control signal driven by a light pen system that informs the 8275that a light pen signal has been detected.

Data Bus (DB0 DB7)This is a bidirectional tri-state data bus that is used for read or write operationsfrom / to the 8275 internal registers.

Ground (GND)This is ground pin (supply return line) for the internal circuit of the 8275.

A0The input address line A0, if goes high, selects the C port or the commandregister and if goes low, selects the P port or the parameter register of 8275.

Chip Select (CS)This is an active-low chip select input. If this is high, all the read or writeoperations to 8275 are disabled.

Character Code Lines (CC0-CC6)These are output lines from the row buffers and are used for character selectionfrom the character generator ROM.

Character Clock (CCLK)This is a clock input that is driven by the dot/timing logic. This frequency decidesthe time duration allotted for display of a character.

Interrupt Request (IRQ)This is an output pin used to generate an interrupt request to the CPU.

Highlight (HLGT)This output signal is used to intensify the display at the particular positions on thescreen as determined by the character attribute codes or the field attribute codes.

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General Purpose Attribute Codes (GPA0 GPA1)These are the outputs enabled by the general purpose field attribute codes.

Video Suppression (VSP)

This is an output signal used to blank the video signal to the CRT, which is activeduring the horizontal and vertical retrace intervals.- At the top and bottom lines of rows, if an underline is programmed to be at

line number 8 or above.- When an end of row or an end of screen is detected.- When DMA overrun occurs.- At regular intervals (1/16 frame frequency for cursor, 1/32 frame frequency

for character and field attribute) to create blinking displays if specified bythe cursor character attribute or field attributes programmed.

Reverse Video (RVV)

This is an input pin used to indicate to the CRT circuit to reverse the video signal.This is active at the cursor positions, if a reverse video block cursor isprogrammed. This is also active at the positions specified by the field attributecodes.

Light Enable (LTEN)This output is used to enable the video signal to CRT. This is active at theprogrammed underline cursor position and at the position specified by theattribute codes.

Line Attribute Codes (LA0 LA1)

These outputs have to be decoded externally by the dot/timing logic to generatethe horizontal and vertical line combinations for the graphic displays as specifiedby the character attribute codes.

VccThis is a +5V power supply pin.

5.8.3 Schematic Interface

The 8275 is programmable to a large number of different display formats. Itprovides raster timing, display row buffering, visual attribute decoding, cursortiming and light pen detection. The 8275 is designed to operate in amicroprocessor system with an 8257 DMA controller and the standard charactergenerator ROM for dot matrix decoding. The dot level timings are to be providedby an external circuitry. The interfacing schematic of 8275 with an 8257 DMAcontroller in a general microprocessor system is shown in figure 5.12.

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Figure 5.12 Interfacing Schematic of 8275 with an 8257 DMAC

The 8275 picks up a row of characters to be displayed from the system memoryand set them into an 80 character row buffer. The 8275 has two such buffers.When one buffer is being filled up with characters, the other buffer is on display.Thus the two row buffers are displayed one by one till the display frame is over.The number of characters per row and the number of rows per display frame areprogrammable. When one buffer is being and the other is already displayed, the8275 requests a DMA cycle to fill the already displayed buffer. This continues tillthe complete display frame is over.


1. What are the functional components of Intel 8275?2. What is the necessity to refresh the display?3. What is the function of buffer input/output controllers of 8275?

5.9 CoprocessorsThe 8086/8 and 80186/8 are general purpose microprocessors, designed for avery wide range of applications. Typically, these applications need fast, efficientdata movement and general purpose control instructions. Arithmetic on data

values tends to be simple in these applications. The 8086/8 and 80186/8 fulfillthese needs in a low cost, effective manner. However, some applications requireextremely fast and complex math functions which are not provided by a generalpurpose processor. Such functions as square root, sine, cosine, and logarithmsare not directly available in a general purpose processor. Software routinesrequired to implement these functions tend to be slow and not very accurate.Integer data types and their arithmetic operations (i.e., add, subtract, multiply anddivide) which are directly available on general purpose processors, still may not

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meet the needs for accuracy, speed and ease of use. Providing fast, accurate,complex math can be quite complicated, requiring large areas of silicon onintegrated circuits. A general data processor does not provide these features dueto the extra cost burden that less complex general applications must take on. Forsuch features, a special numeric data processor is required one which is easy

to use and has a high level of support in hardware and software.

The 8087 is a numeric data coprocessor which is capable of performing complexmathematical functions while the host processor (i.e. the main CPU) performsmore general tasks. It supports the necessary data types and operations andallows use of all the current hardware and software support for the 8086/8 and80186/8 microprocessors. The fact that the 8087 is a coprocessor means it iscapable of operating in parallel with the host CPU, which greatly improves theprocessing power of the system. The 8087 can increase the performance offloating point calculations by 50 to 100 times, providing the performance andprecision required for small business and graphics applications as well as

scientific data processing. The 8087 numeric coprocessor adds 68 floating-pointinstructions and eight 80-bit floating-point registers to the basic 8086programming architecture. All the numeric instructions and data types of the8087 are used by the programmer in the same manner as the general data typesand instructions of the host. The numeric data formats and arithmetic operationsprovided by the 8087 support the proposed IEEE Microprocessor Floating PointStandard. All of the proposed IEEE floating point standard algorithms, exceptiondetection, exception handling, infinity arithmetic and rounding controls areimplemented. The IEEE standard makes it easier to use floating point and helpsto avoid common problems that are inherent to floating point.

Figure 5.13 Internal Architecture of 8087

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5.9.1 Architecture of 8087

The internal architecture of 8087 is shown in figure 5.13. The 8087 is divided intotwo sections internally namely the Control Unit (CU) and the Numeric ExtensionUnit (NEU). The numeric extension unit executes all the numeric processor

instructions while the control unit receives, decodes instructions, reads andwrites memory operands and executes the 8087 control instructions. These twounits may work asynchronously with each other. The control unit is mainlyresponsible for establishing communication between the CPU and memory andalso for coordinating the internal coprocessor execution. The CPU, while fetchingthe instructions from memory, monitors the data bus to check for the 8087instructions. Meanwhile, the 8087 CU internally maintains a parallel queue,identical to the status queue of the main CPU. The CU automatically monitors theBHE/S7 line to detect the CPU type, i.e., 8086 or 8088 and accordingly adjuststhe queue length. The 8087 further uses the QS0 and QS1 pins to identify theinstructions fetched by the host CPU, which identifies the coprocessor

instructions using the ESCAPE code bits in them. Once the CPU recognizes theESCAPE code, it triggers the execution of the numeric processor instruction in8087.

While executing, the ESCAPE code identifies the coprocessor instructions thatrequires memory operand and also one that does not require any memoryoperands. If the instruction requires a memory operand to be fetched frommemory, then the physical address of the operand is calculated using any one ofthe addressing modes allowed in 8086 and a dummy read cycle is initiated by theCPU. However, the CPU does not read the operand, rather 8087 reads it andproceeds for execution. If the coprocessor instruction does not require any

memory operand, then it is directly executed. Whenever the 8087 is ready withthe execution results the CU gets the control of the bus from 8086 and executesa write cycle to write the results in the memory at the pre-specified address.

The Numeric Extension Unit (NEU) executes all the instructions includingarithmetic, logical, transcendental, and data transfer instructions. The internaldata bus is 84 bits wide including 68-bit fraction, 15-bit exponent and a sign bit.When the NEU begins the execution, it pulls up the BUSY signal. This BUSYsignal is connected to the TEST input of 8086. If the BUSY signal of 8087 isasserted by it, the CPU recognizes that the instruction execution is not yetcomplete. This makes 8086 wait till the BUSY pin of 8087, i.e., the TEST inputpin of 8086 goes low or, in other words, till the coprocessor executes theinstruction completely. The microcode control unit generates the control signalsrequired for execution of the instructions. 8087 contains a programmable shifterwhich is responsible for shifting the operands during the execution of instructionslike FUML and FDIV. The data bus interface connects the internal data bus of8087 with the CPU system data bus.

5.9.2 Signal Description of 8087

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The pin diagram of 8087 is shown in figure 5.14. This section deals with thedifferent signals of 8087.

AD0 AD15

These are the time multiplexed address/data lines. These lines carry addressesduring T1 and data during T2,T3,Tw and T4 states. A0 is used, whenever thetransfer is on lower byte (D0 D7) of data bus, to derive the chip select. Theseact as input lines for CPU driven bus cycles, and become input/output lines forthe NDP initiated cycles.

A19/S6-A16/S3These lines are the time multiplexed address/status lines. These function in a

similar way to the corresponding pins of 8086. The S6, S4, and S3 arepermanently high, while the S3 is permanently low.

BHE/S7During T1 the BHE/S7 pin is used to enable data on the higher byte of the 8086data bus. During T2, T3, Tw and T4 this is a status line S7. this does not carryany significance in 8088 based systems. Ti, here, denotes the ith clock state ofan instruction cycle.

QS1, QS0The queue status input signals QS1 and QS0 enable 8087 to keep track of the

instruction prefetch queue status of the CPU, to maintain synchronism with it.The status of these lines can be decoded as given in the following table.

Qs1 Qs0 Queue Status

0 0 No operation

0 1 First byte of opcode fromqueue

1 0 Empty queue

1 1 Subsequent byte from queue

These lines of 8087 are connected with the respective lines of 8086/8088. From

these signals, 8087 comes to know the status of the internal instruction prefetchqueue of 8086.

INTThe interrupt output is used by 8087 to indicate that an unmasked exception hasbeen received during execution. This is usually handled by 8259A.

BUSY

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This output signal, when high, indicates to the CPU that it is busy with theexecution of an allotted instruction. This is usually connected to the TEST pin of8086 or 8088.

READY

This input signal may be used to inform the coprocessor that the addresseddevice will complete the data transfer from its side and the bus is likely to be freefor the next bus cycle. Usually this is synchronized by the clock generator 8284.

RESETThis input signal may be used to abandon the internal activities of thecoprocessor and prepare it for further execution whenever asked by the mainCPU.

CLKThe CLK input provides the basic timings for the processor operation.

VccA +5V supply line is required for operation of the circuit

GNDA return line for the power supply.

S2,S1, and S0These can be either 8087 driven (output) or externally driven (input) by the CPU.If these are driven by 8087, they can be decoded as given in the following table.

S2 S1 S0 Queue Status0 X X Unused

1 0 0 Unused

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

These lines become active during T4 (previous), i.e., prior to actual starting of thebus cycle and remain active till T1 or T2 (current). They are suspended during T3for the next bus cycle. These are used by bus controllers to derive the read andwrite signals. These signals act as input signals if the CPU is executing a task.

RQ/GT0The request/Grant pin is used by the 8087 to gain control of the bus from thehost 8086/8088 for operand transfers. It must be connected to one of therequest/grant pins of the host. The request/grant sequence is described asfollows:

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An active-low pulse of one clock duration is generated by 8087 for thehost to inform it that it wants to gain control of the local bus either for itself or forother coprocessor connected to RQ/GT1 pin of 8087. the 8087 waits for the grantpulse from the host. when it is received, it either initiates a bus cycle if therequest is for itself or else, it passes the grant pulse to RQ/GT1, if the request is

for the other coprocessor. The 8087 will release the bus by sending one morepulse on RQ/GT0 line to the host either after completion of the last bus cycleinitiated by it or as a response to a release pulse on the RQ/GT1 line issued bythe other coprocessor.

RQ/GT1This bidirectional pin is used by the other bus maters to convey their need of thelocal bus access to 8087. This request is further conveyed to the host CPU. Atthe time of the request, if the 8087 does not have control of the bus, the requestis passed on to the host CPU using RQ/GT0 pin. If however, the 8087 hascontrol over the bus when it receives a valid request on RQ/GT1 pin; the 8087

sends a grant pulse during the following T4 or T1 clock, to the requesting masterindicating that it has floated the bus. The requesting master gains the control ofthe bus till it needs. At the end, the requesting master issues an active low, oneclock state wide pulse for 8087, to indicate that the task is over and 8087 mayregain the control of the bus. The request grant pins may be used by the otherbus masters like DMA controllers.

5.9.3 Register Set

The 8087 has a set of eight 80-bit registers. Each of the eight data registers inthe 8087s register stack is 80 bits and is divided into fields corresponding to the

8087s temporary real data type. At a given point in time the TOP field in thecontrol word identifies the current top-of-stack register. A push operationdecrements TOP by 1 and loads a value into the new top register. A popoperation stores the value from the current top register and then increments TOPby 1. Like CPU stacks in memory, the 8087 register stack grows down towardlower-addressed registers.

The status word reflects the overall state of 8087. It is stored in the memory andthen inspected by the CPU code. The status word is a 16-bit register divided intofields as shown in figure 5.14.

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Figure 5.14 Status Word

The busy bit (bit 15) indicates whether the NEU is either executing an instructionor has an interrupt request pending (B=1), or is idle (B=0). Several instructionswhich store and manipulate the status word are executed exclusively by thecontrol unit, and these do not set the busy bit themselves.

The tag word makes the content of each register as shown in figure 5.15. Theprincipal function of the tag word is to optimize the 8087s performance. The tagword can be used, however, to interpret the contents of 8087 registers.

Figure 5.15 Tag WordThe instruction and data pointers as shown in figure 5.16 are provided for user-written error handlers. Whenever the 8087 executes a math instruction, thecontrol unit saves the instruction address, the operand address (if present) andthe instruction opcode. 8087 instructions can store this data into memory.

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Figure 5.16 Instruction and Data Pointer

The control word register of 8087 allows the programmer to select the required

processing options out of available ones. In other words, the 16-bit control wordregister is used to control the operation of the 8087. The bits B0-B5 are used formasking the different exceptions. An exception may be masked by setting therespective bit in the control word register. The M bit is a common interrupt maskfor all the interrupts. If it is set, all the exceptions generated will be masked andthe execution may continue. The precision control and rounding control bitscontrol the precision option and rounding option as shown in figure 5.17. Theinfinity result control bit IC provides control over the number size on both sides,i.e., either + or -.

Figure 5.17 Control Word

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The 8087, while executing an instruction, may generate six different options. Anyof these exceptions, if generated, causes an interrupt to the CPU provided it isnot masked. The CPU will respond if the interrupt flag of the CPU is set. If theexceptions are masked the 8087 continues the execution, independent of the

responses from the CPU. If any of the six exceptions is masked and it isdetected, the 8087 modifies the corresponding bit in the status register, andexecutes an on-chip exception handler that allows it to continue with theexecution. Invalid operation, overflow, underflow, zero divide, denormalizedoperand and inexact result are the six different options.

Figure 5.18 Communication between Microprocessor and Coprocessor

The communication between 8087 and the host CPU have already beendiscussed. In this section, we study the physical interconnections of 8087 with

8086/8088 and 80186/80188. 8087 can be connected with any of these CPUsonly in their maximum mode of operation, i.e., only when the MN/MX pin of theCPU is grounded. In maximum mode, all the control signals are derived using aseparate chip known as a bus controller. The 8288 is 8086/88 compatible buscontroller while 82188 is 80186/80188 compatible bus controller. Thecommunication between the microprocessor and coprocessor is shown in figure5.18.

The BUSY pin of 8087 is connected with the TEST pin of the used CPU. TheQS0 and QS1 lines may be directly connected to the corresponding pins in caseof 8086/8088 based systems. However, in case of 80186/80188 systems these

QS0 and QS1 lines are passed to the CPU through the bus controller. In case of8086/8088 based systems the RQ/GT0 of 8087 may be connected to RQ/GT1 ofthe 8086/8088. The clock pin of 8087 may be connected with the CPU8086/8088 clock input. The interrupt output of 8087 is routed to 8086/8088 viaprogrammable interrupt controller. The pins AD0-AD15, BHE/S7, RESET,

A19/S6-A16/S3 are connected to the corresponding pins of 8086/8088. in case of80186/80188 systems the RQ/GT lines of 8087 are connected with thecorresponding RQ/GT lines of 82188.

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1. What is the necessity of a coprocessor?2. What is the coprocessor for 8086/8088 microprocessor?

3. What are the two functional units of 8087 numeric data coprocessor?4. How the bus is properly shared between the microprocessor and thecoprocessor?

5. What is the purpose of the tagword in 8087?

Summary

1. I/O functions can be done with the help of either simple integrated circuitsor programmable devices. Latches and tri-state buffers are simpleintegrated circuits whose capabilities are limited.

2. On the other hand, a programmable interfacing device is capable of

performing various input/output functions according to the way in whichwe program the device.3. A matrix keyboard is a commonly used input device when more than eight

keys are necessary. A matrix keyboard reduces the number ofconnections and hence reduces the number of interfacing devices.

4. The rows and columns of a matrix keyboard do not have any connectionand the connection occurs when a key is pressed. In other words, wecan say that pressing a key shorts one row and column.

5. In a matrix keyboard, the major task is to identify a key that is pressed anddecode the key in terms of its binary value. This task can beaccomplished through either software or hardware.

6. Intel 8279 is the keyboard/display controller that is used to interface thekeyboard and the display of a system to the microprocessor. Theadvantage of 8279 is that it is able to drive the signals for both thekeyboard and display and hence it is possible for the microprocessor toconcentrate in its routine tasks.

7. When a keyboard is interfaced through Intel 8279, the keys areautomatically debounced and the keyboard can operate in two differentmodes: Two key lockout or N-key rollover.

8. In the two key lockout mode, if two keys are pressed almostsimultaneously, only the first key is recognized. In the N-key rollovermode, simultaneous keys are recognized and their codes are stored inthe internal buffer.

9. Early computers communicated with the user with either indicator lamps orhard copy printers, but today, the primary output device is theelectronic display. This is usually the CRT display, although othertechnologies are available. The CRT display uses the same technologyas the television.

10.A CRT controller generates all the signals and coordinates the supportingactivities for interfacing and controlling a CRT display with a

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microprocessor. Intels 8275 is a programmable CRT controllerdesigned to interface raster scan displays with Intel microcomputersystems.

11.Various functional components of Intel 8275 are data bus buffer,read/write control logic, character count, line counter, light pen

registers, raster timing and video control, row buffers, FIFOs and bufferI/O controllers.12.The 8087 is a numeric data coprocessor which is capable of performing

complex mathematical functions while the host processor (i.e. the mainCPU) performs more general tasks.

13.The 8087 is divided into two sections internally namely the Control Unit(CU) and the Numeric Extension Unit (NEU). The NEU executes all thenumeric processor instructions while the CU receives, decodesinstructions, reads and writes memory operands and executes the8087 control instructions.

In this unit you have learnt about the interfacing of peripherals to the processorusing programmable interfacing devices. Programmable interfacing devicesprovide a number of advantages over handling the peripherals through softwareroutines. You may further explore in this area in terms of the latest processors,their features, embedded systems and other digital systems that are arriving themarket.

Exercises

1. What do the initialization commands specify in 8279 keyboard/displaycontroller?

2. In a key monitor program, register E is used to save 4-bit codes of twodata keys. Write a subroutine to insert a new 4-bit key code that isavailable in the accumulator; the new code must be inserted as a low-order nibble, and the most significant nibble in register E must bediscarded.

3. In a monitor program, register BC is used to save a 16 bit memoryaddress. Write instructions to insert a 4-bit code of a new key in the BCregister as a least significant nibble.

4. Check whether the following statements are true or false.a. Serial data communication can not be implemented using the

memory mapped I/O.b. In a serial transmission from the MPU to a peripheral, bit D0 is

transmitted first after the start bit.c. In a system with the even parity check, the letter M is transmitted

with the code 4CH.d. In a system with the odd parity check, the letter A is transmitted

with the code C1H.e. ASCII is an 8-bit binary code that represents 256 different

characters.

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5. When the 8279 detects a key closure, the IRQ signal interrupts the 8085,using RST 5.5. The interrupt service routine sends the command word toread from the keyboard, reads the character data from the keyboard, andstores it in the input buffer of the systems R/W memory. Write down theinstructions for initialization and interrupt routine to read the keyboard.

Answers

1. The initialization commands specify left or right entry and key rollover,clock frequency prescaler, starting address and incrementing mode ofthe FIFO RAM, RAM address to read and write data and incrementingmode, blanking format.

2. SHIFT: PUSH PSWMOV A,EADD AADD A

ADD AADD AMOV E,APOP PSWANI 0FHORA EMOV E,ARET

3. INSERT: PUSH HMOV H,BMOV L,C

DAD HDAD HDAD HDAD HANI 0FHORA LMOV B,HMOV C,APOP HRET

4. a. Fb. Tc. Fd. Te. F

6. InitializationMVI A,00HSTA 1900H

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Interrupt Routine to Read KeyboardPUSH HPUSH PSWLXI H,1900HMVI M,40H

DCR HMOV A,MANI 3FHSTA IBUFFPOP PSWPOP HRET

unit v peripheral interfacing

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