POWER DIODESPower diodes are made of silicon p-n junction with two terminals, anode and

cathode. P-N junction is formed by alloying, diffusion and epitaxial growth. Modern techniques in diffusion and epitaxial processes permit desired device characteristics.

The diodes have the following advantages

High mechanical and thermal reliability

High peak inverse voltage

Low reverse current

Low forward voltage drop

High efficiency

Compactness.

Diode is forward biased when anode is made positive with respect to the cathode. Diode conducts fully when the diode voltage is more than the cut-in voltage (0.7 V for Si). Conducting diode will have a small voltage drop across it.

Diode is reverse biased when cathode is made positive with respect to anode. When reverse biased, a small reverse current known as leakage current flows. This leakage current increases with increase in magnitude of reverse voltage until avalanche voltage is reached (breakdown voltage).

DYNAMIC CHARACTERISTICS OF POWER SWITCHING DIODESAt low frequency and low current, the diode may be assumed to act as a perfect switch and the dynamic characteristics (turn on & turn off characteristics) are not very important. But at high frequency and high current, the dynamic characteristics plays an important role because it increases power loss and gives rise to large voltage spikes which may damage the device if proper protection is not given to the device.

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Fig: Storage & Transition Times during the Diode Switching

REVERSE RECOVERY CHARACTERISTICReverse recovery characteristic is much more important than forward recovery characteristics because it adds recovery losses to the forward loss. Current when diode is forward biased is due to net effect of majority and minority carriers. When diode is in forward conduction mode and then its forward current is reduced to zero (by applying reverse voltage) the diode continues to conduct due to minority carriers which remains stored in the p-n junction and in the bulk of semi-conductor material. The minority carriers take some time to recombine with opposite charges and to be neutralized. This time is called the reverse recovery time. The reverse recovery time (trr) is measured from the initial zero crossing of the diode current to 25% of maximum reverse current Irr. trr has 2 components, t1 and t2. t1 is as a result of charge storage in the depletion region of the junction i.e., it is the time between the zero crossing and the peak reverse current Irr. t2 is as a result of charge storage in the bulk semi-conductor material.

The waveform in (a) Simple diode circuit.(b)Input waveform applied to the diode circuit in (a); (c) The excess-carrier density at the junction; (d) the diode current; (e) the diode voltage.

The reverse recovery time depends on the junction temperature, rate of fall of forward current and the magnitude of forward current prior to commutation (turning off).

When diode is in reverse biased condition the flow of leakage current is due to minority carriers. Then application of forward voltage would force the diode to carry current in the forward direction. But a certain time known as forward recovery time (turn-ON time) is required before all the majority carriers over the whole junction can contribute to current flow. Normally forward recovery time is less than the reverse recovery time. The forward recovery time limits the rate of rise of forward current and the switching speed.

Reverse recovery charge , is the amount of charge carriers that flow across the diode in the reverse direction due to the change of state from forward conduction to reverse blocking condition. The value of reverse recovery charge is determined form the area enclosed by the path of the reverse recovery current.

POWER DIODES TYPESPower diodes can be classified as

General purpose diodes.

High speed (fast recovery) diodes.

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Schottky diode.

GENERAL PURPOSE DIODESThe diodes have high reverse recovery time of about 25 microsecs (sec). They are used in low speed (frequency) applications. e.g., line commutated converters, diode rectifiers and converters for a low input frequency upto 1 KHz. Diode ratings cover a very wide range with current ratings less than 1 A to several thousand amps (2000 A) and with voltage ratings from 50 V to 5 KV. These diodes are generally manufactured by diffusion process. Alloyed type rectifier diodes are used in welding power supplies. They are most cost effective and rugged and their ratings can go upto 300A and 1KV.

FAST RECOVERY DIODESThe diodes have low recovery time, generally less than 5 s. The major field of applications is in electrical power conversion i.e., in free-wheeling ac-dc and dc-ac converter circuits. Their current ratings is from less than 1 A to hundreds of amperes with voltage ratings from 50 V to about 3 KV. Use of fast recovery diodes are preferable for free-wheeling in SCR circuits because of low recovery loss, lower junction temperature and reduced . For high voltage ratings greater than 400 V they are manufactured by diffusion process and the recovery time is controlled by platinum or gold diffusion. For less than 400 V rating epitaxial diodes provide faster switching speeds than diffused diodes. Epitaxial diodes have a very narrow base width resulting in a fast recovery time of about 50 ns.

SCHOTTKY DIODESA Schottky diode has metal (aluminium) and semi-conductor junction. A layer of metal is deposited on a thin epitaxial layer of the n-type silicon. In Schottky diode there is a larger barrier for electron flow from metal to semi-conductor.

When Schottky diode is forward biased free electrons on n-side gain enough energy to flow into the metal causing forward current. Since the metal does not have any holes there is no charge storage, decreasing the recovery time. Therefore a Schottky diode can switch-off faster than an ordinary p-n junction diode. A Schottky diode has a relatively low forward voltage drop and reverse recovery losses. The leakage current is higher than a p-n junction diode. The maximum allowable voltage is about 100 V. Current ratings vary from about 1 to 300 A. They are mostly used in low voltage and high current dc power supplies. The operating frequency may be as high 100-300 kHz as the device is suitable for high frequency application. Schottky diode is also known as hot carrier diode.

General Purpose Diodes are available upto 5000V, 3500A. The rating of fast-recovery diodes can go upto 3000V, 1000A. The reverse recovery time varies between 0.1 and 5sec. The fast recovery diodes are essential for high frequency switching of power converters. Schottky diodes have low-on-state voltage drop and very small recovery time, typically a few nanoseconds. Hence turn-off time is very low for schottky diodes. The leakage current increases with the voltage rating and their ratings are limited to 100V, 300A. The diode turns on and begins to conduct when it is forward biased. When the anode voltage is greater than the cathode voltage diode conducts.

The forward voltage drop of a power diode is low typically 0.5V to 1.2V. If the cathode voltage is higher than its anode voltage then the diode is said to be reverse biased.

Power diodes of high current rating are available in

Stud or stud-mounted type.

Disk or press pack or Hockey-pack type.

In a stud mounted type, either the anode or the cathode could be the stud.

COMPARISON BETWEEN DIFFERENT TYPES OF DIODES

General Purpose Diodes Fast Recovery Diodes Schottky Diodes

Upto 5000V & 3500A Upto 3000V and 1000A Upto 100V and 300A

Reverse recovery time – High

Reverse recovery time – Low

Reverse recovery time – Extremely low.

= a few nanoseconds

Turn off time - High Turn off time - Low Turn off time – Extremely low

Switching frequency – Low

Switching frequency – High

Switching frequency – Very high.

= 0.7V to 1.2V = 0.8V to 1.5V 0.4V to 0.6V

POWER MOSFETHistorically, bipolar semiconductor devices (i.e, diode, transistor, thyristor, thyristor, GTO etc) have been the front runners in the quest for an ideal power electronic switch. Ever since the invention of the transistor, the development of solid-state switches with increased power handling capability has been of interest for expending the application of these devices. The BJT and the GTO thyristor have been developed over the past 30 years to serve the need of the power electronic industry. Their primary advantage over the thyristors have been the superior switching speed and the ability to interrupt the current without reversal of the device voltage. All bipolar devices, however, suffer from a common set of disadvantages, namely, (i) limited switching speed due to considerable redistribution of minority charge carriers associated with every switching operation; (ii)

relatively large control power requirement which complicates the control circuit design. Besides, bipolar devices can not be paralleled easily.

Introduction of a new MOS gate controlled power device technology in the 1980s. The power MOS field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. The new device promised extremely low input power levels and no inherent limitation to the switching speed. Thus, it opened up the possibility of increasing the operating frequency in power electronic systems resulting in reduction in size and weight. The initial claims of infinite current gain for the power MOSFET were, however, diluted by the need to design the gate drive circuit to account for the pulse currents required to charge and discharge the high input capacitance of these devices. At high frequency of operation the required gate drive power becomes substantial. MOSFETs also have comparatively higher on state resistance per unit area of the device cross section which increases with the blocking voltage rating of the device. Consequently, the use of MOSFET has been restricted to low voltage (less than about 500 volts) applications where the ON state resistance reaches acceptable values. Inherently fast switching speed of these devices can be effectively utilized to increase the switching frequency beyond several hundred kHz.

From the point of view of the operating principle a MOSFET is a voltage controlled majority carrier device. As the name suggests, movement of majority carriers in a MOSFET is controlled by the voltage applied on the control electrode (called gate) which is insulated by a thin metal oxide layer from the bulk semiconductor body. The electric field produced by the gate voltage modulate the conductivity of the semiconductor material in the region between the main current carrying terminals called the Drain (D) and the Source (S). Power MOSFETs, just like their integrated circuit counterpart, can be of two types (i) depletion type and (ii) enhancement type. Both of these can be either n- channel type or p-channel type depending on the nature of the bulk semiconductor. Fig 6.1 (a) shows the circuit symbol of these four types of MOSFETs along with their drain current vs gate-source voltage characteristics (transfer characteristics).

Fig.1: Different types of power MOSFET. (a) Circuit symbols and transfer characteristicsFrom Fig.1 (a) it can be concluded that depletion type MOSFETs are normally ON type switches i.e, with the gate terminal open a nonzero drain current can flow in these devices. This is not convenient in many power electronic applications. Therefore, the enhancement type MOSFETs (particularly of the n-channel variety) is more popular for power electronics applications.

Constructional Features of a Power MOSFET

As mentioned in the introduction section, Power MOSFET is a device that evolved from MOS integrated circuit technology. The first attempts to develop high voltage MOSFETs were by redesigning lateral MOSFET to increase their voltage blocking capacity. The resulting technology was called lateral double diffused MOS (DMOS). However it was However it was soon realized that much larger breakdown voltage and current ratings could be achieved by resorting to a vertically oriented structure. Since then, vertical DMOS (VDMOS) structure has been adapted by virtually all manufacturers of Power MOSFET. A power MOSFET using VDMOS technology has vertically oriented three layer structure of alternating p type and n type semiconductors as shown in Fig 6.2 (a) which is the schematic representation of a single MOSFET cell structure. A large number of such cells are connected in parallel n in to form a complete device.

Fig.2. Structure of a MOSFET

The two n+ end layers labeled “Source” and “Drain” are heavily doped to approximately the same level. The p type middle layer is termed the body (or substrate) and has moderate doping level (2 to 3 orders of magnitude lower than n+ regions on both sides). The n- drain drift region has the lowest doping density. Thickness of this region determines the breakdown voltage of the device. The gate terminal is placed over the n-

and p type regions of the cell structure and is insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate oxide). The source and the drain region of all cells on a wafer are connected to the same metallic contacts to form the Source and the Drain terminals of the complete device. Similarly all gate terminals are also connected together. The source is constructed of many (thousands) small polygon shaped areas that are surrounded by the gate regions. The geometric shape of the source regions, to same extent, influences the ON state resistance of the MOSFET.

Fig.3: Parasitic BJT in a MOSFET cell.

One interesting feature of the MOSFET cell is that the alternating n+ n- p n+ structure embeds a parasitic BJT (with its base and emitter shorted by the source metallization) into each MOSFET cell as shown in Fig .3. The nonzero resistance between the base and the emitter of the

parasitic npn BJT arises due to the body spreading resistance of the p type substrate. In the design of the MOSFET cells special care is taken so that this resistance is minimized and switching operation of the parasitic BJT is suppressed. With an effective short circuit between the body and the source the BJT always remain in cut off and its collector-base junction is represented as an anti parallel diode (called the body diode) in the circuit symbol of a Power MOSFET. Operating principle of a MOSFET

At first glance it would appear that there is no path for any current to flow between the source and the drain terminals since at least one of the p n junctions (source – body and body-Drain) will be reverse biased for either polarity of the applied voltage between the source and the drain. There is no possibility of current injection from the gate terminal either since the gate oxide is a very good insulator. However, application of a positive voltage at the gate terminal with respect to the source will covert the silicon surface beneath the gate oxide into an n type layer or “channel”, thus connecting the Source to the Drain as explained next.The gate region of a MOSFET which is composed of the gate metallization, the gate (silicon) oxide layer and the p-body silicon forms a high quality capacitor. When a small voltage is application to this capacitor structure with gate terminal positive with respect to the source (note that body and source are shorted) a depletion region forms at the interface between the SiO2 and the silicon as shown in Fig.4 a.

Fig. .4: Gate control of MOSFET conduction. (a) Depletion layer formation; (b) Free electron accumulation; (c) Formation of inversion layer.

The positive charge induced on the gate metallization repels the majority hole carriers from the interface region between the gate oxide and the p type body. This exposes the negatively charged acceptors and a depletion region is created. Further increase in VGS causes the depletion layer to grow in thickness. At the same time the electric field at the oxide-silicon interface gets larger and begins to attract free electrons as shown in Fig .4 (b). The immediate source of electron is electron-hole generation by thermal ionization. The holes are repelled into the semiconductor bulk ahead of the depletion region. The extra holes are neutralized by electrons from the source.

As VGS increases further the density of free electrons at the interface becomes equal to the free hole density in the bulk of the body region beyond the depletion layer. The layer of free electrons at

the interface is called the inversion layer and is shown in Fig .4 (c). The inversion layer has all the properties of an n type semiconductor and is a conductive path or “channel” between the drain and the source which permits flow of current between the drain and the source. Since current conduction in this device takes place through an n- type “channel” created by the electric field due to gate source voltage it is called “Enhancement type n-channel MOSFET”. The value of VGS at which the inversion layer is considered to have formed is called the “Gate – Source threshold voltage VGS (th)”. As VGS is increased beyond VGS(th) the inversion layer gets some what thicker and more conductive, since the density of free electrons increases further with increase in VGS. The inversion layer screens the depletion layer adjacent to it from increasing VGS. The depletion layer thickness now remains constant.

Steady state output i-v characteristics of a MOSFET

The MOSFET, like the BJT is a three terminal device where the voltage on the gate terminal controls the flow of current between the output terminals, Source and Drain. The source terminal is common between the input and the output of a MOSFET. The output characteristics of a MOSFET is then a plot of drain current (iD) as a function of the Drain –Source voltage (vDS) with gate source voltage (vGS) as a parameter. Fig .5 (a) shows such a characteristics.

Fig. .5: Output i-v characteristics of a Power MOSFET (a) i-v characteristics; (b) Components of ON-state resistance; (c) Electron drift velocity vs Electric field; (d) Transfer

With gate-source voltage (VGS) below the threshold voltage (vGS (th)) the MOSFET operates in the cut-off mode. No drain current flows in this mode and the applied drain–source voltage (vDS) is supported by the body-collector p-n junction. Therefore, the maximum applied voltage should be below the avalanche break down voltage of this junction (VDSS) to avoid destruction of the device. When VGS is increased beyond vGS(th) drain current starts flowing. For small values of vDS (vDS < (vGS – vGS(th)) iD is almost proportional to vDS. Consequently this mode of operation is called “ohmic mode” of operation. In power electronic applications a MOSFET is operated either in the cut off or in the ohmic mode. The slope of the vDS – iD characteristics in this mode is called the ON state resistance of the MOSFET (rDS (ON)). Several physical resistances as shown in Fig .5 (b) contribute to rDS (ON). Note that rDS (ON) reduces with increase in vGS. This is mainly due to reduction of the channel resistance at higher value of vGS. Hence, it is

desirable in power electronic applications, to use as large a gate-source voltage as possible subject to the dielectric break down limit of the gate-oxide layer.

At still higher value of vDS (vDS > (vGS – vGS (th)) the iD – vDS characteristics deviates from the linear relationship of the ohmic region and for a given vGS, iD tends to saturate with increase in vDS. The exact mechanism behind this is rather complex. It will suffice to state that, at higher drain current the voltage drop across the channel resistance tends to decrease the channel width at the drain drift layer end. In addition, at large value of the electric field, produced by the large Drain – Source voltage, the drift velocity of free electrons in the channel tends to saturate as shown in Fig .5 (c). As a result the drain current becomes independent of VDS and determined solely by the gate – source voltage vGS. This is the active mode of operation of a MOSFET.

The similarity of the output characteristics of a MOSFET with that of a BJT should be apparent. Both of them have three distinct modes of operation, namely, (i)cut off, (ii) active and (iii) ohmic (saturation for BJT) modes. However, there are some important differences as well.

• Unlike BJT a power MOSFET does not undergo second break down. • The primary break down voltage of a MOSFET remains same in the cut off

and in the active modes. This should be contrasted with three different break down voltages (VSUS, VCEO & VCBO) of a BJT.

• The ON state resistance of a MOSFET in the ohmic region has positive temperature coefficient which allows paralleling of MOSFET without any special arrangement for current sharing. On the other hand, vCE (sat) of a BJT has negative temperature coefficient making parallel connection of BJTs more complicated.

The SOA of a MOSFET is plotted on a log-log graph. On the top, the SOA is restricted by the absolute maximum permissible value of the drain current (IDM) which should not be exceeded even under pulsed operating condition. To the left, operating restriction arise due to the non zero value of rDS(ON) corresponding to vGS

= vGS(Max). To the right, the first operating restriction is due to the limit on the maximum permissible junction temperature rise which depends on the power dissipation inside the MOSFET. This limit is different for DC (continuous) and pulsed operation of different pulse widths. As in the case of a BJT the pulsed safe operating areas are useful for shaping the switching trajectory of a MOSFET. A MOSFET does not undergo “second break down” and no corresponding operating limit appears on the SOA. The final operation limit to the extreme right of the SOA arises due to the maximum permissible drain source voltage (VDSS) which is decided by the avalanche break down voltage of the drain -body p-n junction. This is an

instantaneous limit. There is no distinction between the forward biased and the reverse biased SOAs for the MOSFET. They are identical.

Due to the presence of the anti parallel “body diode”, a MOSFET can not block any reverse voltage. The body diode, however, can carry an RMS current equal to IDM. It also has a substantial surge current carrying capacity. When reverse biased it can block a voltage equal to VDSS.

For safe operation of a MOSFET, the maximum limit on the gate source voltage

(VGS (Max)) must be observed. Exceeding this voltage limit will cause dielectric break down of the thin gate oxide layer and permanent failure of the device. It should be noted that even static charge inadvertently put on the gate oxide by careless handling may destroy it. The device user should ground himself before handling any MOSFET to avoid any static charge related problem.

SOA FOR POWER MOSFET.

MOSFET is a voltage controlled majority carrier device. • A Power MOSFET has a vertical structure of alternating p and n layers. • The main current carrying terminals of an n channel enhancement mode MOSFET are called the Drain and the Source and are made up of n+ type semiconductor. • The control terminal is called the Gate and is isolated form the bulk semiconductor by a thin layer of SiO2. • p type semiconductor body separates n+ type source and drain regions. • A conducting n type channel is produced in the p type body region when a positive voltage greater than a threshold voltage is applied at the gate. • Current conduction in a MOSFET occurs by flow of electron from the source to the drain through this channel. • When the gate source voltage is below threshold level a MOSFET remains in the “Cut Off” region and does not conduct any current. • With vGS > vGS (th) and vDS < (vGS – vGS (th)) the drain current in a MOSFET is proportional to vDS. This is the “Ohmic region” of the MOSFET output characteristics. • For larger values of vDS the drain current is a function of vGS alone and does not depend on vDs. This is called the “active region” of the MOSFET. • In power electronic applications a MOSFET is operated in the “Cut Off” and Ohmic regions only. • The on state resistance of a MOSFET (VDS (ON)) has a positive temperature coefficient. Therefore, MOSFETs can be easily paralleled. • A MOSFET does not undergo second break down. • The safe operating area (SOA) of a MOSFET is similar to that of a BJT except that it does not have a second break down limit. • Unlike BJT the maximum forward voltage withstanding capability of a MOSFET does not depend on the drain current. • The safe operating area of a MOSFET does not change under Forward and Reverse bias conditions. • The drain – body junction in a MOSFET structure constitute an anti parallel diode connected between the source and the drain. This is called the MOSFET “body – diode.” • The body diode of a MOSFET has the same break down voltage and forward current rating as the main MOSFET.The switching delays in a MOSFET are due to finite charging and discharging time of the input and output capacitors. • Switching times of a MOSFET can be controlled completely by external gate drive design. The input capacitor along with the gate drive resistance determine the current rise and fall time of a MOSFET during switching. • The transfer capacitor (Cgd) determines the drain voltage rise and fall times. • rDS (ON) of a MOSFET determines the conduction loss during ON period. • rDS (ON) reduces with higher vgs. Therefore, to minimize conduction power loss maximum permissible vgs should be used subject to dielectric break down of the gate oxide layer. • The gate oxide layer can be damaged by static charge. Therefore MOSFETs should be handled only after discharging one self through proper grounding. • For similar voltage rating, a MOSFET has a relatively higher conduction loss and lower switching loss compared to a BJT. Therefore, MOSFETs are more popular for high frequency (>50 kHz) low voltage (<100 V) circuits.

POWER BJT

Power Bipolar Junction Transistor (BJT) is the first semiconductor device to allow full control over its Turn on and Turn off operations. It simplified the design of a large number of Power Electronic circuits that used forced commutated thyristors at that time and also helped realize a number of new circuits. Subsequently, many other devices that can broadly be classified as “Transistors” have been developed. Many of them have superior performance compared to the BJT in some respects. They have, by now, almost completely replaced BJTs. However, it should be emphasized that the BJT was the first semiconductor device to closely approximate an ideal fully controlled Power switch. Other “transistors” have characteristics that are qualitatively similar to those of the BJT (although the physics of operation may differ). Hence, it will be worthwhile studying the characteristics and operation a BJT in some depth. From the point of view of construction and operation BJT is a bipolar (i.e. minority carrier) current controlled device. It has been used at signal level power for a long time.

Basic Operating Principle of a Bipolar Junction Transistor

A junction transistor consists of a semiconductor crystal in which a p type region is sandwiched between two n type regions. This is called an n-p-n transistor. Alternatively an n type region may be placed in between two p type regions to give a p-n-p transistor. Fig shows the circuit symbols and schematic representations of an n-p-n and a p-n-p transistor. The terminals of a transistor are called Emitter (E), Base (B) & Collector (C) as shown in the figure.

Constructional Features of a Power BJT

Power transistors face the same conflicting design requirements (i.e. large off state blocking voltage and large on state current density) as that of a power diode. Therefore, it is only natural to extend some of the constructional features of power diodes to power BJT. Following Section summarizes some of the constructional features of a Power BJT.

Since Power Transistors are predominantly of the n-p-n type, in this section and subsequently only this type of transistor will be discussed.

• A power BJT has a vertically oriented alternating layers of n type and p type semiconductor materials as shown in Fig 3.3(a). The vertical structure is preferred for power transistors because it maximizes the cross sectional area through which the on state current flows. Thus, on state resistance and power lass is minimized.

• In order to maintain a large current gain “ β ” (and hence reduce base drive current) the emitter doping density is made several orders of magnitude higher than the base region. The thickness of the base region is also made as small as possible.

• In order to block large voltage during “OFF” state a lightly doped “collector drift region” is introduced between the moderately doped base region and the heavily doped collector region. The function of this drift region is similar to that in a Power Diode. However, the doping density donation of the base region being “moderate” the depletion region does penetrate considerably into the base. Therefore, the width of the base region in a power transistor can not be made as small as that in a signal level transistor. This comparatively larger base width has adverse effect on the current gain (β) of a Power transistor which

typically varies within 5-20. As will be discusses later the collector drift region has significant effect on the out put characteristics of a Power BJT.

• Practical Power transistors have their emitters and bases interleaved as narrow fingers. This is necessary to prevent “current crowding” and consequent “second break down”. In addition multiple emitter structure also reduces parasitic ohmic resistance in the base current path.

Constructional Features of a Power Bipolar Junction Transistor

Output i-v characteristics of a Power Transistor

A typical output (iC vs VCE) characteristics of an n-p-n type power transistor is shown in Fig .A power transistor exhibits “Cut off”, “Active” and “Saturation regions” of operation in its output characteristics similar to a signal level transistor. In fact output characteristics of a Power Transistor in the “Cut off” and “Active” regions are qualitatively identical to a signal level transistor.

VI Characteristics of POWER BJT.

In the cut off region (iB ≤ 0) the collector current is almost zero. The maximum voltage between collector and emitter under this condition is termed “Maximum forward blocking voltage with base terminal open (iB = 0)” and is denoted by VCEO. For all practical purpose this is the maximum voltage that can be applied in the forward direction (C positive with respect to E) across a power transistor since a power transistor is expected to see any significant forward voltage only with iB = 0. This blocking voltage can however be increased to a value VCBO by keeping the emitter terminal open. In this case iB < o. Actually VCBO is the breakdown voltage of the collector base junction. However, since the open base configuration is more common the value of VCEO is used by the manufacturers as the maximum voltage rating of a power transistor. Power transistors have poor reverse voltage withstanding capability due to low break down voltage of the base-emitter junction. Therefore, reverse voltage (C negative with respect to E) should not

appear across a power transistor. In the active region the ratio of collector current to base current (DC current Gain (β)) remains fairly constant upto certain value of the collector current after which it falls off rapidly. Manufacturers usually provide a graph showing the variation of β as a function of the collector current for different junction temperatures and collector emitter voltages. This graph is useful for designing the base drive of a Power transistor. Typically, the value of the dc current gain of a Power transistor is much smaller compared to their signal level counterpart.

The maximum collector-emitter voltage that a power transistor can withstand in active region is determined by the Base collector avalanche break down voltage. This voltage, denoted by VSUS in Fig, 3.4 is usually smaller than VCEO. The voltage VSUS can be attained only for relatively lower values of collector current. At higher collector current the limit on the “total power dissipation” defines the boundary of the allowable active region as shown in Fig . At still higher levels of collector currents the allowable active region is further restricted by a potential failure mode called “the Second Break down”. It appears on the output characteristics of the BJT as a precipitous drop in the collector-emitter voltage at large collector currents. The collector voltage drop is often accompanied by significant rise in the collector current and a substantial increase in the power dissipation. Most importantly this dissipation is not uniformly spread over the entire volume of the device but is concentrated in highly localized regions. This localized heating is a combined effect of the intrinsic non uniformity of the collector current density distribution across the cross section of the device and the negative temperature coefficient of resistively of minority carrier devices which leads to the formation of “current filamements” (localized areas of very high current density) by a positive feed-back mechanism. Once current filaments are formed localized “thermal runaway” quickly takes the junction temperature beyond the safe limit and the device is destroyed.

It is in the saturation region that the output characteristics of a Power transistor differs significantly from its signal level counterpart. In fact the saturation region of a Power transistor can be further subdivided into a quasi saturation region and a hard saturation region. Appearance of the quasi saturation region in the output characteristics of a power transistor is a direct consequence of introducing the drift region into the structure of a power transistor. In the quasi saturation region the base-collector junction is forward biased but the lightly doped drift region is not completely shorted out by excess minority carrier injection from the base. The resistivity of this region depends to some extent on the base current. Therefore, in the quasi saturation region, the base current still retains some control over the collector current although the value of β decreases significantly. Also, since the resistivity of the drift region is still significant the total voltage drop across the device in this mode of operation is higher for a given

collector current compared to what it will be in the hard saturation region.

In the hard saturation region base current looses control over the collector current which is determined entirely by the collector load and the biasing voltage VCC. This behavior is similar to what happens in a signal transistor except that the drift region of a power transistor continues to offer a small resistance even when it is completely shorted out (by excess carrier injection from the base). Therefore, for larger collector currents the collector-emitter voltage drop is almost proportional to the collector current. Manufacturers usually provide the plots of the variation of VCE (sat) vs. iC for different values of base current and junction temperature. Curves showing the variation of VCE (sat) with iB for different values of iC and junction temperature are also provided by certain manufacturers.

Safe operating Area (SOA) for Power BJT

Applicable operating limits on a power transistors are compactly represented in two diagrams called the Forward Bias Safe Operating Area (FBSOA) and the Reverse Bias Safe Operating Area. (RBSOA) applicable to iB > 0 and iB ≤ 0 conditions respectively.

Safe operating areas of a Power Transistor. (a) FBSOA; (b) RBSOA.

The horizontal upper limit of the FBSOA is determined by the maximum allowable collector current (ICM) that should not be exceeded even as a pulse. Exceeding this current limit may cause bonding wire or metallization of the wafer to vaporize or otherwise fail. Since a power transistor does not have any appreciable reverse voltage blocking capacity they are usually not used in ac circuits. However, if the collector current, for some reason

is not dc or a pulse, the rms value of the collector current waveform should not exceed this limit. The next applicable limit in the FBSOA (green lines) corresponds to the restriction on the maximum allowable power dissipation and maximum junction temperature. Since FBSOA is shown on a log-log scale constant Power dissipation (Pd = VCE iC) limits appear as straight lines. This limit is different for dc and pulsed operation due to the thermal time constant of the device. The “DC” limit is applicable to the average power loss if the transistor remains continuously in the conduction state (active, quasi saturation or saturation). The third limit of the FBSOA (red line) arises due to the “second break down” failure mode of a Power transistor. It shows the limiting combinations of collector voltage and current so that second break down does not occur. On the log –log scale of the FBSOA this limit also appears as a straight limit. Like the maximum power dissipation limit, the second break down limit is also different for “DC” and “Pulsed” operation of different pulse durations. The interpretation of the pulse duration (marked on the right side of Fig 3.5 (a)) corresponding to a particular limit is also same.The final limit of the FBSOA corresponds to the forward biased avalanche break down voltage (VSUS) of the transistor and appear as a vertical line in the FBSOA at VCE = VSuS..

RBSOA is a switching SOA since a transistor can not conduct current for any appreciable duration under reverse biased condition. It essentially shows the limiting permissible combinations of VCE & iC with base emitter junction reverse biased. The upper horizontal limit corresponds to the maximum allowable collector current (ICM) and is same as that in the FBSOA. The right hand side vertical limit corresponds the avalanche break down voltage of the transistor with reverse bias. If the base terminal is open (i,e, iB = 0) then this voltage is VCEO. If a negative voltage is applied across the BE junction the right hand side limit of the RBSOA increases somewhat to the value VCBO at low value of the collector current.

Switching characteristics of a Power Transistor In a power electronic circuit the power transistor is usually employed as a switch i.e. it operates in either “cut off” (switch OFF) or saturation (switch ON) regions. However, the operating characteristics of a power transistor differs significantly from an ideal controlled switch in the following respects.

• It can conduct only finite amount of current in one direction when “ON” • It can block only a finite voltage in one direction. • It has a voltage drop during “ON” condition • It carries a small leakage current during OFF condition • Switching operation is not instantaneous • It requires non zero control power for switching

To turn the transistor ON at t = 0, the base biasing voltage VBB changes to a suitable positive value. This starts the process of charge redistribution at the base-emitter junction. The process is akin to charging of a capacitor. Indeed, the reverse biased base emitter junction is often represented by a voltage dependent capacitor, the value of which is given by the manufacturer as a function of the base-emitter reverse bias voltage. The rising base current that flows during this period can be thought of as this capacitor charging current. Finally at t = t d the BE

junction is forward biased. The junction voltage and the base current settles down to their steady state values.During this period, called the “Turn ON delay time” no appreciable collector current flows. The values of iO and VCE remains essentially at their OFF state levels. At the end of the delay time (td ON) the minority carrier density at the base region quickly approaches its steady state distribution and the collector current starts rising while the diode current (id) starts falling. At t = tdON + tri the collector current becomes equal to the load current (and id becomes zero) IL. At this point D starts blocking reverse voltage and VCE becomes unclamped. tri is called the current rise time of the transistor.

TURN –ON CHARACTERISTICS

The Turn ON delay time can however be reduced by boosting the base current at the beginning of the Turn ON process. This can be achieved by connecting a small capacitance across RB.

TURN –OFF CHARACTERISTICS

The “Turn OFF” process starts with the base drive voltage going negative to a value -VBB. The base-emitter voltage however does not change from its forward bias value of VBE(sat) immediately, due to the excess, minority carriers stored in the base region. A negative base current starts removing this excess carrier at a rate determined by the negative base drive voltage and the base drive resistance. After a time “ts” called the storage time of the transistor, the remaining stored charge in the base becomes insufficient to support the transistor in the hard saturation region. At this point the transistor enters quasi saturation region and the collector voltage starts rising with a small slope. After a further time interval “trv1” the transistor completes traversing through the quasi saturation region and enters the active region. The stored charge in the base region at this point is insufficient to support the full negative base current. VBE starts falling forward –VBB and the negative

base current starts reducing. In the active region, VCE increases rapidly towards VCC and at the end of the time interval “trv2” exceeds it to turn on D. VCE remains clamped at VCC, thereafter by the conducting diode D. At the end of trv2 the stored base charge can no longer support the full load current through the collector and the collector current starts falling. At the end of the current fall time tfi the collector current becomes zero and the load current freewheels through the diode D. Turn OFF process of the transistor ends at this point. The total Turn OFF time is given by Ts (OFF) = ts + trv1 + trv2 + tfi .

IGBTThe IGT device has undergone many improvement cycles to result in the modern Insulated Gate Bipolar Transistor (IGBT). These devices have near ideal characteristics for high voltage (> 100V) medium frequency (< 20 kHZ) applications. This device along with the MOSFET (at low voltage high frequency applications) have the potential to replace the BJT completely. The major difference with the corresponding MOSFET cell structure lies in the addition of a p+ injecting layer. This layer forms a pn junction with the drain layer and injects minority carriers into it. The n type drain layer itself may have two different doping levels. The lightly doped n- region is called the drain drift region. Doping level and width of this layer sets the forward blocking voltage (determined by the reverse break down voltage of J2) of the device. However, it does not affect the on state voltage drop of the device due to conductivity modulation as discussed in connection with the power diode. This construction of the device is called “Punch Trough” (PT) design. The Non-Punch Through (NPT) construction does not have this added n+ buffer layer. The PT construction does offer lower on state voltage drop compared to the NPT construction particularly for lower voltage rated devices. However, it does so at the cost of lower reverse break down voltage for the device, since the reverse break down voltage of the junction J1 is small. The rest of the construction of the device is very similar to that of a vertical MOSFET including the insulated gate structure and the shorted body (p type) – emitter (n+ type) structure. The doping level and physical geometry of the p type body region however, is considerably different from that of a MOSFET in order to defeat the latch up action of a parasitic thyristor embedded in the IGBT structure. A large number of basic cells as shown in Fig are grown on a single silicon wafer and connected in parallel to form a complete IGBT device. The IGBT cell has a parasitic p-n-p-n thyristor structure embedded into it as shown in Fig. The constituent p-n-p transistor, n-p-n transistor and the driver MOSFET are shown by dotted lines in this figure. Important resistances in the current flow path are also indicated.

Vertical cross section of an IGBT cell.

Fig shows the exact static equivalent circuit of the IGBT cell structure. The top p-n-p transistor is formed by the p+ injecting layer as the emitter, the n type drain layer as the base and the p type body layer as the collector. The lower n-p-n transistor has the n+ type source, the p type body and the n type drain as the emitter, base and collector respectively. The base of the lower n-p-n transistor is shorted to the emitter by the emitter metallization. However, due to imperfect shorting, the exact equivalent circuit of the IGBT includes the body spreading resistance between the base and the emitter of the lower n-p-n transistor. If the output current is large enough, the voltage drop across this resistance may forward bias the lower n-p-n transistor and initiate the latch up process of the p-n-p-n thyristor structure. Once this structure latches up the gate control of IGBT is lost and the device is destroyed due to excessive power loss. A major effort in the development of IGBT has been towards prevention of latch up of the parasitic thyristor. This has been achieved by modifying the doping level and physical geometry of the body region. The modern IGBT is latch-up proof for all practical purpose.

Operating principle of an IGBT Operating principle of an IGBT can be explained in terms of the schematic cell structure and equivalent circuit of Fig (a) and (c). From the input side the IGBT behaves essentially as a MOSFET. Therefore, when the gate emitter voltage is less then the threshold voltage no inversion layer is formed in the p type body region and the device is in the off state. The forward voltage applied between the collector and the emitter drops almost entirely across the junction J2. Very small leakage current flows through the device under this condition. In terms of the equivalent current of Fig (c), when the gate emitter voltage is lower than the threshold voltage the driving MOSFET of the Darlington configuration remains off and hence the output p-n-p transistor also remains off.

When the gate emitter voltage exceeds the threshold, an inversion layer forms in the p type body region under the gate. This inversion layer (channel) shorts the emitter and the drain drift layer and an electron current flows from the emitter through this channel to the drain drift region. This in turn causes substantial hole injection from the p+ type collector to the drain drift region. A portion of these holes recombine with the electrons arriving at the drain drift region through the channel. The rest of the holes cross the drift region to reach the p type body where they are collected by the source metallization. From the above discussion it is clear that the n type drain drift region acts as the base of the output p-n-p transistor. The doping level and the thickness of this layer determines the current gain “ ” of the ∝ p-n-p transistor. This is intentionally kept low so that most of the device current flows through the MOSFET and not the output p-n-p transistor collector. This helps to reduced the voltage drop across the “body” spreading resistance shown in Fig (b) and eliminate the possibility of static latch up of the IGBT.

The total on state voltage drop across a conducting IGBT has three components. The voltage drop across J1 follows the usual exponential law of a pn junction. The next component of the voltage drop is due to the drain drift region resistance. This component in an IGBT is considerably lower compared to a MOSFET due to strong conductivity modulation by the injected minority carriers from the collector. This is the main reason for reduced voltage drop across an IGBT compared to an equivalent MOSFET. The last component of the voltage drop across an IGBT is due to the channel resistance and its magnitude is equal to that of a comparable MOSFET.Steady state characteristics of an IGBT The i-v characteristics of an n channel IGBT is shown in Fig. They appear qualitatively similar to those of a logic level BJT except that the controlling parameter is not a base current but the gate-emitter voltage.When the gate emitter voltage is below the threshold voltage only a very small leakage current flows though the device while the collector – emitter voltage almost equals the supply voltage (point C in Fig (a). The device, under this condition is said to be operating in the cut off region. The maximum forward voltage the device can withstand in this mode (marked VCES in Fig (a)) is determined by the avalanche break down voltage of the body – drain p-n junction. Unlike a BJT, however, this break down voltage is independent of the collector current as shown in Fig (a). IGBTs of Non-punch through design can block a maximum reverse voltage (VRM) equal to VCES in the cut off

mode. However, for Punch Through IGBTs VRM is negligible (only a few tens of volts) due the presence of the heavily doped n+ drain buffer layer.

As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the active region of operation. In this mode, the collector current i c is determined by the transfer characteristics of the device as shown in Fig (b). This characteristic is qualitatively similar to that of a power MOSFET and is reasonably linear over most of the collector current range. The ratio of ic to (VgE – vgE(th)) is called the forward transconductance (gfs) of the device and is an important parameter in the gate drive circuit design. The collector emitter voltage, on the other hand, is determined by the external load line ABC as shown in Fig.

CHARACTERISTICS OF IGBT

As the gate emitter voltage is increased further ic also increases and for a given load resistance (RL) vCE decreases. At one point vCE becomes less than vgE – vgE(th). Under this condition the driving MOSFET part of the IGBT enters into the ohmic region and drives the output p-n-p transistor to saturation. Under this condition the device is said to be in the saturation mode. In the saturation mode the voltage drop across the IGBT remains almost constant reducing only slightly with increasing vgE. In power electronic applications an IGBT is operated either in the cut off or in the saturation region of the output characteristics. Since vCE decreases with increasing vgE, it is desirable to use the maximum permissible value of vgE in the ON state of the device. vgE(Max) is limited by the maximum collector current that should be permitted to flow in the IGBT as dictated by the “latch-up” condition discussed earlier. Limiting VgE also helps to limit the fault current through the device. If a short circuit fault occurs in the load resistance RL, the fault load line is given by CF. Limiting vgE to vgE6 restricts the fault current corresponding to the operating point F. Most IGBTs are designed to with stand this fault current for a few microseconds within which the device must be turned off to prevent destruction of the device. It is

interesting to note that an IGBT does not exibit a BJT-like second break down failure. Since, in an IGBT most of the collector current flows through the drive MOSFET with positive temperature coefficient the effective temperature coefficient of vCE in an IGBT is slightly positive. This helps to prevent second break down failure of the device and also facilitates paralleling of IGBTs.

Switching characteristics of IGBT Switching characteristics of the IGBT will be analyzed with respect to the clamped inductive switching circuit shown in Fig. The equivalent circuit of the IGBT shown in Fig (b) will be used to explain the switching waveforms.

SWITCHING AND EQUIVALENT CIRCUIT OF IGBT

The switching waveforms of an IGBT is, in many respects, similar to that of a Power MOSFET. This is expected, since the input stage of an IGBT is a MOSFET as shown in Fig (b). Also in a modern IGBT a major portion of the total device current flows through the MOSFET. Therefore, the switching voltage and current waveforms exhibit a strong similarity with those of a MOSFET. However, the output p-n-p transistor does have a significant effect on the switching characteristics of the device, particularly during turn off. Another important difference is in the gate drive requirement. To avoid dynamic latch up, (to be discussed later) the gate emitter voltage of an IGBT is maintained at a negative value when the device is off.

SWITCHING WAVEFORMS OF IGBT

The switching waveforms of an IGBT is shown in Fig. Similarity of these waveforms with those of a MOSFET is obvious. To turn on the IGBT the gate drive voltage changes from –Vgg to +Vgg. The gate emitter voltage vgE follows Vgg with a time constant τ1. Since the drain source voltage of the drive MOSFET is large the gate drain capacitor assumes the lower value CGD1. The collector current ic does not start increasing till vgE reaches the threshold voltage vgE(th). Thereafter, ic increases following the transfer characteristics of the device till vgE reaches a value vgEIL corresponding to ic = iL. This period is called the current rise time tri. The free wheeling diode current falls from IL to zero during this period. After ic reaches IL, vgE becomes clamped at vgE IL similar to a MOSFET. vCE also starts falling during this period. First vCE falls rapidly (tfv1) and afterwards the fall of vCE

slows down considerably. Two factors contribute to the slowing down of voltage fall. First the gate-drain capacitance Cgd will increase in the MOSFET portion of the IGBT at low drain-source voltages. Second, the pnp transistor portion of the IGBT traverses the active region to its on state more slowly than the MOSFET portion of the IGBT. Once the pnp transistor is fully on after tfv2, the on state voltage of the device settles down to vCE(sat). The turn ON process ends here.

The turn off process of an IGBT follows the inverse sequence of turn ON with one major difference. Once vgE goes below vgE(th) the drive MOSFET of the IGBT equivalent circuit turns off. During this period (t fi1) the device current falls rapidly. However, when the drive MOSFET turns off, some amount of current continues of flow through the output p-n-p transistor due to stored charge in its base. Since there is no reverse voltage applied to the IGBT terminals that could generate a negative drain current, there is no possibility for removing the stored charge by carrier sweep-out. The only way these excess carriers can be removed is by recombination

within the IGBT. During this recombination period (tfi2) the remaining current in the IGBT decays relatively slowly forming a current fail. A long tfi2 is undesirable, because the power dissipation in this interval will be large due to full collector-emitter voltage. tfi2 can be reduced by decreasing the excess carrier life time in the p-n-p transistor base. However, in the process, on state losses will increase. Therefore, judicious design trade offs are made in a practical IGBT to give minimum total loss.

The gate drive circuit of an IGBT should ensure fast and reliable switching of the device. In particular, it should.

• Apply maximum permissible VgE during ON period.

• Apply a negative voltage during off period.

• Control during turn ON and turn off to avoid excessive Electro magnetic interference (EMI).

• Control during switching to avoid IGBT latch up.

• Minimize switching loss.

• Provide protection against short circuit fault.

The IGBT has robust SOA both during turn on and turn off. Fig shows the FBSOA. On the left side it is restricted by the forward voltage drop characteristics. Up to maximum continuous collector current this voltage remains reasonably constant at a low value. However, at ICM this voltage starts increasing as the IGBT starts entering active region. On the top the FBSOA is restricted by ICM.

The other two limits are formed by the maximum power dissipation limit and the maximum forward voltage limit. Like other devices the maximum power dissipation limit increases with reduction in the on pulse width. The RBSOA for low values of is rectangular. However, for increased the upper-right hand corner is progressively cut out.

The reason for this restriction on the RBSOA is to avoid dynamic latch up. The device user can easily control by proper choice of Vgg and the gate drive resistance.

TRIAC

The Triac is a member of the thyristor family. But unlike a thyristor which conducts only in one direction (from anode to cathode) a triac can conduct in both directions. Thus a

triac is similar to two back to back (anti parallel) connected thyristosr but with only three terminals. As in the case of a thyristor, the conduction of a triac is initiated by injecting a current pulse into the gate terminal. The gate looses control over conduction once the triac is turned on. The triac turns off only when the current through the main terminals become zero. Therefore, a triac can be categorized as a minority carrier, a bidirectional semi-controlled device. They are extensively used in residential lamp dimmers, heater control and for speed control of small single phase series and induction motors.

Construction and operating principle

As the Triac can conduct in both the directions the terms “anode” and “cathode” are not used for Triacs. The three terminals are marked as MT1 (Main Terminal 1), MT2 (Main Terminal 2) and the gate by G. As shown in Fig the gate terminal is near MT 1 and is connected to both N3 and P2 regions by metallic contact. Similarly MT1 is connected to N2

and P2 regions while MT2 is connected to N4 and P1 regions.

CIRCUIT SYMBOL AND CONSTRUCTION OF TRIAC

Since a Triac is a bidirectional device and can have its terminals at various combinations of positive and negative voltages, there are four possible electrode potential combinations as given below 1. MT2 positive with respect to MT1, G positive with respect to MT1 2. MT2 positive with respect to MT1, G negative with respect to MT1 3. MT2 negative with respect to MT1, G negative with respect to MT1 4. MT2 negative with respect to MT1, G positive with respect to MT1 The triggering sensitivity is highest with the combinations 1 and 3 and are generally used. However, for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2 and 3 are used. Trigger mode 4 is usually averded.

Conduction mechanism of a triac in trigger modes 1 and 3 (a) Mode – 1 , (b) Mode – 3.

In trigger mode-1 the gate current flows mainly through the P2 N2 junction like an ordinary thyristor. When the gate current has injected sufficient charge into P2 layer the triac starts conducting through the P1 N1 P2 N2 layers like an ordinary thyristor. In the trigger mode-3 the gate current Ig forward biases the P2 P3 junction and a large number of electrons are introduced in the P2 region by N3. Finally the structure P2 N1 P1 N4 turns on completely.

Steady State Output Characteristics and Ratings of a Triac

From a functional point of view a triac is similar to two thyristors connected in anti parallel. Therefore, it is expected that the V-I characteristics of Triac in the 1 st and 3rd

quadrant of the V-I plane will be similar to the forward characteristics of a thyristors. As shown in Fig., with no signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak value is lower than the break over voltage (VBO) of the device. However, the turning on of the triac can be controlled by applying the gate trigger pulse at the desired instance. Mode-1 triggering is used in the first quadrant where as Mode-3 triggering is used in the third quadrant. As such, most of the thyristor characteristics apply to the triac (ie, latching and holding current). However, in a triac the two conducting paths (from MT1 to MT2 or from MT1 to MT1) interact with each other in the structure of the triac. Therefore, the voltage, current and frequency ratings of triacs are considerably lower than thyristors. At present triacs with voltage and current ratings of 1200V and 300A (rms) are available. Triacs also have a larger on state voltage drop compared to a thyristor. Manufacturers usually specify characteristics curves relating rms device current and maximum allowable case temperature as shown in Fig. Curves relating the device dissipation and RMS on state current are also provided for different conduction angles.

RMS ON state current Vs maximum case temperature.

COMPARISON OF MOSFET WITH BJT Power MOSFETS have lower switching losses but its on-resistance and

conduction losses are more. A BJT has higher switching loss bit lower conduction loss. So at high frequency applications power MOSFET is the obvious choice. But at lower operating frequencies BJT is superior.

MOSFET has positive temperature coefficient for resistance. This makes parallel operation of MOSFET’s easy. If a MOSFET shares increased current initially, it heats up faster, its resistance increases and this increased resistance causes this current to shift to other devices in parallel. A BJT is a negative temperature coefficient, so current shaving resistors are necessary during parallel operation of BJT’s.

In MOSFET secondary breakdown does not occur because it have positive temperature coefficient. But BJT exhibits negative temperature coefficient which results in secondary breakdown.

Power MOSFET’s in higher voltage ratings have more conduction losses.

Power MOSFET’s have lower ratings compared to BJT’s . Power MOSFET’s 500V to 140A, BJT 1200V, 800A.

THYRISTORSA thyristor is the most important type of power semiconductor devices. They are extensively used in power electronic circuits. They are operated as bi-stable switches from non-conducting to conducting state.

A thyristor is a four layer, semiconductor of p-n-p-n structure with three p-n junctions. It has three terminals, the anode, cathode and the gate.

The word thyristor is coined from thyratron and transistor. It was invented in the year 1957 at Bell Labs. The Different types of Thyristors are

Silicon Controlled Rectifier (SCR).

TRIAC

DIAC

Gate Turn Off Thyristor (GTO)

SILICON CONTROLLED RECTIFIER (SCR)

Fig.: Symbol

The SCR is a four layer three terminal device with junctions as shown. The construction of SCR shows that the

gate terminal is kept nearer the cathode. The approximate thickness of each layer and doping densities are as indicated in the figure. In terms of their lateral dimensions Thyristors are the largest semiconductor devices made. A complete silicon wafer as large as ten centimeter in diameter may be used to make a single high power thyristor.

Fig.: Structure of a generic thyristor

QUALITATIVE ANALYSISWhen the anode is made positive with respect the cathode junctions are forward biased and junction is reverse biased. With anode to cathode voltage being small, only leakage current flows through the device. The SCR is then said to be in the forward blocking state. If is further increased to a large value, the reverse biased junction will breakdown due to avalanche effect resulting in a large current through the device. The voltage at which this phenomenon occurs is called the forward breakdown voltage

. Since the other junctions are already forward biased, there will be free movement of carriers across all three junctions resulting in a large forward anode current. Once the SCR is switched on, the voltage drop across it is very small, typically 1 to 1.5V. The anode current is limited only by the external impedance present in the circuit.

G ate Cathode

J 3

J 2

J 1

Anode

10 cm17 - 3

10 - 5 x 10 cm13 14 - 3

10 cm17 - 3

10 cm19 - 3

10 cm19 -3 10 cm19 - 3n+ n+

p -

n –

pp+

10 m

30- 100 m

50- 1000 m

30- 50 m

Fig.: Simplified model of a thyristor

Although an SCR can be turned on by increasing the forward voltage beyond , in practice, the forward voltage is maintained well below and the SCR is turned on by applying a positive voltage between gate and cathode. With the application of positive gate voltage, the leakage current through the junction is increased. This is because the resulting gate current consists mainly of electron flow from cathode to gate. Since the bottom end layer is heavily doped as compared to the p-layer, due to the applied voltage, some of these electrons reach junction and add to the minority carrier concentration in the p-layer. This raises the reverse leakage current and results in breakdown of junction

even though the applied forward voltage is less than the breakdown voltage . With increase in gate current breakdown occurs earlier.

V-I CHARACTERISTICS

Fig. Circuit

Fig: V-I Characteristics

A typical V-I characteristics of a thyristor is shown above. In the reverse direction the thyristor appears similar to a reverse biased diode which conducts very little current until avalanche breakdown occurs. In the forward direction the thyristor has two stable states or modes of operation that are connected together by an unstable mode that appears as a negative resistance on the V-I characteristics. The low current high voltage region is the forward blocking state or the off state and the low voltage high current mode is the on

VAAVGG

RL

A

K

state. For the forward blocking state the quantity of interest is the forward blocking voltage which is defined for zero gate current. If a positive gate current is applied to a thyristor then the transition or break over to the on state will occur at smaller values of anode to cathode voltage as shown. Although not indicated the gate current does not have to be a dc current but instead can be a pulse of current having some minimum time duration. This ability to switch the thyristor by means of a current pulse is the reason for wide spread applications of the device.

However once the thyristor is in the on state the gate cannot be used to turn the device off. The only way to turn off the thyristor is for the external circuit to force the current through the device to be less than the holding current for a minimum specified time period.

Fig.: Effects on gate current on forward blocking voltage

HOLDING CURRENT

After an SCR has been switched to the on state a certain minimum value of anode current is required to maintain the thyristor in this low impedance state. If the anode current is reduced below the critical holding current value, the thyristor cannot maintain the current through it and reverts to its off state usually is associated with turn off the device.

LATCHING CURRENT

After the SCR has switched on, there is a minimum current required to sustain conduction. This current is called the latching current. associated with turn on and is usually greater than holding current.

QUANTITATIVE ANALYSISTWO TRANSISTOR MODEL

The general transistor equations are,

The SCR can be considered to be made up of two transistors as shown in above figure.

Considering PNP transistor of the equivalent circuit,

Considering NPN transistor of the equivalent circuit,

From the equivalent circuit, we see that

Two transistors analog is valid only till SCR reaches ON state

Case 1: When ,

The gain of transistor varies with its emitter current . Similarly varies with . In this case, with , varies only with . Initially when the

applied forward voltage is small, .

If however the reverse leakage current is increased by increasing the applied forward voltage, the gains of the transistor increase, resulting in .

From the equation, it is seen that when , the anode current tends towards . This explains the increase in anode current for the break over voltage .

Case 2: With gate current applied.

When sufficient gate drive is applied, we see that is established. This in turn results in a current through transistor , this increases of . But with the existence of

, a current through T, is established. Therefore, . This current in turn is connected to the base of . Thus

the base drive of is increased which in turn increases the base drive of , therefore regenerative feedback or positive feedback is established between the two transistors. This causes to tend to unity therefore the anode current begins to grow towards

a large value. This regeneration continues even if is removed this characteristic of SCR makes it suitable for pulse triggering; SCR is also called a Lathing Device.

SWITCHING CHARACTERISTICS (DYNAMIC CHARACTERISTICS)THYRISTOR TURN-ON CHARACTERISTICS

Fig.: Turn-on characteristics

When the SCR is turned on with the application of the gate signal, the SCR does not conduct fully at the instant of application of the gate trigger pulse. In the beginning, there is no appreciable increase in the SCR anode current, which is because, only a small portion of the silicon pellet in the immediate vicinity of the gate electrode starts conducting. The duration between 90% of the peak gate trigger pulse and the instant the forward voltage has fallen to 90% of its initial value is called the gate controlled / trigger delay time . It is also defined as the duration between 90% of the gate trigger pulse and the instant at which the anode current rises to 10% of its peak value. is usually in the range of 1sec.

Once has lapsed, the current starts rising towards the peak value. The period during which the anode current rises from 10% to 90% of its peak value is called the rise time. It is also defined as the time for which the anode voltage falls from 90% to 10% of its peak value. The summation of and gives the turn on time of the thyristor.

THYRISTOR TURN OFF CHARACTERISTICS

Anode currentbegins todecrease

tCtq

t

t

Commutation didt

Recovery Recombination

t1 t2 t3 t4 t5

tr r tgr

tqtc

V A K

I A

tq=device off tim etc=circuit off tim e

When an SCR is turned on by the gate signal, the gate loses control over the device and the device can be brought back to the blocking state only by reducing the forward current to a level below that of the holding current. In AC circuits, however, the current goes through a natural zero value and the device will automatically switch off. But in DC circuits, where no neutral zero value of current exists, the forward current is reduced by applying a reverse voltage across anode and cathode and thus forcing the current through the SCR to zero.

As in the case of diodes, the SCR has a reverse recovery time which is due to charge storage in the junctions of the SCR. These excess carriers take some time for recombination resulting in the gate recovery time or reverse recombination time . Thus, the turn-off time is the sum of the durations for which reverse recovery current flows after the application of reverse voltage and the time required for the recombination of all excess carriers present. At the end of the turn off time, a depletion layer develops

across and the junction can now withstand the forward voltage. The turn off time is dependent on the anode current, the magnitude of reverse applied ad the magnitude and rate of application of the forward voltage. The turn off time for converte grade SCR’s is 50 to 100sec and that for inverter grade SCR’s is 10 to 20sec.

To ensure that SCR has successfully turned off , it is required that the circuit off time be greater than SCR turn off time .

THYRISTOR TURN ON Thermal Turn on: If the temperature of the thyristor is high, there will be an

increase in charge carriers which would increase the leakage current. This would cause an increase in & and the thyristor may turn on. This type of turn on many cause thermal run away and is usually avoided.

Light: If light be allowed to fall on the junctions of a thyristor, charge carrier concentration would increase which may turn on the SCR.

LASCR: Light activated SCRs are turned on by allowing light to strike the silicon wafer.

High Voltage Triggering: This is triggering without application of gate voltage with only application of a large voltage across the anode-cathode such that it is greater than the forward breakdown voltage . This type of turn on is destructive and should be avoided.

Gate Triggering: Gate triggering is the method practically employed to turn-on the thyristor. Gate triggering will be discussed in detail later.

Triggering: Under transient conditions, the capacitances of the p-n junction

will influence the characteristics of a thyristor. If the thyristor is in the blocking state, a rapidly rising voltage applied across the device would cause a high current to flow through the device resulting in turn-on. If is the current throught the junction and is the junction capacitance and is the voltage across , then

From the above equation, we see that if is large, will be large. A high value

of charging current may damage the thyristor and the device must be protected against

high . The manufacturers specify the allowable .

THYRISTOR RATINGS

First Subscript Second Subscript Third Subscript

D off state W working M Peak Value

T ON state R Repetitive

F Forward S Surge or non-repetitive

R Reverse

VOLTAGE RATINGS

: This specifies the peak off state working forward voltage of the device. This specifies the maximum forward off state voltage which the thyristor can withstand during its working.

: This is the peak repetitive off state forward voltage that the thyristor can block repeatedly in the forward direction (transient).

: This is the peak off state surge / non-repetitive forward voltage that will occur across the thyristor.

: This the peak reverse working voltage that the thyristor can withstand in the reverse direction.

: It is the peak repetitive reverse voltage. It is defined as the maximum permissible instantaneous value of repetitive applied reverse voltage that the thyristor can block in reverse direction.

: Peak surge reverse voltage. This rating occurs for transient conditions for a specified time duration.

: On state voltage drop and is dependent on junction temperature.

: Peak on state voltage. This is specified for a particular anode current and junction temperature.

rating: This is the maximum rate of rise of anode voltage that the SCR has to

withstand and which will not trigger the device without gate signal (refer triggering).

CURRENT RATING

: This is the on state average current which is specified at a particular temperature.

: This is the on-state RMS current.

Latching current, : After the SCR has switched on, there is a minimum current required to sustain conduction. This current is called the latching current. associated with turn on and is usually greater than holding current

Holding current, : After an SCR has been switched to the on state a certain minimum value of anode current is required to maintain the thyristor in this low impedance state. If the anode current is reduced below the critical holding current value, the thyristor cannot

maintain the current through it and reverts to its off state usually is associated with turn off the device.

rating: This is a non repetitive rate of rise of on-state current. This maximum value of

rate of rise of current is which the thyristor can withstand without destruction. When thyristor is switched on, conduction starts at a place near the gate. This small area of

conduction spreads rapidly and if rate of rise of anode current is large compared to

the spreading velocity of carriers, local hotspots will be formed near the gate due to high current density. This causes the junction temperature to rise above the safe limit and the

SCR may be damaged permanently. The rating is specified in .

GATE SPECIFICATIONS

: This is the required gate current to trigger the SCR. This is usually specified as a DC value.

: This is the specified value of gate voltage to turn on the SCR (dc value).

: This is the value of gate voltage, to switch from off state to on state. A value below this will keep the SCR in off state.

: Amount of charge carriers which have to be recovered during the turn off process.

: Thermal resistance between junction and outer case of the device.

GATE TRIGGERING METHODS

Types

The different methods of gate triggering are the following

R-triggering.

RC triggering.

UJT triggering.

RESISTANCE TRIGGERINGA simple resistance triggering circuit is as shown. The resistor limits the current through the gate of the SCR. is the variable resistance added to the circuit to achieve control over the triggering angle of SCR. Resistor ‘R’ is a stabilizing resistor. The diode D is required to ensure that no negative voltage reaches the gate of the SCR.

Fig.: Resistance firing circuit

Fig.: Resistance firing of an SCR in half wave circuit with dc load

(a) No triggering of SCR (b) = 900 (c) < 900

LOAD

v Oa b

i R1

R2

D

R Vg

VTv = V sin tS m

V S

23 4

t

V sin tm

Vg Vgt

t

t

t

t

Vo

io

VT

Vgp VgtVgp

(a)

t

t

t

t

t

t

t

t

t

t

23 4

23 4

VS

Vg

Vo

io

VT

VS

Vg

Vo

io

VT

V =Vgp gt

2700

23 4

900 =900

(c)(b)

<900

V >Vgp gt

DesignWith , we need to ensure that , where is the maximum or peak gate

current of the SCR. Therefore .

Also with , we need to ensure that the voltage drop across resistor ‘R’ does not exceed , the maximum gate voltage

OPERATIONCase 1:

, the peak gate voltage is less then since is very large. Therefore, current ‘I’ flowing through the gate is very small. SCR will not turn on and therefore the load voltage is zero and is equal to . This is because we are using only a resistive network. Therefore, output will be in phase with input.

Case 2: , optimum value.

When is set to an optimum value such that , we see that the SCR is triggered at (since reaches its peak at only). The waveforms shows that the load voltage is zero till and the voltage across the SCR is the same as input voltage till it is triggered at .

Case 3: , small value.

The triggering value is reached much earlier than . Hence the SCR turns on earlier than reaches its peak value. The waveforms as shown with respect to

.

At

Therefore

But

Therefore

Since are constants

RESISTANCE CAPACITANCE TRIGGERINGRC HALF WAVE

Capacitor ‘C’ in the circuit is connected to shift the phase of the gate voltage. is used to prevent negative voltage from reaching the gate cathode of SCR.

In the negative half cycle, the capacitor charges to the peak negative voltage of the supply through the diode . The capacitor maintains this voltage across it, till the supply voltage crosses zero. As the supply becomes positive, the capacitor charges through resistor ‘R’ from initial voltage of , to a positive value.

When the capacitor voltage is equal to the gate trigger voltage of the SCR, the SCR is fired and the capacitor voltage is clamped to a small positive value.

Fig.: RC half-wave trigger circuit

LOAD

v O

R

C

VT

v =V sin tS m

D2

VC

+

-D 1

vs

0

V sin tm

0 t

tt

a vc

- / 2

avc

V gt

vo

vT

Vm

- Vm

vs

0

V sin tm

0 t

a vc

- / 2

avc

Vgt

0

0

vo

vT

Vm Vm

-V m (2 + )

(a) (b)

t t

Fig.: Waveforms for RC half-wave trigger circuit

(a) High value of R (b) Low value of R

Case 1: R Large.

When the resistor ‘R’ is large, the time taken for the capacitance to charge from to is large, resulting in larger firing angle and lower load voltage.

Case 2: R Small

When ‘R’ is set to a smaller value, the capacitor charges at a faster rate towards resulting in early triggering of SCR and hence is more. When the SCR triggers, the voltage drop across it falls to 1 – 1.5V. This in turn lowers, the voltage across R & C. Low voltage across the SCR during conduction period keeps the capacitor discharge during the positive half cycle.

DESIGN EQUATIONFrom the circuit . Considering the source voltage and the gate circuit, we can write . SCR fires when that is .

Therefore . The RC time constant for zero output voltage that is

maximum firing angle for power frequencies is empirically gives as .

RC FULL WAVEA simple circuit giving full wave output is shown in figure below. In this circuit the initial voltage from which the capacitor ‘C’ charges is essentially zero. The capacitor ‘C’ is reset to this voltage by the clamping action of the thyristor gate. For this reason the charging time constant RC must be chosen longer than for half wave RC circuit in order

to delay the triggering. The RC value is empirically chosen as . Also

.

v O

R

C

VT

v = V sin tS m

+

-

LOA D+

-

D1 D3

D4 D2

vd

Fig: RC full-wave trigger circuit

Fig: Wave-forms for RC full-wave trigger circuit

(a) High value of R (b) Low value of R

PROBLEM

1. Design a suitable RC triggering circuit for a thyristorised network operation on a 220V, 50Hz supply. The specifications of SCR are , .

Therefore

vs

vd

vo

vT

t

t

t

t

V sin tm

vd

vc vc vcvgt

V sin tm vs

vd

vo

vT

t

t

t

vgt

(a) (b)

UNI-JUNCTION TRANSISTOR (UJT)

Fig.: (a) Basic structure of UJT (b) Symbolic representation

(c) Equivalent circuit

UJT is an n-type silicon bar in which p-type emitter is embedded. It has three terminals base1, base2 and emitter ‘E’. Between and UJT behaves like ordinary resistor and the internal resistances are given as and with emitter open . Usually the p-region is heavily doped and n-region is lightly doped. The equivalent circuit of UJT is as shown. When is applied across and , we find that potential at A is

is intrinsic stand off ratio of UJT and ranges between 0.51 and 0.82. Resistor is between 5 to 10K.

OPERATION

When voltage is applied between emitter ‘E’ with base 1 as reference and the emitter voltage is less than the UJT does not conduct. is designated as which is the value of voltage required to turn on the UJT. Once is equal to , then UJT is forward biased and it conducts.

The peak point is the point at which peak current flows and the peak voltage is across the UJT. After peak point the current increases but voltage across device drops, this is due to the fact that emitter starts to inject holes into the lower doped n-region. Since p-region is heavily doped compared to n-region. Also holes have a longer life time, therefore number of carriers in the base region increases rapidly. Thus potential at ‘A’ falls but current increases rapidly. acts as a decreasing resistance.

RB2

VBB

+

-

E

B1

RB1 VBB

A+

-

Ve I e

B2

E

B2

B1B1

A

B2

E

RB2

RB1n- type

p- type

Eta-pointEta-point

(a) (b) ( c)

The negative resistance region of UJT is between peak point and valley point. After valley point, the device acts as a normal diode since the base region is saturated and does not decrease again.

Ve

VBBR load line

Vp

Vv

I eIvI p0

Peak Point

Cutoffregion

Negative ResistanceRegion

Saturation region

Valley Point

Fig.: V-I Characteristics of UJT

UJT RELAXATION OSCILLATOR

UJT is highly efficient switch. The switching times is in the range of nanoseconds. Since UJT exhibits negative resistance characteristics it can be used as relaxation oscillator. The circuit diagram is as shown with and being small compared to and of UJT.

Fig.: UJT oscillator (a) Connection diagram and (b) Voltage waveforms

R R2

VBB

R1C

E B2

B1Ve vo

V e

Vp

V V

Vo

t

t

Capacitorcharging

T =RC1

1

T

V +VBB

VP

T =R C2 1

Capacitordischarg ing

V v

(a) (b)

OPERATION

When is applied, capacitor ‘C’ begins to charge through resistor ‘R’ exponentially towards . During this charging emitter circuit of UJT is an open circuit. The rate of charging is . When this capacitor voltage which is nothing but emitter voltage reaches the peak point , the emitter base junction is forward biased and UJT turns on. Capacitor ‘C’ rapidly discharges through load resistance with time constant . When emitter voltage decreases to valley point , UJT turns off. Once again the capacitor will charge towards and the cycle continues. The rate of charging of the capacitor will be determined by the resistor R in the circuit. If R is small the capacitor charges faster towards and thus reaches faster and the SCR is triggered at a smaller firing angle. If R is large the capacitor takes a longer time to charge towards the firing angle is delayed. The waveform for both cases is as shown below.

EXPRESSION FOR PERIOD OF OSCILLATION ‘T’The period of oscillation of the UJT can be derived based on the voltage across the capacitor. Here we assume that the period of charging of the capacitor is lot larger than than the discharging time.

Using initial and final value theorem for voltage across a capacitor, we get

Therefore

If

But

If

Therefore

DESIGN OF UJT OSCILLATORResistor ‘R’ is limited to a value between 3 kilo ohms and 3 mega ohms. The upper limit on ‘R’ is set by the requirement that the load line formed by ‘R’ and intersects the device characteristics to the right of the peak point but to the left of valley point. If the load line fails to pass to the right of the peak point the UJT will not turn on, this condition

will be satisfied if , therefore .

At the valley point and , so the condition for the lower limit on ‘R’ to

ensure turn-off is , therefore .

The recommended range of supply voltage is from 10 to 35V. the width of the triggering pulse .

In general is limited to a value of 100 ohm and has a value of 100 ohm or greater

and can be approximately determined as .