UM10562LPC408x/407x User manualRev. 3 12 March 2014 User manual

Document informationInfo ContentKeywords ARM, ARM Cortex-M4, 32-bit, USB, Ethernet, LCD, CAN, I2C, I2S, Flash,

EEPROM, Microcontroller

Abstract LPC408x/407x user manual

NXP Semiconductors UM10562LPC408x/407x User Manual

Revision historyRev Date Description

3 20140312 Figure 16 EMC block diagram updated and CCLK renamed to EMCCLK throughout the chapter.

Update Section 9.11.1 Mode register setup. Function SSP2_SCK added to pin P5[2]. See Table 75 and Table 90. Function SSP2_SSEL added to pin P5[3]. See Table 75 and Table 90. Updated the description of the ROM_LAT bit in Table 7 Matrix Arbitration register (MATRIXARB

- 0x400F C188) bit description. This bit should be 1 for normal operation. Figure 23 Ethernet packet fields updated with the correct order of octets in the MAC address. Description of FLASHTIM bit values 0x11 and 0x100 corrected in Table 50 Flash Accelerator

Configuration register (FLASHCFG - address 0x400F C000) bit description. IRCCTRL register added. See Table 34 IRC control register (IRCCTRL - address

0x400F C1A4) bit description. Incorrect reference to VREFN removed in Table 684 D/A Pin Description and Table 686 D/A

Converter Register (CR - address 0x4008 C000) bit description. Description of the SPIFI software library removed. The description is available on

LPCWare.com. Description of the SPIFI hardware and register interface added. See Section 15.7. Description of the SLEW bit improved. See Table 83 Type D IOCON registers bit description.

2 20130306 Added LQFP100. Minor updates and corrections.

1 20120913 Initial LPC408x/407x User manual version.

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User manual Rev. 3 12 March 2014 2 of 947

Contact informationFor more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

http://www.lpcware.com

1.1 Introduction

The LPC408x/407x is an ARM Cortex-M4 based microcontroller for embedded applications requiring a high level of integration and low power dissipation.

The Cortex-M4 processor is a high-performance 32-bit processor with a 3-stage pipeline Harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peripherals. The Cortex-M4 uses the Thumb instruction set, providing high code density and reduced program memory requirements. The Cortex-M4 CPU also includes an internal prefetch unit that supports speculative branches. The LPC408x/407x adds a specialized flash memory accelerator to give optimal performance when executing code from flash. The LPC408x/407x is targeted to operate at up to a 120 MHz CPU frequency under worst case commercial conditions.

The peripheral complement of the LPC408x/407x includes up to 512 kB of Flash memory, up to 96 kB of data memory, 4,032 bytes of EEPROM memory, an External Memory Controller for SDRAM and static memory access, an LCD panel controller, an Ethernet MAC, a high speed SPI flash memory interface (SPIFI), a General Purpose DMA controller, a USB device/host/OTG interface, 5 UARTs, 3 SSP controllers, 3 I2C interfaces, an I2S serial audio interface, a 2-channel CAN interface, an SD card interface, an 8 channel 12-bit ADC, a 10-bit DAC, analog comparators, a Motor Control PWM, a Quadrature Encoder Interface, 4 general purpose timers, a 6-output general purpose PWM, an ultra-low power RTC with separate battery supply and event monitor/recorder, a windowed watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins, and more.

See Section 41.2 References for additional documentation related to the LPC408x/407x parts.

UM10562Chapter 1: Introductory informationRev. 3 12 March 2014 User manual

UM10562 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All rights reserved.

User manual Rev. 3 12 March 2014 3 of 947

NXP Semiconductors UM10562Chapter 1: Introductory information

1.2 Features

Refer to Section 1.4 for details of features for specific part numbers.

Functional replacement for LPC23xx and 24xx family devices. ARM Cortex-M4 processor, running at frequencies of up to 120 MHz. The Cortex-M4

executes the Thumb-2 instruction set for optimal performance and code size, including hardware division, single cycle multiply, and bit-field manipulation. A Memory Protection Unit (MPU) supporting eight regions is included.

Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC). Cortex-M4 Floating Point Unit (FPU), supporting single-precision floating-point

computation functionality in compliance with the ANSI/IEEE Standard 754-2008. The FPU provides add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also performs a variety of conversions between fixed-point, floating-point, and integer data formats. The FPU is not available on LPC4074 devices.

Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code/data bus provides high code performance from flash.

Up to 96 kB on-chip SRAM includes: Up to 64 kB of Main SRAM on the CPU code/data bus for high-performance CPU

access. Up to two 16 kB SRAM blocks with separate access paths for higher throughput.

These SRAM blocks may be used for Ethernet, USB, LCD, and DMA memory, as well as for general purpose instruction and data storage.

Up to 4,032 bytes of on-chip EEPROM. External Memory Controller provides support for asynchronous static memory devices

such as RAM, ROM and Flash up to 64 MB, as well as dynamic memories such as Single Data Rate SDRAM.

Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S, UART, SD/MMC, CRC engine, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, GPIO, and for memory-to-memory transfers.

Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, LCD controller, and the USB interface. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time.

Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy.

LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistor (TFT) displays. The LCD controller is not available on LPC407x devices. Dedicated DMA controller. Selectable display resolution (up to 1024 768 pixels).

UM10562 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All rights reserved.

User manual Rev. 3 12 March 2014 4 of 947

NXP Semiconductors UM10562Chapter 1: Introductory information

Supports up to 24-bit true-color mode. Serial interfaces:

Ethernet MAC with MII/RMII interface and dedicated DMA controller. USB 2.0 full-speed controller that can be configured for either device, Host, or

OTG operation with an on-chip PHY for device and Host functions and a dedicated DMA controller. USB Host and OTG are not available on LPC4074 devices.

Five UARTs with fractional baud rate generation, internal FIFOs, IrDA, DMA support, and RS-485/EIA-485 support on most LPC408x/407x devices. UART1 also has a full set of modem handshaking signals. UART4 includes a synchronous mode and a smart card mode supporting ISO 7816-3. UART4 is not available on LPC4074 devices.

Three SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.

Three enhanced I2C-bus interfaces, one with an open-drain output supporting the full I2C specification and Fast mode Plus with data rates of 1Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode.

Two-channel CAN controller. I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate

control. The I2S interface can be used with the GPDMA. The I2S interface supports 3-wire data transmit and receive or 4-wire combined transmit and receive connections, as well as master clock output.

SPIFI (SPI Flash Interface). This interface uses an SPI bus superset with 4 data lines to access off-chip Quad SPI Flash memory at a much higher rate than is possible using standard SPI or SSP interfaces. The SPIFI function allows memory mapping the contents of the off-chip SPI Flash memory such that it can be executed as if it were on-chip code memory. Supports SPI memories with 1 or 4 data lines.

Other peripherals: SD card interface that also supports MMC cards. The SD card interface is not

available on LPC4074 devices. General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open

drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access, and support Cortex-M4 bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate an interrupt. There are 165 GPIOs on 208-pin packages, 141 GPIOs on 180-pin packages, and 109 GPIOs on 144-pin packages.

12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 400 kHz, and