desytrunk/agipd10_manual.pdf · thedraft agipd asic manual julian becker1, roberto dinapoli2, heinz...

DR

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The AGIPD ASIC Manual

Julian Becker1, Roberto Dinapoli2, Heinz Graafsma1∗,

Dominic Greiffenberg2, Alexander Klyuev1, Alessandro Marras1, Davide Mezza2,

Aldo Mozzanica2, Bernd Schmitt2, Xintian Shi2, Ulrich Trunk1

for the AGIPD Colaboration1DESY Deutsches Elektronen-Synchrotron, Hamburg, Germany

2PSI Paul Scherrer Institut, Villingen, Switzerland∗ also Midsweden University, Sundsvall, Sweden

Version 0.6.1, April 10, 2017

Abstract

This document describes the AGIPD 1.01 and AGIPD 1.1 ASICs2 in terms of geometry,

port definitions, electrical specifications, and of the implemented communications protocol.It furthermore provides brief descriptions of circuits implemented and sample command se-quences for the operation of the ASICs.AGIPD 1.0 and AGIPD 1.1 are circuits to read out the AGIPD detector for the European XFEL.The detector features 1M (1024 × 1024) pixels of 200µm pitch and is constructed from sen-sors of 128 × 512 pixels, bump-bonded to 2 × 8 ASICs. Each ASIC consists of the readoutelectronics for 64× 64 pixels:

� A charge sensitive preamplifier with 3-fold self-adapting gain in each pixel

� A correlated double-sampling stage in each pixel

� Analogue storage for 352 samples (images) in each pixel

� Amplifiers and multiplexers to readout these signals via 4 differential analogue outputs

� Circuits for biasing and test signal injection

� A tree-line serial interface to receive commands and digital circuitry to decode these andto steer and control the circuits mentioned above.

1Adaptive Gain Integrating Pixel Detector2Application Specific Integrated Circuit

1

DRAFT -- DRAFT -- DRAFT -- DRAFT -- DRAFT --

Caution!

The AGIPD 1.0 is a DSM CMOS device and implements only very ba-

sic ESD protection. Thus make sure to work only in ESD protected

environment and strictly obey to all ESD protection rules!

1 Document and Chip Version History

Document Version Date Author Description

0.1 25.03.2013 U.T. document created0.2 23.04.2013 U.T. bias and calibration circuits added0.3 28.08.2013 U.T. meaningful menonics for bias and test circuits0.5 25.09.2013 U.T. content to bugs & limitations section added0.5.1 10.10.2013 U.T. reworked bias commands,

removed obsolete ”Reg nn” references, cosmetics

0.5.2 08.01.2014 U.T. content to bugs & limitations section added0.5.3 26.02.2014 U.T. error in SETUPR description and RPAMPA graphic

removed0.6.0 20.01.2016 U.T. New ASIC version AGIPD 1.1 included

revised timing example for correctnessadded sections describing AGIPD 1.1.marked AGIPD 1.0 information superseded by newinformation for AGIPD 1.1.

0.5.3 10.04.2017 U.T. wrong sequence of power pads B42 . . .B48 andB57 . . .B62 in tab. 11 corrected.

∞ N.N. add content hereCheckhttp://photon-science.desy.de/research/technical groups/detectors/projects/agipd

for the latest version

Chip Version Submission Date Changes relating to previous version

AGIPD 1.01 19.04.2013 Full-sized readout chipAGIPD 1.1

1 18.04.2015 Improved version of AGIPD 1.0 in terms ofReadout speed”Ghosting” crosstalkGain and baseline homogeneityGain bit handlingCalibration circuitryPower distributionMinor other improvements

1Submitted via MOSIS as an engineering run

2


Contents

1 Document and Chip Version History 2

2 Chip Architecture 4

3 The Circuits 4

3.1 Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.2 Adaptive gain switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.3 CDS buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.4 Embedded analogue memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.5 Radiation hardness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.6 Readout sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.7 Bias Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.8 Calibration Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.8.1 Calibration Signal Injection Matrix . . . . . . . . . . . . . . . . . . . . . . . 83.8.2 Capacitor Charge Injection Circuits . . . . . . . . . . . . . . . . . . . . . . 83.8.3 Current Source Injection Circuit . . . . . . . . . . . . . . . . . . . . . . . . 9

3.9 Periphery & serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.9.1 Data Format and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.9.2 Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Differences between AGIPD 1.1 and AGIPD 1.0 94

4.1 Handling of gain information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944.2 Calibration Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954.3 Readout Speed and ”Ghosting” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.3.1 Readout Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954.3.2 ”Ghosting” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.4 Power Distribution and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5 Proposed Algorithm for Data Acquisition 96

6 List of known Problems and Bugs 98

6.1 Issues of AGIPD 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986.2 Issues still present in AGIPD 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

A AGIPD 1.0 Pad Layout and Description 100

B AGIPD 1.1 Pad Layout and Description 182

3


AGIPD 1.0Pixel (´4096)

Readout chain

CDS stage

Preamplifier stage

Cf, high

Cf, mid

Cf, low

Preamp RST

Ccouple

CDS RST

Cf, CDS

Vref

Dynamic

gain

switching

DAC

Storage

cell matrix

Storage

cell matrix

Pixel buffer

PXB RST

Cf, PXB

Double column

buffer (´64)

even row

odd rowMux

Offchip drver

(´4)

Cmd based IF, periphery, DACs

Figure 1: Schematic of the AGIPD 1.0 readout ASIC

2 Chip Architecture

Each readout chip contains a square matrix of 64× 64 pixels, read out on four ports. Each pixelcontains

� a charge sensitive preamplifier with switchable gains

� a discriminator

� the gain switch control circuit and a DAC to encode the switch settings

� a CDS3 buffer

� analogue memory of 2× 352 cells

� a charge sensitive readout buffer.

These buffers connect to one of the two readout buses per pixel column, which serve the pixelsof even and odd rows respectively. The pixel matrix is subdivided in 4 blocks of 16 × 64 pixels,operating in parallel. Each of these blocks connects to a multiplexer and output buffer. Thecommand based control of the chip is based on a 3-line serial interface. The block schematic ofthe ASIC is depicted in fig. 1, while fig. 2 shows the layout of a single pixel.

3 The Circuits

3.1 Preamplifier

The preamplifier uses a simple inverter as a core cell. Feedback is provided by means of a 60 fFMiMCap4. For lower sensitivities, additional dual-MiMCaps of 3 pF and 10pF respectively canbe connected in parallel to the initial feedback.

3.2 Adaptive gain switching

The output of the charge sensitive preamplifier not only connects to the CDS buffer as the sub-sequent stage in the signal path, but also to a discriminator. If an input signal triggers thisdiscriminator, the additional feedback capacitors are added to the preamplifier feedback, thuslowering sensitivity and increasing the dynamic range in two steps. Delays in the control circuitryof the gain switching ensure proper operation in case of the instantaneous signal of an FEL.

3correlated double sampling – Samples are only correlated for the highest sensitivity. The correlation is brokenif gain switching occurs.

4Metal-inter-metal capacitor, formed by a thin dielectric and an additional metal layer in the BEOL.

4


Figure 2: Layout of a pixel ofAGIPD 0.4 (and AGIPD 1.0). Only the narrow stripe on the left handside contains active circuitry, most of the area is occupied by the analogue memory

3.3 CDS buffer

The CDS functionality is implemented as a resetable integrator, built around an operationalamplifier with capacitive coupling to the preamplifier. The output of the CDS buffer and ananalogue encoding of the selected gain are written to the analogue memory, which can store 352samples.

3.4 Embedded analogue memory

The analogue memory consists of two types of storage cells: for amplitude values (Cstore ≈ 200fF)and for the encoded gain settings (Cstore ≈ 30fF), as fig 3 shows.

The requirements on amplitude values are demanding an accuracy of better than 0.1 photon toensure the single photon sensitivity of the detector, which translates to 0.1% of the preamplifier-CDS frontend output range, maintained for a storage time of at least 10ms. Thus leakage currentsin the storage capacitors and switches were considered the most critical issue in the ASIC designand investigated with the very first chips submitted (HPAD 0.1 and HPAD 0.2). These storagecells are also considered the part of the circuit most seriously affected by radiation damage, whichwas also investigated with these chips. As a result storage cells use a DGNCAP5 as storageelement and two thin-oxide p-FETs as switches (c.f. fig. 4). The two transistors in series servetwo purposes:

� A logic AND of the row and column lines of the Memory is formed.

� The voltage drop across the lower FET and thus the leakage current is minimised.

For the capacitor a DGNCAP was used, since these devices are radiation hard and show nomeasurable leakage due to the thick dielectric layer employed.

3.5 Radiation hardness

Extensive studies on the radiation hardness of the storage cells have been performed with severalprototype chips. While the floating n-well ensured a very low leakage for non-irradiated chips,surface charges caused an inversion layer around this n-well after ≤ 100kGy. This layer substan-tially increases the area for the collection of minority carriers (i.e. electrons), leading to a rapid

5Thick oxide n-FET in an n-well

5


Figure 3: Layout of the storage cells in the analogue memory of AGIPD: The big capacitor onthe left hand side is used to store the signal amplitude, while the small on on the right hand sidestores the preamplifier gain, encoded to three analogue levels.

ROW_SW

COL_SW

ROW_SW

COL_SW

ROW_SW

COL_SW

VDD

VSS

VC

T0

T1

C0

VIN

VIN

VIN

VDD

VC

VSS

VSS

VC

SD

SD

SD

SD

VDD

S/D

gate

lp

dg

nca

p

VC

lp

Figure 4: Schematic of the storage cells in the analogue memory of AGIPD.

discharge of the n-well. In turn the pn-junction inside the n-well is forward biased, and the ca-pacitor is discharged. To circumvent this behaviour, a diffusion ring, biased to a positive voltagewas placed around the floating n-well. It serves to collect the minority carriers, directly or viathe radiation-induced inversion layer. If the inversion grows stronger, i.e. turns into a parasiticchannel, it pulls up the n-well to a positive potential. Albeit this sacrifices the zero voltage dropacross the switch for higher doses, it reliably prevents the discharge of the storage cells due to aforward biased pn-junction.These radiation hardness studies furthermore showed, that cooling a chip dosed with 100kGy to

6


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Figure 5: Switching sequence of pixels and memory cells onAGIPD. The scheme only shows 3× 3pixels with 3× 3 storage cells. C indicates the column switch and R the row switch being closed,X indicates the readout of the memory cell (i.e. both switches are closed).

−20◦C restored its non-irradiated droop behaviour. It also turned out, that LP6-FETs, whichdue to the higher Vth show a lower initial leakage current, degrade more with dose than theirRVT7-counterparts, which in turn were used for the switches.

3.6 Readout sequence

The access switches of the pipeline form a logic ”AND”, which is exploited as part of the memoryaddressing scheme, and could cause an additional charge loss. However, the foreseen readoutsequence of AGIPD, illustrated in fig. 5, operates the switches in a non-interleaved fashion:The worst case is the last memory cell in the bottom pixel row, its column switch is operated(64× 11)− 1 = 703 times and the row switch 32− 1 = 31 times (due to column parallel readout),before the cell is finally read. Nevertheless, due to the non-interleaved operation of the switches,only the charge on the node between the two switches is lost, as fig. 6 shows.

3.7 Bias Circuits

All amplifier stages of AGIPD 1.0, except for the preamplifier, feature forced bias currents. Thesebias currents are derived from a reference current and are adjustable by means of on-chip DACs8 innormal operation. Also many node voltages, like the threshold level of the discriminator triggeringthe gain switching vth comp, the DC reference level of the CDS stage vref cds and many cascodevoltages (e.g. vcascp pixbuf ) are adjustable via DACs. Control of these DACs is provided viathe command based interfaces (Sect. 3.9) by means of the commands/registers REG03-REG24 (c.f.sect. 3.9.2).

6Low-power (high) Vth7Regular Vth8Digital to Analogue Converters

7


Figure 6: Impact of memory access (switching) on the stored signals (on AGIPD 0.3). The data ofthe red dots are read out without any prior switch operation. For the blue dots the column switchwas operated 70, the row switch 32 times before readout. The ”gaps” of the curves are caused bydata loss due to a disk failure.

Besides the obvious need of adjustable stimuli for calibration, the possibility to change internalnode voltages and biases provides means to compensate for radiation damage, process variationsor thermal effects (e.g. when operating the detector at ambient temperature instead of beingcooled).

All control voltage nodes also connect to pads, thus control voltages can be monitored orstabilised by external circuitry (like blocking capacitors). These pads can also be used to provideexternal control voltages to the ASIC. Also bias currents can be provided eternally. To facilitatethis, the bias currents or control voltages generated on chip can be disconnected from the biasednodes by switches, which are controlled via the command based interfaces (Sect. 3.9) by meansof the commands/registers REG29-REG31 (c.f. sect. 3.9.2). While the external pads for the controlvoltages are always connected to the corresponding node, the pads for bias currents are onlyconnected to the bias network, if the internal source is switched off.

3.8 Calibration Circuits

AGIPD 1.0 implements two possibilities to inject test charges into pixels: Either a voltage step canbe applied to a capacitor to inject a defined (small) charge, or a current source can be connectedto the pixel input. By increasing current and integration time, this method allows also to accesthe medium and low gain regimes of the preamplifier. The pixels to receive a calibration signalcan be selected out of sub-arrays of 8× 8 pixels.

3.8.1 Calibration Signal Injection Matrix

The 64 × 64 pixel matrix of AGIPD 1.0 is divided into 8 × 8 sub-matrices of 8 × 8 pixels each.Pixels inside each of these sub-matrices are selected by the logical AND of the 8 row and 8 columnlines. This way from 64 to 4096 pixels can be selected (in multiples of 64) for signal injection bythe TIROWM and TICOLM commands (c.f. sect. 3.9.2) .

3.8.2 Capacitor Charge Injection Circuits

A voltage step ∆U applied to a capicitor, which has its other node connected to a constant voltage(i.e. low-impedance) node, will inject a a charge ∆Q = C ×∆U into this node. Since the inputof a charge sensitive amplifier is (by design) such a low -impedance node, this scheme is usedas a calibration circuit. In AGIPD 1.0 this calibration procedure relies on passing two analoguevoltages (VC0 , VC1) to each AGIPD pixel. In pixels, which are selected by the TIROWM and TICOLM

commands, a test signal (programmed via the TSTDLY and TSTGAT commands) ca switch thecapacitor node fom VC0 to VC1, and thus will cause a defined charge injection into the preamplifierinput node. Each of these two analogue voltages can be:

8


1. programmed by means a 10-bit DAC;

2. retrived from an external pad;

3. equal to VDD;

4. equal to VSS;

5. left floating

The value of the 10-bit DAC and the settings of the switches connecting VC0 to bespoke DAC, apad, VDD, VSS, or left floating is combined into a 16-bit code set by the commands VPC2HI andVPC2LO . For VC1 the commands VPC1HI and VPC1LO ) are used respectively) c.f. 3.9.2).

3.8.3 Current Source Injection Circuit

In addition to the pulsed capacitor injection circuit, AGIPD 1.0 also features a programmablecurrent source for charge injection. The command ITESTC sets the current itest curr, which canbe integrated for the coincidence of the preamplifier integration time and the signal defined by theTSTDLY and TSTGAT commands. Again pixels for injection are selected via the TIROWM and TICOLM

commands. By increasing the preamplifier’s integration time and TSTGAT , any point within thedynamic range of AGIPD 1.0 becomes accesible, albeit at the cost of a lower expected stabilitythan the pulsed capacitor schema and additional errors (e.g. sensor leakage currents) arising fromthe changed preamplifier integration time.

3.9 Periphery & serial interface

The command based interface uses three lines (fig. 7): clock, data and start of bunch. Thelatter triggers the interpretation of a command, i.e. its execution. Thus it also provides thesynchronisation with the European XFEL’s 4.5MHz bunch timing. Since the command length is16 bits, the clock signal has to be at least 72MHz for sampling and 7.6MHz to accomplish thereadout of 352 × 2 × 16× 64 samples within 99.4ms. This clock signal also serves as an internaltiming reference, i.e. determines the granularity of all internal signals, like preamp reset time andthe CDS integration period, since these are derived from it by means of a programmable sequencer,as shown in fig. 8. At the European XFEL it is planned to operate AGIPD with a 99MHz clock.Thus the sequence to capture a frame is 22 clock cycles long, while the sequence to readout a rowof 16 pixels is 48 cycles in length, since the readout multiplexer uses a programmable clock dividerand sampling at 33MHz is envisaged.The Periphery also implements the random access to the memory and the control of the interleavedcolumn parallel readout (fig. 9): The cells of a defined memory address are read out for one pixelrow and driven down one of the column buses, while the signals of the previous row are stillconnected to the other column bus, are serialised and driven off chip via multiplexer and off-chipdriver. This way the pixel readout buffer can be much slower and less power consuming. Only themultiplexer and the readout buffer operate at the full readout speed.The interface on AGIPD 1.0 implements 6 types of commands:

� Capture frame (argument: memory address)

� Set memory address (argument: memory address), it can also serve as a NOP9 command

� Program the status register (argument: register bits)

� Program internal timings (arguments: function, time in clock cycles)

� Program on-chip DACs/registers (arguments: DAC/register address, DAC/register value)

� Read pixel (arguments: read mode10, prefetch pixel row, mux pixel row)

9no operation103 bits encoding analogue/gain readout, first row, last row

9


Clk

Data

SoB

Command execution

Figure 7: Data format of AGIPD 1.0’s control interface. The gray parts indicate the precedingand subsequent commands, Data is interpreted in MSB-first order. The diagram shows the fastestpossible timing, i.e. command execution within 16 Clk cycles.

MEM_COL

RE

G&

DA

CR

EG

&D

AC

RE

G&

DA

C

STROBE

SR (IF)

Periphery

(CMD & Addr. Decoder,

Slow Control)

MEM_ROW

Data

Clk

SOB

Delay Gate

Delay Gate

PIX_ROW

PIX_COL

DEC

DE

C Pixel Matrix

GLOBAL_SIGNALs

BUS

Delay Gate

RE

G&

DA

C

MUXMUX_CLK, MUX_TOKEN

Figure 8: Block schematic of the interface and control circuit of AGIPD 1.0.

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Mux

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Pix

Mux

Column buffers

Readout buffers

Figure 9: Visualisation ofAGIPD 1.0’s column parallel readout scheme.

3.9.1 Data Format and Timing

3.9.2 Command Set

The following section describes all commands implemented on AGIPD 1.0. It also shows theformat of arguments, a timing diagram for the execution of that particular command and listsdependencies. Thus the effect of configuration related commands is usually visible in the timingdiagrams of the influenced commands in the dependencies section. A comprehensive summary ofall commands can be found in tab. 1.

Table 1: AGIPD 1.0 Command Set.

Memnonic Bit pattern Description Arguments

SETMEM 1000000AAAAAAAAA Set memory address AAAAAAAAA = Memory address

ACQMEM 1000001AAAAAAAAA Acquire image AAAAAAAAA = Memory address

10


Table 1: AGIPD 1.0 Command Set — contd.


RPAMPN 1010PPPPPPMMMMMM (Pre-)Read analogue pixel row, PPPPPP = (Pre-)Read pixel rowno multiplexing MMMMMM = Mux’d pixel row (ignored)

RPAMPA 1011PPPPPPMMMMMM (Pre-)Read analogue pixel row, PPPPPP = (Pre-)Read pixel rowmultiplex analogue pixel row MMMMMM = Multiplexed pixel row

RPNMPA 1001PPPPPPMMMMMM No (Pre-)Read, PPPPPP = Read pixel row (ignored)multiplex analogue pixel row MMMMMM = Multiplexed pixel row

RPDMPN 1110PPPPPPMMMMMM (Pre-)Read gain pixel row, PPPPPP = (Pre-)Read pixel rowno multiplexing MMMMMM = Mux’d pixel row (ignored)

RPDMPD 1111PPPPPPMMMMMM (Pre-)Read gain pixel row, PPPPPP = (Pre-)Read pixel rowmultiplex gain pixel row MMMMMM = Multiplexed pixel row

RPNMPD 1101PPPPPPMMMMMM No (Pre-)Read, PPPPPP = Read pixel row (ignored)multiplex gain pixel row MMMMMM = Multiplexed pixel row

SETUPR 01000000RBBBBBBB Programm the setup register R = Reset, BBBBBBB = Register bits

RSDLYW 010000010VVVVVVV Memory row select delay (write) VVVVVVV = Delay in Clk cycles

RSGATW 010000011VVVVVVV Memory row select width (write) VVVVVVV = Width in Clk cycles

RSDLYR 010000100VVVVVVV Memory row select delay (read) VVVVVVV = Delay in Clk cycles

RPDLYW 010000110VVVVVVV Memory row precharge delay (write) VVVVVVV = Delay in Clk cycles

RPGATW 010000111VVVVVVV Memory row precharge width (write) VVVVVVV = Width in Clk cycles

RPDLYR 010001000VVVVVVV Memory row precharge delay (read) VVVVVVV = Delay in Clk cycles

CSDLYW 010001010VVVVVVV Memory column select delay (write) VVVVVVV = Delay in Clk cycles

CSGATW 010001011VVVVVVV Memory column select width (write) VVVVVVV = Width in Clk cycles

CSDLYR 010001100VVVVVVV Memory column select delay (read) VVVVVVV = Delay in Clk cycles

DS1DLY 010001110VVVVVVV CDS switch 1 delay VVVVVVV = Delay in Clk cycles

DS1GAT 010001111VVVVVVV CDS switch 1 width VVVVVVV = Width in Clk cycles

RSTDLY 010010000VVVVVVV Preamp reset switch delay VVVVVVV = Delay in Clk cycles

RSTGAT 010010001VVVVVVV Preamp reset switch width VVVVVVV = Width in Clk cycles

G1SDLY 010010010VVVVVVV Gain switch 1 delay VVVVVVV = Delay in Clk cycles

G1SGAT 010010011VVVVVVV Gain switch 1 width VVVVVVV = Width in Clk cycles

G2SDLY 010010100VVVVVVV Gain switch 2 delay VVVVVVV = Delay in Clk cycles

G2SGAT 010010101VVVVVVV Gain switch 2 width VVVVVVV = Width in Clk cycles

EGSDLY 010010110VVVVVVV External gain enable delay VVVVVVV = Delay in Clk cycles

EGSGAT 010010111VVVVVVV External gain enable width VVVVVVV = Width in Clk cycles

PXBDLY 010011000VVVVVVV Pixel buffer reset delay VVVVVVV = Delay in Clk cycles

TSTDLY 010011010VVVVVVV Test signal injection delay VVVVVVV = Delay in Clk cycles

TSTGAT 010011011VVVVVVV Test signal injection width VVVVVVV = Width in Clk cycles

MUXDIV 01010000VVVVVVVV Multiplexer clock divider VVVVVVVV = Clk divider -1

TIROWM 01010001BBBBBBBB Test signal injection row mask BBBBBBBB = Mask pattern

TICOLM 01010010BBBBBBBB Test signal injection column mask BBBBBBBB = Mask pattern

VRFCDS 01010011VVVVVVVV vref cds control voltage DAC VVVVVVVV = Register value

IBNPXB 01010100VVVVVVVV ibn pixbuf bias DAC VVVVVVVV = Register value

VRFPXB 01010101VVVVVVVV vref pixbuf control voltage DAC VVVVVVVV = Register value

VCAPXB 01010110VVVVVVVV vcascp pixbuf control voltage DAC VVVVVVVV = Register value

IBPCOL 01010111VVVVVVVV ibp colbuf bias DAC VVVVVVVV = Register value

IBNCOB 01011000VVVVVVVV ibn cob bias DAC VVVVVVVV = Register value

IBPCOB 01011001VVVVVVVV ibp cob bias DAC VVVVVVVV = Register value

IBNFDA 01011010VVVVVVVV ibn fda bias DAC VVVVVVVV = Register value

IBNPRB 01011011VVVVVVVV ibn prebuf bias DAC VVVVVVVV = Register value

IBPPRB 01011100VVVVVVVV ibp prebuf bias DAC VVVVVVVV = Register value

VCMCHB 01011101VVVVVVVV vcom chipbuf control voltage DAC VVVVVVVV = Register value

VCACHB 01011110VVVVVVVV vcasc chipbuf control voltage DAC VVVVVVVV = Register value

VRFCHB 01011111VVVVVVVV vref chipbuf control voltage DAC VVVVVVVV = Register value

IBNLVD 01100000VVVVVVVV ibn lvds bias DAC VVVVVVVV = Register value

IBPLVD 01100001VVVVVVVV ibp lvds bias DAC VVVVVVVV = Register value

11


Table 1: AGIPD 1.0 Command Set — contd.


ITESTC 01100010VVVVVVVV itest curr bias DAC VVVVVVVV = Register value

IBNCMP 01100100VVVVVVVV ibn comp bias DAC VVVVVVVV = Register value

VTHCMP 01100101VVVVVVVV vth comp control voltage DAC VVVVVVVV = Register value

IBPCDS 01100110VVVVVVVV ibp cds bias DAC VVVVVVVV = Register value

VPC1LO 01101001VVVVVVVV Pulsed Capacitor Voltage input LSB1 VVVVVVVV = Register value

VPC1HI 01101010VVVVVVVV Pulsed Capacitor Voltage input MSB1 VVVVVVVV = Register value

VPC2LO 01101011VVVVVVVV Pulsed Capacitor Voltage input LSB0 VVVVVVVV = Register value

VPC2HI 01101100VVVVVVVV Pulsed Capacitor Voltage input MSB0 VVVVVVVV = Register value

SWPXBI 01101101VVVVVVVV pixel bias switches VVVVVVVV = Register value

SWROBI 01101110VVVVVVVV readout bias switches VVVVVVVV = Register value

SWCALV 01101111VVVVVVVV calibration and LVDS bias switches VVVVVVVV = Register value

12


SETMEM 11

Description: Sets the internal memory address register. Since it does not trigger an acqui-sition or readout cycle, it can serve as a NOP (No Operation) command.

Format: 1000000AAAAAAAAA with A = AAAAAAAAA representing the 9-bit memory address.Adresses with A > 351 (A > 101011111) are ignored.

Timing:

Clk

Data

SoB

RST_PREAMPEN_EXT_GAINGAIN1_EXTGAIN2_EXTDS_SW1WRITEROW_PCHRST_PIXBUF

All others

Command execution

Dependencies:

Depends upon:-none-

Influences:RPAMPN , RPAMPA , RPNMPA , RPDMPN , RPDMPD , RPNMPD

11SETMEM is an acronym for SET MEMory address.

13


ACQMEM 12

Description: Acquire an image and store it at memory address M .

Format: 1000001AAAAAAAAA with A = AAAAAAAAA representing the 9-bit memory address.Adresses with A > 351 (A > 101011111) are ignored.

Timing:

Clk

Data

SoB

RST_PREAMP

EN_EXT_GAIN

GAIN1_EXT

GAIN2_EXT

DS_SW1

WRITE

ROW_PCH

ROW_SEL

COL_SEL

TEST_CURR /TEST_CAP

RST_PIXBUF

All others

Command execution

A

A

A

ß àRSTDLY+1 ß àRSTGAT+1

ß àEGSDLY+1 ß àEGSGAT+1

ß àG1SDLY+1 ß àG1SGAT+1

ß àG2SDLY+1 ß àG2SGAT+1

ß àDS1DLY+2 ß àDS1GAT+1

ß àRPDLYW+2 ß àRPGATW+1

ß àRSDLYW+2 ß àRSGATW+1

ß àCSDLYW+2 ß àCSGATW+1

ß àTSTDLY+1 ß àTSTGAT+1

Dependencies:

Depends upon:SETUPR , RSDLYW , RSGATW , RPDLYW ,RPGATW , CSDLYW , CSGATW , DS1DLY ,DS1GAT , RSTDLY , RSTGAT ,G1SDLY ,G1SGAT , G2SDLY , G2SGAT , EGSDLY , EGSGAT

Via SETUPR the following dependencies can be introduced:TSTDLY , TSTGAT , TIROWM , TICOLM

Influences:RPAMPN , RPAMPA , RPNMPA , RPDMPN ,RPDMPD , RPNMPD

12ACQMEM is an acronym for ACQuire image to MEMory address.

14


RPAMPN 13

Description: (Pre-)Read analogue data at memory address A from pixel row P and assertit to the column bus. No data from pixel row M is is multiplexed from the column bus to theoutside. Since all even pixel rows connect to one and all odd pixel rows to the other column bus,the pixel row addresses A and P should differ in their LSB.

Format: 1010PPPPPPMMMMMM with P = PPPPPP and M = MMMMMM representing the 6-bit pixelrow address to be read from the pixel and to be multiplexed off-chip. The RPAMPN command doesnot perform any multiplexing, in this respect M is ignored.

Timing:

Clk

Data

SoB

READ_A

ROW_PCH

ROW_SEL

COL_SEL

All others

Command execution

RST_PIXBUF

_A

_A

_A

RST_PREAMP /EN_EXT_GAIN /GAIN1_EXT /GAIN2_EXT /DS_SW1 /RST_PIXBUF

P

P

PA

PA

PA

¹

ß àPXBDLY+1

ß àRPDLYR+1

ß àRSDLYR+!

ß àCSDLYR+1

Dependencies:

Depends upon:SETMEM or ACQMEM , RSDLYR , RPDLYR ,CSDLYR , PXBDLY

Influences:-none-

13RPAMPN is an acronym for Read Pixel Analogue, MultiPlex None.

15


RPAMPA 14

Description: (Pre-)Read analogue data at memory address A from pixel row P and assertit to the column bus. Data from pixel row M is is multiplexed from the column bus to the outside.This data has to be asserted to the column bus in the immediately preceding command (i.e. M hadto be the A-argument of the immediately preceding RPAMPN or RPAMPA command). Since all evenpixel rows connect to one and all odd pixel rows to the other column bus, the pixel row addressesA and P must differ in their LSB, otherwise err is set and the command will not perform asexpected. It is in the responsibility of the programmer, to ensure that the command duration (interms of Clk-cycles) is greater or equal to 16× (MUXDIV+1) to prevent corruption of the read outdata.

Format: 1011PPPPPPMMMMMM with P = PPPPPP and M = MMMMMM representing the 6-bit pixelrow address to be read from the pixel and to be multiplexed off-chip.

Timing:

Clk

Data

SoB

READ_A

All others

Command execution

RST_PIXBUF

ROW_PCH_A

ROW_SEL_A

COL_SEL_A

ROW_PCH_A

ROW_SEL_A

COL_SEL_A

MUX_Clk

MUX_Token


P

PA

PA

PA

MA

MA

MA

PvM¹

ß àPXBDLY+1

ß àRPDLYR+1

ß àRSDLYR+1

ß àCSDLYR+1

ß àMUXDIV+1

14RPNMPA is an acronym for Read Pixel Analogue, MultiPlex out Analogue.

16


Dependencies:

Depends upon:SETMEM or ACQMEM , RSDLYR , RPDLYR ,CSDLYR , PXBDLY , MUXDIV

Influences:-none-

17


RPNMPA 15

Description: No analogue data from pixel row P is assert to the column bus. Data atmemory address A from pixel row M is is multiplexed from the column bus to the outside. Thisdata has to be asserted to the column bus in the immediately preceding command (i.e. M hadto be the A-argument of the immediately preceding RPAMPN or RPAMPA command). Since all evenpixel rows connect to one and all odd pixel rows to the other column bus, the pixel row addressesA and P should differ in their LSB. It is in the responsibility of the programmer, to ensure thatthe command duration (in terms of Clk-cycles) is greater or equal to 16× (MUXDIV+1) to preventcorruption of the read out data.

Format: 1001PPPPPPMMMMMM with P = PPPPPP and M = MMMMMM representing the 6-bit pixelrow address to be read from the pixel and to be multplexed off-chip. The RPNMPA command doesnot perform any (pre-)reading, in this respect P is ignored.

Timing:

Clk

Data

SoB

READ_A

All others

Command execution

ROW_PCH_A

ROW_SEL_A

COL_SEL_A

MUX_Clk

MUX_Token


MA

MA

MA

PvM¹

ß àMUXDIV+1

Dependencies:

Depends upon:SETMEM or ACQMEM , MUXDIV

15RPNMPA is an acronym for Read Pixel None, MultiPlex out Analogue.

18


Influences:-none-

19


RPDMPN 16

Description: (Pre-)Read gain (digital) data at memory address A from pixel row P andassert it to the column bus. No data from pixel row M is is multiplexed from the column bus tothe outside. Since all even pixel rows connect to one and all odd pixel rows to the other columnbus, the pixel row addresses A and P should differ in their LSB.

Format: 1110PPPPPPMMMMMM with P = PPPPPP and M = MMMMMM representing the 6-bit pixelrow address to be read from the pixel and to be multiplexed off-chip. The RPAMPN command doesnot perform any multiplexing, in this respect M is ignored.

Timing:

Clk

Data

SoB

READ_D

ROW_PCH

ROW_SEL

COL_SEL

All others

Command execution

RST_PIXBUF

_D

_D

_D


P

P

PA

PA

PA

¹

ß àPXBDLY+1

ß àRPDLYR+1

ß àRSDLYR+1

ß àCSDLYR+1

Dependencies:

Depends upon:SETMEM or ACQMEM , RSDLYR , RPDLYR ,CSDLYR , PXBDLY

Influences:-none-

16RPDMPN is an acronym for Read Pixel Digital (gain), MultiPlex None.

20


RPDMPD 17

Description: (Pre-)Read gain (digital) data at memory address A from pixel row P andassert it to the column bus. Data from pixel row M is is multiplexed from the column bus to theoutside. This data has to be asserted to the column bus in the immediately preceding command(i.e. M had to be the A-argument of the immediately preceding RPDMPN or RPDMPD command).Since all even pixel rows connect to one and all odd pixel rows to the other column bus, the pixelrow addresses A and P must differ in their LSB, otherwise err is set and the command will notperform as expected. It is in the responsibility of the programmer, to ensure that the commandduration (in terms of Clk-cycles) is greater or equal to 16× (MUXDIV+1) to prevent corruption ofthe read out data.

Format: 1111PPPPPPMMMMMM with P = PPPPPP and M = MMMMMM representing the 6-bit pixelrow address to be read from the pixel and to be multplexed off-chip.

Timing:

Clk

Data

SoB

READ_D

All others

Command execution

RST_PIXBUF

ROW_PCH_D

ROW_SEL_D

COL_SEL_D

ROW_PCH_D

ROW_SEL_D

COL_SEL_D

MUX_Clk

MUX_Token


P

PA

PA

PA

MA

MA

MA

PvM¹

ß àPXBDLY+1

ß àRPDLYR+1

ß àRSDLYR+1

ß àCSDLYR+1

ß àMUXDIV+1

17RPDMPD is an acronym for Read Pixel Digital (gain), MultiPlex out Digital (gain).

21


Dependencies:

Depends upon:SETMEM or ACQMEM , RSDLYR , RPDLYR ,CSDLYR , PXBDLY , MUXDIV

Influences:-none-

22


RPNMPD 18

Description: No gain (digital) data from pixel row P is assert to the column bus. Data atmemory address A from pixel row M is is multiplexed from the column bus to the outside. Thisdata has to be asserted to the column bus in the immediately preceding command (i.e. M hadto be the A-argument of the immediately preceding RPDMPN or RPDMPD command). Since all evenpixel rows connect to one and all odd pixel rows to the other column bus, the pixel row addressesA and P should differ in their LSB. It is in the responsibility of the programmer, to ensure thatthe command duration (in terms of Clk-cycles) is greater or equal to 16× (MUXDIV+1) to preventcorruption of the read out data.

Format: 1101PPPPPPMMMMMM with P = PPPPPP and M = MMMMMM representing the 6-bit pixelrow address to be read from the pixel and to be multplexed off-chip. The RPNMPD command doesnot perform any (pre-)reading, in this respect P is ignored.

Timing:

Clk

Data

SoB

READ_A

All others

Command execution

ROW_PCH_D

ROW_SEL_D

COL_SEL_D

MUX_Clk

MUX_Token


MA

MA

MA

PvM¹

ß àMUXDIV+1

Dependencies:

Depends upon:SETMEM or ACQMEM , MUXDIV

18RPNMPD is an acronym for Read Pixel None, MultiPlex out Digital (gain).

23


Influences:-none-

24


SETUPR 19

Description: Configures the chip via the internal setup register.

Bit 7 reset – resets all on-chip timing registers, DACs and configuration settings except for thestatus register bits.

Bit 6 error – set and reset the error flag signalling incompatible (i.e. both even or both odd)row addresses for readout.

Bit 5 test cap enables test charge injection to the pixel(s) selected by TICOLM and TIROWM viaa pulsed capacitor.

Bit 4 test curr enables test charge injection to the pixel(s) selected by TICOLM and TIROWM viaa (constant) current source.

Bit 3 ds gain selects the gain of the CDS stage inside each pixel.

Bit 2 en ext gain sets the preamplifier gain to the gains selected by set gain1 and set gain2.This bit overrides the timed en ext gain signal defined by EGSDLY and EGSGAT. If set,AGIPD 1.0 will not encode the selected gain, but always record gain=high in the imagedata.

Bit 1 set gain1 sets the preamplifier into medium gain mode by connecting the 2nd feedbackcapacitor, if en ext gain is high. This bit overrides the timed set gain1 signal defined byG1SDLY and G1SGAT.

Bit 0 set gain2 sets the preamplifier into low gain mode by connecting the 3rd feedback ca-pacitor, if en ext gain is high. This bit overrides the timed set gain2 signal defined byG2SDLY and G2SGAT.

Format: 01000000RBBBBBBB with R = reset and BBBBBBB representing the seven configu-ration bits.

Timing:

Clk

Data

SoB


All others

Command execution

19SETUPR is an acronym for write SETUP Register.

25


Dependencies:

Depends upon:-none-

Influences:ACQMEM , RSDLYW , RSGATW , RSDLYR , RSGATR , RPDLYW , RPGATW , RPDLYR , CSDLYW , CSGATW , CSDLYR ,DS1DLY , DS1GAT , RSTDLY , RSTGAT , G1SDLY , G1SGAT , G2SDLY , G2SGAT , EGSDLY , EGSGAT , PXBDLY ,TSTDLY , TSTGAT , MUXDIV , TIROWM , TICOLM , VRFCDS , IBNPXB , VRFPXB , VCAPXB , IBPCOL , IBNCOB ,IBPCOB , IBNFDA , IBNPRB , IBPPRB , VCMCHB , VCACHB , VRFCHB , IBNLVD , IBPLVD , ITESTC , REG019IBNCMP , VTHCMP , IBPCDS , REG023 , REG024 , VPC1LO , VPC1HI , VPC2LO , VPC2HI , SWPXBI , SWROBI ,SWCALV

26


RSDLYW 20

Description: Sets the delay of the row selection for memory access during ACQMEM , i.e. framecapture.

Format: 010000010VVVVVVV with V = VVVVVVV representing the 7-bit delay in Clk cycles.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:ACQMEM

20RSDLYW is an acronym for Row Select DeLaY for Write access

27


RSGATW 21

Description: Sets the duration of the row selection for memory access during ACQMEM , i.e.frame capture.

Format: 010000010VVVVVVVwith V = VVVVVVV representing the 7-bit duration in Clk cycles.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:ACQMEM

21RSGATW is an acronym for Row Select GATe for Write access

28


RSDLYR 22

Description: Sets the delay of the row selection for memory access during RPAMPN , RPAMPA ,RPDMPN , RPDMPD , i.e. pre-read phase of a pixel row readout.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:RPAMPN , RPAMPA , RPDMPN , RPDMPD

22RSDLYR is an acronym for Row Select DeLaY for Read access

29


RPDLYW 23

Description: Sets the delay of the row line precharge for memory access during ACQMEM , i.e.frame capture. For an effective precharging of the lines, RPDLYW < RSDLYW should be chosen.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:ACQMEM

23RPDLYW is an acronym for Row Precharge DeLaY for Write access

30


RPGATW 24

Description: Sets the duration of the row line precharge for memory access during ACQMEM ,i.e. frame capture. For an effective precharging of the lines, RPDLYW+ RPGATW ≥ RSDLYW+ RSGATW

should be chosen.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:ACQMEM

24RPGATW is an acronym for Row Precharge GATe for Write access

31


RPDLYR 25

Description: Sets the delay of the row line precharge for memory access during RPAMPN ,RPAMPA , RPDMPN , RPDMPD , i.e. pre-read phase of a pixel row readout. For an effective prechargingof the lines, RPDLYR < RSDLYP should be chosen.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-


25RPDLYR is an acronym for Row Precharge DeLaY for Read access

32


CSDLYW 26

Description: Sets the delay of the column selection for memory access during ACQMEM , i.e.frame capture.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:ACQMEM

26CSDLYW is an acronym for Column Select DeLaY for Write access

33


CSGATW 27

Description: Sets the duration of the column selection for memory access during ACQMEM ,i.e. frame capture.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:ACQMEM

27CSGATW is an acronym for Column Select GATe for Write access

34


CSDLYR 28

Description: Sets the delay of the column selection for memory access during RPAMPN ,RPAMPA , RPDMPN , RPDMPD ,i.e. pre-read phase of a pixel row readout.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-


28CSDLYR is an acronym for Column Select DeLaY for Read access

35


DS1DLY 29

Description: Sets the delay for the the start of the integration interval of the CDS stage,i.e. the position of the 1st (reference/baseline) sample.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:ACQMEM

29DS1DLY is an acronym for Double-Sampling switch 1 DeLaY

36


DS1GAT 30

Description: Sets the duration of the integration interval of the CDS stage. The position ofthe 2nd (signal) sample is given by the disconnection of the memmory cell, i.e. (DS1DLY+DS1GAT) >min((CSDLYW+ CSGATW), (RSDLYW+ RSGATW), (RPDLYW+ RPGATW)) should be chosen.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:ACQMEM

30DS1GAT is an acronym for Double-Sampling switch 1 GATe

37


RSTDLY 31

Description: Sets the delay for the the start of the integration interval of the preamplifierstage, i.e. the start of the charge integration.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:ACQMEM

31RSTDLY is an acronym for preamplifier ReSeT switch DeLaY

38


RSTGAT 32

Description: Sets the duration of the integration interval of the preamplifier stage, i.e.of the charge integration. It should extend beyond the position of the 2nd CDS sample, i.e.(RSTDLY+ RSTGAT) > min((CSDLYW+ CSGATW), (RSDLYW+ RSGATW), (RPDLYW+ RPGATW)) should bechosen.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:ACQMEM

32RSTGAT is an acronym for preamplifier ReSeT switch GATe

39


G1SDLY 33

Description: Sets the delay of set gain1 being removed during ACQMEM. set gain1 sets thepreamplifier into medium gain mode by connecting the 2nd feedback capacitor, if en ext gain ishigh. The set gain1 bit in the status register overrides the timed set gain1 signal defined byG1SDLY and G1SGAT. Timing should closely match RSTDLY.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SETUPR

Influences:ACQMEM

33GS1DLY is an acronym for preamplifier Gain 1 Switch DeLaY

40


G1SGAT 34

Description: Sets the duration for which set gain1 is being removed during ACQMEM. set gain1

sets the preamplifier into medium gain mode by connecting the 2nd feedback capacitor, if en ext gain

is high. The set gain1 bit in the status register overrides the timed set gain1 signal defined byG1SDLY and G1SGAT. Timing should closely match RSTDLY.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SETUPR

Influences:ACQMEM

34GS1DLY is an acronym for preamplifier Gain 1 Switch GATe

41


G2SDLY 35

Description: Sets the delay of set gain2 being removed during ACQMEM. set gain2 setsthe preamplifier into low gain mode by connecting the 3rd feedback capacitor, if en ext gain ishigh. The set gain1 bit in the status register overrides the timed set gain2 signal defined byG2SDLY and G2SGAT. Timing should closely match RSTDLY.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SETUPR

Influences:ACQMEM

35GS1DLY is an acronym for preamplifier Gain 2 Switch DeLaY

42


G2SGAT 36

Description: Sets the duration for which set gain2 is being removed during ACQMEM. set gain1

sets the preamplifier into low gain mode by connecting the 3rd feedback capacitor, if en ext gain

is high. The set gain1 bit in the status register overrides the timed set gain1 signal defined byG2SDLY and G2SGAT. Timing should closely match RSTDLY.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SETUPR

Influences:ACQMEM

36GS2DLY is an acronym for preamplifier Gain 2 Switch GATe

43


EGSDLY 37

Description: Sets the delay of en ext gain signal being removed during ACQMEM. en ext gain

facilitates the preamplifier to be set into medium or low gain mode by enabling the set gain1 andset gain2 signals. The en ext gain bit in the status register overrides the timed en ext gain

signal defined by EGSDLY and EGSGAT. Timing should closely match RSTDLY.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SETUPR

Influences:ACQMEM

37EGSDLY is an acronym for preamplifier External Gain Set DeLaY

44


EGSGAT 38

Description: Sets the duration for which the en ext gain signal is removed during ACQMEM.en ext gain facilitates the preamplifier to be set into medium or low gain mode by enabling theset gain1 and set gain2 signals. The en ext gain bit in the status register overrides the timeden ext gain signal defined by EGSDLY and EGSGAT. Timing should closely match RSTDLY.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SETUPR

Influences:ACQMEM

38EGSGAT is an acronym for preamplifier External Gain Set GATe

45


PXBDLY 39

Description: Sets the delay after which the the integration interval of the pixel readoutbuffer starts during (pre-)readout.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-


39PXBDLY is an acronym for PiXel readout Buffer reset DeLaY.

46


TSTDLY 40

Description: Sets the time, after which a test current is injected into the pixel, if thetest curr in the staus register is set. TSTDLY also defines the position of the rising edge ofthe test pule applied to a charge injection capacitor, if the test cap bit in the status register isset. A test signal is only injected to the pixel pattern selected by TICOLM and TIROWM.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SETUPR , TICOLM , TIROWM

Influences:ACQMEM

40TSTDLY is an acronym for TeST signal injection DeLay.

47


TSTGAT 41

Description: Sets the duration for which a test current is injected into the pixel, if thetest curr in the staus register is set. TSTDLY+ TSTGAT defines the position of the falling edge ofthe test pule applied to a charge injection capacitor, if the test cap bit in the status register isset. A test signal is only injected to the pixel pattern selected by TICOLM and TIROWM.


Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SETUPR , TICOLM , TIROWM

Influences:ACQMEM

41TSTGAT is an acronym for TeST signal injection GATe.

48


MUXDIV 42

Description: Sets the ratio between the system Clk and the readout Clock MUX Clk. Itis f(MUXClk) = f(Clk)/(MUXDIV + 1). In turn the length of the influenced commands is 16 ×(MUXDIV+ 1) Clk cycles in order to read all 16 pixel columns connected to one output port.

Format: 01010000VVVVVVVVwith V = VVVVVVVV representing the 8-bit Clk-to-MUX Clk ratio-1.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:-none-

Influences:RPAMPA , RPNMPA , RPDMPD , RPNMPD

42MUXDIV is an acronym for readout MUltipleXer clock DIVider.

49


TIROWM 43

Description: The pixel matrix is divided in 8× 8 submatrices of 8× 8 pixels. Pixels for testcharge injection are selected by a logic AND of the corresponding row and column bits in eachsubmatrix. TIROWM sets the pixel row mask. Thus test charge injection will happen into 64×n×mpixels, where m and n are the number of set bits in TIROWM and TICOLM respectively.

Format: 01010001BBBBBBBBwith B = BBBBBBBB representing the 8-bit pattern of pixel rowsfor test charge injection.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SETUPR

Influences:ACQMEM

43TIROWM is an acronym for Test signal Injection ROW Mask.

50


TICOLM 44

Description: The pixel matrix is divided in 8 × 8 submatrices of 8 × 8 pixels. Pixels fortest charge injection are selected by a logic AND of the corresponding row and column bits ineach submatrix. TICOLM sets the pixel column mask. Thus test charge injection will happen into64× n×m pixels, where m and n are the number of set bits in TIROWM and TICOLM respectively.

Format: 01010010BBBBBBBB with B = BBBBBBBB representing the 8-bit pattern of pixelcolumn for test charge injection.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SETUPR

Influences:ACQMEM

VRFCDS

44TICOLM is an acronym for Test signal Injection COLumn Mask.

51


VRFCDS 45

Description: Set DAC output value to bias vref cds.

Format: 01010011 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for vref cds (0.55V), a value of 0’b01110000 (112) is to beinserted into this register. If the bias needs to be set a different value refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWPXBI (pixel bias switch) must be set.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWPXBI

45VRFCDS is an acronym for the vref cds DAC setting

52


IBNPXB 46

Description: Set DAC output value to bias ibn pixbuf.

Format: 01010100 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for ibn pixbuf (20µA), a value of 0’b10000000 [128] is to beinserted into this register. If the bias needs to be set a different value refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor coming from the external pad), the appropriate bit in SWPXBI (pixel bias switch) must be set.If the external pad is used (istead of the internal DAC) to bias the circuit, the relation betweenthe external applied current and the biasing current is reported in the third column of the table

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWPXBI

46IBNPXB is an acronym for the ibn pixbuf DAC setting

53


VRFPXB 47

Description: Set DAC output value to bias vref pixbuf.

Format: 01010101 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for vref pixbuf (0.85V), a value of 0’b10100111 [167] is to beinserted into this register. If you need to apply different bias values refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (coming from the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWPXBI (pixel bias switch) must be set.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWPXBI

47VRFPXB is an acronym for the vref pixbuf DAC setting

54


VCAPXB 48

Description: Set DAC output value to bias vcascp pixbuf.

Format: 01010110 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for vcascp pixbuf (1V), a value of 0’b11000001 [193] is to beinserted into this register. If you need to apply different bias values refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWPXBI (pixel bias switch) must be set.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWPXBI

48VCAPXB is an acronym for the vcascp pixbuf DAC setting

55


IBPCOL 49

Description: Set DAC output value to bias ibp colbuf.

Format: 01010111 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for ibp colbuf (100µA), a value of 0’b10010101 [149] is to beinserted into this register. If you need to apply different bias values refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWPXBI (pixel bias switch) must be set.If the external pad is used (istead of the internal DAC) to bias the circuit, the relation betweenthe external applied current and the biasing current is reported in the third column of the table

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWPXBI

49IBPCOL is an acronym for the ibp colbuf DAC setting

56


IBNCOB 50

Description: Set DAC output value to bias ibn cob.

Format: 01011000 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for ibn cob (150µA), a value of 0’b10111000 [184] is to beinserted into this register. If you need to apply different bias values refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWROBI (readout bias switch) must be set.If the external pad is used (istead of the internal DAC) to bias the circuit, the relation betweenthe external applied current and the biasing current is reported in the third column of the table

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWROBI

50IBNCOB is an acronym for the ibn cob DAC setting

57


IBPCOB 51

Description: Set DAC output value to bias ibp cob.

Format: 01011001 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for ibp cob (150µA), a value of 0’b01100110 [102] is to beinserted into this register. If you need to apply different bias values refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWROBI (readout bias switch) must be set.If the external pad is used (istead of the internal DAC) to bias the circuit, the relation betweenthe external applied current and the biasing current is reported in the third column of the table

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWROBI

51IBPCOB is an acronym for the ibp cob DAC setting

58


IBNFDA 52

Description: Set DAC output value to bias ibn fda.

Format: 01011010 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for ibn fda (150µA), a value of 0’b10100000 [160] is to beinserted into this register. If you need to apply different bias values refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWROBI (readout bias switch) must be set.If the external pad is used (istead of the internal DAC) to bias the circuit, the relation betweenthe external applied current and the biasing current is reported in the third column of the table

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWROBI

52IBNFDA is an acronym for the ibn fda DAC setting

59


IBNPRB 53

Description: Set DAC output value to bias ibn prebuf.

Format: 01011011 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for ibn prebuf (30µA), a value of 0’b01011111 [95] is to beinserted into this register. If you need to apply different bias values refer to table 3. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWROBI (readout bias switch) must be set.If the external pad is used (istead of the internal DAC) to bias the circuit, the relation betweenthe external applied current and the biasing current is reported in the third column of the table

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWROBI

53IBNPRB is an acronym for the ibn prebuf DAC setting

60


IBPPRB 54

Description: Set DAC output value to bias ibp prebuf .

Format: 01011100 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for ibp prebuf (30µA), a value of 0’b01100010 [98] is to beinserted into this register. If you need to apply different bias values refer to table 3. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWROBI (readout bias switch) must be set.If the external pad is used (istead of the internal DAC) to bias the circuit, the relation betweenthe external applied current and the biasing current is reported in the third column of the table

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWROBI

54IBPPRB is an acronym for the ibp prebuf DAC setting

61


VCMCHB 55

Description: Set DAC output value to bias vcom chipbuf.

Format: 01011101 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for vcom chipbuf (0.75V), a value of 0’b10010100 [148] is to beinserted into this register. If you need to apply different bias values refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor coming from the external pad), the appropriate bit in SWROBI (pixel bias switch) must be set.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWROBI

55VCMCHB is an acronym for the vcom chipbuf DAC setting

62


VCACHB 56

Description: Set DAC output value to bias vcasc chipbuf.

Format: 01011110 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for vcasc chipbuf (0.45V), a value of 0’b01011101 [93] is to beinserted into this register. If you need to apply different bias values refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor coming from the external pad), the appropriate bit in SWROBI (pixel bias switch) must be set.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWROBI

56VCACHB is an acronym for the vcasc chipbuf DAC setting

63


VRFCHB 57

Description: Set DAC output value to bias vref chipbuf.

Format: 01011111 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for vref chipbuf (0.8V), a value of 0’b10110100 [180] is to beinserted into this register. If you need to apply different bias values refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor coming from the external pad), the appropriate bit in SWROBI (pixel bias switch) must be set.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWROBI

57VRFCHB is an acronym for the vref chipbuf DAC setting

64


IBNLVD 58

Description: Set DAC output value to bias ibn lvds.

Format: 01100000 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for ibn lvds (178µA), a value of 0’b10101011 [171] is to beinserted into this register. If you need to apply different bias values refer to table 3. Noticethat this command only make the internal DAC to generate the analogue value: it does not passthe generated analogue value to the AGIPD core. Either this internal-DAC-generated analoguevalue could be passed to the AGIPD core, or an external output (applied to the appropriateexternal pad) could be passed to the AGIPD core. In order to define which one is used (internallygenerated or applied to the external pad), the appropriate bit in SWCALV (calibration and LVDSbias switch) must be set. If the external pad is used (istead of the internal DAC) to bias thecircuit, the relation between the external applied current and the biasing current is reported inthe third column of the table. The PowerUp Reset circuit should guarantee that at startup thebits in the registers are set to ”10000000” [128] (which, even if it is not the nominal bias, is enoughto have the the lvds working)

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWCALV

58IBNLVD is an acronym for the ibn lvds DAC setting

65


IBPLVD 59

Description: Set DAC output value to bias ibp lvds.

Format: 01100001 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value forthe DAC. In order to get nominal bias for ibp lvds (37µA), a value of 0’b11001010 [202] is tobe inserted into this register. If you need to apply different bias values refer to table 3. Noticethat this command only make the internal DAC to generate the analogue value: it does not passthe generated analogue value to the AGIPD core. Either this internal-DAC-generated analoguevalue could be passed to the AGIPD core, or an external output (applied to the appropriateexternal pad) could be passed to the AGIPD core. In order to define which one is used (internallygenerated or applied to the external pad), the appropriate bit in SWCALV (calibration and LVDSbias switch) must be set. If the external pad is used (istead of the internal DAC) to bias thecircuit, the relation between the external applied current and the biasing current is reported inthe third column of the table. The PowerUp Reset circuit should guarantee that at startup thebits in the registers are set to ”10000000” [128] (which, even if it is not the nominal bias, is enoughto have the the lvds working)

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWCALV

59IBPLVD is an acronym for the ibp lvds DAC setting

66


ITESTC 60

Description: Set DAC output value to define itest curr (current injector calibration circuit).

Format: 01100010 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal value for itest curr (1µA), a value of 0’b10010111 [151] is to beinserted into this register. If you need to apply different bias values refer to table 3. Noticethat this command only make the internal DAC to generate the analogue value: it does not passthe generated analogue value to the AGIPD core. Either this internal-DAC-generated analoguevalue could be passed to the AGIPD core, or an external output (applied to the appropriateexternal pad) could be passed to the AGIPD core. In order to define which one is used (internallygenerated or applied to the external pad), the appropriate bit in SWCALV (calibration and LVDSbias switch) must be set. If the external pad is used (istead of the internal DAC) to bias thecircuit, the relation between the external applied current and the biasing current is reported inthe third column of the table

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWCALV

60ITESTC is an acronym for the itest curr DAC setting

67


IBNCMP 61

Description: Set DAC output value to bias ibn comp.

Format: 01100100 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for ibn comp (18µA), a value of 0’b10001011 [139] is to beinserted into this register. If you need to apply different bias values refer to table 3. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWPXBI (pixel bias switch) must be set.If the external pad is used (istead of the internal DAC) to bias the circuit, the relation betweenthe external applied current and the biasing current is reported in the third column of the table

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWPXBI

61IBNCMP is an acronym for the ibn comp DAC setting

68


VTHCMP 62

Description: Set DAC output value to set vth comp.

Format: 01100101 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for vth comp (0.55V), a value of 0’b01110000 [112] is to beinserted into this register. If you need to apply different bias values refer to table 2. Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWPXBI (pixel bias switch) must be set.

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWPXBI

62VTHCMP is an acronym for the vth comp DAC setting

69


IBPCDS 63

Description: Set DAC output value to bias ibp cds.

Format: 01100110 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. In order to get nominal bias for ibp cds (100µA), a value of 0’b11010011 [211] is to beinserted into this register. If you need to apply different bias values refer to table 3 . Notice thatthis command only make the internal DAC to generate the analogue value: it does not pass thegenerated analogue value to the AGIPD core. Either this internal-DAC-generated analogue valuecould be passed to the AGIPD core, or an external output (applied to the appropriate externalpad) could be passed to the AGIPD core. In order to define which one is used (internally generatedor applied to the external pad), the appropriate bit in SWPXBI (pixel bias switch) must be set.If the external pad is used (istead of the internal DAC) to bias the circuit, the relation betweenthe external applied current and the biasing current is reported in the third column of the table

Timing:

Clk

Data

SoB


All others

Command execution

Dependencies:

Depends upon:SWPXBI

63IBPCDS is an acronym for the ibp cds DAC setting

70


Table 2: AGIPD 1.0 & AGIPD 1.1 Bias DACs (1).

DAC Value Output Voltage [V] Bias Current [A]

vref cds ibn pixbuf ibp colbuf ibn cob ibn fda ibp cob

vref pixbuf

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vcom chipbuf

vcasc chipbuf

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vth comp

0 0.01 2.64E-008 1.64E-004 4.25E-009 1.19E-007 2.24E-004

1 0.01 2.61E-008 1.64E-004 4.33E-009 1.21E-007 2.24E-004

2 0.01 2.66E-008 1.64E-004 4.41E-009 1.23E-007 2.24E-004

3 0.01 2.72E-008 1.64E-004 4.50E-009 1.25E-007 2.24E-004

4 0.02 2.78E-008 1.64E-004 4.61E-009 1.28E-007 2.24E-004

5 0.02 2.85E-008 1.64E-004 4.72E-009 1.31E-007 2.24E-004

6 0.02 2.92E-008 1.63E-004 4.86E-009 1.35E-007 2.24E-004

7 0.02 3.01E-008 1.63E-004 5.00E-009 1.39E-007 2.24E-004

8 0.02 3.11E-008 1.63E-004 5.16E-009 1.43E-007 2.23E-004

9 0.03 3.21E-008 1.63E-004 5.35E-009 1.48E-007 2.23E-004

10 0.03 3.33E-008 1.63E-004 5.55E-009 1.54E-007 2.23E-004

11 0.03 3.47E-008 1.63E-004 5.78E-009 1.60E-007 2.23E-004

12 0.03 3.62E-008 1.63E-004 6.04E-009 1.67E-007 2.23E-004

13 0.04 3.78E-008 1.63E-004 6.33E-009 1.74E-007 2.22E-004

14 0.04 3.97E-008 1.63E-004 6.65E-009 1.83E-007 2.22E-004

15 0.04 4.18E-008 1.63E-004 7.01E-009 1.93E-007 2.22E-004

16 0.05 4.42E-008 1.62E-004 7.42E-009 2.04E-007 2.22E-004

17 0.05 4.69E-008 1.62E-004 7.88E-009 2.16E-007 2.21E-004

18 0.05 4.99E-008 1.62E-004 8.41E-009 2.30E-007 2.21E-004

19 0.06 5.33E-008 1.62E-004 9.00E-009 2.46E-007 2.21E-004

20 0.06 5.72E-008 1.62E-004 9.67E-009 2.63E-007 2.20E-004

21 0.07 6.16E-008 1.62E-004 1.04E-008 2.83E-007 2.20E-004

22 0.07 6.65E-008 1.61E-004 1.13E-008 3.06E-007 2.20E-004

23 0.07 7.22E-008 1.61E-004 1.23E-008 3.32E-007 2.19E-004

24 0.08 7.86E-008 1.61E-004 1.35E-008 3.62E-007 2.19E-004

25 0.08 8.60E-008 1.61E-004 1.48E-008 3.96E-007 2.18E-004

26 0.09 9.44E-008 1.60E-004 1.63E-008 4.35E-007 2.18E-004

27 0.09 1.04E-007 1.60E-004 1.81E-008 4.80E-007 2.17E-004

28 0.1 1.15E-007 1.60E-004 2.01E-008 5.31E-007 2.17E-004

29 0.1 1.28E-007 1.60E-004 2.25E-008 5.90E-007 2.16E-004

30 0.11 1.42E-007 1.59E-004 2.52E-008 6.57E-007 2.16E-004

31 0.11 1.59E-007 1.59E-004 2.84E-008 7.35E-007 2.15E-004

32 0.12 1.78E-007 1.59E-004 3.21E-008 8.24E-007 2.14E-004

33 0.12 2.00E-007 1.58E-004 3.64E-008 9.25E-007 2.14E-004

34 0.13 2.25E-007 1.58E-004 4.14E-008 1.04E-006 2.13E-004

35 0.13 2.54E-007 1.57E-004 4.74E-008 1.18E-006 2.12E-004

36 0.14 2.87E-007 1.57E-004 5.43E-008 1.33E-006 2.12E-004

37 0.14 3.24E-007 1.57E-004 6.24E-008 1.50E-006 2.11E-004

38 0.15 3.67E-007 1.56E-004 7.20E-008 1.70E-006 2.10E-004

39 0.15 4.15E-007 1.56E-004 8.32E-008 1.92E-006 2.09E-004

40 0.16 4.68E-007 1.55E-004 9.64E-008 2.18E-006 2.08E-004

41 0.16 5.29E-007 1.55E-004 1.12E-007 2.46E-006 2.08E-004

42 0.17 5.96E-007 1.55E-004 1.30E-007 2.78E-006 2.07E-004

43 0.17 6.71E-007 1.54E-004 1.51E-007 3.13E-006 2.06E-004

44 0.18 7.53E-007 1.54E-004 1.76E-007 3.51E-006 2.05E-004

45 0.18 8.43E-007 1.53E-004 2.05E-007 3.94E-006 2.04E-004

71


Table 2: AGIPD 1.0 & AGIPD 1.1 Bias DACs (1) — contd.



vref pixbuf

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46 0.19 9.41E-007 1.53E-004 2.39E-007 4.41E-006 2.03E-004

47 0.19 1.05E-006 1.52E-004 2.79E-007 4.91E-006 2.02E-004

48 0.2 1.16E-006 1.52E-004 3.25E-007 5.45E-006 2.02E-004

49 0.2 1.28E-006 1.51E-004 3.78E-007 6.04E-006 2.01E-004

50 0.21 1.42E-006 1.51E-004 4.40E-007 6.66E-006 2.00E-004

51 0.22 1.55E-006 1.50E-004 5.12E-007 7.33E-006 1.99E-004

52 0.22 1.70E-006 1.50E-004 5.94E-007 8.03E-006 1.98E-004

53 0.23 1.85E-006 1.49E-004 6.89E-007 8.77E-006 1.97E-004

54 0.23 2.01E-006 1.49E-004 7.98E-007 9.54E-006 1.96E-004

55 0.24 2.18E-006 1.48E-004 9.21E-007 1.04E-005 1.95E-004

56 0.24 2.35E-006 1.48E-004 1.06E-006 1.12E-005 1.94E-004

57 0.25 2.53E-006 1.47E-004 1.22E-006 1.21E-005 1.93E-004

58 0.25 2.72E-006 1.47E-004 1.40E-006 1.30E-005 1.92E-004

59 0.26 2.91E-006 1.46E-004 1.60E-006 1.39E-005 1.92E-004

60 0.26 3.10E-006 1.46E-004 1.82E-006 1.48E-005 1.91E-004

61 0.27 3.30E-006 1.45E-004 2.07E-006 1.58E-005 1.90E-004

62 0.28 3.51E-006 1.45E-004 2.34E-006 1.68E-005 1.89E-004

63 0.28 3.71E-006 1.44E-004 2.65E-006 1.78E-005 1.88E-004

64 0.29 3.92E-006 1.44E-004 2.97E-006 1.89E-005 1.87E-004

65 0.29 4.14E-006 1.43E-004 3.33E-006 1.99E-005 1.86E-004

66 0.3 4.35E-006 1.43E-004 3.72E-006 2.10E-005 1.85E-004

67 0.3 4.58E-006 1.42E-004 4.14E-006 2.21E-005 1.84E-004

68 0.31 4.80E-006 1.42E-004 4.59E-006 2.32E-005 1.83E-004

69 0.31 5.03E-006 1.41E-004 5.07E-006 2.43E-005 1.82E-004

70 0.32 5.26E-006 1.41E-004 5.59E-006 2.55E-005 1.81E-004

71 0.32 5.49E-006 1.40E-004 6.13E-006 2.67E-005 1.80E-004

72 0.33 5.73E-006 1.40E-004 6.71E-006 2.78E-005 1.79E-004

73 0.34 5.96E-006 1.39E-004 7.32E-006 2.90E-005 1.78E-004

74 0.34 6.20E-006 1.39E-004 7.95E-006 3.02E-005 1.77E-004

75 0.35 6.44E-006 1.38E-004 8.62E-006 3.14E-005 1.76E-004

76 0.35 6.69E-006 1.38E-004 9.31E-006 3.26E-005 1.75E-004

77 0.36 6.93E-006 1.37E-004 1.00E-005 3.39E-005 1.74E-004

78 0.36 7.18E-006 1.37E-004 1.08E-005 3.51E-005 1.73E-004

79 0.37 7.42E-006 1.36E-004 1.16E-005 3.63E-005 1.73E-004

80 0.37 7.67E-006 1.36E-004 1.24E-005 3.76E-005 1.72E-004

81 0.38 7.92E-006 1.35E-004 1.32E-005 3.89E-005 1.71E-004

82 0.38 8.17E-006 1.35E-004 1.40E-005 4.01E-005 1.70E-004

83 0.39 8.42E-006 1.34E-004 1.49E-005 4.14E-005 1.69E-004

84 0.4 8.68E-006 1.34E-004 1.58E-005 4.27E-005 1.68E-004

85 0.4 8.93E-006 1.33E-004 1.67E-005 4.40E-005 1.67E-004

86 0.41 9.19E-006 1.33E-004 1.76E-005 4.53E-005 1.66E-004

87 0.41 9.44E-006 1.32E-004 1.86E-005 4.66E-005 1.65E-004

88 0.42 9.70E-006 1.32E-004 1.96E-005 4.79E-005 1.64E-004

89 0.42 9.96E-006 1.31E-004 2.05E-005 4.92E-005 1.63E-004

90 0.43 1.02E-005 1.31E-004 2.16E-005 5.06E-005 1.62E-004

91 0.43 1.05E-005 1.30E-004 2.26E-005 5.19E-005 1.61E-004

72





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92 0.44 1.07E-005 1.30E-004 2.36E-005 5.32E-005 1.60E-004

93 0.45 1.10E-005 1.29E-004 2.47E-005 5.46E-005 1.59E-004

94 0.45 1.13E-005 1.29E-004 2.57E-005 5.59E-005 1.58E-004

95 0.46 1.15E-005 1.28E-004 2.68E-005 5.73E-005 1.57E-004

96 0.46 1.18E-005 1.28E-004 2.79E-005 5.86E-005 1.56E-004

97 0.47 1.20E-005 1.27E-004 2.90E-005 6.00E-005 1.55E-004

98 0.47 1.23E-005 1.27E-004 3.01E-005 6.13E-005 1.54E-004

99 0.48 1.26E-005 1.26E-004 3.13E-005 6.27E-005 1.53E-004

100 0.48 1.28E-005 1.26E-004 3.24E-005 6.41E-005 1.52E-004

101 0.49 1.31E-005 1.25E-004 3.36E-005 6.54E-005 1.51E-004

102 0.49 1.34E-005 1.25E-004 3.47E-005 6.68E-005 1.50E-004

103 0.5 1.36E-005 1.24E-004 3.59E-005 6.82E-005 1.49E-004

104 0.51 1.39E-005 1.24E-004 3.71E-005 6.96E-005 1.48E-004

105 0.51 1.42E-005 1.23E-004 3.83E-005 7.09E-005 1.47E-004

106 0.52 1.44E-005 1.23E-004 3.95E-005 7.23E-005 1.46E-004

107 0.52 1.47E-005 1.22E-004 4.07E-005 7.37E-005 1.45E-004

108 0.53 1.50E-005 1.21E-004 4.20E-005 7.51E-005 1.44E-004

109 0.53 1.52E-005 1.21E-004 4.32E-005 7.65E-005 1.44E-004

110 0.54 1.55E-005 1.20E-004 4.45E-005 7.79E-005 1.43E-004

111 0.54 1.58E-005 1.20E-004 4.57E-005 7.93E-005 1.42E-004

112 0.55 1.60E-005 1.19E-004 4.70E-005 8.07E-005 1.41E-004

113 0.56 1.63E-005 1.19E-004 4.82E-005 8.21E-005 1.40E-004

114 0.56 1.66E-005 1.18E-004 4.95E-005 8.35E-005 1.39E-004

115 0.57 1.68E-005 1.18E-004 5.08E-005 8.50E-005 1.38E-004

116 0.57 1.71E-005 1.17E-004 5.21E-005 8.64E-005 1.37E-004

117 0.58 1.74E-005 1.17E-004 5.34E-005 8.78E-005 1.36E-004

118 0.58 1.77E-005 1.16E-004 5.47E-005 8.92E-005 1.35E-004

119 0.59 1.79E-005 1.16E-004 5.60E-005 9.06E-005 1.34E-004

120 0.59 1.82E-005 1.15E-004 5.73E-005 9.20E-005 1.33E-004

121 0.6 1.85E-005 1.15E-004 5.87E-005 9.35E-005 1.32E-004

122 0.61 1.87E-005 1.14E-004 6.00E-005 9.49E-005 1.31E-004

123 0.61 1.90E-005 1.14E-004 6.13E-005 9.63E-005 1.30E-004

124 0.62 1.93E-005 1.13E-004 6.27E-005 9.77E-005 1.29E-004

125 0.62 1.95E-005 1.13E-004 6.40E-005 9.92E-005 1.28E-004

126 0.63 1.98E-005 1.12E-004 6.54E-005 1.01E-004 1.27E-004

127 0.63 2.01E-005 1.12E-004 6.67E-005 1.02E-004 1.26E-004

128 0.64 2.04E-005 1.11E-004 6.80E-005 1.03E-004 1.25E-004

129 0.64 2.06E-005 1.11E-004 6.94E-005 1.05E-004 1.24E-004

130 0.65 2.09E-005 1.10E-004 7.08E-005 1.06E-004 1.23E-004

131 0.65 2.12E-005 1.10E-004 7.22E-005 1.08E-004 1.22E-004

132 0.66 2.14E-005 1.09E-004 7.35E-005 1.09E-004 1.21E-004

133 0.67 2.17E-005 1.09E-004 7.49E-005 1.11E-004 1.20E-004

134 0.67 2.20E-005 1.08E-004 7.63E-005 1.12E-004 1.19E-004

135 0.68 2.23E-005 1.07E-004 7.77E-005 1.14E-004 1.18E-004

136 0.68 2.25E-005 1.07E-004 7.91E-005 1.15E-004 1.17E-004

137 0.69 2.28E-005 1.06E-004 8.05E-005 1.16E-004 1.16E-004

73





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138 0.69 2.31E-005 1.06E-004 8.19E-005 1.18E-004 1.15E-004

139 0.7 2.33E-005 1.05E-004 8.34E-005 1.19E-004 1.14E-004

140 0.7 2.36E-005 1.05E-004 8.48E-005 1.21E-004 1.14E-004

141 0.71 2.39E-005 1.04E-004 8.62E-005 1.22E-004 1.13E-004

142 0.72 2.42E-005 1.04E-004 8.76E-005 1.24E-004 1.12E-004

143 0.72 2.44E-005 1.03E-004 8.90E-005 1.25E-004 1.11E-004

144 0.73 2.47E-005 1.03E-004 9.05E-005 1.27E-004 1.10E-004

145 0.73 2.50E-005 1.02E-004 9.19E-005 1.28E-004 1.09E-004

146 0.74 2.52E-005 1.02E-004 9.33E-005 1.30E-004 1.08E-004

147 0.74 2.55E-005 1.01E-004 9.48E-005 1.31E-004 1.07E-004

148 0.75 2.58E-005 1.01E-004 9.62E-005 1.32E-004 1.06E-004

149 0.75 2.61E-005 1.00E-004 9.77E-005 1.34E-004 1.05E-004

150 0.76 2.63E-005 9.96E-005 9.91E-005 1.35E-004 1.04E-004

151 0.77 2.66E-005 9.91E-005 1.01E-004 1.37E-004 1.03E-004

152 0.77 2.69E-005 9.86E-005 1.02E-004 1.38E-004 1.02E-004

153 0.78 2.72E-005 9.81E-005 1.04E-004 1.40E-004 1.01E-004

154 0.78 2.74E-005 9.75E-005 1.05E-004 1.41E-004 1.00E-004

155 0.79 2.77E-005 9.70E-005 1.06E-004 1.43E-004 9.91E-005

156 0.79 2.80E-005 9.65E-005 1.08E-004 1.44E-004 9.81E-005

157 0.8 2.83E-005 9.60E-005 1.09E-004 1.46E-004 9.72E-005

158 0.8 2.85E-005 9.54E-005 1.11E-004 1.47E-004 9.62E-005

159 0.81 2.88E-005 9.49E-005 1.12E-004 1.49E-004 9.53E-005

160 0.82 2.91E-005 9.44E-005 1.14E-004 1.50E-004 9.43E-005

161 0.82 2.93E-005 9.39E-005 1.15E-004 1.51E-004 9.34E-005

162 0.83 2.96E-005 9.34E-005 1.17E-004 1.53E-004 9.24E-005

163 0.83 2.99E-005 9.28E-005 1.18E-004 1.54E-004 9.15E-005

164 0.84 3.02E-005 9.23E-005 1.20E-004 1.56E-004 9.05E-005

165 0.84 3.04E-005 9.18E-005 1.21E-004 1.57E-004 8.96E-005

166 0.85 3.07E-005 9.13E-005 1.23E-004 1.59E-004 8.86E-005

167 0.85 3.10E-005 9.07E-005 1.24E-004 1.60E-004 8.77E-005

168 0.86 3.13E-005 9.02E-005 1.26E-004 1.62E-004 8.67E-005

169 0.87 3.15E-005 8.97E-005 1.27E-004 1.63E-004 8.58E-005

170 0.87 3.18E-005 8.92E-005 1.29E-004 1.65E-004 8.49E-005

171 0.88 3.21E-005 8.87E-005 1.30E-004 1.66E-004 8.39E-005

172 0.88 3.24E-005 8.81E-005 1.32E-004 1.68E-004 8.30E-005

173 0.89 3.26E-005 8.76E-005 1.33E-004 1.69E-004 8.20E-005

174 0.89 3.29E-005 8.71E-005 1.35E-004 1.71E-004 8.11E-005

175 0.9 3.32E-005 8.66E-005 1.36E-004 1.72E-004 8.02E-005

176 0.9 3.34E-005 8.60E-005 1.38E-004 1.74E-004 7.93E-005

177 0.91 3.37E-005 8.55E-005 1.39E-004 1.75E-004 7.83E-005

178 0.92 3.40E-005 8.50E-005 1.41E-004 1.76E-004 7.74E-005

179 0.92 3.43E-005 8.45E-005 1.42E-004 1.78E-004 7.65E-005

180 0.93 3.45E-005 8.40E-005 1.44E-004 1.79E-004 7.55E-005

181 0.93 3.48E-005 8.34E-005 1.45E-004 1.81E-004 7.46E-005

182 0.94 3.51E-005 8.29E-005 1.47E-004 1.82E-004 7.37E-005

183 0.94 3.54E-005 8.24E-005 1.48E-004 1.84E-004 7.28E-005

74





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184 0.95 3.56E-005 8.19E-005 1.50E-004 1.85E-004 7.18E-005

185 0.95 3.59E-005 8.14E-005 1.51E-004 1.87E-004 7.09E-005

186 0.96 3.62E-005 8.08E-005 1.53E-004 1.88E-004 7.00E-005

187 0.97 3.65E-005 8.03E-005 1.54E-004 1.90E-004 6.91E-005

188 0.97 3.67E-005 7.98E-005 1.56E-004 1.91E-004 6.82E-005

189 0.98 3.70E-005 7.93E-005 1.57E-004 1.93E-004 6.73E-005

190 0.98 3.73E-005 7.87E-005 1.59E-004 1.94E-004 6.64E-005

191 0.99 3.75E-005 7.82E-005 1.61E-004 1.96E-004 6.55E-005

192 0.99 3.78E-005 7.77E-005 1.62E-004 1.97E-004 6.46E-005

193 1 3.81E-005 7.72E-005 1.64E-004 1.99E-004 6.37E-005

194 1 3.84E-005 7.67E-005 1.65E-004 2.00E-004 6.28E-005

195 1.01 3.86E-005 7.62E-005 1.67E-004 2.02E-004 6.19E-005

196 1.02 3.89E-005 7.56E-005 1.68E-004 2.03E-004 6.10E-005

197 1.02 3.92E-005 7.51E-005 1.70E-004 2.05E-004 6.01E-005

198 1.03 3.95E-005 7.46E-005 1.71E-004 2.06E-004 5.92E-005

199 1.03 3.97E-005 7.41E-005 1.73E-004 2.08E-004 5.83E-005

200 1.04 4.00E-005 7.36E-005 1.74E-004 2.09E-004 5.74E-005

201 1.04 4.03E-005 7.30E-005 1.76E-004 2.10E-004 5.65E-005

202 1.05 4.05E-005 7.25E-005 1.77E-004 2.12E-004 5.56E-005

203 1.05 4.08E-005 7.20E-005 1.79E-004 2.13E-004 5.47E-005

204 1.06 4.11E-005 7.15E-005 1.80E-004 2.15E-004 5.39E-005

205 1.07 4.14E-005 7.10E-005 1.82E-004 2.16E-004 5.30E-005

206 1.07 4.16E-005 7.05E-005 1.84E-004 2.18E-004 5.21E-005

207 1.08 4.19E-005 6.99E-005 1.85E-004 2.19E-004 5.13E-005

208 1.08 4.22E-005 6.94E-005 1.87E-004 2.21E-004 5.04E-005

209 1.09 4.25E-005 6.89E-005 1.88E-004 2.22E-004 4.95E-005

210 1.09 4.27E-005 6.84E-005 1.90E-004 2.24E-004 4.87E-005

211 1.1 4.30E-005 6.79E-005 1.91E-004 2.25E-004 4.78E-005

212 1.1 4.33E-005 6.74E-005 1.93E-004 2.27E-004 4.69E-005

213 1.11 4.35E-005 6.69E-005 1.94E-004 2.28E-004 4.61E-005

214 1.12 4.38E-005 6.63E-005 1.96E-004 2.30E-004 4.52E-005

215 1.12 4.41E-005 6.58E-005 1.97E-004 2.31E-004 4.44E-005

216 1.13 4.44E-005 6.53E-005 1.99E-004 2.33E-004 4.36E-005

217 1.13 4.46E-005 6.48E-005 2.01E-004 2.34E-004 4.27E-005

218 1.14 4.49E-005 6.43E-005 2.02E-004 2.36E-004 4.19E-005

219 1.14 4.52E-005 6.38E-005 2.04E-004 2.37E-004 4.11E-005

220 1.15 4.54E-005 6.33E-005 2.05E-004 2.39E-004 4.02E-005

221 1.15 4.57E-005 6.28E-005 2.07E-004 2.40E-004 3.94E-005

222 1.16 4.60E-005 6.22E-005 2.08E-004 2.42E-004 3.86E-005

223 1.17 4.63E-005 6.17E-005 2.10E-004 2.43E-004 3.78E-005

224 1.17 4.65E-005 6.12E-005 2.11E-004 2.44E-004 3.70E-005

225 1.18 4.68E-005 6.07E-005 2.13E-004 2.46E-004 3.61E-005

226 1.18 4.71E-005 6.02E-005 2.14E-004 2.47E-004 3.53E-005

227 1.19 4.73E-005 5.97E-005 2.16E-004 2.49E-004 3.45E-005

228 1.19 4.76E-005 5.92E-005 2.18E-004 2.50E-004 3.38E-005

229 1.2 4.79E-005 5.87E-005 2.19E-004 2.52E-004 3.30E-005

75





vref pixbuf

vcascp pixbuf

vcom chipbuf

vcasc chipbuf

vref chipbuf

vth comp

230 1.2 4.82E-005 5.82E-005 2.21E-004 2.53E-004 3.22E-005

231 1.21 4.84E-005 5.77E-005 2.22E-004 2.55E-004 3.14E-005

232 1.22 4.87E-005 5.72E-005 2.24E-004 2.56E-004 3.06E-005

233 1.22 4.90E-005 5.67E-005 2.25E-004 2.58E-004 2.99E-005

234 1.23 4.92E-005 5.62E-005 2.27E-004 2.59E-004 2.91E-005

235 1.23 4.95E-005 5.57E-005 2.28E-004 2.61E-004 2.83E-005

236 1.24 4.98E-005 5.52E-005 2.30E-004 2.62E-004 2.76E-005

237 1.24 5.00E-005 5.47E-005 2.31E-004 2.64E-004 2.68E-005

238 1.25 5.03E-005 5.42E-005 2.33E-004 2.65E-004 2.61E-005

239 1.25 5.06E-005 5.37E-005 2.35E-004 2.67E-004 2.54E-005

240 1.26 5.08E-005 5.32E-005 2.36E-004 2.68E-004 2.46E-005

241 1.26 5.11E-005 5.27E-005 2.38E-004 2.69E-004 2.39E-005

242 1.27 5.14E-005 5.22E-005 2.39E-004 2.71E-004 2.32E-005

243 1.28 5.17E-005 5.17E-005 2.41E-004 2.72E-004 2.25E-005

244 1.28 5.19E-005 5.12E-005 2.42E-004 2.74E-004 2.18E-005

245 1.29 5.22E-005 5.07E-005 2.44E-004 2.75E-004 2.11E-005

246 1.29 5.25E-005 5.02E-005 2.45E-004 2.77E-004 2.04E-005

247 1.3 5.27E-005 4.97E-005 2.47E-004 2.78E-004 1.97E-005

248 1.3 5.30E-005 4.92E-005 2.48E-004 2.80E-004 1.91E-005

249 1.31 5.33E-005 4.87E-005 2.50E-004 2.81E-004 1.84E-005

250 1.31 5.35E-005 4.82E-005 2.51E-004 2.83E-004 1.78E-005

251 1.32 5.38E-005 4.78E-005 2.53E-004 2.84E-004 1.71E-005

252 1.32 5.41E-005 4.73E-005 2.54E-004 2.85E-004 1.65E-005

253 1.33 5.43E-005 4.68E-005 2.56E-004 2.87E-004 1.59E-005

254 1.34 5.46E-005 4.63E-005 2.58E-004 2.88E-004 1.53E-005

255 1.34 5.48E-005 4.58E-005 2.90E-004 1.47E-005

Table 3: AGIPD 1.0 & AGIPD 1.1 Bias DACs (2).

Bias Current [A]

DAC ibn prebuf ibp prebuf ibn lvds ibp lvds ibn comp ibp cds itest curr itest curr

Value AGIPD 1.0 AGIPD 1.1

0 1.59E-008 4.58E-005 1.77E-009 9.71E-005 1.33E-008 3.36E-004 2.81E-06 3.61E-07

1 1.62E-008 4.57E-005 1.36E-009 9.71E-005 1.35E-008 3.36E-004 2.80E-06 3.58E-07

2 1.65E-008 4.57E-005 1.36E-009 9.71E-005 1.38E-008 3.36E-004 2.80E-06 3.55E-07

3 1.68E-008 4.57E-005 1.36E-009 9.70E-005 1.40E-008 3.36E-004 2.79E-06 3.52E-07

4 1.72E-008 4.56E-005 1.37E-009 9.70E-005 1.44E-008 3.36E-004 2.79E-06 3.49E-07

5 1.77E-008 4.56E-005 1.38E-009 9.70E-005 1.47E-008 3.36E-004 2.78E-06 3.46E-07

6 1.81E-008 4.56E-005 1.39E-009 9.70E-005 1.51E-008 3.36E-004 2.77E-06 3.42E-07

7 1.87E-008 4.55E-005 1.40E-009 9.70E-005 1.55E-008 3.36E-004 2.77E-06 3.38E-07

8 1.93E-008 4.55E-005 1.41E-009 9.69E-005 1.60E-008 3.35E-004 2.76E-06 3.34E-07

9 2.00E-008 4.54E-005 1.43E-009 9.69E-005 1.66E-008 3.35E-004 2.75E-06 3.30E-07

10 2.07E-008 4.53E-005 1.44E-009 9.69E-005 1.72E-008 3.35E-004 2.74E-06 3.25E-07

11 2.16E-008 4.53E-005 1.46E-009 9.69E-005 1.79E-008 3.35E-004 2.74E-06 3.20E-07

12 2.25E-008 4.52E-005 1.47E-009 9.68E-005 1.86E-008 3.35E-004 2.73E-06 3.15E-07

13 2.36E-008 4.51E-005 1.49E-009 9.68E-005 1.95E-008 3.35E-004 2.72E-06 3.10E-07

76



Bias Current [A]



14 2.48E-008 4.50E-005 1.51E-009 9.68E-005 2.05E-008 3.34E-004 2.71E-06 3.05E-07

15 2.61E-008 4.49E-005 1.54E-009 9.67E-005 2.15E-008 3.34E-004 2.70E-06 2.99E-07

16 2.76E-008 4.48E-005 1.56E-009 9.67E-005 2.28E-008 3.34E-004 2.69E-06 2.94E-07

17 2.93E-008 4.47E-005 1.59E-009 9.66E-005 2.41E-008 3.34E-004 2.67E-06 2.88E-07

18 3.12E-008 4.46E-005 1.62E-009 9.66E-005 2.57E-008 3.33E-004 2.66E-06 2.82E-07

19 3.34E-008 4.44E-005 1.65E-009 9.65E-005 2.74E-008 3.33E-004 2.65E-06 2.76E-07

20 3.59E-008 4.43E-005 1.69E-009 9.65E-005 2.94E-008 3.32E-004 2.64E-06 2.69E-07

21 3.87E-008 4.42E-005 1.73E-009 9.64E-005 3.16E-008 3.32E-004 2.63E-06 2.63E-07

22 4.19E-008 4.40E-005 1.78E-009 9.63E-005 3.41E-008 3.32E-004 2.61E-06 2.57E-07

23 4.55E-008 4.39E-005 1.83E-009 9.63E-005 3.70E-008 3.31E-004 2.60E-06 2.51E-07

24 4.97E-008 4.38E-005 1.89E-009 9.62E-005 4.03E-008 3.31E-004 2.59E-06 2.44E-07

25 5.45E-008 4.36E-005 1.95E-009 9.61E-005 4.40E-008 3.30E-004 2.57E-06 2.38E-07

26 6.00E-008 4.35E-005 2.02E-009 9.60E-005 4.83E-008 3.29E-004 2.56E-06 2.31E-07

27 6.63E-008 4.33E-005 2.09E-009 9.59E-005 5.32E-008 3.29E-004 2.55E-06 2.25E-07

28 7.36E-008 4.32E-005 2.18E-009 9.58E-005 5.89E-008 3.28E-004 2.53E-06 2.19E-07

29 8.21E-008 4.30E-005 2.27E-009 9.57E-005 6.53E-008 3.27E-004 2.52E-06 2.12E-07

30 9.18E-008 4.28E-005 2.38E-009 9.56E-005 7.28E-008 3.27E-004 2.50E-06 2.06E-07

31 1.03E-007 4.27E-005 2.50E-009 9.55E-005 8.13E-008 3.26E-004 2.49E-06 2.00E-07

32 1.16E-007 4.25E-005 2.63E-009 9.54E-005 9.10E-008 3.25E-004 2.48E-06 1.94E-07

33 1.31E-007 4.23E-005 2.77E-009 9.53E-005 1.02E-007 3.24E-004 2.46E-06 1.88E-07

34 1.49E-007 4.22E-005 2.93E-009 9.52E-005 1.15E-007 3.23E-004 2.45E-06 1.82E-07

35 1.70E-007 4.20E-005 3.12E-009 9.50E-005 1.30E-007 3.22E-004 2.43E-06 1.76E-07

36 1.93E-007 4.18E-005 3.32E-009 9.49E-005 1.47E-007 3.21E-004 2.42E-06 1.71E-07

37 2.21E-007 4.17E-005 3.54E-009 9.47E-005 1.67E-007 3.20E-004 2.40E-06 1.65E-07

38 2.53E-007 4.15E-005 3.80E-009 9.46E-005 1.89E-007 3.19E-004 2.39E-06 1.60E-07

39 2.90E-007 4.13E-005 4.08E-009 9.44E-005 2.14E-007 3.18E-004 2.38E-06 1.54E-07

40 3.33E-007 4.11E-005 4.40E-009 9.43E-005 2.43E-007 3.17E-004 2.36E-06 1.49E-07

41 3.83E-007 4.10E-005 4.75E-009 9.41E-005 2.76E-007 3.16E-004 2.35E-06 1.44E-07

42 4.41E-007 4.08E-005 5.15E-009 9.40E-005 3.12E-007 3.15E-004 2.33E-06 1.39E-07

43 5.08E-007 4.06E-005 5.60E-009 9.38E-005 3.53E-007 3.14E-004 2.32E-06 1.34E-07

44 5.84E-007 4.04E-005 6.11E-009 9.36E-005 3.99E-007 3.13E-004 2.30E-06 1.29E-07

45 6.71E-007 4.02E-005 6.67E-009 9.35E-005 4.51E-007 3.12E-004 2.29E-06 1.25E-07

46 7.71E-007 4.01E-005 7.30E-009 9.33E-005 5.07E-007 3.11E-004 2.27E-06 1.20E-07

47 8.85E-007 3.99E-005 8.02E-009 9.31E-005 5.69E-007 3.10E-004 2.26E-06 1.16E-07

48 1.01E-006 3.97E-005 8.81E-009 9.29E-005 6.37E-007 3.09E-004 2.25E-06 1.11E-07

49 1.16E-006 3.95E-005 9.71E-009 9.27E-005 7.10E-007 3.08E-004 2.23E-06 1.07E-07

50 1.32E-006 3.93E-005 1.07E-008 9.25E-005 7.90E-007 3.06E-004 2.22E-06 1.03E-07

51 1.50E-006 3.91E-005 1.19E-008 9.23E-005 8.76E-007 3.05E-004 2.20E-06 9.90E-08

52 1.71E-006 3.90E-005 1.31E-008 9.22E-005 9.67E-007 3.04E-004 2.19E-06 9.52E-08

53 1.93E-006 3.88E-005 1.46E-008 9.20E-005 1.07E-006 3.03E-004 2.17E-06 9.14E-08

54 2.18E-006 3.86E-005 1.62E-008 9.18E-005 1.17E-006 3.02E-004 2.16E-06 8.78E-08

55 2.45E-006 3.84E-005 1.80E-008 9.16E-005 1.28E-006 3.01E-004 2.14E-06 8.42E-08

56 2.74E-006 3.82E-005 2.01E-008 9.14E-005 1.39E-006 2.99E-004 2.13E-06 8.08E-08

57 3.06E-006 3.80E-005 2.24E-008 9.12E-005 1.51E-006 2.98E-004 2.11E-06 7.75E-08

58 3.40E-006 3.78E-005 2.50E-008 9.10E-005 1.64E-006 2.97E-004 2.10E-06 7.43E-08

59 3.78E-006 3.77E-005 2.79E-008 9.07E-005 1.77E-006 2.96E-004 2.09E-06 7.12E-08

60 4.17E-006 3.75E-005 3.11E-008 9.05E-005 1.90E-006 2.95E-004 2.07E-06 6.81E-08

61 4.59E-006 3.73E-005 3.48E-008 9.03E-005 2.04E-006 2.93E-004 2.06E-06 6.52E-08

62 5.04E-006 3.71E-005 3.89E-008 9.01E-005 2.18E-006 2.92E-004 2.04E-06 6.24E-08

63 5.52E-006 3.69E-005 4.36E-008 8.99E-005 2.33E-006 2.91E-004 2.03E-06 5.97E-08

64 6.00E-006 3.67E-005 4.86E-008 8.97E-005 2.48E-006 2.90E-004 2.01E-06 5.71E-08

77



Bias Current [A]



65 6.53E-006 3.65E-005 5.44E-008 8.95E-005 2.63E-006 2.89E-004 2.00E-06 5.46E-08

66 7.07E-006 3.63E-005 6.09E-008 8.93E-005 2.79E-006 2.87E-004 1.98E-06 5.22E-08

67 7.64E-006 3.61E-005 6.82E-008 8.90E-005 2.95E-006 2.86E-004 1.97E-06 4.98E-08

68 8.23E-006 3.60E-005 7.63E-008 8.88E-005 3.12E-006 2.85E-004 1.96E-06 4.75E-08

69 8.85E-006 3.58E-005 8.54E-008 8.86E-005 3.28E-006 2.84E-004 1.94E-06 4.54E-08

70 9.48E-006 3.56E-005 9.56E-008 8.84E-005 3.45E-006 2.82E-004 1.93E-06 4.33E-08

71 1.01E-005 3.54E-005 1.07E-007 8.81E-005 3.63E-006 2.81E-004 1.91E-06 4.13E-08

72 1.08E-005 3.52E-005 1.20E-007 8.79E-005 3.80E-006 2.80E-004 1.90E-06 3.93E-08

73 1.15E-005 3.50E-005 1.34E-007 8.77E-005 3.98E-006 2.79E-004 1.88E-06 3.75E-08

74 1.22E-005 3.48E-005 1.50E-007 8.74E-005 4.16E-006 2.78E-004 1.87E-06 3.57E-08

75 1.29E-005 3.46E-005 1.68E-007 8.72E-005 4.34E-006 2.76E-004 1.86E-06 3.40E-08

76 1.37E-005 3.44E-005 1.88E-007 8.70E-005 4.53E-006 2.75E-004 1.84E-06 3.23E-08

77 1.45E-005 3.42E-005 2.10E-007 8.67E-005 4.71E-006 2.74E-004 1.83E-06 3.07E-08

78 1.52E-005 3.40E-005 2.35E-007 8.65E-005 4.90E-006 2.73E-004 1.81E-06 2.92E-08

79 1.60E-005 3.38E-005 2.63E-007 8.62E-005 5.09E-006 2.71E-004 1.80E-06 2.78E-08

80 1.68E-005 3.36E-005 2.94E-007 8.60E-005 5.28E-006 2.70E-004 1.78E-06 2.64E-08

81 1.76E-005 3.34E-005 3.28E-007 8.58E-005 5.47E-006 2.69E-004 1.77E-06 2.51E-08

82 1.85E-005 3.33E-005 3.67E-007 8.55E-005 5.67E-006 2.68E-004 1.76E-06 2.38E-08

83 1.93E-005 3.31E-005 4.10E-007 8.53E-005 5.86E-006 2.66E-004 1.74E-06 2.26E-08

84 2.02E-005 3.29E-005 4.58E-007 8.50E-005 6.06E-006 2.65E-004 1.73E-06 2.14E-08

85 2.10E-005 3.27E-005 5.12E-007 8.47E-005 6.26E-006 2.64E-004 1.71E-06 2.03E-08

86 2.19E-005 3.25E-005 5.72E-007 8.45E-005 6.45E-006 2.63E-004 1.70E-06 1.93E-08

87 2.28E-005 3.23E-005 6.39E-007 8.42E-005 6.65E-006 2.61E-004 1.68E-06 1.83E-08

88 2.37E-005 3.21E-005 7.14E-007 8.40E-005 6.86E-006 2.60E-004 1.67E-06 1.73E-08

89 2.46E-005 3.19E-005 7.97E-007 8.37E-005 7.06E-006 2.59E-004 1.66E-06 1.64E-08

90 2.55E-005 3.17E-005 8.90E-007 8.35E-005 7.26E-006 2.57E-004 1.64E-06 1.55E-08

91 2.65E-005 3.15E-005 9.93E-007 8.32E-005 7.47E-006 2.56E-004 1.63E-06 1.47E-08

92 2.74E-005 3.13E-005 1.11E-006 8.29E-005 7.67E-006 2.55E-004 1.61E-06 1.39E-08

93 2.84E-005 3.11E-005 1.24E-006 8.27E-005 7.88E-006 2.54E-004 1.60E-06 1.32E-08

94 2.93E-005 3.09E-005 1.38E-006 8.24E-005 8.09E-006 2.52E-004 1.59E-06 1.24E-08

95 3.03E-005 3.07E-005 1.54E-006 8.21E-005 8.29E-006 2.51E-004 1.57E-06 1.18E-08

96 3.12E-005 3.05E-005 1.71E-006 8.18E-005 8.50E-006 2.50E-004 1.56E-06 1.11E-08

97 3.22E-005 3.03E-005 1.91E-006 8.16E-005 8.71E-006 2.49E-004 1.54E-06 1.05E-08

98 3.32E-005 3.01E-005 2.12E-006 8.13E-005 8.92E-006 2.47E-004 1.53E-06 9.92E-09

99 3.42E-005 2.99E-005 2.36E-006 8.10E-005 9.13E-006 2.46E-004 1.52E-06 9.38E-09

100 3.52E-005 2.97E-005 2.63E-006 8.07E-005 9.34E-006 2.45E-004 1.50E-06 8.86E-09

101 3.62E-005 2.95E-005 2.92E-006 8.04E-005 9.56E-006 2.43E-004 1.49E-06 8.36E-09

102 3.72E-005 2.93E-005 3.25E-006 8.01E-005 9.77E-006 2.42E-004 1.47E-06 7.88E-09

103 3.82E-005 2.91E-005 3.61E-006 7.99E-005 9.98E-006 2.41E-004 1.46E-06 7.44E-09

104 3.93E-005 2.89E-005 4.00E-006 7.96E-005 1.02E-005 2.40E-004 1.45E-06 7.01E-09

105 4.03E-005 2.87E-005 4.44E-006 7.93E-005 1.04E-005 2.38E-004 1.43E-06 6.61E-09

106 4.13E-005 2.85E-005 4.92E-006 7.90E-005 1.06E-005 2.37E-004 1.42E-06 6.23E-09

107 4.24E-005 2.83E-005 5.45E-006 7.87E-005 1.08E-005 2.36E-004 1.40E-06 5.87E-09

108 4.34E-005 2.81E-005 6.03E-006 7.84E-005 1.11E-005 2.34E-004 1.39E-06 5.53E-09

109 4.45E-005 2.79E-005 6.66E-006 7.81E-005 1.13E-005 2.33E-004 1.38E-06 5.21E-09

110 4.55E-005 2.77E-005 7.36E-006 7.78E-005 1.15E-005 2.32E-004 1.36E-06 4.90E-09

111 4.66E-005 2.75E-005 8.11E-006 7.75E-005 1.17E-005 2.31E-004 1.35E-06 4.62E-09

112 4.77E-005 2.73E-005 8.93E-006 7.72E-005 1.19E-005 2.29E-004 1.34E-06 4.35E-09

113 4.87E-005 2.71E-005 9.82E-006 7.68E-005 1.22E-005 2.28E-004 1.32E-06 4.09E-09

114 4.98E-005 2.69E-005 1.08E-005 7.65E-005 1.24E-005 2.27E-004 1.31E-06 3.85E-09

115 5.09E-005 2.67E-005 1.18E-005 7.62E-005 1.26E-005 2.25E-004 1.29E-06 3.62E-09

78



Bias Current [A]



116 5.20E-005 2.65E-005 1.29E-005 7.59E-005 1.28E-005 2.24E-004 1.28E-06 3.40E-09

117 5.30E-005 2.63E-005 1.41E-005 7.56E-005 1.30E-005 2.23E-004 1.27E-06 3.20E-09

118 5.41E-005 2.61E-005 1.54E-005 7.53E-005 1.33E-005 2.22E-004 1.25E-06 3.01E-09

119 5.52E-005 2.59E-005 1.68E-005 7.49E-005 1.35E-005 2.20E-004 1.24E-06 2.83E-09

120 5.63E-005 2.57E-005 1.82E-005 7.46E-005 1.37E-005 2.19E-004 1.23E-06 2.66E-09

121 5.74E-005 2.55E-005 1.98E-005 7.43E-005 1.39E-005 2.18E-004 1.21E-06 2.50E-09

122 5.85E-005 2.53E-005 2.14E-005 7.39E-005 1.41E-005 2.16E-004 1.20E-06 2.35E-09

123 5.97E-005 2.51E-005 2.31E-005 7.36E-005 1.44E-005 2.15E-004 1.19E-06 2.20E-09

124 6.08E-005 2.49E-005 2.49E-005 7.33E-005 1.46E-005 2.14E-004 1.17E-06 2.07E-09

125 6.19E-005 2.47E-005 2.68E-005 7.29E-005 1.48E-005 2.13E-004 1.16E-06 1.94E-09

126 6.30E-005 2.45E-005 2.88E-005 7.26E-005 1.50E-005 2.11E-004 1.15E-06 1.83E-09

127 6.41E-005 2.43E-005 3.09E-005 7.22E-005 1.53E-005 2.10E-004 1.13E-06 1.71E-09

128 6.52E-005 2.42E-005 3.29E-005 7.19E-005 1.55E-005 2.09E-004 1.12E-06 1.61E-09

129 6.63E-005 2.40E-005 3.52E-005 7.15E-005 1.57E-005 2.07E-004 1.11E-06 1.51E-09

130 6.75E-005 2.38E-005 3.75E-005 7.12E-005 1.59E-005 2.06E-004 1.09E-06 1.42E-09

131 6.86E-005 2.36E-005 3.98E-005 7.08E-005 1.61E-005 2.05E-004 1.08E-06 1.33E-09

132 6.97E-005 2.34E-005 4.23E-005 7.05E-005 1.64E-005 2.03E-004 1.07E-06 1.25E-09

133 7.09E-005 2.32E-005 4.49E-005 7.01E-005 1.66E-005 2.02E-004 1.05E-06 1.18E-09

134 7.20E-005 2.30E-005 4.75E-005 6.98E-005 1.68E-005 2.01E-004 1.04E-06 1.10E-09

135 7.32E-005 2.28E-005 5.01E-005 6.94E-005 1.70E-005 2.00E-004 1.03E-06 1.04E-09

136 7.43E-005 2.26E-005 5.29E-005 6.90E-005 1.73E-005 1.98E-004 1.01E-06 9.74E-10

137 7.55E-005 2.24E-005 5.57E-005 6.86E-005 1.75E-005 1.97E-004 1.00E-06 9.15E-10

138 7.66E-005 2.22E-005 5.86E-005 6.83E-005 1.77E-005 1.96E-004 9.88E-07 8.59E-10

139 7.78E-005 2.20E-005 6.15E-005 6.79E-005 1.79E-005 1.94E-004 9.75E-07 8.08E-10

140 7.89E-005 2.18E-005 6.45E-005 6.75E-005 1.82E-005 1.93E-004 9.62E-07 7.59E-10

141 8.01E-005 2.16E-005 6.76E-005 6.71E-005 1.84E-005 1.92E-004 9.49E-07 7.13E-10

142 8.13E-005 2.14E-005 7.07E-005 6.67E-005 1.86E-005 1.90E-004 9.36E-07 6.70E-10

143 8.24E-005 2.12E-005 7.38E-005 6.63E-005 1.89E-005 1.89E-004 9.24E-07 6.31E-10

144 8.36E-005 2.10E-005 7.70E-005 6.60E-005 1.91E-005 1.88E-004 9.11E-07 5.92E-10

145 8.48E-005 2.08E-005 8.03E-005 6.56E-005 1.93E-005 1.86E-004 8.98E-07 5.58E-10

146 8.59E-005 2.06E-005 8.36E-005 6.52E-005 1.95E-005 1.85E-004 8.86E-07 5.24E-10

147 8.71E-005 2.04E-005 8.69E-005 6.48E-005 1.98E-005 1.84E-004 8.73E-07 4.94E-10

148 8.83E-005 2.02E-005 9.03E-005 6.43E-005 2.00E-005 1.83E-004 8.61E-07 4.66E-10

149 8.95E-005 2.00E-005 9.38E-005 6.39E-005 2.02E-005 1.81E-004 8.48E-07 4.38E-10

150 9.06E-005 1.98E-005 9.72E-005 6.35E-005 2.04E-005 1.80E-004 8.35E-07 4.13E-10

151 9.18E-005 1.96E-005 1.01E-004 6.31E-005 2.07E-005 1.79E-004 8.23E-07 3.89E-10

152 9.30E-005 1.94E-005 1.04E-004 6.27E-005 2.09E-005 1.77E-004 8.11E-07 3.67E-10

153 9.42E-005 1.92E-005 1.08E-004 6.23E-005 2.11E-005 1.76E-004 7.98E-07 3.46E-10

154 9.54E-005 1.90E-005 1.12E-004 6.18E-005 2.14E-005 1.75E-004 7.86E-07 3.29E-10

155 9.66E-005 1.88E-005 1.15E-004 6.14E-005 2.16E-005 1.73E-004 7.74E-07 3.08E-10

156 9.77E-005 1.86E-005 1.19E-004 6.10E-005 2.18E-005 1.72E-004 7.62E-07 2.90E-10

157 9.89E-005 1.84E-005 1.23E-004 6.05E-005 2.20E-005 1.71E-004 7.49E-07 2.75E-10

158 1.00E-004 1.82E-005 1.26E-004 6.01E-005 2.23E-005 1.69E-004 7.37E-07 2.62E-10

159 1.01E-004 1.80E-005 1.30E-004 5.96E-005 2.25E-005 1.68E-004 7.25E-07 2.46E-10

160 1.03E-004 1.78E-005 1.34E-004 5.92E-005 2.27E-005 1.67E-004 7.13E-07 2.33E-10

161 1.04E-004 1.76E-005 1.38E-004 5.88E-005 2.30E-005 1.66E-004 7.01E-07 2.21E-10

162 1.05E-004 1.74E-005 1.41E-004 5.83E-005 2.32E-005 1.64E-004 6.90E-07 2.10E-10

163 1.06E-004 1.72E-005 1.45E-004 5.78E-005 2.34E-005 1.63E-004 6.78E-07 1.98E-10

164 1.07E-004 1.70E-005 1.49E-004 5.74E-005 2.37E-005 1.62E-004 6.66E-07 1.87E-10

165 1.09E-004 1.68E-005 1.53E-004 5.69E-005 2.39E-005 1.60E-004 6.54E-07 1.79E-10

166 1.10E-004 1.66E-005 1.57E-004 5.64E-005 2.41E-005 1.59E-004 6.43E-07 1.71E-10

79



Bias Current [A]



167 1.11E-004 1.64E-005 1.61E-004 5.60E-005 2.43E-005 1.58E-004 6.31E-07 1.62E-10

168 1.12E-004 1.62E-005 1.65E-004 5.55E-005 2.46E-005 1.56E-004 6.20E-07 1.54E-10

169 1.13E-004 1.60E-005 1.69E-004 5.50E-005 2.48E-005 1.55E-004 6.08E-07 1.46E-10

170 1.15E-004 1.58E-005 1.73E-004 5.45E-005 2.50E-005 1.54E-004 5.97E-07 1.40E-10

171 1.16E-004 1.56E-005 1.77E-004 5.40E-005 2.53E-005 1.52E-004 5.85E-07 1.33E-10

172 1.17E-004 1.54E-005 1.81E-004 5.35E-005 2.55E-005 1.51E-004 5.74E-07 1.27E-10

173 1.18E-004 1.52E-005 1.85E-004 5.30E-005 2.57E-005 1.50E-004 5.63E-07 1.21E-10

174 1.19E-004 1.50E-005 1.89E-004 5.25E-005 2.60E-005 1.48E-004 5.52E-07 1.16E-10

175 1.21E-004 1.48E-005 1.93E-004 5.20E-005 2.62E-005 1.47E-004 5.41E-07 1.11E-10

176 1.22E-004 1.46E-005 1.97E-004 5.15E-005 2.64E-005 1.46E-004 5.30E-07 1.06E-10

177 1.23E-004 1.44E-005 2.01E-004 5.10E-005 2.66E-005 1.45E-004 5.19E-07 1.02E-10

178 1.24E-004 1.42E-005 2.05E-004 5.05E-005 2.69E-005 1.43E-004 5.08E-07 9.77E-11

179 1.25E-004 1.40E-005 2.09E-004 5.00E-005 2.71E-005 1.42E-004 4.98E-07 9.35E-11

180 1.27E-004 1.39E-005 2.13E-004 4.94E-005 2.73E-005 1.41E-004 4.87E-07 8.96E-11

181 1.28E-004 1.37E-005 2.18E-004 4.89E-005 2.76E-005 1.39E-004 4.76E-07 8.63E-11

182 1.29E-004 1.35E-005 2.22E-004 4.83E-005 2.78E-005 1.38E-004 4.66E-07 8.31E-11

183 1.30E-004 1.33E-005 2.26E-004 4.78E-005 2.80E-005 1.37E-004 4.55E-07 7.98E-11

184 1.32E-004 1.31E-005 2.30E-004 4.73E-005 2.83E-005 1.35E-004 4.45E-07 7.68E-11

185 1.33E-004 1.29E-005 2.34E-004 4.67E-005 2.85E-005 1.34E-004 4.35E-07 7.41E-11

186 1.34E-004 1.27E-005 2.38E-004 4.62E-005 2.87E-005 1.33E-004 4.25E-07 7.16E-11

187 1.35E-004 1.25E-005 2.42E-004 4.56E-005 2.89E-005 1.31E-004 4.15E-07 6.90E-11

188 1.36E-004 1.23E-005 2.47E-004 4.50E-005 2.92E-005 1.30E-004 4.05E-07 6.66E-11

189 1.38E-004 1.21E-005 2.51E-004 4.45E-005 2.94E-005 1.29E-004 3.95E-07 6.44E-11

190 1.39E-004 1.19E-005 2.55E-004 4.39E-005 2.96E-005 1.28E-004 3.85E-07 6.23E-11

191 1.40E-004 1.17E-005 2.59E-004 4.33E-005 2.99E-005 1.26E-004 3.75E-07 6.02E-11

192 1.41E-004 1.15E-005 2.63E-004 4.27E-005 3.01E-005 1.25E-004 3.66E-07 5.87E-11

193 1.43E-004 1.14E-005 2.67E-004 4.21E-005 3.03E-005 1.24E-004 3.56E-07 5.66E-11

194 1.44E-004 1.12E-005 2.72E-004 4.15E-005 3.06E-005 1.22E-004 3.47E-07 5.49E-11

195 1.45E-004 1.10E-005 2.76E-004 4.10E-005 3.08E-005 1.21E-004 3.38E-07 5.32E-11

196 1.46E-004 1.08E-005 2.80E-004 4.04E-005 3.10E-005 1.20E-004 3.29E-07 5.17E-11

197 1.48E-004 1.06E-005 2.84E-004 3.98E-005 3.12E-005 1.18E-004 3.20E-07 5.02E-11

198 1.49E-004 1.04E-005 2.88E-004 3.91E-005 3.15E-005 1.17E-004 3.11E-07 4.89E-11

199 1.50E-004 1.02E-005 2.92E-004 3.85E-005 3.17E-005 1.16E-004 3.02E-07 4.75E-11

200 1.51E-004 1.00E-005 2.97E-004 3.79E-005 3.19E-005 1.15E-004 2.93E-07 4.62E-11

201 1.52E-004 9.85E-006 3.01E-004 3.73E-005 3.22E-005 1.13E-004 2.85E-07 4.50E-11

202 1.54E-004 9.67E-006 3.05E-004 3.67E-005 3.24E-005 1.12E-004 2.76E-07 4.39E-11

203 1.55E-004 9.48E-006 3.09E-004 3.61E-005 3.26E-005 1.11E-004 2.68E-07 4.27E-11

204 1.56E-004 9.30E-006 3.13E-004 3.54E-005 3.28E-005 1.09E-004 2.60E-07 4.17E-11

205 1.57E-004 9.11E-006 3.17E-004 3.48E-005 3.31E-005 1.08E-004 2.52E-07 4.07E-11

206 1.59E-004 8.93E-006 3.22E-004 3.42E-005 3.33E-005 1.07E-004 2.44E-07 3.97E-11

207 1.60E-004 8.75E-006 3.26E-004 3.36E-005 3.35E-005 1.05E-004 2.36E-07 3.88E-11

208 1.61E-004 8.57E-006 3.30E-004 3.29E-005 3.37E-005 1.04E-004 2.28E-07 3.80E-11

209 1.62E-004 8.39E-006 3.34E-004 3.23E-005 3.40E-005 1.03E-004 2.21E-07 3.70E-11

210 1.64E-004 8.21E-006 3.38E-004 3.17E-005 3.42E-005 1.02E-004 2.13E-07 3.62E-11

211 1.65E-004 8.03E-006 3.42E-004 3.10E-005 3.44E-005 1.00E-004 2.06E-07 3.54E-11

212 1.66E-004 7.85E-006 3.46E-004 3.04E-005 3.46E-005 9.90E-005 1.99E-07 3.46E-11

213 1.67E-004 7.67E-006 3.50E-004 2.98E-005 3.49E-005 9.77E-005 1.92E-07 3.39E-11

214 1.68E-004 7.49E-006 3.54E-004 2.92E-005 3.51E-005 9.64E-005 1.85E-07 3.32E-11

215 1.70E-004 7.31E-006 3.58E-004 2.86E-005 3.53E-005 9.51E-005 1.78E-07 3.25E-11

216 1.71E-004 7.14E-006 3.63E-004 2.79E-005 3.55E-005 9.38E-005 1.71E-07 3.18E-11

217 1.72E-004 6.96E-006 3.67E-004 2.73E-005 3.57E-005 9.26E-005 1.65E-07 3.11E-11

80



Bias Current [A]



218 1.73E-004 6.79E-006 3.71E-004 2.67E-005 3.60E-005 9.13E-005 1.59E-07 3.05E-11

219 1.75E-004 6.62E-006 3.75E-004 2.61E-005 3.62E-005 9.00E-005 1.53E-07 2.98E-11

220 1.76E-004 6.44E-006 3.79E-004 2.55E-005 3.64E-005 8.87E-005 1.47E-07 2.92E-11

221 1.77E-004 6.27E-006 3.83E-004 2.49E-005 3.66E-005 8.75E-005 1.41E-07 2.86E-11

222 1.78E-004 6.10E-006 3.87E-004 2.43E-005 3.68E-005 8.62E-005 1.35E-07 2.80E-11

223 1.80E-004 5.93E-006 3.91E-004 2.37E-005 3.70E-005 8.49E-005 1.29E-07 2.73E-11

224 1.81E-004 5.77E-006 3.95E-004 2.31E-005 3.73E-005 8.37E-005 1.24E-07 2.68E-11

225 1.82E-004 5.60E-006 3.99E-004 2.26E-005 3.75E-005 8.24E-005 1.19E-07 2.61E-11

226 1.83E-004 5.43E-006 4.02E-004 2.20E-005 3.77E-005 8.11E-005 1.14E-07 2.54E-11

227 1.85E-004 5.27E-006 4.06E-004 2.14E-005 3.79E-005 7.99E-005 1.09E-07 2.48E-11

228 1.86E-004 5.11E-006 4.10E-004 2.08E-005 3.81E-005 7.86E-005 1.04E-07 2.41E-11

229 1.87E-004 4.95E-006 4.14E-004 2.03E-005 3.83E-005 7.74E-005 9.91E-08 2.34E-11

230 1.88E-004 4.79E-006 4.18E-004 1.97E-005 3.85E-005 7.61E-005 9.46E-08 2.27E-11

231 1.89E-004 4.63E-006 4.22E-004 1.92E-005 3.87E-005 7.49E-005 9.02E-08 2.20E-11

232 1.91E-004 4.47E-006 4.26E-004 1.87E-005 3.90E-005 7.36E-005 8.60E-08 2.13E-11

233 1.92E-004 4.31E-006 4.29E-004 1.81E-005 3.92E-005 7.24E-005 8.19E-08 2.05E-11

234 1.93E-004 4.16E-006 4.33E-004 1.76E-005 3.94E-005 7.11E-005 7.79E-08 1.98E-11

235 1.94E-004 4.01E-006 4.37E-004 1.71E-005 3.96E-005 6.99E-005 7.41E-08 1.90E-11

236 1.96E-004 3.86E-006 4.41E-004 1.66E-005 3.98E-005 6.87E-005 7.04E-08 1.83E-11

237 1.97E-004 3.71E-006 4.44E-004 1.61E-005 4.00E-005 6.74E-005 6.69E-08 1.75E-11

238 1.98E-004 3.56E-006 4.48E-004 1.55E-005 4.02E-005 6.62E-005 6.35E-08 1.68E-11

239 1.99E-004 3.42E-006 4.52E-004 1.51E-005 4.04E-005 6.50E-005 6.02E-08 1.60E-11

240 2.01E-004 3.28E-006 4.55E-004 1.46E-005 4.07E-005 6.38E-005 5.71E-08 1.53E-11

241 2.02E-004 3.14E-006 4.59E-004 1.41E-005 4.09E-005 6.26E-005 5.41E-08 1.46E-11

242 2.03E-004 3.00E-006 4.62E-004 1.36E-005 4.11E-005 6.13E-005 5.12E-08 1.39E-11

243 2.04E-004 2.86E-006 4.66E-004 1.32E-005 4.13E-005 6.01E-005 4.84E-08 1.33E-11

244 2.05E-004 2.73E-006 4.69E-004 1.27E-005 4.15E-005 5.89E-005 4.58E-08 1.27E-11

245 2.07E-004 2.60E-006 4.73E-004 1.22E-005 4.17E-005 5.77E-005 4.32E-08 1.21E-11

246 2.08E-004 2.47E-006 4.76E-004 1.18E-005 4.19E-005 5.65E-005 4.08E-08 1.15E-11

247 2.09E-004 2.35E-006 4.80E-004 1.14E-005 4.21E-005 5.54E-005 3.85E-08 1.10E-11

248 2.10E-004 2.23E-006 4.83E-004 1.09E-005 4.23E-005 5.42E-005 3.63E-08 1.05E-11

249 2.12E-004 2.11E-006 4.86E-004 1.05E-005 4.25E-005 5.30E-005 3.42E-08 1.00E-11

250 2.13E-004 1.99E-006 4.90E-004 1.01E-005 4.27E-005 5.18E-005 3.22E-08 9.59E-12

251 2.14E-004 1.88E-006 4.93E-004 9.71E-006 4.30E-005 5.07E-005 3.03E-08 9.21E-12

252 2.15E-004 1.77E-006 4.96E-004 9.32E-006 4.32E-005 4.95E-005 2.85E-08 8.84E-12

253 2.16E-004 1.66E-006 4.99E-004 8.94E-006 4.34E-005 4.84E-005 2.68E-08 8.50E-12

254 2.18E-004 1.56E-006 5.02E-004 8.56E-006 4.36E-005 4.72E-005 2.51E-08 8.18E-12

255 2.19E-004 1.46E-006 5.06E-004 8.20E-006 4.38E-005 4.61E-005 2.36E-08 7.91E-12

Table 4: VPC1 register bits.

definition of analogue V C1

info from VPC1HI info from VPC1LO

MSB17 6 5 4 3 2 1 MSB10 LSB17 6 5 4 3 2 1 LSB10connect to DAC/ DAC valuepad/VDD/VSS (10 bits)

81


Table 5: VPC2 register bits.

definition of analogue V C0

info from VPC2HI info from VPC2LO

MSB07 6 5 4 3 2 1 MSB00 LSB07 6 5 4 3 2 1 LSB00connect to DAC/ DAC valuepad/VDD/VSS (10 bits)

82


VPC1LO 64

Description: Set the register LSB1 for the Pulsed Capacitor calibration circuit.

Format: 01101001 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. The value of VPC1LO, along with the two least significant bit of VPC1HI (see sect. 3.9.2)form a 10-bit number, which will be converted in an analogue value. The 10-bit number will beformed in this way:

VPC1HI1 VPC1HI0 VPC1LO7 VPC1LO6 . . . . . . . . . . . . VPC1LO1 VPC1LO0

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

where D = [ D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ] is the 10-bit number, which will be convertedto an analogue value. Refer to table 6 for the relation between the 10-bit input number and theanalogue value Notice that this command only sets the internal DAC to generate the analoguevalue: it does not pass the generated analogue value to the AGIPD core. The remaining bits ofMSB1 determine, if the DAC-generated analogue value is actually used or not (see sect. 3.9.2).

Table 6: AGIPD 1.0 & AGIPD 1.1 Bias DACs for V PCstepper.

DAC Output DAC Output DAC Output DAC OutputValue Voltage [V] Value Voltage [V] Value Voltage [V] Value Voltage [V]

0 0.01110 256 0.19600 512 0.52440 768 0.85990

1 0.01120 257 0.19720 513 0.52570 769 0.86120

2 0.01120 258 0.19850 514 0.52700 770 0.86260

3 0.01130 259 0.19970 515 0.52830 771 0.86390

4 0.01140 260 0.20100 516 0.52960 772 0.86520

5 0.01150 261 0.20220 517 0.53090 773 0.86650

6 0.01150 262 0.20350 518 0.53220 774 0.86780

7 0.01160 263 0.20470 519 0.53350 775 0.86910

8 0.01170 264 0.20600 520 0.53480 776 0.87050

9 0.01180 265 0.20720 521 0.53610 777 0.87180

10 0.01190 266 0.20850 522 0.53740 778 0.87310

11 0.01200 267 0.20970 523 0.53870 779 0.87440

12 0.01210 268 0.21100 524 0.54000 780 0.87570

13 0.01220 269 0.21230 525 0.54130 781 0.87700

14 0.01230 270 0.21350 526 0.54260 782 0.87840

15 0.01240 271 0.21480 527 0.54390 783 0.87970

16 0.01250 272 0.21600 528 0.54520 784 0.88100

17 0.01260 273 0.21730 529 0.54650 785 0.88230

18 0.01270 274 0.21850 530 0.54790 786 0.88360

19 0.01280 275 0.21980 531 0.54920 787 0.88490

20 0.01290 276 0.22110 532 0.55050 788 0.88630

21 0.01300 277 0.22230 533 0.55180 789 0.88760

22 0.01320 278 0.22360 534 0.55310 790 0.88890

23 0.01330 279 0.22490 535 0.55440 791 0.89020

24 0.01340 280 0.22610 536 0.55570 792 0.89150

25 0.01350 281 0.22740 537 0.55700 793 0.89280

26 0.01370 282 0.22860 538 0.55830 794 0.89410

27 0.01380 283 0.22990 539 0.55960 795 0.89550

28 0.01390 284 0.23120 540 0.56090 796 0.89680

29 0.01410 285 0.23240 541 0.56220 797 0.89810

30 0.01420 286 0.23370 542 0.56350 798 0.89940

31 0.01440 287 0.23500 543 0.56480 799 0.90070

64VPC1LO is an acronym for the Pulsed Capacitor Voltage input LSB1

83


Table 6: AGIPD 1.0 & AGIPD 1.1 Bias DACs for V PCstepper — contd.


32 0.01450 288 0.23620 544 0.56610 800 0.90200

33 0.01470 289 0.23750 545 0.56740 801 0.90340

34 0.01480 290 0.23870 546 0.56870 802 0.90470

35 0.01500 291 0.24000 547 0.57000 803 0.90600

36 0.01520 292 0.24130 548 0.57130 804 0.90730

37 0.01530 293 0.24250 549 0.57260 805 0.90860

38 0.01550 294 0.24380 550 0.57400 806 0.90990

39 0.01570 295 0.24510 551 0.57530 807 0.91120

40 0.01590 296 0.24630 552 0.57660 808 0.91260

41 0.01610 297 0.24760 553 0.57790 809 0.91390

42 0.01630 298 0.24890 554 0.57920 810 0.91520

43 0.01650 299 0.25010 555 0.58050 811 0.91650

44 0.01660 300 0.25140 556 0.58180 812 0.91780

45 0.01690 301 0.25270 557 0.58310 813 0.91910

46 0.01710 302 0.25390 558 0.58440 814 0.92050

47 0.01730 303 0.25520 559 0.58570 815 0.92180

48 0.01750 304 0.25650 560 0.58700 816 0.92310

49 0.01770 305 0.25780 561 0.58830 817 0.92440

50 0.01790 306 0.25900 562 0.58960 818 0.92570

51 0.01820 307 0.26030 563 0.59090 819 0.92700

52 0.01840 308 0.26160 564 0.59220 820 0.92840

53 0.01860 309 0.26280 565 0.59360 821 0.92970

54 0.01890 310 0.26410 566 0.59490 822 0.93100

55 0.01910 311 0.26540 567 0.59620 823 0.93230

56 0.01940 312 0.26660 568 0.59750 824 0.93360

57 0.01960 313 0.26790 569 0.59880 825 0.93490

58 0.01990 314 0.26920 570 0.60010 826 0.93620

59 0.02020 315 0.27050 571 0.60140 827 0.93760

60 0.02040 316 0.27170 572 0.60270 828 0.93890

61 0.02070 317 0.27300 573 0.60400 829 0.94020

62 0.02100 318 0.27430 574 0.60530 830 0.94150

63 0.02130 319 0.27560 575 0.60660 831 0.94280

64 0.02160 320 0.27680 576 0.60790 832 0.94410

65 0.02190 321 0.27810 577 0.60920 833 0.94540

66 0.02220 322 0.27940 578 0.61050 834 0.94680

67 0.02250 323 0.28060 579 0.61180 835 0.94810

68 0.02280 324 0.28190 580 0.61320 836 0.94940

69 0.02320 325 0.28320 581 0.61450 837 0.95070

70 0.02350 326 0.28450 582 0.61580 838 0.95200

71 0.02380 327 0.28570 583 0.61710 839 0.95330

72 0.02420 328 0.28700 584 0.61840 840 0.95460

73 0.02450 329 0.28830 585 0.61970 841 0.95600

74 0.02490 330 0.28960 586 0.62100 842 0.95730

75 0.02520 331 0.29080 587 0.62230 843 0.95860

76 0.02560 332 0.29210 588 0.62360 844 0.95990

77 0.02600 333 0.29340 589 0.62490 845 0.96120

78 0.02640 334 0.29470 590 0.62620 846 0.96250

79 0.02670 335 0.29600 591 0.62760 847 0.96390

80 0.02710 336 0.29720 592 0.62890 848 0.96520

81 0.02750 337 0.29850 593 0.63020 849 0.96650

82 0.02800 338 0.29980 594 0.63150 850 0.96780

83 0.02840 339 0.30110 595 0.63280 851 0.96910

84




84 0.02880 340 0.30230 596 0.63410 852 0.97040

85 0.02920 341 0.30360 597 0.63540 853 0.97170

86 0.02970 342 0.30490 598 0.63670 854 0.97310

87 0.03010 343 0.30620 599 0.63800 855 0.97440

88 0.03050 344 0.30750 600 0.63930 856 0.97570

89 0.03100 345 0.30870 601 0.64070 857 0.97700

90 0.03150 346 0.31000 602 0.64200 858 0.97830

91 0.03190 347 0.31130 603 0.64330 859 0.97960

92 0.03240 348 0.31260 604 0.64460 860 0.98090

93 0.03290 349 0.31390 605 0.64590 861 0.98230

94 0.03340 350 0.31510 606 0.64720 862 0.98360

95 0.03390 351 0.31640 607 0.64850 863 0.98490

96 0.03440 352 0.31770 608 0.64980 864 0.98620

97 0.03490 353 0.31900 609 0.65110 865 0.98750

98 0.03540 354 0.32030 610 0.65240 866 0.98880

99 0.03600 355 0.32150 611 0.65380 867 0.99010

100 0.03650 356 0.32280 612 0.65510 868 0.99140

101 0.03710 357 0.32410 613 0.65640 869 0.99280

102 0.03760 358 0.32540 614 0.65770 870 0.99410

103 0.03820 359 0.32670 615 0.65900 871 0.99540

104 0.03880 360 0.32800 616 0.66030 872 0.99670

105 0.03930 361 0.32920 617 0.66160 873 0.99800

106 0.03990 362 0.33050 618 0.66290 874 0.99930

107 0.04050 363 0.33180 619 0.66420 875 1.00100

108 0.04110 364 0.33310 620 0.66560 876 1.00200

109 0.04180 365 0.33440 621 0.66690 877 1.00300

110 0.04240 366 0.33570 622 0.66820 878 1.00500

111 0.04300 367 0.33690 623 0.66950 879 1.00600

112 0.04360 368 0.33820 624 0.67080 880 1.00700

113 0.04430 369 0.33950 625 0.67210 881 1.00900

114 0.04490 370 0.34080 626 0.67340 882 1.01000

115 0.04560 371 0.34210 627 0.67470 883 1.01100

116 0.04630 372 0.34340 628 0.67600 884 1.01200

117 0.04700 373 0.34460 629 0.67740 885 1.01400

118 0.04760 374 0.34590 630 0.67870 886 1.01500

119 0.04830 375 0.34720 631 0.68000 887 1.01600

120 0.04900 376 0.34850 632 0.68130 888 1.01800

121 0.04980 377 0.34980 633 0.68260 889 1.01900

122 0.05050 378 0.35110 634 0.68390 890 1.02000

123 0.05120 379 0.35240 635 0.68520 891 1.02200

124 0.05190 380 0.35360 636 0.68650 892 1.02300

125 0.05270 381 0.35490 637 0.68790 893 1.02400

126 0.05340 382 0.35620 638 0.68920 894 1.02600

127 0.05420 383 0.35750 639 0.69050 895 1.02700

128 0.05490 384 0.35870 640 0.69170 896 1.02800

129 0.05570 385 0.36000 641 0.69310 897 1.02900

130 0.05650 386 0.36130 642 0.69440 898 1.03100

131 0.05730 387 0.36260 643 0.69570 899 1.03200

132 0.05810 388 0.36390 644 0.69700 900 1.03300

133 0.05890 389 0.36520 645 0.69830 901 1.03500

134 0.05970 390 0.36650 646 0.69960 902 1.03600

135 0.06050 391 0.36780 647 0.70090 903 1.03700

85




136 0.06140 392 0.36900 648 0.70220 904 1.03900

137 0.06220 393 0.37030 649 0.70360 905 1.04000

138 0.06310 394 0.37160 650 0.70490 906 1.04100

139 0.06390 395 0.37290 651 0.70620 907 1.04300

140 0.06480 396 0.37420 652 0.70750 908 1.04400

141 0.06560 397 0.37550 653 0.70880 909 1.04500

142 0.06650 398 0.37680 654 0.71010 910 1.04700

143 0.06740 399 0.37810 655 0.71140 911 1.04800

144 0.06830 400 0.37940 656 0.71270 912 1.04900

145 0.06920 401 0.38070 657 0.71410 913 1.05000

146 0.07010 402 0.38190 658 0.71540 914 1.05200

147 0.07100 403 0.38320 659 0.71670 915 1.05300

148 0.07190 404 0.38450 660 0.71800 916 1.05400

149 0.07290 405 0.38580 661 0.71930 917 1.05600

150 0.07380 406 0.38710 662 0.72060 918 1.05700

151 0.07470 407 0.38840 663 0.72190 919 1.05800

152 0.07570 408 0.38970 664 0.72330 920 1.06000

153 0.07660 409 0.39100 665 0.72460 921 1.06100

154 0.07760 410 0.39230 666 0.72590 922 1.06200

155 0.07860 411 0.39360 667 0.72720 923 1.06400

156 0.07950 412 0.39480 668 0.72850 924 1.06500

157 0.08050 413 0.39610 669 0.72980 925 1.06600

158 0.08150 414 0.39740 670 0.73110 926 1.06800

159 0.08250 415 0.39870 671 0.73250 927 1.06900

160 0.08350 416 0.40000 672 0.73380 928 1.07000

161 0.08450 417 0.40130 673 0.73510 929 1.07100

162 0.08550 418 0.40260 674 0.73640 930 1.07300

163 0.08650 419 0.40390 675 0.73770 931 1.07400

164 0.08760 420 0.40520 676 0.73900 932 1.07500

165 0.08860 421 0.40650 677 0.74030 933 1.07700

166 0.08960 422 0.40780 678 0.74160 934 1.07800

167 0.09070 423 0.40910 679 0.74300 935 1.07900

168 0.09170 424 0.41030 680 0.74430 936 1.08100

169 0.09280 425 0.41160 681 0.74560 937 1.08200

170 0.09380 426 0.41290 682 0.74690 938 1.08300

171 0.09490 427 0.41420 683 0.74820 939 1.08500

172 0.09590 428 0.41550 684 0.74950 940 1.08600

173 0.09700 429 0.41680 685 0.75080 941 1.08700

174 0.09810 430 0.41810 686 0.75220 942 1.08800

175 0.09920 431 0.41940 687 0.75350 943 1.09000

176 0.10030 432 0.42070 688 0.75480 944 1.09100

177 0.10140 433 0.42200 689 0.75610 945 1.09200

178 0.10250 434 0.42330 690 0.75740 946 1.09400

179 0.10360 435 0.42460 691 0.75870 947 1.09500

180 0.10470 436 0.42590 692 0.76000 948 1.09600

181 0.10580 437 0.42720 693 0.76140 949 1.09800

182 0.10690 438 0.42850 694 0.76270 950 1.09900

183 0.10800 439 0.42980 695 0.76400 951 1.10000

184 0.10910 440 0.43110 696 0.76530 952 1.10100

185 0.11030 441 0.43240 697 0.76660 953 1.10300

186 0.11140 442 0.43360 698 0.76790 954 1.10400

187 0.11250 443 0.43490 699 0.76920 955 1.10500

86




188 0.11370 444 0.43620 700 0.77060 956 1.10700

189 0.11480 445 0.43750 701 0.77190 957 1.10800

190 0.11600 446 0.43880 702 0.77320 958 1.10900

191 0.11710 447 0.44010 703 0.77450 959 1.11100

192 0.11820 448 0.44140 704 0.77580 960 1.11200

193 0.11940 449 0.44270 705 0.77710 961 1.11300

194 0.12060 450 0.44400 706 0.77840 962 1.11500

195 0.12170 451 0.44530 707 0.77970 963 1.11600

196 0.12290 452 0.44660 708 0.78110 964 1.11700

197 0.12410 453 0.44790 709 0.78240 965 1.11800

198 0.12520 454 0.44920 710 0.78370 966 1.12000

199 0.12640 455 0.45050 711 0.78500 967 1.12100

200 0.12760 456 0.45180 712 0.78630 968 1.12200

201 0.12880 457 0.45310 713 0.78760 969 1.12400

202 0.12990 458 0.45440 714 0.78900 970 1.12500

203 0.13110 459 0.45570 715 0.79030 971 1.12600

204 0.13230 460 0.45700 716 0.79160 972 1.12800

205 0.13350 461 0.45830 717 0.79290 973 1.12900

206 0.13470 462 0.45960 718 0.79420 974 1.13000

207 0.13590 463 0.46090 719 0.79550 975 1.13100

208 0.13710 464 0.46220 720 0.79680 976 1.13300

209 0.13830 465 0.46350 721 0.79820 977 1.13400

210 0.13950 466 0.46480 722 0.79950 978 1.13500

211 0.14070 467 0.46610 723 0.80080 979 1.13700

212 0.14190 468 0.46740 724 0.80210 980 1.13800

213 0.14310 469 0.46870 725 0.80340 981 1.13900

214 0.14430 470 0.47000 726 0.80470 982 1.14100

215 0.14550 471 0.47130 727 0.80610 983 1.14200

216 0.14670 472 0.47250 728 0.80740 984 1.14300

217 0.14790 473 0.47380 729 0.80870 985 1.14400

218 0.14910 474 0.47510 730 0.81000 986 1.14600

219 0.15040 475 0.47640 731 0.81130 987 1.14700

220 0.15160 476 0.47770 732 0.81260 988 1.14800

221 0.15280 477 0.47900 733 0.81400 989 1.15000

222 0.15400 478 0.48030 734 0.81530 990 1.15100

223 0.15520 479 0.48160 735 0.81660 991 1.15200

224 0.15640 480 0.48290 736 0.81790 992 1.15300

225 0.15770 481 0.48420 737 0.81920 993 1.15500

226 0.15890 482 0.48550 738 0.82050 994 1.15600

227 0.16010 483 0.48680 739 0.82180 995 1.15700

228 0.16130 484 0.48810 740 0.82320 996 1.15900

229 0.16260 485 0.48940 741 0.82450 997 1.16000

230 0.16380 486 0.49070 742 0.82580 998 1.16100

231 0.16500 487 0.49200 743 0.82710 999 1.16300

232 0.16630 488 0.49330 744 0.82840 1000 1.16400

233 0.16750 489 0.49460 745 0.82970 1001 1.16500

234 0.16870 490 0.49590 746 0.83110 1002 1.16600

235 0.17000 491 0.49730 747 0.83240 1003 1.16800

236 0.17120 492 0.49860 748 0.83370 1004 1.16900

237 0.17240 493 0.49990 749 0.83500 1005 1.17000

238 0.17370 494 0.50120 750 0.83630 1006 1.17200

239 0.17490 495 0.50250 751 0.83760 1007 1.17300

87




240 0.17610 496 0.50380 752 0.83900 1008 1.17400

241 0.17740 497 0.50510 753 0.84030 1009 1.17500

242 0.17860 498 0.50640 754 0.84160 1010 1.17700

243 0.17990 499 0.50770 755 0.84290 1011 1.17800

244 0.18110 500 0.50900 756 0.84420 1012 1.17900

245 0.18240 501 0.51030 757 0.84550 1013 1.18100

246 0.18360 502 0.51160 758 0.84690 1014 1.18200

247 0.18480 503 0.51290 759 0.84820 1015 1.18300

248 0.18610 504 0.51420 760 0.84950 1016 1.18400

249 0.18730 505 0.51550 761 0.85080 1017 1.18600

250 0.18860 506 0.51680 762 0.85210 1018 1.18700

251 0.18980 507 0.51810 763 0.85340 1019 1.18800

252 0.19110 508 0.51940 764 0.85480 1020 1.19000

253 0.19230 509 0.52070 765 0.85610 1021 1.19100

254 0.19360 510 0.52200 766 0.85740 1022 1.19200

255 0.19480 511 0.52330 767 0.85870 1023 1.19300

Dependencies:

Depends upon:VPC1HI , VPC2LO , VPC2HI

88


VPC1HI 65

Description: Set the register MSB1 for the Pulsed Capacitor calibration circuit.

Format: 01101010 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. The two least significant bits of VPC1HI, along with the value of VPC1LO (see sect. 3.9.2)form a 10-bit number, which will be converted to an analogue value. The 10-bit number will beformed in this way:


D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

where D = [ D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ] is the 10-bit number, which will be convertedto an analogue value. Refer to tab. 6 for the relation between the 10-bit input number and theanalogue valueThe 6 most significant bits of MSB1 will determine, if the DAC-generated analogue value is passedto the AGIPD core.

VPC1HI7 VPC1HI6 VPC1HI5 VPC1HI4 VPC1HI3 VPC1HI2 analogue voltage is

0 0 0 0 0 0 generated by the internal DAC0 0 1 1 0 0 shorted to external pad1 1 0 0 0 0 shorted to VDD0 0 0 0 1 1 shorted to VSS

anything else floating

Dependencies:

Depends upon:VPC1LO , VPC2LO , VPC2HI

65VPC1HI is an acronym for the Pulsed Capacitor Voltage input MSB1

89


VPC2LO 66

Description: Set the register LSB0 for the Pulsed Capacitor calibration circuit.

Format: 01101011 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. The value of VPC2LO, along with the two least significant bit of VPC2HI (see sect 3.9.2)form a 10-bit number, which will be converted to an analogue value. The 10-bit number will beformed in this way:


D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

where D = [ D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ] is the 10-bit number, which will be convertedto an analogue value. Refer to the table 6 for the relation between the 10-bit input number andthe analogue value Notice that this command only sets the internal DAC to generate the analoguevalue: it does not pass the generated analogue value to the AGIPD core. The remaining bits ofMSB0 determine if the DAC-generated analogue value is actually used or not (see sect. 3.9.2)

Dependencies:

Depends upon:VPC1LO , VPC1HI , VPC2HI

66VPC2LO is an acronym for the Pulsed Capacitor Voltage input LSB0

90


VPC2HI 67

Description: Set the register MSB0 for the Pulsed Capacitor calibration circuit.

Format: 01101100 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theDAC. The two least significant bits of VPC2HI, along with the value of VPC12LO (see sect. 3.9.2)form a 10-bit number, which will be converted in an analogue value. The 10-bit number will beformed in this way:


D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

where D = [ D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ] is the 10-bit number, which will be convertedto an analogue value. Refer to table 6 for the relation between the 10-bit input number and theanalogue valueThe 6 most significant bits of MSB0 will determine if the DAC-generated analogue value is passedto the AGIPD core.

VPC2HI7 VPC2HI6 VPC2HI5 VPC2HI4 VPC2HI3 VPC2HI2 analogue voltage is

0 0 0 0 0 0 generated by the internal DAC0 0 1 1 0 0 shorted to external pad1 1 0 0 0 0 shorted to VDD0 0 0 0 1 1 shorted to VSS

anything else floating

Dependencies:

Depends upon:VPC1LO , VPC1HI , VPC2LO

67VPC2HI is an acronym for the Pulsed Capacitor Voltage input MSB0

91


SWPXBI 68

Description: Define whether the bias values for Ibn comp, vth comp, Ibp cds, vref cds,ibn pixbuf, vref pixbuf, vcascp pixbuf, ibp colbuf are taken from the bias DACs or from the externalpads

Format: 01101101 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theregister. The command determine whether the internal-DAC-generated anaolg values are used tobias the AGIPD ASIC, or if the bias current/voltages are rertieved by external pads. It does thatrecording values on a 8-bit register: each bit on those register keep track on whether one of thebias value is retreived from the internal DAC or from the appropriate output pad. If a ”1” isstored in the register, then that bias is taken from the internal DAC; if instead a ”0” is stored inthe register, then that bias is rertieved from an external pad. The command affects the AGIPDbias in the way described in table 7.

Table 7: AGIPD 1.0 & AGIPD 1.1 bias switches (pixel related cur-rents and voltages).

SWPXBI affected bias

7 (MSB) ibp colbuf

6 vcascp pixbuf

5 vref pixbuf

4 ibn pixbuf

3 vref cds

2 ibp cds

1 vth comp

0 (LSB) ibn comp

where SWPXBI= [SWPXBI7 SWPXBI6 SWPXBI5 SWPXBI4 SWPXBI3 RSWPXBI2SWPXBI1 SWPXBI0 ] is the 8-bit value defined for that register.The PowerUp Reset circuit should guarantee that at startup all the bits in the registers are set to”1” (i.e. all the biases are driven by the internal DACs)

Dependencies:

Depends upon:IBPCOL, VCAPXB, VRFPXB, IBNPXB, VRFCDS, IBPCDS, VTHCMP, IBNCMP

68SWPXBI is an acronym for the pixel bias switches

92


SWROBI 69

Description: Define whether the bias values for ibn cob, ibp cob, ibn fda, ibn prebuf, ibp prebuf,vcom chipbuf, Vcasc chipbuf, Vref chipbuf are taken from the bias DACs or from the external pads

Format: 01101110 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theregister. The command determine whether the internal-DAC-generated anaolg values are used tobias the AGIPD ASIC, or if the bias current/voltages are rertieved by external pads. It does thatrecording values on a 8-bit register: each bit on those register keep track on whether one of thebias value is retreived from the internal DAC or from the appropriate output pad. If a ”1” isstored in the register, then that bias is taken from the internal DAC; if instead a ”0” is stored inthe register, then that bias is rertieved from an external pad. The command affects the AGIPDbias in the way described in tabele 8.

Table 8: AGIPD 1.0 & AGIPD 1.1 bias switches (off-chip driver re-lated currents and voltages).

SWROBI affected bias

7 (MSB) vref chipbuf

6 vcasc chipbuf

5 vcom chipbuf

4 ibp prebuf

3 ibn prebuf

2 ibn fda

1 ibp cob

0 (LSB) ibn cob

where SWROBI= [SWROBI7 SWROBI6 SWROBI5 SWROBI4 SWROBI3 SWROBI2SWROBI1 SWROBI0 ] is the 8-bit value defined for that register.The PowerUp Reset circuit should guarantee that at startup all the bits in the registers are set to”1” (i.e. all the biases are driven by the internal DACs)

Dependencies:

Depends upon:VCACHB, VCMCHB, IBPPRB, IBNPRB, IBNFDA, IBPCOB, IBNCOB

69SWROBI is an acronym for the readout bias switches

93


SWCALV 70

Description: Define whether the bias values for Ibn lvds, Ibp lvds, I testcurr are taken fromthe bias DACs or from the external pads

Format: 01101111 VVVVVVVV with V = VVVVVVVV representing the 8-bit input value for theregister. The command determine whether the internal-DAC-generated anaolg values are used tobias the AGIPD ASIC, or if the bias current/voltages are rertieved by external pads. It does thatrecording values on a 8-bit register: each bit on those register keep track on whether one of thebias value is retreived from the internal DAC or from the appropriate output pad. If a ”1” isstored in the register, then that bias is taken from the internal DAC; if instead a ”0” is stored inthe register, then that bias is rertieved from an external pad. The command affects the AGIPDbias in the way described in tabele 9.

Table 9: AGIPD 1.0 & AGIPD 1.1 bias switches (calibration andLVDS related currents and voltages).

SWCALV affected bias

7 (MSB) not used6 not used5 not used4 not used3 not used2 Itest curr

1 ibp lvds

0 (LSB) ibn lvds

where SWCALV= [SWCALV7 SWCALV6 SWCALV5 SWCALV4 SWCALV3 SWCALV2

SWCALV1 SWCALV0 ] is the 8-bit value defined for that register.The PowerUp Reset circuit should guarantee that at startup all the bits in the registers are set to”1” (i.e. all the biases are driven by the internal DACs)

Dependencies:

Depends upon:ITESTC, IBPLVD, IBNLVD

4 Differences between AGIPD 1.1 and AGIPD 1.0

AGIPD 1.1 differs from AGIPD 1.0 in the following parts:

4.1 Handling of gain information

The levels encoding the gain of the preamplifier have been changed:

AGIPD 1.0 AGIPD 1.1

Gain Level Voltage Level Voltage

high VSS 0V 1

2VDD 0.75V

medium 2

3VDD 1.0V 3

4VDD 1.125V

low VDD 1.5V VDD 1.5V

70SWCALV is an acronym for the calibration and LVDS bias switches

94


Since these voltages are written to the analogue memory via p-mos switches, the lowest voltageon a storage cell is ≈ VSS−Vth = |Vth|

71, the voltage to encode high gain was chosen Vgain=high ≫|Vth| on AGIPD 1.1 – also to provide some margin for radiation induced changes of Vth. Furthermorethe sensitivity of the pixel buffer for gain data readout is doubled on AGIPD 1.1, in order to achievea better separation of the levels. In Addition the encoded gain information is also stored in fixedgain mode, i.e. according to set gain1 and set gain2 bits if also the en ext gain bit in thesetup register is set.

4.2 Calibration Circuits

The current source injection circuit (c.f. sect. 3.8.3) has been modified to provide also access to thehigh gain mode of the preamplifier. To achieve this a modified current mirror was implemented. Itdroped the enclosed layout implemented on AGIPD 1.0 (which always features W

L≫ 1) in favour

of a linear one with a more conservative W

L-ratio of ≈ 1. Drawback is an increased sensitivity to

radiation damage, from which a need for more frequent cross- and re-calibration can be expected.

4.3 Readout Speed and ”Ghosting”

AGIPD 1.0 suffered from a relatively low readout speed and crosstalk between the four readoutports.

4.3.1 Readout Speed

Readout of AGIPD 1.0 with reasonable performance could only be achieved at relatively low read-out speeds. This was caused by an unfortunate combination of parasitic resistances and capaci-tances in the readout path. These were also different for the four ports, resulting in an apparentlydifferent performance of the four pixel blocks. Parasitic simulations reproduced the issue andrevealed, that the interconnect from the pixel column multiplexer to the off-chip driver was re-sponsible. On AGIPD 1.1 the parasitic capacitance was much reduced by decreasing the widthof the metal traces involved, while the impact of series resistance was reduced by ”stacking”connection lines. Both changes were confirmed with simulations.

4.3.2 ”Ghosting”

A relatively large cross-talk of opposite polarity was observed between the four output ports. Theseare driven by fully differential amplifiers with resistive feedback (also known as instrumentation

amplifiers). While the readout signal is fed to the corresponding NFB path via a buffer amplifier,a static offset is provided to the other branch. It is provided from a common on-chip DAC anda single buffer for all four drivers in parallel. Due to the finite impedance of the connections andthe offset buffer, any signal on one port induces a weaker signal of opposite polarity on the other3 ports. On AGIPD 1.1 this problem was solved by inserting the same type of buffer, as it is usedin the signal branch into the offset branch of each port. This way the off-chip driver obtained acompletely symmetric topology and the offset inputs where effectively decoupled.

4.4 Power Distribution and Routing

A pedestal map of AGIPD 1.0’s memory featured characteristic ’stripes’ for certain rows andcolumns, which for some cases also depended on weather and which test signal injection methodwas chosen. Parasitic extraction revealed excessive capacitive coupling of several memory controllines to the preamplifier input. Similar couplings were found for some of the test pulse injectioncircuitry. This coupling was reduced by re-routing of these signals and shielding of sensitive nodesto a negligible level.An inhomogeneous pedestal structure was also observed for the pixel matrix on AGIPD 1.0. Unlike

71since Vth ≤ 0 for p-mos FETs

95


the ’memory map’ this pedestal structure varied between chips. As a reason the (parasitic) resis-tance of the power supply and ground routing was identified: It was dominated by via resistances,which could contribute between a few ohms to some 10W from the global power distribution to theactive part of an individual pixel. On AGIPD 1.1 the area of interconnect vias was vastly increasedand the global power supply layers were arranged as a real mesh – reducing the resistance byabout one order of magnitude.

5 Proposed Algorithm for Data Acquisition

The following section describes – in a human-readable meta language – the sequence to initialiseAGIPD 1.0 (& AGIPD 1.1), to record 352 frames, to selectively overwrite recorded images, if thesehave been vetoed, and the readout sequence of all 352 frames. Numbers are in decimal notation,unless prefixed by a base identifier.

The actual commands to be sent to the AGIPD 1.0 (& AGIPD 1.1) ASIC are noted in assemblylanguage style, eg. ACQMEM 31 actually means 16′b1000001000000000∨ 16′b0000000000011111 =16′b1000001000011111 or 2′x8200∨ 2′x001F = 2′x821F. according to sect. 3.9.2.

integer frame, row; \ frame number, (readout) pixel row

integer vetoed, vetoptr; \ number of vetoed addresses, pointer to

\ last vetoed address

integer[2700] vframe; \ array holding vetoed addresses

boolean Train; \ ext. bunch train signal

boolean Run; \ ext. run control signal

boolean Veto; \ ext. veto signal

integer Vetoaddr \ external address to be overwritten by veto

frame = 0;

row = 0;

vetoed = 0;

vetoptr = 0;

SETUPR 8’b10001000; \ reset the chip and set DS gain high

RSDLYW 10; \ setup the default timings for

RSGATW 11; \ European-XFEL operation:

RSDLYR 11; \ system clock = 100MHz

RPDLYW 9; \ 4.5MHz bunch rate = 24 clock cycles / bunch

RPGATW 13; \ readout at 33MHz pixel clock

RPDLYR 1; \ timings/clocks are (unlike in an HDL

CSDLYW 8; \ description) not explicitly included

CSGATW 12; \ in the algorithm

CSDLYR 10;

DS1DLY 8;

DS1GAT 14;

RSTDLY 8;

RSTGAT 14;

G1SDLY 5;

G1SGAT 17;

G2SDLY 6;

G2SGAT 16;

EGSDLY 7;

EGSGAT 15;

PXBDLY 8;

96


TSTDLY 12;

TSTGAT 4;

MUXDIV 7;

TIROWM 240;

TICOLM 15;

VRFCDS 112; \ Biases and voltages are set to

IBNPXB 128; \ default values

VRFPXB 167;

VCAPXB 193;

IBPCOL 149;

IBNCOB 184;

IBPCOB 102;

IBNFDA 160;

IBNPRB 95;

IBPPRB 98;

VCMCHB 148;

VCACHB 93;

VRFCHB 180;

IBNLVD 171;

IBPLVD 202;

ITESTC 151;

IBNCMP 139;

VTHCMP 112;

IBPCDS 211;

VPC1LO 0;

VPC1HI 252;

VPC2LO 0;

VPC2HI 252;

SWPXBI 0; \> to be confirmed

SWROBI 0; \> to be confirmed

SWCALV 0; \> to be confirmed

while(Run) \ Run control signals data taking

begin

while(not Train); \ wait for a bunch train

while(Train)

begin

if(frame < 352) \ record the first 352 frames in order

begin

ACQMEM frame; \ record the frame

frame++;

if(Veto) \ if there is a veto

begin

vframe[vetoed] = Vetoaddr; \ store vetoed address

vetoed++;

end

end

else \ overwrite vetoed addresses

begin

if(vetoptr < vetoed) \ valid address available

begin

97


ACQMEM vframe[vetoptr]; \ record the frame

vetoptr++;

end

if(Veto) \ if there is a veto

begin

vframe[vetoed] = Vetoaddr; \ store vetoed address

vetoed++;

end

end

end

for(frame < 352, frame = 0, frame++) \ read amplitude values of all frames

begin

SETMEM frame;

RPAMPN 0 0; \ precharge first row

for(row < 62, row = 0, row ++)

RPAMPA (row+1) row; \ mux row and precharge row+1

RPNMPA 0 63; \ mux last row

end

for(frame < 352, frame = 0, frame++) \ read gain values of all frames

begin

SETMEM frame;

RPDMPN 0 0; \ precharge first row

for(row < 62, row = 0, row ++)

RPDMPD (row+1) row; \ mux row and precharge row+1

RPNMPD 0 63; \ mux last row

end

frame = 0; \ reset variables

row = 0;

vetoed = 0;

vetoptr = 0;

end

6 List of known Problems and Bugs

6.1 Issues of AGIPD 1.0

� Low bandwidth of some readout ports.

The -3 dB bandwidth of the four analogue readout ports is 188.7MHz, 59.0MHz, 34.9MHzand 24.4MHz due to the parasitic capacitance of the interconnect between the column bufferand the off-chip driver. The bandwithh of 3 ports is too low for a readout speed of 33MHz,while a readout at 10MHz is feasible – in terms of bandwidth as well as compatibility withEuropean XFEL timings.Fixed by largely reduced and balanced paracitics of the interconnect on AGIPD 1.1.

� ”Ghosting” crosstalk between readout ports.

Large signals on one output port induce signals of opposite polarity on the three other ones.Reason for this behaviour is the unbuffered parallel connection of vref chipbuf to the resistivefeedback of the off-chip driver amplifiers.Fixed by individual buffers for vref chipbuf at each output port on AGIPD 1.1.

� High gain range not accessible via the current source injection circuit

Even with ITSTC set for minimum current (i.e. 255) and TSTGAT to minimum (1 clock cycleof 100 ns) the injected charge will switch the preamplifier into medium gain mode. Therefore

98


cross-calibration with the capacitor charge injection circuit – which just reaches the mediumgain – is difficult.

6.2 Issues still present in AGIPD 1.1

� PN-junction between storage cell and floating n-well can turn into forward bias.

If the readout-related switches are operated in the intuitive sequence (ROW PCH, COL SEL,RST PIXBUF, ROW SEL), the PN-junction between storage cell and floating n-well canturn into forward bias, if vref pixbuf is lower than the voltage on the storage capacitor (e.g.VDD encoding low gain). This results in a deterioration of analogue performance and a poorseparation of the levels encoding medium and low gain. The same effect can occur duringwrite cycles if ROW PCH or COL SEL are not released before RST PREAMP (or the endof the write cycle).Workarounds

Operation of the switches in the correct order: ROW PCH, RST PIXBUF, COL SEL,ROW SEL.

� To be confirmed: Truncated last pulse of a readout sequence.

The duration of the readout commands RPAMPA, RPNMPA, RPDMPD and RPNMPD isactually about 1 . . . 2 clock cycles (depending on MUXDIV) longer than 16 × (MUXDIV + 1).For consecutive readout commands (RPAMPA, RPDMPD) this has no effect (except for aconstat pahse shift of the readout wrt. to SoB). For the last readout in a sequence (usuallyRPNMPA 0 63 or RPNMPD 0 63 reading the bottom line of a frame), the readout data canbe truncated.Workarounds

1. Delay the next command (i.e. SoB) by 1 . . . 2 clock cycles.2. Continue reading (e.g. at the top of the frame) such that only meaningless data (whichhas been read already) is affected. E.g. changeRPAMPN 0 1RPAMPA 1 0. . .RPAMPA 63 62RPNMPA 0 63 ←− truncatedtoRPAMPN 0 1RPAMPA 1 0. . .RPAMPA 63 62RPAMPA 0 63RPNMPA 1 0 ←− truncated, but already read

99


A AGIPD 1.0 Pad Layout and Description

Figure 10: AGIPD 1.0 Pad Layout

100


Table 11: AGIPD 1.0 & AGIPD 1.1 Wirebond Pad Description. All wire-bond pads are 174 µm×100µm, coordinates indicate the lower left padcorner wrt. the lower left chip corner.

Nr. Name X [µm] Y [µm] Type Description

bottom

B0 VSS 253.00 24.56 neg. power supply (0V)


B2 VDD Preamp 653.00 24.56 pos. power supply (1.5V) preamplifiers

B3 VDD analogue 853.00 24.56 pos. power supply (1.5V) analogue circuits

B4 VDD digital 1053.00 24.56 pos. power supply (1.5V) digital circuits

B5 VDD IO 1253.00 24.56 pos. power supply (1.5V) digital I/O and protection structures

B6 Clk p 1453.00 24.56 LVDS (pos.) input System clock

B7 Clk n 1653.00 24.56 LVDS (neg.) input System clock

B8 Data p 1853.00 24.56 LVDS (pos.) input Command data

B9 Data n 2053.00 24.56 LVDS (neg.) input Command data

B10 SoB p 2253.00 24.56 LVDS (pos.) input Start of bunch

B11 SoB n 2453.00 24.56 LVDS (neg.) input Start of Bunch

B12 CS 2653.00 24.56 LVCMOS input Chip select







B19 VDD Diode 4053.00 24.56 pos. power supply (> 1.5V) pixel input protection structures

B20 ibn comp 4253.00 24.56 Blocking comparator bias

B21 ibn pixbuf 4453.00 24.56 Blocking pixel buffer bias

B22 ibp cds 4653.00 24.56 Blocking CDS amplifier bias

B23 testcurr 4853.00 24.56 current input calibration signal

B24 ibn prebuf 5053.00 24.56 Blocking pre buffer bias

B25 ibn cob 5253.00 24.56 Blocking chip output buffer bias

B26 ibp cob 5453.00 24.56 Blocking chip output bias

B27 ibp LVDS 5653.00 24.56 Blocking/Bias LVDS input bias

B28 ibn LVDS 5853.00 24.56 Blocking/Bias LVDS input bias

B29 ibp prebuf 6053.00 24.56 Blocking pre buffer bias

B30 ibp colbuf 6253.00 24.56 Blocking column buffer bias

B31 ibp fda 6453.00 24.56 Blocking fda bias

B32 vth comp 6653.00 24.56 Blocking gain switching threshold level

B33 vref ds 6853.00 24.56 Blocking CDS baseline level

B34 vref pixbuf 7053.00 24.56 Blocking pixel buffer baseline level

B35 vcom chipbuf 7253.00 24.56 Blocking chip output offset level

B36 casc chipbuf 7453.00 24.56 Blocking chip output buffer cascode level

B37 cref chipbuf 7653.00 24.56 Blocking chip output buffer reference level

B38 vcascp pixbuf 7853.00 24.56 Blocking pixel buffer cascode level

B39 testcap 8053.00 24.56 analogue input charge injection voltage step

B40 PowerupReset 8253.00 24.56 special (N/C) power up reset internal node

B41 err 7453.00 24.56 LVCMOS (output) invalid column address error

B42 VDD Diode 7653.00 24.56 pos. power supply (> 1.5V) pixel input protection structures







B49 AOUT<0> p 9053.00 24.56 Diff. analogue output (pos.) readout signal < 0 >

101


Table 11: AGIPD 1.0 & AGIPD 1.1 Wirebond Pad Description — contd.


B50 AOUT<0> n 9253.00 24.56 Diff. analogue output (neg.) readout signal < 0 >













Table 12: AGIPD 1.0 & AGIPD 1.1 TSV Landing Pad Description. AllTSV landing pads are 100 µm×100 µm, coordinates indicate the centreof the pad wrt. the lower left chip corner.


TSV

T0 VSS 125.40 976.40 neg. power supply (0V)


T2 VDD Preamp 976.40 976.40 pos. power supply (1.5V) preamplifiers

T3 Clk p 1323.40 875.16 LVDS (pos.) input System clock

T4 Clk n 1683.40 875.16 LVDS (neg.) input System clock

T5 Data p 2043.40 875.16 LVDS (pos.) input Command data

T6 Data n 2403.40 875.16 LVDS (neg.) input Command data

T7 CS 2763.40 875.16 LVCMOS input Chip select

T8 SoB p 3106.40 983.70 LVDS (pos.) input Start of bunch

T9 SoB n 3463.40 983.70 LVDS (neg.) input Start of Bunch

T10 VDD IO 3924.00 875.16 pos. power supply (1.5V) digital I/O and protection structures

T11 VDD Diode 4284.00 875.16 pos. power supply (> 1.5V) pixel input protection structures

T12 VDD analogue 4644.00 875.16 pos. power supply (1.5V) analogue circuits

T13 VDD digital 5004.00 875.16 pos. power supply (1.5V) digital circuits









T22 PowerupReset 8244.00 875.16 special (N/C) power up reset internal node

T23 VDD Diode 8604.00 875.16 pos. power supply (> 1.5V) pixel input protection structures

T24 AOUT<0> p 8957.06 875.16 Diff. analogue output (pos.) readout signal < 0 >

T25 AOUT<0> n 9412.90 960.60 Diff. analogue output (neg.) readout signal < 0 >








102


Table 12: AGIPD 1.0 & AGIPD 1.1 TSV Landing Pad Description —contd.




Table 13: AGIPD 1.0 & AGIPD 1.1 Bumpbond Pad Description. Allbump-bond pads are 30µm diameter, coordinates indicate the centrewrt. the lower left chip corner.


core

C0 Pix<0> in 274.58 1578.36 analogue input Pixel < 0 >











































103


Table 13: AGIPD 1.0 & AGIPD 1.1 Bumpbond Pad Description — contd.























































104

























































105

























































106

























































107

























































108

























































109

























































110

























































111

























































112

























































113

























































114

























































115

























































116

























































117

























































118

























































119

























































120

























































121

























































122

























































123

























































124

























































125

























































126

























































127

























































128

























































129

























































130

























































131

























































132

























































133

























































134

























































135

























































136

























































137

























































138

























































139

























































140

























































141

























































142

























































143

























































144

























































145

























































146

























































147

























































148

























































149

























































150

























































151

























































152

























































153

























































154

























































155

























































156

























































157

























































158

























































159

























































160

























































161

























































162

























































163

























































164

























































165

























































166

























































167

























































168

























































169

























































170

























































171

























































172

























































173

























































174

























































175

























































176

























































177

























































178

























































179





























C4096 VSS 219.60 1479.36 analogue ground sensor bias ring connection




























180








































181


B AGIPD 1.1 Pad Layout and Description

Figure 11: AGIPD 1.1 Pad Layout

The pad layout of AGIPD 1.1 is identical to that of AGIPD 1.0, with the exception of threeadditional probe pads to characterise the power distribution across the ASIC. The shape of thesepads is identical to that of the bumpbond pads. Their positions are given in tab. 14.

In addition AGIPD 1.1 features two passivation openings intended as markers for alignmentpurposes in the bump-bonding process. Tab. 15 lists the positions of these markers.

182


Table 14: AGIPD 1.1 Test Pad Description. All test pads are 30µm diameter, coordinates indicatethe centre wrt. the lower left chip corner.


M0 VSS 12949.76 14171.69 neg. power supply (0V)M1 VDD Preamp 13002.39 14119.10 pos. power supply (1.5V) preamplifiersM2 VDD analogue 13038.62 14049.97 pos. power supply (1.5V) analogue circuits

Table 15: AGIPD 1.1 Alignment Markers. The passivation openings are 30µm × 30µm in size.The coordinates indicate the lower left corner wrt. the lower left chip corner.

Nr. X [µm] Y [µm]

A0 33.54 7603.40A1 13006.82 7603.40

References

[1] CMOS8RF (CMRF8SF) Design Manual V1.4.0.0, IBM Microelectronics Division,861A,1000 River St, EssexJunction, VT 05452-4299, ES 57P9006 (2007)

[1] The European XFEL http://www.xfel.eu/en/index.php

[2] TheAGIPD detector, http://hasylab.desy.de/science/developments/ detec-tors/agipd/index eng.html

[3] G. Potdevin et al., Performance simulation of a detector for 4th generation photon

sources: TheAGIPD , Nucl. Instrum. Meth. A 607 (2009) 51

[4] G. Potdevin et al., HORUS, an HPAD X-ray detector simulation program, 2009 JINST4 P09010

[5] J. Becker et al., Simulation study of the impact ofAGIPD design choices on X-ray Photon

Correlation Spectroscopy utilizing the intensity autocorrelation technique, J. Inst. 6 2011P11005

[6] B. Henrich et al., The Adaptive Gain Integrating Pixel DetectorAGIPD : A Detector for

the European XFEL, Proceedings of the 11th iWoRiD Conference, June 28 - July 2, 2009,Prague, Czech Republic, Nucl. Instrum. Meth. A 633 (2011) 11-14

[7] X. Shi et al., Challenges in chip design for theAGIPD detector, Nucl. Instrum. Meth. A624 (2010) 387-391

[8] J. Becker et al. Impact of plasma effects on the performance of silicon sensors at an X-ray

FEL, Nucl. Instrum. Meth. A 615 (2010) 230-236

[9] J. Zhang et al. Study of X-ray Radiation Damage in Silicon Sensors, Proceedings of the13th iWoRiD Conference, July 3-7 2011, Zurich, Switzerland, arXiv:1111.1180v1

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