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1© Synopsys 2011
Transition from Planar
MOSFETs to FinFETs and its
Impact on Design and Variability
Victor Moroz
2© Synopsys 2011
Discussion Topics
3© Synopsys 2011
Discussion Topics
4© Synopsys 2011
TEM Images of High Performance FETs
90nm node 65nm node 45nm node 32nm node
All TEM images here have the same scale
• Very little change in physical gate length, only ~0.9x per node
• The gate pitch is scaling fast, as 0.7x per node and area scales as 0.5x
• Most of the transistor innovation is in stress engineering and HKMG
100nm
5© Synopsys 2011
TEM Images of High Performance FETs
90nm node 65nm node 45nm node 32nm node
All TEM images here have the same scale
• Very little change in physical gate length, only ~0.9x per node
• The gate pitch is scaling fast, as 0.7x per node and area scales as 0.5x
• Most of the transistor innovation is in stress engineering and HKMG
100nm
0.7x scaling
6© Synopsys 2011
• ITRS for a long time
(from 2003 to 2008)
insisted on extrapolating
poly gate length to zero
• This corresponds to
straightforward 0.7x
scaling per generation
• Meanwhile, the industry
kept a much slower, 0.9x
scaling pace from 90nm
to 30nm
Transistor Size Evolution: Poly Gate
-10
0
10
20
30
40
50
60
70
0102030405060708090S
ize
, n
m
Technology node, nm
Lgate, logic ITRS '03-'08
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Transistor Size Evolution: Poly Gate
-10
0
10
20
30
40
50
60
70
0102030405060708090S
ize
, n
m
Technology node, nm
Lgate, logic Linear trend
ITRS '03-'08 Gate pitch • ITRS for a long time
(from 2003 to 2008)
insisted on extrapolating
poly gate length to zero
• This corresponds to
straightforward 0.7x
scaling per generation
• Meanwhile, the industry
kept a much slower, 0.9x
scaling pace from 90nm
to 30nm
8© Synopsys 2011
Source Drain
Gate
S/D overlap
Transistor Size Evolution: S/D Overlap
-10
0
10
20
30
40
50
60
70
0102030405060708090S
ize
, n
m
Technology node, nm
Lgate, logic S/D overlap
Linear trend ITRS '03-'08
Gate pitch• Source/drain overlap
has been quickly
shrinking
9© Synopsys 2011
Scaling of Leff (Junction-to-Junction)
100nm
90 nm node 32 nm node
25nm 24nm
30nm45nm
100nm
• Lgate shrinks very slow
• S/D overlap shrinks fast
• Leff stays almost fixed
10© Synopsys 2011
Transistor Size Evolution: L Effective
25 25 25
24
-10
0
10
20
30
40
50
60
70
0102030405060708090S
ize
, n
m
Technology node, nm
Lgate, logic S/D overlap
Leff, logic Linear trend
ITRS '03-'08 Gate pitch• Effective channel length
did not change at all!
• Effective channel length is defined as distance between source and drain junctions
• It determines how far the electrons/holes have to go
• It determines carrier transport and transistor variability
11© Synopsys 2011
• Classic scaling is dead
• Stress engineering is
huge, bigger than HKMG
• At 32nm node, stress
enhances hole mobility
by 3.5x
• SiGe plays a key role in
PMOS
• Si:C is used in NMOS,
but is less efficient
Role of Stress Engineering in CMOS
K. Kuhn et al, ECS 2010 (Intel)
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Transistor Size Evolution: Extrapolation?
25 25 25
24
-10
0
10
20
30
40
50
60
70
0102030405060708090S
ize
, n
m
Technology node, nm
Lgate, logic S/D overlap
Leff, logic Linear trend
ITRS '03-'08 Gate pitch• There is a sweet spot in
terms of Leff that
nobody wants to change
• This is not a “brick wall”,
but the best Ion/Ioff ratio
• Shorter transistors with
conventional planar bulk
architecture are inferior
13© Synopsys 2011
Transistor Size Evolution: Extrapolation?
25 25 25
24
-10
0
10
20
30
40
50
60
70
0102030405060708090S
ize
, n
m
Technology node, nm
Lgate, logic S/D overlap
Leff, logic Linear trend
ITRS '03-'08 Gate pitch• There is a sweet spot in
terms of Leff that
nobody wants to change
• This is not a “brick wall”,
but the best Ion/Ioff ratio
• Shorter transistors with
conventional planar bulk
architecture are inferior
• This trend can not
continue, as there’s no
space left for the contact
14© Synopsys 2011
Transistor Size Evolution: Gate Pitch
• Conventional planar
MOSFET quickly runs
out of space for contacts200nm space
for a contact
at 90nm node
30nm space
for a contact
at 32nm node
No space
left for
contact
120nm for
gate and
spacers
80nm for
gate and
spacers
Gate length + 2 spacers
Gate length
0
50
100
150
200
250
300
0102030405060708090
Siz
e, n
mTechnology node, nm
Lgate, logic
Gate pitch
15© Synopsys 2011
• Yes, here are several examples:
• But, their performance is inferior to the
current MOSFET with Leff = 25nm
Are Smaller Transistors Possible?
15nm AMD IEDM 2001 10nm Intel Tech. J. 2002 6nm IBM SSDM 2002
16© Synopsys 2011
Why MOSFETs Dislike Scaling?
Good current is
controlled by the
gate (can be turned
off)
Bad current is too
far from the gate
High halo doping is
used to suppress
DIBL, but it degrades
the on-current and
increases BTBT
leakage
Source Drain
Gate
Meta
l 0
Bad
current
17© Synopsys 2011
Typical Drain Junction Leakage Map
• Band-to-band tunneling
happens at the tip of
drain extension, just
outside of the gate
• This is where high field
overlaps with high halo
doping
18© Synopsys 2011
• Simple solution:
– Keep the channel close to the gate
– Remove current paths that are away from the
gate
• This can be achieved in either:
– FDSOI, or
– FinFET
What Can Be Done?
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Transistor Size Evolution: Future
25 25 25
24 23
2218
16
-10
0
10
20
30
40
50
60
70
0102030405060708090S
ize
, n
m
Technology node, nm
Lgate, logic S/D overlap
Leff, logic Linear trend
ITRS '03-'08 Gate pitch• At 20nm node, the trend
can continue
• At 15nm node, switch to
FinFETs or FDSOI is
necessary
• FinFETs benefit from
S/D underlap, not
overlap
20© Synopsys 2011
Transistor Size Evolution: ITRS 2009
25 25 25
24 23
2218
16
-10
0
10
20
30
40
50
60
70
0102030405060708090S
ize
, n
m
Technology node, nm
Lgate, logic S/D overlapLeff, logic Linear trendITRS '03-'08 ITRS 2009Gate pitch
• At 20nm node, the trend
will continue
• At 15nm node, switch to
FinFETs or FDSOI is
necessary
• FinFETs benefit from
S/D underlap, not
overlap
• ITRS 2009 is in line with
this vision (finally!)
21© Synopsys 2011
Transistor Size Evolution: SRAM
25 25 25
24 23
2218
16
-10
0
10
20
30
40
50
60
70
0102030405060708090S
ize
, n
m
Technology node, nm
Lgate, logic S/D overlapLeff, logic Linear trendLgate, SRAM ITRS '03-'08ITRS 2009 Gate pitch
• SRAM occupies large
part of the chip
• Yet, it’s size lags 4
generations behind the
logic!
• This is due to the:– Variability
– Leakage
22© Synopsys 2011
Scaling vs. Modeling Approaches
24 23
22
18
16
-10
0
10
20
30
40
010203040
Siz
e, n
m
Technology node, nm
Lgate, logic
S/D overlap
Leff, logic
Linear trend
Number of
lattice
atoms
along Leff
Number of
lattice
atoms in
channel
Number of
electrons/
holes per
switch
90 >= 640,000 >= 60
64 >= 160,000 >= 40
40 >= 32,000 >= 20
16 >= 1,000 >= 3
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Scaling vs. Modeling Approaches
24 23
22
18
16
-10
0
10
20
30
40
010203040
Siz
e, n
m
Technology node, nm
Lgate, logic
S/D overlap
Leff, logic
Linear trendBallis-
tisity
fraction
Adequate model
~10% Augmented drift-diffusion
~30% Augmented drift-diffusion
>30% NEGF + scattering
>50% DFT
24© Synopsys 2011
Discussion Topics
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ETSOI aka UTSOI aka FDSOI
26© Synopsys 2011
Current Is Always Within Gate’s Reach
Current density map
SOI thickness has to
be ~5nm +/-1nm
across 300mm wafer
Source Drain
Gate
oxide
Si wafer
co
nta
ct
co
nta
ct
27© Synopsys 2011
• FDSOI has very low stress
transfer efficiency for both
SiGe S/D and strained gate
• Only ~12% of stress is
transferred to the channel
• Compare this to >50%
stress transfer efficiency for
bulk planar FETs & FinFETs
20nm FDSOI MOSFET Stress Engineering
FDSOI similar to the one reported by IBM at IEDM 2009
1 GPa
stress
source
120 MPa
28© Synopsys 2011
• Can be scaled better than planar MOSFET
• Low off-state leakage – good for LP
• Similar layout style to planar MOSFETs
• Expensive
• No good stress engineering
• Can not compete with FinFET’s
performance
FDSOI Summary
29© Synopsys 2011
Discussion Topics
30© Synopsys 2011
SuVolta Monster Patent
• Keep the same masks, same libraries as in standard CMOS
• Less Vt variability, therefore possible to reduce Vdd and power consumption
31© Synopsys 2011
“SuVolta Claims Half the Power for Mobile SoCs”
• Keep all stress engineering tricks
• Add a couple epi steps
• In a way, it mimics FDSOI
• Can be scaled down to 15nm
32© Synopsys 2011
Discussion Topics
33© Synopsys 2011
• A must for Si
• Perhaps not necessary for high-m
materials
• No good way to do it in SOI
• No SMT for FinFETs and nano-wires
• For gate-last HKMG:
– CESL is useless
– Main stress source is strained elevated S/D
Stress Engineering
34© Synopsys 2011
Stress Source Evolution
PMOS
eSiGe
PMOS
eSiGe
PMOS
eSiGePMOS
eSiGe
PMOS
eSiGe
CESLCESL
90 nm 65 nm 45 nm 32 nm 22 nm
NMOS
SMT
NMOS
SMT
NMOS
SMT
Gate-
Last
Gate-
Last
Gate-
Last
NMOS
eSi:C
NMOS
eSi:C
35© Synopsys 2011
• During SPER with
restricted boundary,
amorphized Si S/D gets
dislocations with {111}
stacking faults
• Each stacking fault is a
missing {111} plane (i.e.
vacancies)
• The missing {111} plane
creates tensile stress in the
direction perpendicular to
the plane
{111} Stacking Faults Due to SMT
Intel 32nm NMOSFET
36© Synopsys 2011
Stress Induced by {111} Stacking Fault
• Missing (i.e. vacancy)
{111} plane due to SMT
for a 30nm deep
amorphized Si
• ~350 MPa tensile
longitudinal stress is
present in the channel
• Each pair of stacking
faults increases electron
mobility by 5%
37© Synopsys 2011
It is a Bad Idea to Amorphize FinFETs
Experimental results from Duffy et al.
Appl. Phys. Lett. 90, 241912 (2007)
38© Synopsys 2011
Discussion Topics
39© Synopsys 2011
Three Major Issues for Non-Si Channels
Planar MOSFET modeled with Schroedinger eq’n L. Smith et al, MRS 2007
Can not scale Leff <15nm Can not scale W <4nm Huge interface traps
No
Si IP
LW
ith
Si IP
L
Oktyabrsky et al, Mat. Sci. Eng. B 2006
40© Synopsys 2011
32 22 16 11 8 6 4
Op
po
rtu
nit
y
Technology node, nm
• Any new technology has to last at least 2 nodes
• SiGe channel is easier to manufacture
• High Ge content SiGe or pure Ge or GeSn to follow
• III-V materials have a narrow opportunity window
Opportunity Window for Non-Si Channel
III-V process
is not ready
III-V becomes
worse than Si
SiGe,
Ge,
GeSn
III-V
41© Synopsys 2011
Discussion Topics
42© Synopsys 2011
FinFET Analysis
Proximity effects
{111} facets
Gate 1
Gate 2
Drain
S
S
Variability
Conformal doping
PatterningStress engineering
Leakage
Parasitic R & C
Collapse
43© Synopsys 2011
Thin-Layer Mobility for (100) & (110) Si
Experimental Data
- e- µ for (100) – K. Uchida, IEDM2002 pp47-50
- h+ µ for (100) – K. Uchida, IEDM2002 pp47-50
- e- µ for (110) – T. Hiramoto, IEDM2005 pp729-732
- h+ µ for (110) – T. Hiramoto, EDL2005 pp836-838
0
100
200
300
400
500
2 4 6 8 10
Mo
bilit
y [
cm
2/V
s]
Tsi [nm]
eMobility - (100) Experiment
eMobility - (110) Experiment
eMobility - (100) Model
eMobility - (110) Model0
100
200
300
2 4 6 8 10M
ob
ilit
y [
cm
2/V
s]
Tsi [nm]
hMobility - (100) Experiment
hMobility - (110) Experiment
hMobility - (100) Model
hMobility - (110) Model
Electrons Holes
Severe mobility degradation
happens below ~3 nm
44© Synopsys 2011
• This means that it really
pays off to narrow the fin
• To narrow the fin, two STI
depths are required
10nm FinFET: Improves As Fin Narrows
0.33
1.00
1.85
3.16
5.42
1.562.18
2.69
0
1
2
3
4
5
6
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Rela
tiv
e D
riv
ing
Cu
rren
t
Fin Width / Channel Length
scaled pitch
fixed pitch
DIB
LF
in p
itc
h
Assumptions: L=10nm, Leff=16nm, EOT=1nm, Fin pitch=3*fin
width, Vdd=0.8V, Undoped bulk fin, Ioff=1nA/um, Fin height=30nm
Wide finNarrow fin
Fixed fin pitch Scaled fin pitch
45© Synopsys 2011
• Auto-Orientation is a must
• High-order planes?
• Rough side surfaces?
Orientation Effects
S D
(110)
46© Synopsys 2011
• Auto-Orientation is a must
• High-order planes?
• Rough side surfaces?
Orientation Effects
S D
(110)
47© Synopsys 2011
Planar MOSFETs are not Planar Anyway!
Even in a 90nm planar MOSFET, the channel surface
is not planar, but everybody models it as a flat (100)
48© Synopsys 2011
• Key for scaling power consumption
• Currently dominated by RDF
• For undoped FinFETs and nano-wires
variability will be dominated by CD and
LER
Variability
49© Synopsys 2011
• -1 GPa
• -5 GPa
• Zero stress
• Huge stress
variations,
especially at the
S/D junctions
• To get average fin
stress of ~2 GPa,
peak stress in the
fin exceeds
dangerous 5 GPa
Non-Uniform Fin Stress Patterns
50© Synopsys 2011
• Double vias are not necessary any more, so:
– No corners/jogs
– All lines on all levels can be straight lines
• Patterning can be done with double and quadruple spacer litho
• LER is an increasing issue
• {111} epi and etch facets can help to extend patterning to the end of roadmap
Patterning
51© Synopsys 2011
Larger Scale: Time evolution. |
52© Synopsys 2011
Larger Scale: Time evolution. -
53© Synopsys 2011
Larger Scale: Time evolution. |
54© Synopsys 2011
• {100} planes are
the roughest
• {110} planes are
smoother
• {111} planes are
the smoothest
Microscopic Surface Roughness
{111} nano-
islands
{111}
plane
{100} plane {110} plane
55© Synopsys 2011
• Requires changes in process & design
• Very sensitive to geometry
• Requires spacer lithography
• Insensitive to random dopant fluctuations
• Provides high performance
• Easy for stress engineering
• Enables scaling to 15nm and 10nm
• Will likely become mainstream architecture
FinFET Conclusions
56© Synopsys 2011
• Major players consider it for DRAM
• Good potential for “universal memory”
• Can be used for low-power logic
– Requires different circuits
– Driven by I, not V
• CoFeB demonstrated working down to
5nm islands
STT-RAM: DRAM Replacement?
57© Synopsys 2011
Summary