asymmetrically doped finfets for low-power robust...

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 12, DECEMBER 2011 4241

Asymmetrically Doped FinFETs forLow-Power Robust SRAMs

Farshad Moradi, Member, IEEE, Sumeet Kumar Gupta, Student Member, IEEE,Georgios Panagopoulos, Student Member, IEEE, Dag T. Wisland, Member, IEEE,

Hamid Mahmoodi, Member, IEEE, and Kaushik Roy, Fellow, IEEE

Abstract—We propose FinFETs with unequal source and draindoping concentrations [asymmetrically doped (AD) FinFETs] forlow-power robust SRAMs. The effect of asymmetric source/draindoping on the device characteristics is extensively analyzed, andthe key differences between conventional and AD FinFETs areclearly shown. We show that asymmetry in the device structureleads to unequal currents for positive and negative drain biases,which is exploited to achieve mitigation of read–write conflict in6T SRAMs. The proposed device exhibits superior short-channelcharacteristics compared to a conventional FinFET due to reducedelectric fields from the terminal that has a lower doping. Thisresults in significantly lower cell leakage in AD-FinFET-based6T SRAM. Compared to the conventional FinFET-based 6TSRAM, AD-FinFET SRAM shows 5.2%–8.3% improvement inread static noise margin (SNM), 4.1%–10.2% higher write mar-gin, 4.1%–8.8% lower write time, 1.3%–3.5% higher hold SNM,and 2.1–2.5× lower cell leakage at the cost of 20%–23% higheraccess time. There is no area penalty associated with the proposedtechnique.

Index Terms—Asymmetric doping, FinFET, SRAM.

I. INTRODUCTION

AGGRESSIVE device scaling has led to statistical vari-ability in device parameters and increased short-channel

effects (SCEs) [1], [2]. Thinner gate oxide helps to improvethe SCEs. However, thinner gate oxide leads to exponentiallyhigher gate leakage. Thus, to overcome SCE, different candi-date transistor structures have been investigated to replace thebulk MOSFETs [3]–[10]. Among them, FinFETs are consid-ered to be a promising candidate for scaled CMOS devices inscaled technology nodes. FinFETs show increased immunity toSCE due to improved channel control by the gate voltage [11].Furthermore, threshold voltage (VTH) can be easily controlled

Manuscript received March 1, 2011; revised August 21, 2011; acceptedSeptember 14, 2011. Date of publication October 19, 2011; date of currentversion November 23, 2011. The review of this paper was arranged by EditorH. S. Momose.

F. Moradi is with the Integrated Circuit and Electronics Laboratory, AarhusSchool of Engineering, Aarhus University, 8000 Aarhus, Denmark (e-mail:[email protected]).

S. K. Gupta, G. Panagopoulos, and K. Roy are with the School of Electricaland Computer Engineering, Purdue University, West Lafayette, IN 47907 USA(e-mail: [email protected]; [email protected]; [email protected]).

D. T. Wisland is with Novelda AS, 0319 Oslo, Norway, and also withthe Nanoelectronics Research Group, University of Oslo, 0316 Oslo, Norway(e-mail: [email protected]).

H. Mahmoodi is with the School of Engineering, San Francisco StateUniversity, San Francisco, CA 94132 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2011.2169678

by engineering the metal gate work function. Moreover, VTH

variations due to random dopant fluctuation in the channelregion are reduced due to almost intrinsic channel doping[12], [13].

Since memories take up 80% of the die area in high-performance processors, there is a need for high-performance,low-leakage, and highly robust SRAMs [14]. Unfortunatelyin scaled technologies, particularly under scaled supply volt-ages, the read and write stabilities of SRAMs are affected byprocess variations. Due to a large number of small geometrytransistors in a memory array, process variations have a sig-nificant impact—leading to possible read, write, and accessfailures, particularly at lower supply voltages. Furthermore,in conventional 6T SRAMs, the conflict between read andwrite stabilities is an unavoidable design constraint [15] andaggravates the effect of process variations on SRAM stabilityand performance.

One option to improve the conflicting read and write re-quirements is to decouple the read/write operations, for whichresearchers have considered new bit cells such as 8T and 10T[16], [17]. However, such cells come with an increased area.Several other techniques have been proposed to improve the6T SRAM stability, performance, and/or leakage by introduc-ing optimized devices [18]–[28]. Although these techniquesimprove device characteristics, the tradeoffs are not clearly ad-dressed, and improvement in conflicting read and write marginsis marginal.

An interesting design option to achieve mitigation ofread–write conflict is to introduce asymmetry in the accesstransistor such that unequal currents flow for positive and neg-ative VDS’s. One such technique uses asymmetric halo in bulkMOSFETs [27]. However, this leads to aggravation of SCEsand an increase in leakage of the device. For FinFETs, anothertechnique has been proposed in [28] in which asymmetric drainunderlap is introduced in the device (by employing asymmetricspacers). In this technique, the drain-induced barrier lowering(DIBL), subthreshold swing (SS), and subthreshold leakagecurrent are improved. However, asymmetric spacer FinFETsmay lead to increased variations in such devices.

In this paper, we propose to achieve asymmetry in the deviceby unequally doping the drain and source terminals of FinFETs[asymmetrically doped (AD) FinFETs]. Depending on the de-vice biasing, the proposed modification to the device structureleads to different currents from the source and the drain sides,respectively. Based on that, we design a FinFET SRAM bit cellto simultaneously improve read and write margins in scaled

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4242 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 12, DECEMBER 2011

Fig. 1. (a) Device structure of AD FinFET. (b) Circuit symbols for n-type andp-type AD FinFETs (the thicker line indicates the terminal with lower doping).(c) Doping profile for asymmetric FinFET device.

technologies, thus mitigating the read–write conflict. In addi-tion, AD FinFETs exhibit improved short-channel characteris-tics (lower DIBL, SS, and subthreshold current), which resultsin significant reduction in leakage of AD-FinFET SRAM cell.AD-FinFET SRAMs also show improvement in hold stabilityand write time at the cost of increase in access time with noarea penalty.

The remainder of this paper is organized as follows. InSection II, we present the proposed asymmetric FinFET, ex-plaining the benefits compared to the conventional symmetricFinFET. AD-FinFET SRAM is introduced in Section III andcompared with the conventional FinFET SRAM cell in termsof cell stability, performance, leakage, and area. Finally, theconclusions are drawn in Section IV.

II. AD FinFETs

Fig. 1 shows the structure and circuit symbols of the pro-posed AD FinFET. The device structure is similar to a con-ventional FinFET except for the doping concentrations in thesource and drain regions. In a conventional FinFET, the sourceand drain regions are doped symmetrically. [Henceforth, con-ventional FinFET is referred to as symmetrically doped (SD)FinFET.] On the other hand, the source and drain regions of ADFinFETs are doped differently, such that one of the terminals(defined as drain in Fig. 1) has a lower dopant concentrationthan the other terminal (source in Fig. 1). Due to unequaldopant concentrations in the two terminals [Fig. 1(c)NDopD

and NDopS], AD FinFETs exhibit asymmetry in the devicecharacteristics for positive and negative drain-to-source biases(VDS). In the rest of this paper, the polarity of VDS and thedopant concentrations in the source/drain will be defined byconsidering the terminal with lower doping as the drain and theother terminal as the source. Therefore, VDS > 0 implies thata higher bias is applied at the terminal with lower doping anddrain current (ID) flows from the terminal with lower dopingto that with higher doping. Similarly, VDS < 0 implies that ahigher bias is applied at the terminal with higher doping and ID

flows from the terminal with higher doping to that with lowerdoping. Furthermore, lower dopant concentration is representedas NDopD, i.e., NDopD < NDopS for AD FinFETs.

In order to understand the effect of asymmetric source/draindoping on the device characteristics, we now present a physics-based discussion on the device electrostatics, drain current, gateleakage, and capacitance of AD FinFETs. Two-dimensionalsimulations are performed on AD and SD FinFETs usingTaurus [29] to analyze the effect of asymmetric source/draindoping. The device parameters are shown in Table I. ForSD FinFETs, NDopD = NDopS = 1020 cm−3 is used. For thediscussion in this section, AD FinFETs are simulated withNDopS = 1020 cm−3 and NDopD = 1019 cm−3. We present thediscussion for n-type FinFETs only. This discussion can beextended for p-type FinFETs as well.

A. Electrostatics of AD FinFETs

Fig. 2 shows the conduction band profiles for n-type AD andSD FinFETs at gate voltage (VG) = 0 V and VDS = 0, 0.9, and−0.9 V. For VDS = 0 V, AD FinFETs show the conductionband edge in the drain region (ECD) at a higher energy thanthat in the source region (ECS). This is due to the fact thatNDopD < NDopS, which implies that (EF − ECD) < (EF −ECS). (Here, EF is the Fermi level in the source and drainregions at VDS = 0 V). Fig. 2 also shows a wider depletionregion on the drain side. At VDS = 0.9 V, a significant im-provement in DIBL can be observed for AD FinFETs comparedto SD FinFETs. This is due to reduced electric fields from thedrain terminal due to the wider depletion region. Even at VDS =−0.9 V (i.e., VD = 0 and VS = 0.9 V), DIBL improvementcan be observed. However, the improvement is less comparedto VDS = 0.9 V since the drain bias is applied at the terminalwith a higher dopant concentration. (Note that DIBL is definedas the lowering of the barrier on the side of the terminal withthe lower bias induced by the terminal at the higher bias. ForVDS > 0, DIBL is induced by the terminal with lower doping,defined as drain in Fig. 1, while for VDS < 0, DIBL is inducedby the terminal with higher doping, defined as source in Fig. 1.)Fig. 2(a) also shows that the barrier height for AD FinFETsis more compared to SD FinFETs, which implies lower OFFcurrent, which we shall discuss in the next section. It may bementioned that improvement in SCEs in AD FinFETs is notdue to the asymmetry in the device but because of lower electricfields from the terminal with lower doping.

Fig. 3 shows the conduction band profiles for AD and SDn-type FinFETs at VG = 0.9 V for positive and negative VDS’s.While SD FinFETs exhibit symmetric conduction band profiles

MORADI et al.: ASYMMETRICALLY DOPED FinFETs FOR LOW-POWER ROBUST SRAMs 4243

TABLE IDEVICE PARAMETERS

Fig. 2. Conduction band profiles of SD and AD FinFETs for (a) positive and(b) negative VDS’s at VG = 0 V (SD: NDopS = NDopD = 1020 cm−3; AD:NDopS = 1020 cm−3 and NDopD = 1019 cm−3).

for VDS = 0.9 and −0.9 V, asymmetry in the conduction bandprofiles for AD FinFETs can be observed. The effect of increasein the drain resistance due to lower doping is manifested inthe conduction band profile by more gradual (less sharp) bandbending in the drain region. The asymmetry in the conductionband profiles shown in Fig. 3 results in asymmetry in the drainand gate currents at positive and negative VDS’s, which wediscuss next.

B. Current–Voltage Characteristics of AD FinFETs

Fig. 4 shows the drain current (ID) versus VG characteristicsof n-type AD and SD FinFETs. For VDS > 0, AD FinFETsexhibit 10× reduction in subthreshold current (ISUB), 2.5×reduction in DIBL, and 14% reduction in SS compared to

Fig. 3. Conduction band profiles of SD and AD FinFETs for positive andnegative VDS’s at VG = 0.9 V (SD: NDopS = NDopD = 1020 cm−3; AD:NDopS = 1020 cm−3 and NDopD = 1019 cm−3).

SD FinFETs. Improvement in short-channel characteristics isobtained due to lower drain doping and, hence, reduced electricfield lines from the drain terminal affecting the source barrier.

Lower ISUB is due to higher source barrier, as is evidentfrom Fig. 2. For VDS < 0 (i.e., VD = 0 and VS = −VDS), 3.5×reduction in ISUB, 1.7× reduction in DIBL, and 4% reductionin SS are achieved compared to SD FinFETs. Improvement insubthreshold characteristics of AD FinFETs comes at the costof ON current (ION), which can also be seen in Fig. 5. ADFinFETs show 7% and 36% degradations in ION with respect toSD FinFETs for VDS > 0 and VDS < 0, respectively. Reductionin ION for VDS > 0 can be attributed to the increase in drainresistance due to lower NDopD. For VDS < 0, degradation inION is higher because the terminal which acts as the sourcefor the carriers (electrons, in this case) has a lower dopingand lower carrier concentration in its vicinity which leadsto reduction in current. The asymmetry in ID for positiveand negative VDS’s is evident in Fig. 5, and this property ofAD FinFETs is exploited to achieve mitigation in read–writeconflict in SRAMs, as will be discussed in the next section.The differences in current–voltage characteristics of AD andSD FinFETs are summarized in Fig. 6.

C. Gate Leakage in AD FinFETs

Gate current (IG) characteristics of AD and SD FinFETsare shown in Fig. 7. IG has two components—direct tunneling


Fig. 4. Transfer characteristics of AD and SD FinFETs for (a) positiveVDS and (b) negative VDS’s (SD: NDopS = NDopD = 1020 cm−3; AD:NDopS = 1020 cm−3 and NDopD = 1019 cm−3).

Fig. 5. Output characteristics of AD and SD FinFETs for (a) positive VDS and(b) negative VDS’s (SD: NDopS = NDopD = 1020 cm−3; AD: NDopS =

1020 cm−3 and NDopD = 1019 cm−3).

current (IDT) and edge tunneling current (IET). For VGS >VTH (VTH is the transistor threshold voltage), IDT is the dom-inant component of IG due to high carrier concentration in the

Fig. 6. Comparison of device characteristics of AD and SD FinFETs (SD:NDopS = NDopD = 1020 cm−3; AD: NDopS = 1020 cm−3 and NDopD =

1019 cm−3).

Fig. 7. (a) IG–VG and (b) IG–VDS for AD and SD FinFETs (SD:NDopS = NDopD = 1020 cm−3; AD: NDopS = 1020 cm−3 and NDopD =

1019 cm−3).

channel. On the other hand, IET is dominant for VGS < VTH.Let us discuss each of these cases one by one.

For high VGS, AD FinFETs show higher IG at VDS = 0.9 V[Fig. 7(a)]. This can be explained by considering the followingrelationship between gate voltage and surface potential (ψS):

VGS = ψS + EOX ∗ tOX. (1)

Here, EOX is the electric field in the gate dielectric and tOX

is the oxide thickness. From Fig. 3, it can be observed thatthe conduction band edge in the channel for AD FinFET ishigher than that for SD FinFET at VDS = 0.9 V. This implieslower ψS in the channel region (which is negative of conductionband in electronvolts) and, hence, higher EOX, as suggestedby (1). Higher EOX leads to larger IDT and higher IG. AtVDS = −0.9 V, the conduction band edge for AD FinFET is


Fig. 8. Variation of ION−IOFF ratio with (a) tSi (b) tOX, and (c) LG for AD and SD FinFETs.

lower, which implies higher ψS , lower EOX, and lower IG, ascan be observed in Fig. 7(a) at high VG. At VDS = 0 V, ψS forSD and AD FinFETs are similar, which results in similar IG.Fig. 7(b) shows that, as |VDS| increases, the difference betweenIG’s for AD and SD FinFETs increases.

For low VGS, AD FinFETs exhibit lower IG for VDS = 0.9 V[Fig. 7(a)]. This is because the dominant component IET flowsbetween gate and drain (terminal at a higher bias), and sincedrain has a lower doping and a reduced carrier concentration,reduction in IET and IG is achieved. For VDS < 0 (VD = 0 andVS = −VDS), IET flows between the gate and the terminal withhigher doping (which is the same as in SD FinFETs). Hence,AD and SD FinFETs show similar IET and IG for VDS < 0.

D. Effect of Parameter Variations on Device Characteristics

In this section, we investigate the impact of variations indevice parameters like silicon body thickness (tSi), gate oxidethickness (tOX), and gate length (LG) on the characteristics ofAD and SD FinFETs. We vary the device parameters around itsnominal value (listed in Table I) and evaluate the degradation ofION − IOFF ratio with respect to each parameter. (Note that theOFF current IOFF is the sum of subthreshold current ISUB andgate current (IG) at VG = 0 V and |VDS| = 0.9 V). In order toquantify the increase in ION−IOFF ratio over its nominal valuedue to variation in device parameter (x—where x is tSi, tOX,and LG), we define degradation in ION−IOFF ratio (D) as

D =

(nom

(ION

IOFF

)− min

(ION

IOFF

))/nom

(ION

IOFF

)

|ext(x) − min(x)| /nom(x). (2)

Here, max, ext, and nom refer to maximum, extreme, andnominal values of their arguments. Note that the extreme valueis the maximum or minimum value of the parameter whichresults in minimum ION−IOFF ratio. D, as defined in (2),indicates the percent degradation in ION−IOFF ratio for 1%change in the device parameter with respect to its nominalvalue.

Fig. 8 shows the plot of ION−IOFF ratio versus the de-vice parameters. It can be observed that AD FinFETs exhibitconsistently higher ION−IOFF ratio compared to SD FinFETsfor VDS > 0 and comparable ION−IOFF ratio for VDS < 0for a range of tSi, tOX, and LG due to superior short-channelcharacteristics of AD FinFETs. Also note that, as tSi and tOX

decrease or LG increases, ION−IOFF ratio for AD FinFETs

with VDS < 0 approaches that of SD FinFETs. This is because,as tSi and tOX decrease or LG increases, ISUB starts to decreaseexponentially while IG is either relatively insensitive (e.g., withrespect to tSi and LG) or increases exponentially (e.g., withrespect to tOX). As a result, for small tSi, small tOX, andlarge LG, IG starts to dominate IOFF. Recall that the IG atVG = 0 and |VDS| = 0.9 V is similar for SD and AD FinFETswhen VDS < 0, while ION is relatively lower for AD FinFETs.Hence, ION−IOFF ratio for AD FinFETs (VDS < 0) starts toapproach that of SD FinFETs for small tSi, small tOX, and largeLG. On the other hand, for VDS > 0, AD FinFETs have lowerIG at VG = 0 and |VDS| = 0.9 V compared to SD FinFETs andhence show higher ION−IOFF ratio across the entire range ofparameters. Let us now compare the degradation in ION−IOFF

ratio of AD and SD FinFETs due to the variation in the deviceparameters. Fig. 8 shows the degradation of ION−IOFF ratiowith increasing tSi, increasing tOX, and decreasing LG due todegradation of SCEs. Since AD FinFETs exhibit superior short-channel characteristics compared to SD FinFETs, the effect ofvariation in device parameters is reduced. SD FinFETs show3.87%, 3.74%, and 3.98% degradations in ION−IOFF ratiofor 1% tSi, tOX, and LG variations, respectively. AD FinFETsshow 3.63%, 3.44%, and 3.88% degradations in ION−IOFF

ratio for VDS > 0 and 3.47%, 5.4%, and 3.92% degradationsin ION−IOFF ratio for VDS < 0 for 1% variations in tSi, tOX,and LG, respectively. Higher variation with respect to tOX inAD FinFETs at VDS < 0 compared to SD FinFETs is due tothe effect of the gate current, as described previously in thissection.

Fig. 8(c) shows another important advantage of AD FinFETs.As LG is scaled, larger improvement in ION−IOFF ratio ofAD FinFETs with respect to SD FinFETs is observed. Hence,the proposed technique provides an alternate method to controlSCEs in scaled technology nodes, at which other device designtechniques like scaling of fin thickness and oxide thickness maybe challenging due to quantum mechanical effects and increasein gate leakage, respectively.

E. Comparison With Previously ProposedAsymmetric MOSFETs

In this section, we compare AD FinFETs with the MOSFETswith asymmetric halo proposed in [27] and FinFETs with asym-metric drain underlap proposed in [28]. In [27], MOSFETs with


Fig. 9. Schematic of AD-FinFET-based 6T SRAM showing voltages at different nodes during (a) read operation and (b) write operation and (c) thin-cell layoutof AD-FinFET-based SRAM.

asymmetric halo suffer from increased SCEs compared to theconventional MOSFETs. On the other hand, AD FinFETs showsignificant improvement in SCEs compared to SD FinFETs.The asymmetric FinFETs proposed in [28] show improvementin SCEs like AD FinFETs compared to conventional FinFETs.However, introducing asymmetric underlap in FinFETs is muchmore challenging from the point of view of fabrication thandoping the source and drain terminals with different dopantconcentrations. Although both AD FinFETs and the FinFETsproposed in [28] require an extra mask, AD FinFETs are muchsimpler to fabricate.

With the understanding of the device characteristics ofAD FinFETs discussed in this section, let us now presentAD-FinFET-based 6T SRAMs and evaluate their benefits overconventional FinFET 6T SRAMs.

III. AD-FinFET-BASED 6T SRAM

Fig. 9 shows the schematic of the proposed AD-FinFET-based 6T SRAM (during read and write operations) along withthe thin-cell layout. The thick line on the transistors indicatesthe terminal with lower doping. Note that, for the pull-down(NL and NR) and access transistors (AXL and AXR), the ter-minals with lower doping are connected to the same nodes (thestorage nodes). Hence, the contacts of access transistors can beshared with those of the corresponding pull-down transistors[Fig. 9(c)], as in conventional FinFET SRAMs. Thus, there isno area penalty associated with the proposed technique. Let usnow discuss the operation of AD-FinFET SRAM and explainthe mitigation of read–write conflict achieved by exploiting theasymmetry.

A. Cell Operation

During the read operation, bitlines BL and BLB areprecharged to the power supply voltage (VDD). Let us assume(without any loss of generality) that node “Q” stores “0” and“QB” stores “1.” On asserting the wordline, the voltage at node“Q” (VQ) rises to a positive voltage VREAD, which depends onthe resistive divider action of AXL and NL. Read failure mayoccur if VREAD becomes greater than the trip point (VM ) ofthe inverter formed by AXR, NR, and PR. Hence, for higherread stability, low strength of the access transistors is desired.During the write operation, BL is precharged to VDD, and BLBis discharged to GND. On asserting the wordline, the voltage atQB (VQB) is discharged to a voltage VWRITE depending on theresistive divider action of PR and AXR. If VWRITE is less thanVM of the inverter formed by PL and NL, write operation occurssuccessfully. For superior write ability, high strength of AXR isdesired. Note the conflicting requirements for the strength ofthe access transistor in a conventional FinFET SRAM for highread and write stabilities.

In AD-FinFET-based SRAM, mitigation of the aforemen-tioned read–write conflict is achieved. During the read oper-ation of AD-FinFET SRAM [Fig. 9(a)], the terminal of AXLwith the lower doping (indicated by the thick lines) is at a lowervoltage than the other terminal (i.e., VDS < 0 for AXL; recall inSection II that the terminal with the lower doping was defined asthe drain). Hence, the strength of AXL is reduced (see Figs. 5and 6), which lowers VREAD and increases the read stability.During the write operation of AD-FinFET SRAM [Fig. 9(b)],the terminal of AXR with a lower doping concentration (drain)is at a higher voltage than the other terminal (source), i.e.,VDS > 0. Therefore, the strength of AXR is larger (see Figs. 5


Fig. 10. (a) Read SNM and write margin. (b) Hold SNM and cell leakage. (c) Cell write time and access time versus drain doping (NDopD). NDopD =

1020 cm−3 corresponds to SD FinFET SRAM. The rest of the points on the x-axis are for AD-FinFET SRAMs with different values of drain doping.

Fig. 11. (a) Read SNM, (b) write margin, (c) hold SNM, (d) cell access time, (e) cell write time, and (f) cell leakage versus VDD. (SD FinFET SRAM:NDopS = NDopD = 1020 cm−3; AD-FinFET SRAM: NDopS = 1020 cm−3 and NDopD = 2 × 1019 cm−3).

and 6), which results in higher write ability. The mitigation ofread–write conflict in AD-FinFET SRAMs comes at the costof larger access time due to weak access transistors during theread operation.

Let us now quantify the stability, performance, and leakageof an AD-FinFET SRAM and compare it with a conven-tional (SD) FinFET SRAM. We simulate AD-FinFET SRAMswith different drain dopant concentrations (NDopD) less thanthe source doping (NDopS = 1020 cm−3). For SD FinFET,NDopD = NDopS = 1020 cm−3.

B. Comparison of AD and SD FinFET SRAMs

Fig. 10(a) shows the read static noise margin (SNM) versusNDopD. An increase ranging from 2.1%–7.3% in read SNM canbe observed for AD-FinFET SRAM compared with SD FinFETSRAM (corresponding to NDopD = 1020 cm−3). At the sametime, 2.9%–23% improvement in write margin [30] is achievedfor AD FinFETs [Fig. 10(a)], thus resulting in the mitigation ofread–write conflict. In addition, due to superior short-channel

characteristics of AD FinFETs, 0.5%–1.3% increase in holdSNM and 1.3–2.8× reduction in cell leakage can be observed[Fig. 10(b)]. Improvement in cell write time ranging from3%–12% is also achieved [Fig. 10(c)] due to lower NDopD and,hence, lower capacitance at the storage nodes in AD-FinFETSRAM compared to SD FinFET SRAM. Fig. 10(c) also showsthe 6%–42% higher cell access time, which is due to weakeraccess transistor during read.

To sum up, AD-FinFET SRAM shows simultaneous im-provement in the read stability, write ability, cell write time,hold stability, and cell leakage at the cost of increase in theaccess time. There is no area penalty associated with theproposed technique [Fig. 9(c)].

C. Analysis Across a Range of VDD’s

In this section, we compare SD FinFET SRAM (NDopD =NDopS = 1020 cm−3) with AD-FinFET SRAM (NDopD =2 × 1019 cm−3 and NDopS = 1020 cm−3) across a range ofsupply voltages (0.6–0.9 V). Fig. 11 shows the comparison


of read SNM, write margin, hold SNM, cell leakage, cellaccess time, and cell write time for different VDD’s. Com-pared with SD FinFET SRAM, AD-FinFET SRAM shows5.2%–8.3% higher read SNM, 4.1%–10.2% higher write mar-gin. 1.3%–3.5% improved hold SNM, 2.1–2.5× lower cellleakage, and 4.1%–8.8% lower cell write time at the cost of20%–23% larger cell access time. The benefits of AD-FinFETSRAM in terms low power and high cell stability are evidentacross a range of VDD’s.

IV. CONCLUSION

We have proposed AD FinFETs in which the source anddrain regions are doped with different dopant concentrations.Asymmetry in the device structure results in unequal currentsfor positive and negative drain biases, which is exploitedto achieve mitigation of read–write conflict in 6T SRAMs.AD FinFETs also show superior short-channel characteristics,viz., lower DIBL, reduced SS, and lower subthreshold current.As a result, AD-FinFET SRAMs show significant reductionin cell leakage and increase in hold stability. Simultaneousimprovement in read stability, write ability, cell write time, holdstability, and cell leakage is achieved for AD-FinFET SRAMscompared to conventional SD FinFET SRAMs, at the cost ofincrease in cell access time. There is no increase in the cell areaof AD-FinFET SRAMs compared to SD FinFET SRAMs.

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Farshad Moradi (S’09–M’11) received the B.S.degree in electrical engineering from Isfahan Uni-versity of Technology, Isfahan, Iran, in 2001, theM.S. degree in electrical engineering from FerdowsiUniversity of Mashhad, Mashahd, Iran, in 2005, andthe Ph.D. degree from the University of Oslo, Oslo,Norway, in 2011.

From 2005 to 2008, he was a Senior Lecturerwith Ilam University, Ilam, Iran. From 2009 to 2010,he visited the Nanoelectronic Laboratory, PurdueUniversity, West Lafayette, IN. He is currently an

Assistant Professor with the Integrated Circuit and Electronics Laboratory,Aarhus School of Engineering, Aarhus University, Aarhus, Denmark. Hiscurrent research interests include ultralow-power digital/memory circuit/devicedesign for low-power applications.


Sumeet Kumar Gupta (S’05) received the B.Techdegree in electrical engineering from the Indian In-stitute of Technology, Delhi, India, in 2006 and theM.S. degree in electrical and computer engineeringfrom Purdue University, West Lafayette, IN, in 2008,where he is currently working toward the Ph.D.degree in the School of Electrical and ComputerEngineering.

In 2007, he was an intern with Advanced MicroDevices Inc. In 2010, he was a summer intern withIntel Corporation, Hillsboro, OR. His research inter-

ests include nanoscale device modeling and low-power digital circuit design.Mr. Gupta was the recipient of the Magoon Award and the Outstanding

Teaching Assistant Award from Purdue University in 2007 and the Intel Ph.D.Fellowship Award in 2009.

Georgios Panagopoulos (S’05) received theDiploma degree (with honors) in computer andcommunication engineering from the University ofThessaly, Volos, Greece, in 2006. Since 2007, he hasbeen working toward the Ph.D. degree in electricaland computer engineering in the School of Electricaland Computer Engineering, Purdue University, WestLafayette, IN.

From 2006 to 2007, he was a Research Assistantwith the University of Thessaly, Greece, where hedesigned analog circuits. He was a summer intern

with Intel Corporation in 2011. His current research interests include very largescale integration device/circuit codesign for nanoscaled silicon and nonsilicontechnologies for reliable and low-power applications.

Mr. Panagopoulos has received Academic Excellence Awards and severalscholarships during his studies.

Dag T. Wisland (M’00) received the M.Sc. andDr.Sc. degrees in electrical engineering from theUniversity of Oslo, Oslo, Norway, in 1996 and 2003,respectively.

He is a Cofounder and currently the CEO of thefabless semiconductor company Novelda AS, Oslo,and is also a part-time Associate Professor with theNanoelectronics Group, University of Oslo. From2004 to 2008, he was heading the NanoelectronicsResearch Group, University of Oslo. His currentresearch interests include low-power analog/mixed-

signal CMOS design, ultrawideband radio, and design of ADC/DAC with aparticular focus on delta–sigma data converters. In his research, he has focusedon conceptually new methods and topologies combined with low-power design.

Dr. Wisland is a TC member of the IEEE CAS Society Analog SignalProcessing and Biomedical Circuits and Systems technical committees.

Hamid Mahmoodi (S’00–M’05) received the B.S.degree in electrical engineering from Iran Universityof Science and Technology, Tehran, Iran, in 1998, theM.S. degree in electrical and computer engineeringfrom the University of Tehran, Tehran, in 2000, andthe Ph.D. degree in electrical and computer engi-neering from Purdue University, West Lafayette, IN,in 2005.

He is currently an Associate Professor of elec-trical and computer engineering with the Schoolof Engineering, San Francisco State University,

San Francisco, CA. His research interest includes low-power, reliable, andhigh-performance circuit design for nanoscale technologies. He has manypublications in journals and conferences and is the holder of five U.S. patents.

Dr. Mahmoodi was a recipient of the 2008 SRC Inventor Recognition Award,the 2006 IEEE Circuits and Systems Society VLSI Transactions Best PaperAward, the 2005 SRC Technical Excellence Award, and the Best Paper Awardof the 2004 International Conference on Computer Design. He is a technicalprogram committee member of the International Symposium on Low PowerElectronics Design and the International Symposium on Quality ElectronicsDesign.

Kaushik Roy (F’02) received the B.Tech. degree inelectronics and electrical communications engineer-ing from the Indian Institute of Technology (IIT),Kharagpur, India, and the Ph.D. degree from theElectrical and Computer Engineering Department,University of Illinois, Urbana, in 1990.

He was with the Semiconductor Process and De-sign Center, Texas Instruments, Dallas, where heworked on FPGA architecture development and low-power circuit design. He was a Research VisionaryBoard Member of Motorola Laboratories (in 2002)

and held the M. K. Gandhi Distinguished Visiting Faculty at IIT, Bombay,India. Since 1993, he has been with the School of Electrical and ComputerEngineering, Purdue University, West Lafayette, IN, where he is currently aProfessor and holds the Roscoe H. George Chair of Electrical and ComputerEngineering. He is Purdue University Faculty Scholar. He has publishedmore than 500 papers in refereed journals and conferences, is the holder of15 patents, has graduated 51 Ph.D. students, and is the coauthor of two bookson Low Power CMOS VLSI Design (John Wiley and McGraw Hill). Hisresearch interests include spintronics, VLSI design/CAD for nanoscale siliconand nonsilicon technologies, low-power electronics for portable computing andwireless communications, VLSI testing and verification, and reconfigurablecomputing.

Dr. Roy has been in the editorial board of the IEEE DESIGN AND TEST,IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSAC-TIONS ON VLSI SYSTEMS. He was a Guest Editor for the Special Issue onLow-Power VLSI in the IEEE DESIGN AND TEST (in 1994), IEEE TRANSAC-TIONS ON VLSI SYSTEMS (in June 2000), and IEE Proceedings—Computersand Digital Techniques (in July 2002). He was a recipient of the NationalScience Foundation Career Development Award in 1995, IBM Faculty Part-nership Award, ATT/Lucent Foundation Award, the 2005 SRC TechnicalExcellence Award, SRC Inventors Award, Purdue College of Engineering Re-search Excellence Award, Humboldt Research Award in 2010, the 2010 IEEECircuits and Systems Society Technical Achievement Award, DistinguishedAlumnus Award from IIT, Kharagpur, the 2005 IEEE Circuits and SystemSociety Outstanding Young Author Award (with Chris Kim), the 2006 IEEETRANSACTIONS ON VLSI SYSTEMS Best Paper Award, and the Best PaperAwards at the 1997 International Test Conference, the 2000 IEEE InternationalSymposium on Quality of IC Design, the 2003 IEEE Latin American TestWorkshop, the 2003 IEEE NANO, the 2004 IEEE International Conference onComputer Design, and the 2006 IEEE/ACM International Symposium on LowPower Electronics and Design.

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