transformative power semiconductor technologies to impact
TRANSCRIPT
Transformative Power Semiconductor Technologies to Impact 21st Century Energy
Economy, and Space and Defense Electronics
Krishna Shenai, PhDProfessor
Electrical Engineering and Computer Science University of Toledo
Birck Nanotechnology CenterPurdue UniversityWest Lafayette, IN
July 8, 2010
Our Research
The Interface
Material Technologies
Advanced Systems
Power Generator TransmissionSubstation
High Voltage Transmission Lines
Today’s AC Power Grid
DistributionSubstation
Commercial Consumer
Industrial Consumer
Residential Consumer
3 PhaseAC Power
Step Up Voltage Transformer155,000 to 765,000 Volts
7,200 volts
Transformer120 volts AC
60 Hz
Generation Loss
Transmission Loss
Distribution Loss
Reference: www.epri.com Electricity Technology Roadmap
Step Down Voltage Transformer (7,200 Volts)
Electro Mechanical Switches
Energy EfficiencyEnergy Efficiency
Reference: www.epri.com Energy Efficiency: A Renewed Imperative
Energy Loss From Generation through End-Use
Generation35 % Efficient
Coal
100 Units
Transmission & Distribution93% Efficient
Electricity Compact Fluorescent Lamp22% Efficient
End Use Utilization
Electricity
~ 32 Units
Incandescent Bulb12% Efficient
Light
~ 32 Units
Light
~ 35 Units
~ 4 Units
~ 7 Units
Light Emitting Diode (LED)Light Emitting Diode (LED)
New energy law approved by US Congress to ban
incandescent bulbs by 2014.
Replace existing incandescent with Compact Fluorescent
Lamp (CFL) and LED beginning 2012.
Light Emitting Diode bulb
Compact Fluorescent Lamp
Incandescent Light BulbIncandescent Light Bulb
LED CFL Incandescent
Life Span 50,000 hours 8,000 hours 1,200 hours
Power Consumed
6 - 8 watts 13-15 watts 60 watts
Annual Operating
Cost*
$42.16/year $84.32/year $361.35/year
* Usage of 30 bulbs 5 hours a day Reference - www.mrbeams.com/index.asp?PageAction=Custom&ID=2www.worldnetdaily.com/news/article.asp?ARTICLE_ID=59298
What is the problem?
CostEfficiencyReliabilitySecurity
Environmental ImpactGen
erat
ion
Uti
lizat
ion
The Opportunity
• The greatest technical achievement of the 20th century isthe electrification - Thomas Edison
• Silicon will reconfigure today’s fragile electric powergrid just the same way as it did the information infrastructure of the 20th century - Morgan Stanley
• A perfect power system is the one that has plentiful ofenergy and never fails its customers - Bob Galvin
• Information-quality power is the greatest businessopportunity of our time – George Gilder
Perfect Power System
Perfect Power System - Plentiful green energy, secure and reliable
20th Century Wireless Information Technology
21st Century Green Energy & Power Technologies
Utilization of Distributed Renewable Energy Generators (DREGs)
• Chip-Scale Power – up to few hundred Watts
• Medium Power – from few hundred Wattsto few hundred kilo Watts
• Utility-Scale Power – more than a fewhundred kilo Watts
Solar-Powered Data Center
Why Solar-Powered Data Centers?
• 1.5% of US electricity used• $4.5B annual electricity bill• > 2X increase in electricity need by 2011• Efficient PV integration into DC system• 4% - 6% efficiency improvement
for DC system over existing AC
Features of PV DC/DC Converter:
• 98% efficient SiC Boost Converter• Integrated smart PPT• Smart load balancing• Wireless smart control• Dramatic cost reduction• Significant improvement in reliability
Sponsor - NSF
Power Supply Tradeoffs – an Example
• IBM eServer 900
• 30% volume taken by PS
• 10% volume by cooling
10 kW Power Supply
50 kHz to 75 kHz
= 50% reduction in size
and 50% reduction in cooling
Cost
(¢/W
)
50
8
4
Frequency (kHz)100 150
Effic
ienc
y (%
)
12 90
85
80
Si
MTB
F (a
.u.)
1
10
1
Power Density (a.u.)2 3
Cool
ing
Cost
(a.u
.)
100 4
2
1
Lossy Components and Packaging!
ROADBLOCK !
P. Singh, et.al., IBM J. Res. & Dev., Nov. 2002
Power Switching Fundamentals
iL Load
Power Switch
A
D
B
C
VSUP
0 Ton T
VGS
G
D
S
RG
VGS
time
A
B
AA
BB
R LL Diode
Power Switching Circuit Typical Loads
Typical Power Switch and Control
Power MOSFET Switching
Current SourceIC
LOADIDS
VGS CIN
IGS
VIN
VOUT
=ILOAD
PSW = CINV2GSf
VGS
Time
D
T = 1/f
PC = IDS2RON
PL = ILOADVSUP
VSUP ON-state Loss
EnergySupplied
EnergyRecoverable
Figure of Merit (FOM) = RONCIN; RONQGS
K. Shenai, IEEE TED, vol. 37, no. 4, pp. 1141-1153, April 1990
POFF = ILKVSUP OFF-state Loss
HARD vs. SOFT SwitchingVo
ltag
e (V
)
5
Time (μsec)10 15
Curr
ent (
A)
1000 100
Curr
ent (
A)
5
Time (μsec)10 15
Volt
age
(V)
1000 100
HARD
Turn-on
Turn-offVo
ltag
e (V
)
5
Time (μsec)10 15
Curr
ent (
A)
1000 100
Curr
ent (
A)
5
Time (μsec)10 15
Volt
age
(V)
1000 100
SOFT
ZVS Turn-on
ZCS Turn-off
dv/dt(- ve)
di/dt(+ ve)
dv/dt(+ ve)
di/dt(- ve)
dv/dt(- ve)
di/dt(+ ve)
dv/dt(+ ve)
di/dt(- ve)
Current High-End Computer Power Supply
New PowerMOSFET
New PowerMOSFET
Simplify BulkyHV Driver
New PowerMOSFET
High-End Computer Power Supply
PFC BULK
DC-DC
ISOLATED
DC-DC
2.95kW
110-220VAC
2.65kW
48V
2.44kW
12VBUCKDC-DC
5V POL
12V POL
BUCKDC-DC
3.3V POL
BUCKDC-DC
1.xV POL
90%, High Current 48V Bus 92%, $0.2-$0.5/W 82%, Multiple Output VRM 2kW
Overall: 68% Efficient, 950W Power Loss, $1020 Cost and MTBF of ~ 200,000 Hours.
Current Power System Cost, Energy Efficiency, and Reliability are Dictated
by Power Semiconductor Switch Loss.
Current Industry Standard
More Integrated Solution
Replace with Efficient Power Switches and IC, Eliminate HV DriverIncrease Overall Efficiency to 90%, Reduce Cost by 60%
New PowerMOSFET
New PowerMOSFET
NewSR IC
New IC withSimple HV Driver
New PowerMOSFET
High-End Server Power Supply
PFC BULK
DC-DC
2.2kW
110-220VAC
2.1kW
12VBUCKDC-DC
5V POL
12V POL
BUCKDC-DC
3.3V POL
BUCKDC-DC
1.xV POL
95%, Low Current 380V Bus 95%, Multiple Output VRM 2kW
Quantum Leap in System Performance & Reliability
Goal: 90% Efficient, 200W Power Loss, $400 Cost and MTBF ~ 500,000 Hours.
60% Savings in System Cost80% Savings in Power LossImproved Field Reliability
Field-Reliability Paradigm
Need “End-of-Life” SOA
that accounts for sustained
dynamic application stresses
K. Shenai, IEEE Spectrum, pp. 50-55, July 2000
Field-Failure of Power MOSFETs
K. Shenai, 12th Ann. Automotive Reliability Workshop, Nashville, TN, 2007 (invited)
Vendor
Field MTBF Improvement – an Example
K. Shenai et al., IECEC Conference, pp. 1480-1490, 2000
Monolithic Mobile Platform
● Present Solution: multiple, cascaded, independent DC-DC power converters.
inefficient, narrow band PA with poor S/N performance.
● Need: Integrate DC-DC converters and broadband PA into a single power management chip; develop single-chip mobile platform.
Digital (1–3.6 V)– Processor– Memory– RF baseband– Control
Mixed-Signal (1.5–5 V)– DSP– Multimedia– Signal converters
RF/Analog (2.5–12V)– Filters and mixers– VCO– LNA and opamp– Sensors– PA
Power (1–12 V)– Converter– Regulator– On-chip power supply
Power
Communication
A/DDigitalSignal
ProcessingD/A
INTERFACE
INTERFACE
PhysicalInput Video
Display
ElectricalOptical
Battery and Power Management Evolution
1990 20042002200019961993
DiscreteRegulator
LDORegulator
IntegratedLDO
Dc/Dc Converter
PowerManagementLDO
µLDO
High EfficiencyDC Converters
SOC
Gas Gauge
BatteryCharger
DPM
3GBATTERY
RUN
TI
ME
3G’s next step
LI
NiMhSmallerCircuitSize
LowerNoise
ENERGY
HARVESTING
OEM Loads and SMPS Specifications
RADIO,FLASH
CPU,DSP
LDO, Hybrid50% - 92%$0.3 - $3Li-ion Cell
(2.7 - 4.2V)
DISPLAY
RFPA
4 – 28V10 – 200mALow speed (ms)
2.5 – 3.2V1 – 20mAMedium speed(ms - µs)
0.8 – 2.5V1 – 800mAHigh speed(µs- ns)
0.4 – 3.4V10mA – 2ALow speed (ms)
LDO, Hybrid30% - 92%$0.3 - $1.5
Hybrid70% - 92%$0.8 - $1.2
Hybrid70% - 92%$1 - $1.5Slow
Boo
stB
uck
Buc
k-B
oost
Concept Power Range Efficiency Speed Profile
Charge Pump ~ few 100 mA 70% - 90% Slow Single Chip/Hybrid
Switch Capacitor ~ few 100 mA 70% - 90% Slow Single Chip/Hybrid
LDO ~ several Amps 50% Slow Single Chip
Note: All of the above techniques are RC time limited to a response time of several µsecs., and generally deliver very low power (few hundred mW).
Switch Mode (SMPS) ~ several Amps 70% - 95% Slow Hybrid
Note: To obtain high power conversion efficiency, switch-mode power conversion is performed mostly at < 3 MHz; it is slow and in hybrid circuitry form.
Chip-Scale DC-DC Power Conversion Techniques
• Wide input range- Down to 0.5 V- As high as 3 V
• Variable output- Voltage doubling- Voltage tuning (± 5%)
• Performance- Over 90% efficiency- Under 1% ripple- Under 100-kHz clock
• Uses standard CMOS• Ideal for constant-load
applications
5
4
3
2
1
0
OU
TPU
T C
UR
REN
T (A
)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5INPUT VOLTAGE (V)
High-Current Charge Pumps
Patents Pending
Cell Phone Application
Backlight Driver
High VoltageLow Current
PADriver
High Power
Baseband(DSP, Arm, Audio amp, …)
High Speed
BatteryCharger
Low VoltageHigh Current
60 – 70%10 – 20%
10 – 20%
Hybrid SMPS
Integrated LDO, SC, CP
External LDO, SMPS
12
4
3
Hybrid SMPS
Switch Mode (SMPS) Converter in Handheld DevicesMaxim 8506-8508 in a Cell Phone
PA Power SupplyMaxim 1582 in a NotebookWhite LED Power Supply
Large External Passives
High-frequency (@ > 1 MHz) switch-mode power conversion facilitates on-chip integration of passive elements.
Efficiency vs. Load Current – Maxim 8506-8508 used for Cell Phone RFPA power supply
1 10 100 1000Load Current (mA)
Effi
cien
cy (%
)100
90
80
70
50
PWMMode
VOUT = 2.5V
VOUT = 1.2V
VIN = 2.5V
Circuit Size and Height
RF PA SMPS InductorSize: 6 x 6 X 2.0 mmHybrid inductor size is 10x our chip
Our Power Management ChipSize: 3 x 3 x .84 mm
Chip Scale Power Inductor
0.1 0.2 0.3 0.4 0Frequency (GHz)
Q
25
30
35
40
|Eqn|Q_sample3
|Eqn|Q_sample4
RES
R=ID=
0.5023 OhmR1
RES
R=ID=
Rac OhmR2
IND
L=ID=
53.45 nHL1
CAP
C=ID=
0 pFC1
RES
R=ID=
2.835e7 OhmR3
CAP
C=ID=
0.1747 pFC2
CAP
C=ID=
0.07287 pFC3
PORT
Z=P=
50 Ohm1 PORT
Z=P=
50 Ohm2
Rac=k*1e-6*(sqrt(f))
k=179.9
f=_FREQ
Rac: { 1.799,2.544,3.116,3.598,4.023 }
Extracted Model from HFSS Simulation.
60 nH 1.6 mm x 1.6 mm; W=40 µm, S=35 µm
Radiation Boundary on Top Surface with Air Dielectric 50 μm Polyimide Tape
Air gap below inductor varied 300 to 500 μm.
500 µm air gap
300 µm air gap
PatentsPending
ADC with Embedded Power Management
• Specifications- High resolution (high
sensitivity at low VDD), 10-bit or better
- Low power, <500 mW- High sample rate,
>50 MSPS
• Target markets- Multimedia- Wireless telephony- Digital photography- Analog and digital video
cameras
ADC Power Dissipation (mW)
4
6
8
10
12
14
16
1.E+05 1.E+06 1.E+07 1.E+08 1.E+09Sample Rate (Sa/sec)
1999199819971996199519941993B
it R
esol
utio
n (b
its)
Our work
Area is proportional to ADC power dissipation
US 6,608,503 – Hybrid Comparatorand Method
Adaptive Intelligent Power Management (AIPM)
• Activity level is determined by
- Voice, data, streaming multimedia and static web contents access
- Links to peripherals, e.g. display, keypad etc.
• Impact of activity on power dissipation
- Some components frequently idle
- Some components require constant alertness
- Active components have power profile that is proportional to “activity” level
• Present solution: power regulation is unresponsive to activity levels• Innovative solution: dynamic power minimization based on user activity levels
- Increase effective battery lifetime by 2x to 5x
AIPM Concept
• Generate multiple supply voltages • Use more slices for fast multiplexing• Produce rapid tuning of supply voltage• Develop single chip power supply
technology
• Provide real-time statistics on activity of logic blocks or clusters
• Scale VDD per logic block or cluster• Permit tuning of power vs.
performance per logic block or cluster • Provide continuous execution in low-
power modes • Develop analog building blocks
amenable to variable-VDD operation
1
2
3
4
US 5,959,439 –Monolithic DC-DC Converter
US 6,791,341 –Current Derivative Sensor
US 6,714,049 –Logic StateTransitionSensor
MAX2291 PA with Variable Vcc from MAX8506 switching regulator – Measured PAE and Gain vs. Output Power
Pout is function of closeness to Base station
2x battery life
Dynamic PowerManagementExample.
Chip Scale Power Integration
D2D
D2D
D2D D2D
D2D
Power Source
PoL Power PoN Power
• Cell Phone• PDA• Laptop
• Microprocessor• DSP• Data Converter• PA for Handheld OEM
GaN Power FETs and DC-DC Converters
T. McDonald, Electronics in Motion and Conversion, vol. 11, pp. 2-42, April 2009
Heterogeneous Chip-Scale Power Integration
CMOSControl
IC
RL
Vin
L
CD
Q1
Q2
VG1
VG2 Vo
+
-
+-C1
D1
VdrQ3
Q4
Q1Vin
Synchronous Buck Converter
Gate Drive for “Normally On” FET
K. Shenai, IEEE Electron Device Letters, vol. 11, pp. 520-522, 1990
Advanced GaN HEMT Structures
D/S DGSG G
AlGaN back barrierInAlN/AlNSelectively oxidized InAlN
E-mode D-mode
S G1G2
Substrate
M2
Metal 1
G
S2
G2
G2
D1
G1
G1
D2/S1
S2
M1
D1
Output
ILD
ILD
(Top view)
Key innovations:Selectively thermally oxidized AlInN(a) E-mode(b) Vbr/Ron tunability (G-D region)(c) Gate leakage reduction
Novel interleaved cell layout(a) Reduced parasitics(b) Reduced power loss
GaN
Collaborator: Dr. Xuili (Grace) XingUniversity of Notre Dame
Advanced Si MOS Power Diode Structures
p+
n
n+
n+
p
K
n
n+
n+
K(a) (b)
MetalPolyOxide
IMOSIPN IMOS
ISB
Notre Dame “Quilt Packaging”a) Concept
b) Nodules
c) Proposed inductor
a)
b)c)
Collaborator: Dr. G. H. BernsteinUniversity of Notre Dame
QP Allows World-Record Chip-to-Chip Bandwidth
• De-embedded insertion loss compared with recent papers on wire bonds, ball grid array, MS-to-CPW RF-via, flip chip.
• 0.25 dB lower than coaxial flip-chip via at 40 GHz
• 1.7 dB lower than standard flip-chip at 110 GHz
• 0.8 dB lower than RF-via at 70 GHz
Quilt Packaging
Courtesy: Dr. G. H. BernsteinUniversity of Notre Dame
Electro Osmotic DC Micro Cooling
QuiltWater toheat rejector
Water from heat rejector
Pump inlet at the bottom
Pump outlet at the top
Water being pumped up
Water into MCHS
EO pump structure: Top - Cathode/wire electrodeMiddle - Porous membrane
(e.g. grit filter) Bottom: Anode/wire electrode
HeatRejector
Pump
Converter quilt
MCHS
Collaborator: Dr. Jie (Jayne) WuUniversity of Tennessee at Knoxville
Performance of 12V/1V, 10W Synchronous Buck Converter
6065707580859095
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5
Best Commercial Silicon MOSFET
Best Commercial GaN HEMT
Proposed GaN HEMT
Frequency (MHz)
Effic
ienc
y (%
)
0
0.1
0.2
0.3
0.4
0.5
0
50
100
150
200
250
0.5 2.5 4.5 6.5 8.5 10
µF µH
Frequency (MHz)
Capacitor Inductor
Transmitters with Amplitude-Modulated Signals
LINEAR AMPLIFIERHIGH-LEVEL AMPLITUDE MODULATION
Patent Pending
Collaborator: Dr. Frederick H. RaabGreen Mountain Radio Research Company, VT
Electronically Tuned Power Amplifier (ETPA)
Load Impedance Varies with:FrequencyGroundProximityTime (heating)Power (plasma)
Antenna Tuner Plasma GeneratorBIAS/CONTROLBIAS/CONTROL
PA PA
Patent PendingPatent Pending
Prototype Electronically Tuned PA
ETPA - Tuning Performance
POWER OUTPUT EFFICIENCY
OPERATING FREQUENCY RANGE
Fixed conventional: 23.0 - 25.5 MHz (1.11:1)Electronic: 18.75 - 31.5 MHz (1.68:1)
Load -Modulated Class-E PAMeasured Efficiency
INSTANTANEOUS EFFICIENCY AVERAGE EFFICIENCY
• Only one bias (T network) varied• Average efficiency x 2.7 for 10-dB peak-to-average ratio
Load-Modulated Class-E PA Efficiency
Only one element (T- network capacitor) varied
Average efficiency 87% for 10-dB peak-to-average ratio
INSTANTANEOUS EFFICIENCY AVERAGE EFFICIENCY
Our Vision for RF Power Module
SiC Substrate
GaN RFPower FET
L C
GaNIMN
GaNOMN
GaN SMPSPower FET
SOIControl
IC
PowerSource
Utilization of DC Power
PV Supplemented Adjustable Speed Motor DrivesPV Supplemented Resistive Loads
Conventional AC Power Input
(utility)
Rectifier
Resistive Heat Element
DC Bus (250-600V)
PV Array (< 10kW)
DC Level Converter
Conventional AC Power Input
(utility)
Drive Rectifier Unit
DC Bus (250-600V)
PV Array
DC Level Converter
Adjustable Speed Drive Inverter
Overall ASD UnitEPRI White Paper
COM & COMP
Lighting
SolarWind
Fuel CellsOther
Renewable Sources
SMART WIRELESS DIGITAL
CONTROLLER
HVAC
Energy Conversion &
Power Management
AC Grid
Edison Grid @
DC BUS
Energy Storage
10 kW Distributed Smart DC Solar MicrogridMajor Goal:
Increase < 86% (current) efficiency to >93% with
direct DC distribution and utilization.
Achieve 50% cost reduction in power electronics.Collaborator:
Nextek Power SystemsMicrel
Medium Power Integration
>95%
>97%
High-Penetration of DC Microgrid
High penetration of DC microgrid could potentially lead to > 22% gain in energy efficiency in residential, commercial, manufacturing and data centers in the US.
Impact of DC Microgrid on US National Economy
P. Savage et al, Yale School of Forestry and Environmental Studies, pp. 51-66, June 2010.
Sector Potential TWh Saved
Potential Efficiency Gain (%)
Potential Reduction in US Load (%)
ResidentialCommercialManufacturingData CentersTotal
1211237715
337
2519202822
33
1.90.48.3
High-Power Technology
Hubert Mills Digital Power Report
Expand the speed x power envelope
High-Power Converters• 5.8kV Si IGBT module• Integrated current sensor• ZCTS topology• PEBB packaging
M. Trivedi and K. Shenai, APEC Digest, 2001
C
E
B
100 kW Inverter (DOE)
150 kW DC-DC Converter
• 1.2kV, 100A Si IGBT module
• 1.2 kV SiCSchottky Diode
• Hard Switching• Liquid Cooling
New
Collaborators: ABB, AdTranz & Hitachi
Collaborator: RMS Power Systems
Thermal Management
Heat Exchanger Flow Channel Approach
Perfect Semiconductor Power Switch
S
G
D
20th Century Technology 21st Century Technology
Si MOSFET SiC IGBT
Shenai et al, IEEE TED, vol. 36, no. 9, pp. 1811-1823, Sept. 1989
G
E
C
S S
D
P+Substrate
N- Drift region
P Base P Base
N+ N+N+Oxide
N+
Substrate
P-
N
P+PP
N+ N+
G G
K
Sio2Co
Meta
Metal
Si IGBT SiC MCT
MOS-Controlled Thyristor –The “Holy Grail” of Power Switch
V. Temple, EPRI Technical Report # TR – 106991, Nov. 1996
Lowest On-State Power Loss
Turn-off Failure
Why Silicon Carbide (SiC) ?
Silicon for Power
Silicon Carbide Offers• Higher Switching Frequency• Higher Voltage Devices • High Temperature Operation
Compact Power Converter High Power Operation Energy and Cost Savings Harsh Environmental Operation
The Roadblock to SiC adoption has been:ReliabilityCost
Si 4H SiC 3C SiC
Band Gap (eV) 1.12 3.2 2.2
Electron Mobility (cm2/Vs)
1400 800 750
Breakdown Field (MV/cm)
0.25 3.0 2.2
Thermal Conductivity
(W/cm.K)
1.5 3.5 3.5
Qss (cm-2) 1012-1013 1011
SBD MOSFET& SBD
Reduced Cooling
High TempHigh Speed
High Voltage
Lower VTBlocking Voltage (< 8 kV)Current Density -Thermal Limits (< 100 A/cm2)
Has hit a brick wall
SiC Schottky vs SiC PiN Diode
Silicon Carbide (SiC) Power Converter
Shenai’s Figure of Merit -
2400x improvement
QF 2 = λσ AEM
Shenai’s Figure of Merit -
2400x improvement
QF 2 = λσ AEM
Application: 2 kV, 7 kW PS-ZVS FB DC-DC Converter
Silicon Power Switch
SiC Power Switch
Parameter SiC SiFrequency (kHz) 500 50
Filter Capacitance (μF) 10 100
Filter Inductance (mH) 0.6 6
Transformer Volume (cm3) 63 215
Efficiency (%) 95 @ 22C89 @ 150C85 @ 300C
92 @ 22CNoNo
Power Density (W/cm3) 8 4
K. Shenai et al, IECEC Conference Digest, pp. 30-36, 2000
50,000 cm3
18 kg
4,500 cm3
0.2 kgCollaboration NASA Glenn Research Center
K. Shenai et al, IEEE TED, pp. 1811-1823, 1989
Poor Turn-Off dv/dt of SiC Schottky Diode
Diodes are leaky and NOT avalanche rated
K. Acharya and K. Shenai, Proc. PET Conference, pp. 672-677, Oct. 2002
SW2 SiC Schottky Diode : 6A/600V; PD2 Si PiN Diode : 8A/600VSW1 SiC Schottky Diode : 10A/300V; SD1 Si Schottky Diode : 12A/200V
• SiC Schottky diode fails at dv/dt = 57 V/ns• No failure observed even at dv/dt = 70V/ns for silicon diode of similar rating• Activation of SiC defects at high dv/dt causes high current and failure, failure
may be related to poor edge termination
600V Devices
dv/dt1
TC = 25 C
0
1.5
3
4.5
6
0 15 30 45 60
SW2
PD2
Peak
Dio
de C
urre
nt (A
)
Failure Instant
Voltage = 600V
0
0.75
1.5
2.25
3
0 15 30 45 60
SW1
SD1
dv/dt1Pe
ak D
iode
Cur
rent
(A)
200/300V Devices
Failure Instant
Voltage = 200V
TC = 25 C
Schottky Junction ON and OFF States
Metal
Depletion Region
N
1.1V
100A
1000V
250 µA
1.5V
100A
dv/dt(+ ve)
di/dt(- ve)
dv/dt(- ve)
di/dt(+ ve)
ON ONOFF
Low E-field High E-fieldNeed high τSC
Low E-field
N
P+
Junction JunctionMetal
Depletion Region
N
Metal
Depletion Region
N
dv/dt failure is due to excess charge generation in the depletion region
10-9
10-8
10-7
10-6
10-5
10-4
10-3
-100 -80 -60 -40 -20 0
Cur
rent
(A)
Voltage (V)
With
Without1c ScrewDislocation(s)
Optical Photo (No Metal)
X-Ray Topograph
Closed Core (1c)Screw Dislocations
BreakdownMicroplasmas
SiC PN Diode Closed Core Screw Dislocation Study
Reverse I-V Properties
100 µm
- Increased reverse leakage.
- Softened breakdown I-V knee (repeatable).
- Local microplasma breakdown.
Courtesy of Dr. Phil Neudeck, NASA GRC
PN Junction Failure at Micropipe
P-type
N-type
micropipes
failuremicroplasma
P 6H-SiC
N 6H
-SiC
+ -
Microscope
Lightsource
Micropipe
V R
1 m
m
Micropipe propagates through wafer & epilayer normal to wafer surface.
Causes large reduction in breakdown voltage, localized junction failure.
Courtesy of Dr. Phil Neudeck, NASA GRC
λ = 313 nm Vbias = 500 V
a)
λ = 313 nm Vbias = 300 V
b)
Figures from Frischholz et. al., MRS Symp. Proc. 512, p. 157 (1998)
Localized leakage, breakdown, and hot-spot formation is undesired in power devices.
Localized Currents in SiC Power Devices
OBIC* of “Good” Diode OBIC* of “Bad” Diode
- Device’s ability to withstand dynamic circuit faults is reduced.- Lowers device avalanche energy rating.- Decreases power device reliability.
*OBIC = Optical Beam Induced Current
Courtesy of Dr. Phil Neudeck, NASA GRC
Kimoto et. al., IEEE Trans. Electron Devices, vol. 46 (3), p. 471, 1999
SiC PN Diode Performance vs. Area
Extracted defect density 1000 - 2000 per square cm.
6.0 V @ 1.0 A 6.9 V @ 1.0 A
Type-1 Images at 1.0 A
Before and After Current Stressing
Lower current capacity in dark areas
Courtesy of Dr. Robert Stahlbush, NRL
PN Junction ON and OFF States
Depletion Region
1.5V
100A
Depletion Region
1000V
250 µA
Depletion Region
1.5V
100A
dv/dt(+ ve)
di/dt(- ve)
dv/dt(- ve)
di/dt(+ ve)
ON ONOFF
Low E-fieldNeed high τn0 and τp0
High E-fieldNeed high τSC
Need low τn0 and τp0
Low E-fieldNeed high τn0 and τp0
P+
N
N
N
P+
P+
Junction Junction
Silicon Carbide (SiC) – Potential Benefits & Status
• For more than TWO decades, it has been recognized that SiliconCarbide (SiC) can provide major advantages over silicon inhigh-power and harsh environmental electronics [1].
Because of superior electrical, thermal, mechanical, and chemical properties, SiC power devices promise dramatic improvements in energy efficiency at significantly reduced cost.
• Much of the research and funding on SiC material in the pasthas been directed at eliminating the bulk micropipes [2].
Several wafer manufacturers including Cree and Dow Corning are marketing Zero Micropipe (ZMP) 4 inch diameter SiC wafers at reasonable cost. However, these wafers typically contain ~104 cm-2 total dislocation defects (screw dislocations, basal plane dislocations, edge dislocations, etc.).
• However, broad based commercial and military benefits of SiChave not yet been realized due to high density of bulk defects [3].
Researchers world-wide have conclusively demonstrated that high density of bulk defects prevent the manufacturing and application of high-voltage and high-current SiC power devices, cause poor field-reliability of power converters, and result in prohibitively high die cost.
[1] K. Shenai et al, IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1811-1823, Sept. 1989.[2] M. Skowronski and S. Ha, J. Appl. Phys., vol. 99, pp. 011101-1 – 011101-24, 2006.[3] K. Shenai, IEEE Spectrum, vol. 37, no. 7, pp. 50-55, July 2000 (invited paper).
Silicon Carbide (SiC) – What is Needed?
• Existing SiC wafer production is inherently flawed in that a highdensity of screw dislocations (SDs) is necessary to achievecommercially viable SiC boule growth rates (the order of 0.5 mm/h) [1].
Current state-of-the-art wide bandgap crystal growth techniques yield more than 103 screw dislocation defectsper cm2 for SiC material and more than 107 per cm2 defects for GaN semiconductor. A defect-free SiC substrateis also crucial to manufacture high-quality of III-Nitride semiconductors used for solar cell and LED applications.
• Our contention is that a NEW approach is needed for SiC bulkcrystal growth in order to achieve its widespread use in powerelectronics, photovoltaics, light emitting diodes, energy harvesting and other energy conversion devices [2].
Must reduce total wafer dislocation density by 100 to 1000 fold compared to the current state-of-the-art.
[1] J. A. Lely, US Patent # 2,854,364, issued on Sept. 30, 1958.[2] J. A. Powell et al, US Patent # 7,449,065 B1, issued on Nov. 11, 2008.
Existing SiC Wafer Growth Approach(Sublimation growth or High Temperature CVD)
C-axis (vertical) growth proceeds from top surface of large-area seed crystal via thousands of screw dislocations.
Crystal enlargement is vertical (up c-axis).Negligible lateral enlargement.
Thermal gradient driven growth at T > 2200 °CHigh thermal stress/strain
Vertical growth rate would not be commercially viable (i.e., would not be high enough) without high density (> 100 cm-2) of screw dislocations.
Fundamental Flaw: Abundant screw dislocation defects are needed for present SiC wafer growth approach, yet these same defects harm SiC power device yield and performance (cause blocking voltage de-rating, leakage, etc.).- High thermal stress also generates dislocation defects.
Future: Game Changer - Large Tapered Crystal (LTC) Growth(US Patent 7,449,065 Owned by OAI, Sest, Inc., with NASA Rights)
Vertical Growth Process:Fiber-like growth of small-
diameter columnar tip region (from single screw dislocation)
Small-diameter c-axis fiber from single screw dislocation at mm/hour rate.
Lateral Growth Process:CVD growth enlargementon sidewalls to produce
large-diameter boule(T = 1500 - 2000 °C)
MOST of crystal grown via epitaxy process on laterally expanding taper at significantly lower growth temperature (lower thermal stress) and growth rate.
Completed boule sectionReady for slicing into wafers
Large diameter wafers yielded at mm/hour (wafers/hour) growth rate!
Tapered portion is then re-loaded into growth system as seed for subsequent boule growth cycle.
“Game Changing” Technology
• 4 in. dia. low-cost, low defect-density commercial wafers• Robust high-performance devices
• Low-cost manufacturing• 250C packaging and 300C sensors
Each Small Black Dot is a Crystal Defect
4H-SiC Diode Etched to Show Defects
100’s of Defects in < 10 Amp device
Best 0.2 x 0.2 mm SD-free 3C mesa(oxidized to map polytype and defects)
Defect-free SiCNeed
Commercialization
LTC Game Changing TechnologyLTC Vision: Dramatically improved SiC wafer quality realized at higher volumes and lower
production cost.
Present-Day SiC Wafer
~100-10,000 screw dislocations/cm2
< 0.5 wafers per hourCost: > $2000/4-inch waferCommercial Power Devices
Limited to < 50 A, ~1 kV
LTC SiC Wafer
< 1 screw dislocation/cm2
> 1 wafer per hourCost: < $500 /6-inch waferCommercial Power Devices
100-1000 A, > 10kV
Drastic wafer improvement sufficient to unlock full SiC power device potential.(Approach also applicable to 3C-SiC, GaN, Diamond, and other semiconductors)
Collaborators: Mike Dudley (SUNY - SB)Phil Neudeck, Andy Trunek, and A. Powell (NASA – GRC)
Hot-Wall SiC CVD Reactor
Gas flowpattern
Temperature gradients Deposition pattern
InletInlet
InletInlet
Outlet
Inlet
Reliable Efficient Semiconductor Power SwitchHigh-Temperature Control IC
High-Temperature, Low-Loss Magnetic and Passive ComponentsNovel Sensors
Compact Thermal Management
POUT = 100 kW@ 100 kHz
TAMB < 200 Cη > 96%
What is Needed ?
Target Specs.
ReliabilityCostSize
Weight
Criteria
POUT = 1 MWTAMB < 200 Cη > 98%
DC-DC Converter Inverter
July 8, 2010 Purdue BNC Seminar
Thanks