Towards a Scalable and Reliable Wireless Network-on-Chip

Amlan Ganguly, Ph.DSchool of EECS, Washington State University

2

Outline

• Introduction• Multi-core & Network-on-Chip (NoC) paradigm

• Performance limitations of conventional planar NoCs• Alternative interconnect technology

• Wireless NoC (WiNoC)• On-chip antennas• Architecture & communication protocols• Performance evaluation

• Reliability• Error Control Coding

• Wireline links• Wireless links

• Future Directions

3

Why Multi-Core Chips?

• The need for explosive computational power• Scientific applications

• Weather prediction, Astrophysics• Bioinformatics, forensics• Language processing

• Consumer electronics • Graphics, Animation

• Soon be in the Exascale age!

The era of single processor systems is over

4

Moore’s Law: so far so good!

• The number of transistors on a chip doubles every 18 months• Has provided the computational power demanded so far

• Now poses major challenges• Soaring power dissipation due to scaling frequency up

Original Moore's Law graph, 1965

5

0.10.1

11

1010

100100

1,0001,000

10,00010,000

’’7171 ’’7474 ’’7878 ’’8585 ’’9292 ’’0000 ’’0404 ’’0808

Power DensityPower Density(Watts/cu. m)(Watts/cu. m)

40044004

8008800880808080

80858085

80868086

286286

386386

486486

PentiumPentium®®

processorsprocessors

Hot PlateHot PlateNuclear ReactorNuclear Reactor

Rocket NozzleRocket NozzleSun’s SurfaceSun’s Surface

Source: Intel

Power Dissipation

• Scaling up speed/frequency is impossible

6

The era of Multi-Core systems

• To keep up with demands on computational power• Scaling of clock frequency is not possible

• Solution: Increase number of cores - parallelism• Intel, AMD dual-core and quad-core CPUs

• Custom Systems-on-Chip (SoCs)• Number of cores need to increase manifold in the next 5-10 years

Nokia Sparrow

Intel 80 core processor

New challenge: interconnection of the cores!

7

The new interconnection paradigm: Network-on-Chip (NoC)

• Driven by• Massive levels of

integration• New designs

counting 100s of embedded cores

• Need for platform-based interconnection infrastructure

• time-to-market

8

NoC Features and Advantages

• Packet switched on-chip network• Route packets, not wires –Bill Dally, 2000.

• Dedicated infrastructure for data transport• Decoupling of functionality from communication

High-bandwidthmemory interface

High-performanceARM processor

High-bandwidthARM processor

DMA Busmaster

BRI

DGE

UART

PIOKeypad

TimerAHB APB

NoC infrastructureAMBA bus: ARM

Multiple publications in IEEE ISSCC, 2010 from Intel, IBM, AMD, Renesas Tech. and Sun Microsystems show that multi-core NoC is a reality

9

Outline

• Introduction• Multi-core & Network-on-Chip (NoC) paradigm

• Performance limitations of conventional planar NoCs• Alternative interconnect technology

• Wireless NoC (WiNoC)• On-chip antennas• Architecture & communication protocols• Performance evaluation

• Reliability• Error Control Coding

• Wireline links• Wireless links

• Future Directions

10

Limitations of a Traditional NoC

• Multi-hop wireline communication• High Latency and energy dissipation

source destination

-core

-NoC interface

-NoC switch

80% of chip power will be from on-chip interconnects in the next 5 years – ITRS, 2007

11

Wireless/RFInterconnects

Optical Interconnects

Three DimensionalIntegration

Novel Interconnect Paradigms for Multicore designs

High Bandwidth and

Low Energy Dissipation

12

3D NoC

• Pavlidis et al., “3-D topologies for Networks-on-Chip”, IEEE Transactions on Very Large Scale Integration (TVLSI), 2007.

• Stacking multiple active layers

• Manufacturability• Mismatch between various

layers• Yield is an issue

• Temperature concerns• Despite power advantages,

reduced footprint increases power density

13

Photonic NoC

• High bandwidth photonic links for high payload transfers

• Challenges: On-going research• On-chip integration of photonic components

• A. Shacham et al., “Photonic Network-on-Chip for Future Generations of Chip Multi-Processors”, IEEE Transactions on Computers, 2008.

14

NoC with RF Interconnects

•Use of transmission lines out of package or IC structures like parallel metal wires

•Challenges:•Routing of long

transmission lines without eliminating any existing links

•Causes hotspots at drop-points

RF Interconnect

NoC Switch

Wireline NoC links

RF/Wireline Drop Point

• M. F. Chang et al. “CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect”, Proc. of IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2008.

15

State-of-the-art in emerging NoCs

3D NoC Photonic NoC NoC with RF-I

Design RequirementsMultiple layers with

active devicesSilicon photonic

componentsOn-chip waveguide

Performance Gains

BandwidthHigher connectivity

& less hop countHigh speed optical

devices and linksHigh bandwidth RF

waveguide

Lower Power

Shorter average path length

Negligible power dissipation in optical data

transport

Low power dissipation in RF-I

Reliability Vertical Via FailureCrosstalk in photonic

waveguidesSignal interference in

the waveguide

ChallengesHeat dissipation

due to higher power density

Integration of on-chip photonic components

Precision high frequency

oscillators and filters

16

Outline

• Introduction• Multi-core & Network-on-Chip (NoC) paradigm

• Performance limitations of conventional planar NoCs• Alternative interconnect technology

• Wireless NoC (WiNoC)• On-chip antennas• Architecture & communication protocols• Performance evaluation

• Reliability• Error Control Coding

• Wireline links• Wireless links

• Future Directions

17

The Wireless Network-on-Chip (WiNoC)

Use of on-chip wireless links

High bandwidth: 500 Gbps - ~ 1 Tbps

Wires: ~ 3 Gbps

Latency: True speed-of-light

Wires: ~ 400 ps

Long distance: ~ 15 mm - 25 mm

Wires: ~ 2 - 3 mm

•No physical interconnect layout is necessary

Reduce latency and energy dissipation in communication

18

Early example of on-chip wireless interconnects

• First utilized for distribution of clock signal• Technology: 0.18 um CMOS• Operating frequency: 15 GHz

• Single Tone• Modulation and Channelization was not a concern

• Floyd et al., IEEE Journal of Solid-State Circuits,2002.

19

Adopted Technology:Carbon Nanotube (CNT) antennas

• High B/W, frequency light (IR, visible, UV)• Small wavelength: small antennas• less area

• CNTs as Optical Antennas

• Directional radiation characteristics • Quantitative agreement with

conventional radio antenna theory and simulations

• Laser excitation

• Kempa, et al., "Carbon Nanotubes as Optical Antennae," Advanced Materials, 2007.

• Slepyan, et al., "Theory of optical scattering by achiral carbon nanotubes and their potential as optical

nanoantennas," Physical Review B, 2006.

20

Design Constraints

• Limited wireless channels• Off-chip laser sources

• On-chip wireless nodes have associated overhead

• Transceiver• Modulator/demodulator• antennas

How to efficiently distribute the wireless resources?

Everything fine?

21

Hybrid nature of the WiNoC

• Augment wireline with wireless• Not completely wireless

• Divide the whole NoC into multiple subnets

• Communication within the subnets is still through wires

• Utilize wireless links for inter-subnet data exchange

• Each subnet will have a hub• Equipped with Wireless Base

Station (WB)Embedded Cores

Wireline NoC Switch Antenna

STARMESH

IRREGULAR

TREE

Wireless Base stations

• Subnet architectures may vary and even be heterogeneous on the same chip

22

Network Design Principles

• Topology• Establish connectivity among the subnets through hubs• Reduce multi-hop communication using the wireless

channels• Near constant bandwidth over all range of communication• Can be used as long-distance shortcuts

→ Adopt SMALL-WORLD network topology

• Communication mechanism• How to send bits through the CNT antennas

• Minimize the WB overhead• Simple yet efficient physical layer

23

Connecting the Hubs• Small-World graphs: The Watts-Strogatz Model• Often found in nature• Scales well: low average distance

regular latticeL: HiC: Hi

Small-worldL: LoC: Hi

random graphL: LoC: Lo

o Few high speed shortcuts: Wirelesso Local, shorter links: Wireline

24

Proposed Hybrid, Hierarchical WiNoC Architecture

HubWireless linkWireline link

Small World network of hubs

• Mesh-based wireline subnets• Each subnet has a hub

• Interconnected with neighboring hubs in a ring topology

• Some hubs have WBs• Providing wireless shortcuts• Creating small-world topology in the upper level

Embedded CoreSwitch

Subnet

25

How to establish wireless links? Simulated Annealing

• Shortcuts, but where?

• Optimization metric• Distance, frequency of communication

• Convergence is faster than exhaustive search• Scalable technique• Stable convergence for several cooling profiles

ji

ijij fh,

0

100

200

300

400

500

600

8 16 32Number of Subnets

Nu

mb

er

of

ite

rati

on

s

SAExhaustive search

0 20 40 60 80 100 120 140 160 180 2006.3

6.4

6.5

6.6

Number of Iterations

Val

ue

of

op

tim

izat

ion

mer

ic

T0=0.1T0=0.5T=1.0

26

Network Design Principles

• Topology• Establish connectivity among the subnets through hubs• Reduce multi-hop communication using the wireless

channels• Near constant bandwidth over all range of communication• Can be used as long-distance shortcuts

→ Adopt SMALL-WORLD network topology

• Communication mechanism• How to send bits through the CNT antennas

• Minimize the WB overhead• Simple yet efficient physical layer

27

Communication mechanisms with CNT antennas

• Multiband laser sources to excite the antennas• Frequency Division Multiplexing (FDM)

• Different frequency channels can be assigned to pairs of communicating subnets• Antenna elements tuned to different frequencies• No complex MAC required

• Electro-Optic Conversions• Mach-Zehnder Modulators (MZM)• Perform OOK on light carrier

• Supported B/W of 10Gbps/channel

An ultra compact 10 Gbps silicon modulator

Green et. al., “Ultra-compact, low RF power, 10Gb/s silicon Mach-Zehnder modulator,” Optics Express, 2007

28

Adopted channelization scheme

8 Time Slots

f1

4 bits

32 bits

TDM

FDM

f2

f4

f3

4 Wireless Channels

0.1ns• 32-bit flit width

• 24 distinct frequency channels• Total wireless B/W of

240 Gbps

• m wireless links• 1-24 links• 24/m distinct

frequency channels per link

• Combination of FDM and TDM.

Performance Evaluation

• Comparison with Flat wireline mesh

• Scaling methods with size

• Comparisons with other emerging NoCs

• Overheads

30

Compared with flat wireline mesh

• System size: 256 cores• Throughput• Packet Energy

0.0 0.2 0.4 0.6 0.8 1.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.8 0.9 1.00.680.690.700.710.720.73

Th

rou

gh

pu

t (f

lits/

core

/cyc

le)

Injection Load (flits/core/cycle)

1 Wi-Link 6 Wi-Links 24 Wi-Links 256 core Mesh

System Size

Flat Mesh (nJ)

WiNoC (nJ) ratio

128 1319 22.57 58

256 2936 24.02 122

512 4992 37.48 133

• Orders of magnitude less !

• Gets better with size

Ganguly et al., “Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-Core Systems”, IEEE Transactions on Computers (TC), 2010.

31

Establishment of scaling trend

Subnet Size = 16

0

10

20

30

40

50

60

8 16 32

Number Of Subnets

Pac

ket

En

ergy

(n

J)

1 Wi-Links6 Wi-Links24 Wi-Links

Number Of Subnets = 16

0

10

20

30

40

50

60

8 16 32Subnet Size

Pac

ket

Ene

rgy

(nJ)

1 Wi-Links6 Wi-Links24 Wi-Links

Scales better with increase in number of subnets

• Packet Energy dissipation • Varying subnet size and number• Varying number of wireless links

32

Comparative Performance Evaluation

• Case study:128 cores• Achievable network bandwidth

• Packet Energy dissipation 0

2

4

6

8

WiN

oC

Phot

onic

NoC

3D N

oC

RF-

I NoC

Emerging NoCs

Pack

et e

nerg

y pe

r ban

dwid

th

(nJ/

Tbps

)

0

0.4

0.8

1.2

Ban

dwid

th (T

Bps

)

Packet energy per bandwidth

Bandwidth

WiNoC performs best

33

Overheads• Area Overhead

• Wiring overheads• Additional links

• Core-hub• Inter-hub

0

30

60

90

NS = 8,SS = 16

NS = 16,SS = 8

NS = 16,SS = 16

NS = 16,SS = 32

NS = 32,SS = 16

System size/configuration

To

tal

are

a o

f N

oC

sw

itc

he

s a

nd

hu

bs

(s

q.

mm

)

total hub area inWiNoC

total switch area ina flat mesh

0

400

800

1200

1600

NS

= 8

, S

S =

16

NS

= 1

6, S

S =

8

flat

mes

h

NS

= 1

6, S

S =

16

flat

mes

h

NS

= 1

6, S

S =

32

NS

= 3

2, S

S =

16

flat

mes

h

128 256 512System size/configuration

Nu

mb

er o

f li

nks

0.625mm

1.25mm

2.5mm

3.75mm

5mm

7.5mm

10mm

About 10-20% area overhead depending on the system size

34

Summary of WiNoC Performance

• Up to 2 orders of magnitude less energy dissipation

• Much higher bandwidth compared to wireline NoCs of same size

• Better performance than all other emerging NoC paradigms

• Reasonable real estate overheads

35

Outline

• Introduction• Multi-core & Network-on-Chip (NoC) paradigm

• Performance limitations of conventional planar NoCs• Alternative interconnect technology

• Wireless NoC (WiNoC)• On-chip antennas• Architecture & communication protocols• Performance evaluation

• Reliability• Error Control Coding

• Wireline links• Wireless links

• Future Directions

36

Reliability and Signal Integrity

According to ITRS signal integrity will become a major issue in future technologies

• Shrinking geometries: less charge/information

• Increased probability of transient events like:• Crosstalk• Ground Bounce• Alpha particle hits

• WiNoCs• Use of inherently defect prone CNT technology

Error Control Coding is a solution

ECC: Wireline links

• Joint Codes• Crosstalk Avoidance

Codes• Error Correction

Codes

• Proposed codes• CADEC: double error• JTEC: triple error• JTEC-SQED:

quadruple error

• Optimization• Hsiao SEC-DED code

(38,32)Hamming encoding

32 38

38 parity, bit76

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 74

bit 75

32 bit i/p

77 bit o/p

Hamming encoding

DAP duplication

Joint Codes

• Voltage Swing reduction• Lower noise margins

10-20

10-15

10-10

10-5

0.2

0.4

0.6

0.8

1

Word Error Probability

Vo

ltag

e S

win

g (

V)

ED

DAP/DR

CADEC

JTEC

JTEC-SQED

• Asymptotic reduction• Increasing error correction capability

• Disadvantageous beyond 4 errors 0 1 2 3 4 5

0.4

0.5

0.6

0.7

0.8

0.9

1

Error Correction Capability

Vo

ltag

e S

win

g (

V)

2ddVQ

)(

)ˆ(ˆ1

1

Q

QVV dddd

)()ˆ( UNCECC PP

39

Energy Dissipation Characteristics

• ECCs in subnet links

• 64 core wireline NoC

0

500

1000

1500

2000

2500

3000

3500

4000

4500

5000

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Injection Load

En

erg

y D

iss

ipa

tio

n (

pJ

)

uncodedEDDAPCADECJTECJTEC-SQED

Ganguly et al., “Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NoC Interconnects”, IEEE Transactions on VLSI (TVLSI) 2009.

47%33%

40

ECC: Wireless links

• Each CNT antenna element responsible for multiple bit transmission• Burst Errors• Multi-bit error

• Multi-path interference• Packaging surfaces 4

1 2

3

ceiling

ground

LOS

TxRx

2

2

,

2

,

4

2

343

2

332

2

221

2

11

2

,

4321

4

ground

Rj

groundgroundTceiling

Rj

celingceilingT

Rj

T

Rj

T

Rj

T

Rj

TLOS

Rj

LOST

TR

R

R

eG

R

eG

R

eG

R

eG

R

eG

R

eG

R

eG

PA

Pgroundceling

LOS

SNR & BER

• Single transmitter position

• Reception across die area

• Non-coherent OOK modem

05

1015

20

0

5

10

15

200

10

20

30

40

50

60

X-dimension of the die (mm)Y-dimension of the die (mm)

SN

R (

dB)

5

10

15

20

25

30

35

40

45

50

0 2 4 6 8 10 12 14 16 18 2010

-30

10-25

10-20

10-15

10-10

10-5

100

SNR (dB)

BE

R

SNR-BER characteristics for non-coherent OOKBER of the wireless links

0.001

Product Code

• Using simple ECCs on both spatial and time axes• Hamming codes

• Hamming-Product Code (H-PC)

(38,

32)

Ham

min

g E

nco

der

0

37

(7,4) Hamming Encoded Data in Time domain

Message Bits Parity Bits

(38

,32)

Ha

mm

ing

En

co

de

d

Da

ta in

sp

ati

al d

irec

tio

n

32 bit i/p

Structure of the product code encoder

Results

• Increase reliability

• Keep energy dissipation low

• Low latency

1

10

100

1000

10000

MESH MESH-ECC WiNoC WiNoC-ECC

NoC Architectures

Pa

ck

et

En

erg

y (

nJ

)

1.00E-20

1.00E-12

1.00E-04

1.00E+04

Eff

ec

tiv

e B

ER

Packet Energy

BER

0

400

800

1200

1600

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Injection Load (flits/core/cycle)

Lat

ency

(cy

cles

) WiNoCMESHWiNoC-ECCMESH-ECC

0 2 4 6 8 10 12 14 16 18 2010

-100

10-80

10-60

10-40

10-20

100

SNR (dB)

BE

R

SNR-BER characteristics for non-coherent OOK

BER of the wireless links without H-PC

Wireless link BER with H-PC

1E-3

1E-12

44

Outline

• Introduction• Multi-core & Network-on-Chip (NoC) paradigm

• Performance limitations of conventional planar NoCs• Alternative interconnect technology

• Wireless NoC (WiNoC)• On-chip antennas• Architecture & communication protocols• Performance evaluation

• Reliability• Error Control Coding

• Wireline links• Wireless links

• Future Directions

45

Future Directions

1. Wireless NoCs with millimeter-wave Interconnects

2. Extension of the ECC schemes

3. Unified design framework with alternative interconnect technologies• Complex Networks

46

Alternative Antennas

• CNTs still have manufacturing issues

• Metal Zig-Zag antennas

• Bandwidth: ~ tens of GHz80

µm

1 mm

30°

10 µm

47

Another alternative antenna

• Electrolumiscence in CNTs• No separate modulator/demodulators required• Much less overhead

• Range of communication needs to be investigated• Can be used for short range wireless interconnects

Nojeh et. al., "Reliability of wireless on-chip interconnects based on carbon nanotube antennas," International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW), 2008.

Extension of ECC schemes

• Use of multiple error correction codes• Space• Time• Both

• Correct multiple bursts in either direction• BCH codes• RS codes

• Study performance• Performance-overhead trade-offs

49

Unified Framework• All alternative interconnect technologies

• Network topologies with all the possible interconnects

• Determine each one’s spot in the design space

• Look across varying granularity for optimization• Nodes: subnets to even devices• Develop CAD methodologies for novel

interconnects

• Can an optimal solution for N cores readily be scaled up to 10N or 1000N cores? • If not, what is the difference and what are the

design rules as the system scales up?

• Super low-power interconnects• Sustainability of computing: Scalability• Green computing paradigms

Fault Tolerance: Complex Networks

• Small-World/Exponential graphs• Nodes with similar degrees

• Resilient to targeted attacks

• Scale-free graphs• Few high-degree nodes

• Resilient to random failures

R. Albert, H. Jeong and A. Barabási, “Error and Attack Tolerance of Complex Networks”,

Nature, Vol. 406, July 2000, pp. 378-382.

51

Conclusions

• NoC is a reality• Limitations: performance & energy

• Alternative interconnect technology• High bandwidth, low power• Long distance shortcuts

• Adopt nature-inspired topologies• Optimize network

• Increase reliability• ECC• Complex Network theory

52

Journal Publications

1. Amlan Ganguly, Kevin Chang, Sujay Deb, Partha Pande, Benjamin Belzer, Christof Teuscher, “Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-Core Systems”, IEEE Transactions on Computers (TC), June, 2010, accepted for publication.

2. Amlan Ganguly, Partha Pande, Benjamin Belzer, “Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NoC Interconnects”, IEEE Transactions on VLSI (TVLSI) Vol. 17, No.11, November 2009, pp. 1626-1639.

3. Amlan Ganguly, Partha Pande, Benjamin Belzer, Cristian Grecu, "Design of Low power & Reliable Networks on Chip through joint Crosstalk Avoidance and Multiple Error Correction Coding", Journal of Electronic Testing: Theory and Applications (JETTA), Special Issue on Defect and Fault Tolerance, June 2008, pp. 67-81.

4. Partha Pande, Amlan Ganguly, Haibo Zhu, Cristian Grecu, “Energy Reduction through Crosstalk Avoidance Coding in Networks on Chip", Journal of System Architecture (JSA), Vol. 54/ 3-4, March-April 2008, pp.441-451.

53

Conference Publications/Book Chapters

1. Partha Pratim Pande, Cristian Grecu, Amlan Ganguly, Andre Ivanov, and Resve Saleh, “Test and Fault Tolerance of NoC Infrastructures”, In Networks-on-Chips: Theory and Practice, Fayez Gebali, Haytham Elmiligi, and M.Watheq El-Kharashi (eds.), Taylor & Francis Group LLC - CRC Press.

2. Sujay Deb, Kevin Chang, Amlan Ganguly and Partha Pande, “Comparative Performance Evaluation of Wireless and Optical NoC Architectures”, Proceedings of IEEE International SOC Conference (SOCC), 27th-29th September 2010.

3. Sujay Deb, Amlan Ganguly, Kevin Chang, Benjamin Belzer, Deuk Heo, “Enhancing Performance of Network-on-Chip Architectures with Millimeter-Wave Wireless Interconnects”, Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2010.

4. Partha Pande, Amlan Ganguly, Kevin Chang, Christof Teuscher, “Hybrid Wireless Network-on-Chip: A New Paradigm in Multi-Core Design”, invited paper, Second International Workshop on Network-on-Chip Architectures (NoCArc), December 12, 2009.

5. Amlan Ganguly, Kevin Chang, Partha Pratim Pande, Benjamin Belzer and Alireza Nojeh, "Performance Evaluation of Wireless Networks on Chip Architectures", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), 16th-18th March 2009.

6. Partha Pande, Amlan Ganguly, Benjamin Belzer, Alireza Nojeh, Andre Ivanov, “Novel Interconnect Infrastructures for Massive Multicore Chips”, Proceedings of IEEE Symposium on Circuits and Systems (ISCAS) , May, 2008, pp. 2777 - 2780.

Conference Publications contd.7. A. Nojeh, P. Pande, A. Ganguly, S. Sheikhaei, B. Belzer and A. Ivanov,

"Reliability of wireless on-chip interconnects based on carbon nanotube antennas," Proceedings of IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW) June 2008, pp. 1-6.

8. Amlan Ganguly, Partha Pande, Benjamin Belzer, Cristian Grecu, “Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding”, Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2007, May, 2007, pp. 317 - 324.

9. Partha Pande, Amlan Ganguly, Brett Feero, Cristian Grecu, “Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics”, Proceedings of IEEE International ON-line Test Symposium (IOLTS), July, 2007, pp. 161-166.

10. Partha Pande, Amlan Ganguly, Brett Feero, Benjamin Belzer, Cristian Grecu, "Design of Low Lower & Reliable Networks on Chip through Joint Crosstalk Avoidance and Forward Error Correction Coding", Proceedings of IEEE Defect and Fault Tolerance in VLSI Systems (DFT), 2006, pp. 466 – 476.

11. Partha Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu, “Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm", Proceedings of IEEE EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD) 2006, pp. 689 – 695.

12. Partha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu, "Crosstalk-aware Energy Reduction in NoC Communication Fabrics", Proceedings of IEEE International SOC Conference (SOCC), 2006, pp. 225 – 228.

55

Acknowledgements

• Advisor • Dr. Partha Pande, WSU

• through NSF CAREER Grant

• Collaborators• Dr. Benjamin Belzer, WSU• Dr. Alireza Nojeh, UBC• Dr. Christof Teuscher, PSU• Dr. Deuk Heo, WSU• Intel, CRL, OR

• Colleagues in my Lab• Mr. Kevin Chang, WSU• Mr. Sujay Deb, WSU

• Family• Parents• Rini

56

Thank you