Topological Design of Clock Topological Design of Clock Distribution Networks Based Distribution Networks Based

on Non-Zero Clock Skewon Non-Zero Clock SkewSpecificationSpecification

A Class Presentation for VLSI courseA Class Presentation for VLSI course By: By: Sareh MohebaliSareh Mohebali

Based on the work presented in:Based on the work presented in:

Design of Clock Distribution NetworksDesign of Clock Distribution NetworksAuthors:Authors:

Jose Luis Neves and Eby G.FriedmanJose Luis Neves and Eby G.FriedmanDepartment of Electrical EngineeringDepartment of Electrical Engineering

University of RochesterUniversity of Rochester

OutlineOutline

DETERMINATION OF CLOCK PATH DELAYTheoretical BackgroundClock Path Delay Algorithm

TOPOLOGY OF CLOCK DISTRIBUTION NETWORKConstruction Of The Clock Tree StructureCalculation Of Branch DelayReorganization Of The Clock Tree

Increasing Performance Of Clock Distribution Network

Repeater InsertionRepeater Insertion To convert highly resistive-capacitive To convert highly resistive-capacitive

networks into effectively capacitive networksnetworks into effectively capacitive networks Symmetric Distribution Networks such as Symmetric Distribution Networks such as

H-tree StructuresH-tree Structures To ensure minimal clock skewTo ensure minimal clock skew

Zero Skew Clock Routing AlgorithmsZero Skew Clock Routing Algorithms To automatically layout these high speed To automatically layout these high speed

networks in cell-based designsnetworks in cell-based designs

Determination of Clock Path DelayDetermination of Clock Path Delay

Negative Clock Skew (Cycle Stealing) Negative Clock Skew (Cycle Stealing) Shifts delay from the faster neighboring local data Shifts delay from the faster neighboring local data

paths into the slower critical pathspaths into the slower critical paths Reducing the system-wide clock periodReducing the system-wide clock period Improving overall circuit performanceImproving overall circuit performance

Investigating any relationship between the clock Investigating any relationship between the clock skews of the sequentially adjacent registers skews of the sequentially adjacent registers within a global data pathwithin a global data path

Describing the clock skew of global data paths Describing the clock skew of global data paths which contain feedback paths which contain feedback paths

Clock Path Delay AlgorithmClock Path Delay Algorithm

Choosing the local data path with the Choosing the local data path with the largest clock skewlargest clock skew

Positive clock skewPositive clock skew Negative clock skewNegative clock skew Graph representation of the circuitGraph representation of the circuit Path_Delay procedurePath_Delay procedure

Calculating Clock DelayCalculating Clock Delay

Algorithm to Find the Optimal Clock Algorithm to Find the Optimal Clock Delay to each RegisterDelay to each Register

Topology of Clock Distribution Topology of Clock Distribution NetworkNetwork

Providing an independent path delay for each Providing an independent path delay for each registerregister Isolating each clock signalIsolating each clock signal Requiring simple circuit composed of cascaded Requiring simple circuit composed of cascaded

invertersinverters Expending significant chip areaExpending significant chip area

Tree structureTree structure Extracting hierarchy of the circuit from the circuit Extracting hierarchy of the circuit from the circuit

netlistnetlist Calculating the individual clock delaysCalculating the individual clock delays Internal and External branchesInternal and External branches

Hierarchical representation of the Hierarchical representation of the data path exampledata path example

Determining the Individual Branch Determining the Individual Branch DelayDelay

Delay of external branchesDelay of external branches When both registers within a local data path are driven by the When both registers within a local data path are driven by the

same branching point same branching point

Delay of internal branchesDelay of internal branches Having a global data path driven Having a global data path driven by more than one branching pointby more than one branching point Delay shiftingDelay shifting

Reorganize the delay of the externalReorganize the delay of the external branches to reduce the total numberbranches to reduce the total number of delay units of delay units Increasing flexibility of the circuit Increasing flexibility of the circuit implementationimplementation

Reorganization of the Clock TreeReorganization of the Clock Tree

Having circuit Having circuit descriptions which descriptions which are completely or are completely or partially flatpartially flat

Having a clock Having a clock distribution network distribution network with independent with independent clock paths for each clock paths for each registerregister

ResultsResults

The algorithms for The algorithms for determining the determining the minimum clock delay minimum clock delay of each register and of each register and for calculating the for calculating the clock delay and circuit clock delay and circuit topology of the clock topology of the clock distribution network distribution network