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Audio Serial Data Interface

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLV320AIC3104-Q1SLAS715B –JUNE 2010–REVISED FEBRUARY 2017

TLV320AIC3104-Q1 Low-Power Stereo Audio Codec for Infotainment and Cluster

1

1 Features1• Qualified for Automotive Applications• AEC-Q100 Qualified With the Following Results:

– Device Temperature Grade 3: –40°C to 85°CAmbient Operating Temperature Range

– Device HBM ESD Classification Level 2– Device CDM ESD Classification Level C6

• Stereo Audio DAC– 102-dBA Signal-to-Noise Ratio– 16-, 20-, 24-, or 32-Bit Data– Supports Sample Rates From 8 kHz to 96 kHz– 3D, Bass, Treble, EQ, De-Emphasis Effects– Flexible Power Saving Modes and

Performance are Available• Stereo Audio ADC

– 92-dBA Signal-to-Noise Ratio– Supports Sample Rates From 8 kHz to 96 kHz– Digital Signal Processing and Noise Filtering

Available During Record• Six Audio Input Pins

– One Stereo Pair of Single-Ended Inputs– One Stereo Pair of Fully Differential Inputs

• Six Audio Output Drivers– Fully Differential or Single-Ended Stereo

Headphone Drivers– Fully Differential Stereo Line Outputs

• Low Power: 14-mW Stereo 48-kHz Playback With3.3-V Analog Supply

• Ultralow-Power Mode with Passive Analog Bypass• Programmable Input/Output Analog Gains• Automatic Gain Control (AGC) for Record• Programmable Microphone Bias Level• Programmable PLL for Flexible Clock Generation• I2C Control Bus• Audio Serial Data Bus Supports I2S, Left/Right-

Justified, DSP, and TDM Modes• Extensive Modular Power Control• Power Supplies:

– Analog: 2.7 V to 3.6 V– Digital Core: 1.525 V to 1.95 V– Digital I/O: 1.1 V to 3.6 V

2 Applications• Cluster• Head Unit• Car Audio• Emergency Call (E-Call)• Telematics Control Unit

3 DescriptionThe TLV320AIC3104-Q1 is a low-power stereo audiocodec with stereo headphone amplifiers, as well asmultiple inputs and outputs that are programmable insingle-ended or fully differential configurations.Extensive register-based power control is included,enabling stereo 48-kHz DAC playback as low as 14mW from a 3.3-V analog supply, making it ideal forcar audio applications in cluster and head unitsystems.

The record path of the TLV320AIC3104-Q1 containsintegrated microphone bias, digitally controlled stereomicrophone preamplifier, and automatic gain control(AGC), with mix/mux capability among the multipleanalog inputs. Programmable filters are availableduring record which can remove audible noise thatcan occur during noisy and unpredictableenvironments, such as when an e-call system isactivated. The playback path includes mix/muxcapability from the stereo DAC and selected inputs,through programmable volume controls, to thevarious outputs.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)TLV320AIC3104-Q1 VQFN (32) 5.00 mm × 5.00 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Simplified Diagram

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TLV320AIC3104-Q1SLAS715B –JUNE 2010–REVISED FEBRUARY 2017 www.ti.com

Product Folder Links: TLV320AIC3104-Q1

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Description (continued)......................................... 36 Device Comparison Table ..................................... 37 Pin Configuration and Functions ......................... 48 Specifications......................................................... 5

8.1 Absolute Maximum Ratings ...................................... 58.2 ESD Ratings.............................................................. 58.3 Recommended Operating Conditions....................... 68.4 Thermal Information .................................................. 68.5 Electrical Characteristics........................................... 68.6 Switching Characteristics I2S/LJF/RJF Timing in

Master Mode ............................................................ 108.7 Switching Characteristics I2S/LJF/RJF Timing in

Slave Mode .............................................................. 108.8 Switching Characteristics DSP Timing in Master

Mode ........................................................................ 118.9 Switching Characteristics DSP Timing in Slave

Mode ........................................................................ 118.10 Typical Characteristics .......................................... 14

9 Detailed Description ............................................ 15

9.1 Overview ................................................................. 159.2 Functional Block Diagram ....................................... 169.3 Feature Description................................................. 179.4 Device Functional Modes........................................ 329.5 Programming........................................................... 349.6 Register Maps ......................................................... 42

10 Application and Implementation........................ 7510.1 Application Information.......................................... 7510.2 Typical Applications .............................................. 75

11 Power Supply Recommendations ..................... 7812 Layout................................................................... 78

12.1 Layout Guidelines ................................................. 7812.2 Layout Example .................................................... 79

13 Device and Documentation Support ................. 8013.1 Device Support...................................................... 8013.2 Documentation Support ........................................ 8013.3 Receiving Notification of Documentation Updates 8013.4 Community Resources.......................................... 8013.5 Trademarks ........................................................... 8013.6 Electrostatic Discharge Caution............................ 8013.7 Glossary ................................................................ 81

14 Mechanical, Packaging, and OrderableInformation ........................................................... 81

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (March 2016) to Revision B Page

• Changed the Input Impedance and VCM Control section.................................................................................................... 25• Changed the Hardware Reset section.................................................................................................................................. 33• Added the Receiving Notification of Documentation Updates section ................................................................................. 80• Changed the Electrostatic Discharge Caution statement..................................................................................................... 80

Changes from Original (June 2010) to Revision A Page

• Added Device Information table, Pin Configuration and Functions section, Specifications section, DetailedDescription section, Application and Implementation section, Power Supply Recommendations section, Layoutsection, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section...... 1

• Changed D0 to "R/W" in the Page 0/Register 86: LEFT_LOP/M Output Level Control Register table ............................... 61• Changed D0 to "R/W" in the Page 0/Register 93: RIGHT_LOP/M Output Level Control Register table............................. 62• Changed D2 and D6 of the Page 0/Register 108: Passive Analog Signal Bypass Selection During Power Down

Register table to "R" only and marked as reserved registers............................................................................................... 67


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5 Description (continued)The TLV320AIC3104-Q1 contains four high-power output drivers as well as two fully differential output drivers.The high-power output drivers are capable of driving a variety of load configurations, including up to fourchannels of single-ended 16-Ω headphones using AC-coupling capacitors, or stereo 16-Ω headphones in acapless output configuration. These parameters enable the TLV320AIC3104-Q1 to act as an interface betweenthe MCU and speaker amplifiers, such as the TPA3111D1-Q1, in various audio applications in the infotainmentand cluster fields.

The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filteringin the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz,44.1-kHz, and 48-kHz sample rates. The stereo audio ADC supports sampling rates from 8 kHz to 96 kHz and ispreceded by programmable gain amplifiers (PGA) or an automatic gain control (AGC) circuit that can provide upto 59.5-dB analog gain for low-level microphone inputs. The TLV320AIC3104-Q1 provides an extremely highrange of programmability for both attack (8 ms to 1,408 ms) and for decay (0.05 s to 22.4 s). This extended AGCrange allows the AGC to be tuned for many types of applications.

Where neither analog nor digital signal processing are required, the device can be put in a special analog signalpassthrough mode. This mode significantly reduces power consumption, as most of the device is powered downduring this passthrough operation.

The serial control bus supports the I2C protocol, whereas the serial audio data bus is programmable for I2S,left/right-justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation andsupport for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, withspecial attention paid to the most-popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz systemclocks.

The TLV320AIC3104-Q1 operates from an analog supply of 2.7 V to 3.6 V, a digital core supply of 1.525 V to1.95 V, and a digital I/O supply of 1.1 V to 3.6 V.

6 Device Comparison Table

DEVICE NAME DIFFERENCESTLV320AIC3104-Q1 6 inputs 6 outputsTLV320AIC3106-Q1 10 inputs 7 outputs


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Thermal

Pad

32

DV

DD

9S

DA

1MCLK 24 DRVDD

31

RE

SE

T1

0M

IC1

LP

/LIN

E1

LP

2BCLK 23 HPROUT

30

RIG

HT

_L

OM

11

MIC

1L

M/L

INE

1L

M3WCLK 22 HPRCOM

29

RIG

HT

_L

OP

12

MIC

1R

P/L

INE

1R

P4DIN 21 DRVSS

28

LE

FT

_L

OM

13

MIC

1R

M/L

INE

1R

M5DOUT 20 HPLCOM

27

LE

FT

_L

OP

14

MIC

2L

/LIN

E2

L/M

ICD

ET

6DVSS 19 HPLOUT

26

AV

SS

21

5M

ICB

IAS

7IOVDD 18 DRVDD

25

AV

DD

16

MIC

2R

/LIN

E2

R8SCL 17 AVSS1

4




7 Pin Configuration and Functions

RHB Package32-Pin VQFN With Exposed Thermal Pad

Top View

NOTE: Connect device thermal pad to DRVSS.

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.AVDD 25 — Analog DAC voltage supply, 2.7 V to 3.6 VAVSS1 17 — Analog ADC ground supply, 0 VAVSS2 26 — Analog DAC ground supply, 0 VBCLK 2 I/O Audio serial data bus bit clock input/outputDIN 4 I Audio serial data bus data inputDOUT 5 O Audio serial data bus data outputDRVDD 18 — Analog ADC and output driver voltage supply, 2.7 V to 3.6 VDRVDD 24 — Analog output driver voltage supply, 2.7 V to 3.6 VDRVSS 21 — Analog output driver ground supply, 0 VDVDD 32 — Digital core voltage supply, 1.525 V to 1.95 VDVSS 6 — Digital core / I/O ground supply, 0 VHPLCOM 20 O High-power output driver (left –, or multifunctional)HPLOUT 19 O High-power output driver (left +)


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Pin Functions (continued)PIN

I/O DESCRIPTIONNAME NO.HPRCOM 22 O High-power output driver (right –, or multifunctional)HPROUT 23 O High-power output driver (right +)IOVDD 7 — Digital I/O voltage supply, 1.1 V to 3.6 VLEFT_LOM 28 O Left line output (–)LEFT_LOP 27 O Left line output (+)MCLK 1 I Master clock inputMIC1LM/LINE1LM 11 I Left input – (diff only)MIC1LP/LINE1LP 10 I Left input 1 (SE) or left input + (diff)MIC1RM/LINE1RM 13 I Right input – (diff only)MIC1RP/LINE1RP 12 I Right input 1 (SE) or right input + (diff)MIC2L/LINE2L/MICDET 14 I Left input 2 (SE); can support microphone detectionMIC2R/LINE2R 16 I Right input 2 (SE)MICBIAS 15 O Microphone bias voltage outputRESET 31 I ResetRIGHT_LOM 30 O Right line output (–)RIGHT_LOP 29 O Right line output (+)SCL 8 I/O I2C serial clock inputSDA 9 I/O I2C serial data input/outputWCLK 3 I/O Audio serial data bus word clock input/output

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8 Specifications

8.1 Absolute Maximum Ratingssee (1)

MIN MAX UNITAVDD to AVSS, DRVDD to DRVSS –0.3 3.9 VAVDD to DRVSS –0.3 3.9 VIOVDD to DVSS –0.3 3.9 VDVDD to DVSS –0.3 2.5 VAVDD to DRVDD –0.1 0.1 VDigital input voltage to DVSS –0.3 IOVDD + 0.3 VAnalog input voltage to AVSS –0.3 AVDD + 0.3 VPower dissipation (TJ Max - TA) / RθJA WJunction temperature, TJ 105 °COperating temperature range –40 85 °CStorage temperature, Tstg –65 105 °C

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

8.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman-body model (HBM), per AEC Q100-002 (1) ±2000

VCharged-device model (CDM), per AEC Q100-011 ±1000


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(1) Analog voltage values are with respect to AVSS1, AVSS2, DRVSS; digital voltage values are with respect to DVSS.

8.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITAVDD,DRVDD1/2 Analog supply voltage (1) 2.7 3.3 3.6 V

DVDD Digital core supply voltage (1) 1.525 1.8 1.95 VIOVDD Digital I/O supply voltage (1) 1.1 1.8 3.6 VVI Analog full-scale 0-dB input voltage (DRVDD1 = 3.3 V) 0.707 VRMS

Stereo line output load resistance 10 kΩStereo headphone output load resistance 16 ΩDigital output load capacitance 10 pF

TA Operating free-air temperature –40 85 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

8.4 Thermal Information

THERMAL METRIC (1)TLV320AIC3104-Q1

UNITRHB (VQFN)32 PINS

RθJA Junction-to-ambient thermal resistance 32.3 °C/WRθJC(top) Junction-to-case (top) thermal resistance 17.0 °C/WRθJB Junction-to-board thermal resistance 6.0 °C/WψJT Junction-to-top characterization parameter 0.2 °C/WψJB Junction-to-board characterization parameter 6.0 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 1.8 °C/W

(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a20-Hz to 20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter mayresult in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filterremoves out-of-band noise, which, although not audible, may affect dynamic specification values.

8.5 Electrical CharacteristicsAt 25°C, AVDD_DAC = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AUDIO ADC

Input signal level Single-ended 0.707 VRMS

SNR Signal-to-noise ratio (1) (2) A-weighted, fS = 48 ksps, 0-dB PGA gain,inputs AC-shorted to ground 80 92 dB

Dynamic range (1) (2) fS = 48 ksps; 0-dB PGA gain;1-kHz, –60-dB full-scale input signal 93 dB

THD Total harmonic distortion fS = 48 ksps; 0-dB PGA gain;1-kHz, –2-dB full-scale input signal –89 –75 dB

PSRR Power-supply rejection ratio217-Hz signal applied to DRVDD 55

dB1-kHz signal applied to DRVDD 44

Input channel separation 1-kHz, –2-dB full-scale signal, MIC1L to MIC1R –71 dB

Gain error fS = 48 ksps; 0-dB PGA gain; 1-kHz, –2-dB full-scaleinput signal 0.82 dB

ADC programmable-gain amplifiermaximum gain 1-kHz input tone 59.5 dB

ADC programmable-gain amplifier stepsize 0.5 dB


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Electrical Characteristics (continued)At 25°C, AVDD_DAC = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted)


(3) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16-Ωsingle-ended load.

Input resistance

MIC1L/MIC1R inputs routed to single ADC inputmix attenuation = 0 dB 20

kΩ




Input resistance 80 kΩ

Input capacitance MIC1/LINE1 inputs 10 pF

Input level control minimum attenuationsetting 0 dB

Input level control maximum attenuationsetting 12 dB

Input level control attenuation step size 1.5 dB

ANALOG PASSTHROUGH MODE

RDS(on) Input-to-output switch resistanceMIC1/LIN1 to LINEOUT 330

ΩMIC2/LIN2 to LINEOUT 330

INPUT SIGNAL LEVEL, DIFFERENTIAL

SNR Signal-to-noise ratio A-weighted, fS = 48 ksps, 0-dB PGA gain, inputsAC‑shorted to ground 92 dB

THD Total harmonic distortion fS = 48 kHz;0-dB PGA gain, 1 kHz, –2-dB full-scale input signal –94 dB

ADC DIGITAL DECIMATION FILTER, fS = 48 kHz

Filter gain

From 0 to 0.39 fS ±0.1

dB

At 0.4125 fS –0.25

At 0.45 fS –3

At 0.5 fS –17.5

From 0.55 fS to 64 fS –75

Filter group delay 17/fS s

MICROPHONE BIAS

Bias voltage

Programmable setting = 2 V 2

VProgrammable setting = 2.5 V 2.3 2.455 2.7

Programmable setting = DRVDD DRVDD - 0.24

Current sourcing Programmable setting = 2.5 V 4 mA

AUDIO DAC - DIFFERENTIAL LINE OUTPUT, RLOAD = 10 kΩ

Full-scale output voltage 0-dB input full-scale signal, output common-modesetting = 1.35 V, output volume control = 0 dB

1.414 VRMS

4 VPP

Signal-to-noise ratio (3) A-weighted, fS = 48 kHz, output volume control = 0 dB,no input signal, referenced to full-scale input level 90 102 dB

Dynamic rangeA-weighted, fS = 48 kHz, –60-dB input full-scale signal,output volume control = 0 dB, output common-modesetting = 1.35 V

97 dB

Total harmonic distortionfS = 48 kHz; 0-dB, 1-kHz input full-scale signal;output volume control = 0 dB;output common-mode setting = 1.35 V

–95 –75 dB

PSRR Power-supply rejection ratio217-Hz signal applied to DRVDD, AVDD_DAC 78

dB1-kHz signal applied to DRVDD, AVDD_DAC 80

DAC channel separation 0-dB full-scale input signal between left andright lineout 86 dB

DAC interchannel gain mismatch 1-kHz input, 0-dB gain 0.1 dB

DAC gain error0-dB, 1-kHz input full-scale signal; output volumecontrol = 0 dB; output common-mode setting = 1.35 V;fS = 48 kHz

–0.2 dB


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(4) Ratio of output level with a 1-kHz full-scale input, to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to 20-kHz bandwidth.

AUDIO DAC - SINGLE ENDED LINE OUTPUT, RLOAD = 10 kΩ

Full-scale output voltage 0-dB input full-scale signal, output common-modesetting = 1.35 V, output volume control = 0 dB 0.707 VRMS

SNR Signal-to-noise ratio A-weighted, fS = 48 kHz, output volume control = 0 dB,no input signal, output common-mode setting = 1.35 V 97 dB

THD Total harmonic distortionfS = 48 kHz; 0-dB, 1-kHz input full-scale signal;output volume control = 0 dB;output common-mode setting = 1.35 V

–84 dB


0.55 dB

AUDIO DAC - SINGLE-ENDED HEADPHONE OUTPUT, RLOAD = 16 Ω

Full-scale output voltage 0-dB input full-scale signal, output common-modesetting = 1.35 V, output volume control = 0 dB 0.707 VRMS

SNR Signal-to-noise ratio

A-weighted, fS = 48 kHz, output volume control = 0 dB,no input signal, referenced to full-scale input level 96

dBA-weighted, fS = 48 kHz, output volume control = 0 dB,no input signal, referenced to full-scale input level, 50%DAC current-boost mode

97

Dynamic rangeA-weighted, fS = 48 kHz, –60-dB input full-scale signal,output volume control = 0 dB, output common-modesetting = 1.35 V

91 dB

THD Total harmonic distortion fS = 48 kHz, 0-dB input full-scale signal, output volumecontrol = 0 dB, output common-mode setting = 1.35 V –71 –65 dB

PSRR Power-supply rejection ratio217-Hz signal applied to DRVDD, AVDD_DAC 43

dB1-kHz signal applied to DRVDD, AVDD_DAC 41

DAC channel separation Right headphone out 89 dB


–0.85 dB

DAC DIGITAL INTERPOLATION - FILTER fS = 48 kHz

Pass band 0 0.45 fS Hz

Pass-band ripple ±0.06 dB

Transition band 0.45 fS 0.55 fS Hz

Stop band 0.55 fS 7.5 fS Hz

Stop-band attenuation 65 dB

Group delay 21/fS s

STEREO HEADPHONE DRIVER - AC-COUPLED OUTPUT CONFIGURATION (3)

0-dB full-scale output voltage 0-dB gain to high-power outputs. Output common‑modevoltage setting = 1.35 V 0.707 VRMS

Programmable output common-modevoltage (applicable to line outputs also)

First option 1.35

VSecond option 1.5

Third option 1.65

Fourth option 1.8

Maximum programmable output levelcontrol gain 9 dB

Programmable output level control gainstep size 1 dB

PO Maximum output powerRL = 32 Ω 15

mWRL = 16 Ω 30

Signal-to-noise ratio (4) A-weighted 94 dB


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9






(5) When IOVDD < 1.6 V, minimum VIH is 1.1 V.(6) Additional power is consumed when the PLL is powered.

Total harmonic distortion

1-kHz output, PO = 5 mW, RL = 32 Ω–77

dB%

0.014


0.016


0.022


0.028

Channel separation 1-kHz, 0-dB input 90 dB

Power supply rejection ratio 217 Hz, 100 mVpp on AVDD, DRVDD1/2 48 dB

Mute attenuation 1-kHz output 107 dB

DIGITAL I/O

VIL Input low level –0.3 0.3 IOVDD V

VIH Input high level (5) IOVDD > 1.6 V 0.7 IOVDDV

IOVDD ≤ 1.6 V 1.1

VOL Output low level 0.1 IOVDD V

VOH Output high level 0.8 IOVDD V

CURRENT CONSUMPTION - DRVDD = AVDD_DAC = IOVDD = 3.3 V, DVDD = 1.8 V

IIN

IDRVDD + IAVDD_DACRESET held low

0.1μA

IDVDD 0.2

IDRVDD + IAVDD_DAC Mono ADC record, fS = 8 ksps, I2S slave, AGC off,no signal

2.15

mA

IDVDD 0.48

IDRVDD + IAVDD_DAC Stereo ADC record, fS = 8 ksps, I2S slave, AGC off,no signal

4.1

IDVDD 0.62

IDRVDD + IAVDD_DAC Stereo ADC record, fS = 48 ksps, I2S slave, AGC off,no signal

4.31 (6)

IDVDD 2.45 (6)

IDRVDD + IAVDD_DAC Stereo DAC playback to lineout, analog mixerbypassed, fS = 48 ksps, I2S slave

3.5

IDVDD 2.3

IDRVDD + IAVDD_DAC Stereo DAC playback to lineout, fS = 48 ksps,I2S slave, no signal

4.9

IDVDD 2.3

IDRVDD + IAVDD_DAC Stereo DAC playback to stereo single-endedheadphone, fS = 48 ksps, I2S slave, no signal

6.7

IDVDD 2.3

IDRVDD + IAVDD_DACStereo linein to stereo lineout, no signal

3.11

IDVDD 0

IDRVDD + IAVDD_DACExtra power when PLL enabled

1.4

IDVDD 0.9

IDRVDD + IAVDD_DAC All blocks powered down. Headset detection enabled,headset not inserted

28μA

IDVDD 2


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8.6 Switching Characteristics I2S/LJF/RJF Timing in Master ModeAll specifications at 25°C, DVDD = 1.8 V. See Figure 1.

PARAMETER MIN MAX UNIT

td(WS) ADWS/WCLK delay timeIOVDD = 1.1 V 50

nsIOVDD = 3.3 V 15

td(DO-WS) ADWS/WCLK to DOUT delay timeIOVDD = 1.1 V 50

nsIOVDD = 3.3 V 20

td(DO-BCLK) BCLK to DOUT delay timeIOVDD = 1.1 V 50

nsIOVDD = 3.3 V 15

ts(DI) DIN setup timeIOVDD = 1.1 V 10

nsIOVDD = 3.3 V 6

th(DI) DIN hold timeIOVDD = 1.1 V 10

nsIOVDD = 3.3 V 6

tr Rise timeIOVDD = 1.1 V 30

nsIOVDD = 3.3 V 10

tf Fall timeIOVDD = 1.1 V 30

nsIOVDD = 3.3 V 10

8.7 Switching Characteristics I2S/LJF/RJF Timing in Slave ModeAll specifications at 25°C, DVDD = 1.8 V. See Figure 2.


tH(BCLK) BCLK high periodIOVDD = 1.1 V 70

nsIOVDD = 3.3 V 35

tL(BCLK) BCLK low periodIOVDD = 1.1 V 70

nsIOVDD = 3.3 V 35

ts(WS) ADWS/WCLK setup timeIOVDD = 1.1 V 10

nsIOVDD = 3.3 V 6

th(WS) ADWS/WCLK hold timeIOVDD = 1.1 V 10

nsIOVDD = 3.3 V 6

td(DO-WS) ADWS/WCLK to DOUT delay time (for LJF Mode only)IOVDD = 1.1 V 50

nsIOVDD = 3.3 V 35


nsIOVDD = 3.3 V 20


nsIOVDD = 3.3 V 6


nsIOVDD = 3.3 V 6


nsIOVDD = 3.3 V 4


nsIOVDD = 3.3 V 4


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8.8 Switching Characteristics DSP Timing in Master ModeAll specifications at 25°C, DVDD = 1.8 V. See Figure 3.


td(WS) ADWS/WCLK delay timeIOVDD = 1.1 V 50

nsIOVDD = 3.3 V 15


nsIOVDD = 3.3 V 15


nsIOVDD = 3.3 V 6


nsIOVDD = 3.3 V 6


nsIOVDD = 3.3 V 10


nsIOVDD = 3.3 V 10

8.9 Switching Characteristics DSP Timing in Slave ModeAll specifications at 25°C, DVDD = 1.8 V. See Figure 4.


tH(BCLK) BCLK high periodIOVDD = 1.1 V 70

nsIOVDD = 3.3 V 35

tL(BCLK) BCLK low periodIOVDD = 1.1 V 70

nsIOVDD = 3.3 V 35

ts(WS) ADWS/WCLK setup timeIOVDD = 1.1 V 10

nsIOVDD = 3.3 V 8

th(WS) ADWS/WCLK hold timeIOVDD = 1.1 V 10

nsIOVDD = 3.3 V 8


nsIOVDD = 3.3 V 20


nsIOVDD = 3.3 V 6


nsIOVDD = 3.3 V 6


nsIOVDD = 3.3 V 4


nsIOVDD = 3.3 V 4


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T0145-02

WCLK

BCLK

SDOUT

SDIN

t (WS)h

t (BCLK)H

t (DO-BCLK)d

t (DO-WS)d

t (DI)S

t (BCLK)L

t (DI)h

t (WS)S

T0145-01

WCLK

BCLK

SDOUT

SDIN

t (DO-BCLK)dt (DO-WS)d

t (WS)d

t (DI)S t (DI)h

12




Figure 1. I2S/LJF/RJF Timing in Master Mode

Figure 2. I2S/LJF/RJF Timing in Slave Mode


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T0146-02

WCLK

BCLK

SDOUT

SDIN

t (WS)h t (WS)h

t (BCLK)L

t (DO-BCLK)d

t (DI)S

t (BCLK)H

t (DI)h

t (WS)S t (WS)S

T0146-01

WCLK

BCLK

SDOUT

SDIN

t (DO-BCLK)d

t (WS)d t (WS)d

t (DI)S t (DI)h

13




Figure 3. DSP Timing in Master Mode

Figure 4. DSP Timing in Slave Mode


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MICBIAS = AVDD

MICBIAS = 2.5 V

MICBIAS = 2 V

Supply Voltage (V)

2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6

MIC

BIA

S O

utp

ut V

oltage (

V)

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

MICBIAS = AVDD

MICBIAS = 2.5 V

MICBIAS = 2 V

MIC

BIA

S O

utp

ut

Vo

lta

ge

(V

)

1.8

2

2.2

2.4

2.6

2.8

3

3.2

Ambient Temperature (°C)

–45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85

Input = −65 dBFS

Sig

nal-to

-Nois

e R

atio (

dB

)

24

26

28

30

32

34

36

38

40

42

PGA Gain Setting (dB)

0 10 20 30 40 50 60

0.85

0.8

0.75

0.7

0.65

0.6

0.55

0.5

0.45

0.40 10 20 30 40 50 60 70

PGA Setting (dB)

Ga

in E

rro

r (d

B)

Left ADC

Right ADC

G009

Am

plit

ude (

dB

)

−160

−140

−120

−100

−80

−60

−40

−20

0

Frequency (kHz)

0 2 4 6 8 10 12 14 16 18 20

Am

plit

ude (

dB

)

−160

−140

−120

−100

−80

−60

−40

−20

0

Frequency (kHz)

0 2 4 6 8 10 12 14 16 18 20

14




8.10 Typical Characteristics

Figure 5. DAC to Line Output FFT Plot Figure 6. Line Input to ADC FFT Plot

Figure 7. ADC SNR vs PGA Gain Setting, –65-dBfs Input Figure 8. ADC Gain Error vs PGA Gain Setting

Figure 9. MICBIAS Output Voltage vs AVDD Figure 10. MICBIAS Output Voltage vs Ambient Temperature


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15




9 Detailed Description

9.1 OverviewThe TLV320AIC3104-Q1 is a highly flexible, low-power, stereo audio codec with extensive feature integration,intended for applications in infotainment or cluster systems such as head unit, telematics, cluster, emergencycalls (eCall), navigation systems, and other car entertainment applications. The device integrates a host offeatures to reduce cost, board space, and power consumption in space-constrained, battery-powered, portableapplications.

The TLV320AIC3104-Q1 consists of the following blocks:• Stereo audio multibit delta-sigma DAC (8 kHz to 96 kHz)• Stereo audio multibit delta-sigma ADC (8 kHz to 96 kHz)• Programmable digital audio effects processing (3D, bass, treble, midrange, EQ, notch filter, de-emphasis)• Four audio inputs• Four high-power audio output drivers (headphone drive capability)• Two fully differential line output drivers• Fully programmable PLL• Headphone/headset jack detection available as register status bit


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Au

dio

Seria

lB

us

Inte

rfa

ce

I2 CS

eria

lC

on

tro

lB

us

Bia

s/

Refe

ren

ce

MICBIAS

SCL

SDA

RESET

Vo

ltag

eS

upp

lies

Au

dio

Clo

ck

Ge

nera

tion

MCLK

PG

A0/+

59

.5d

B0.5

dB

Ste

ps

AD

C+

+

+

+ + +VC

M

VC

M

DA

C

L

+

Vo

lum

eC

on

tro

lE

ffe

cts

DIN

DOUT

BCLK

WCLK

DINL

DINR

DOUTL

DOUTR

MIC

2R

/LIN

E2

R

AD

C

PG

A0/+

59

.5d

B0.5

dB

Ste

ps

+D

AC

R

Vo

lum

eC

on

tro

lE

ffects

AG

C

AG

C

SW

-D2

SW

-D1

SW

-D3

SW

-D4

DVDD

DRVDD

DRVDD

DRVSS

DVSS

IOVDD

AVSS1

AVDD

AVSS2

HP

RO

UT

HP

RC

OM

HP

LC

OM

HP

LO

UT

LE

FT

_LO

P

LE

FT

_LO

M

LIN

E1

LP

LIN

E1L

M

LIN

E1

RM

SW

-L0

SW

-L1

SW

-L4

SW

-L3

SW

-R4

SW

-R3

RIG

HT

_LO

P

RIG

HT

_LO

M

LIN

E1R

P

SW

-R0

SW

-R1

B0151-0

1

MIC

1R

P/L

INE

1R

P

MIC

1R

M/L

INE

1R

M

LIN

E1

RP

LIN

E1

RM

MIC

1LP

/LIN

E1

LP

MIC

1LM

/LIN

E1

LM

LIN

E1

LP

LIN

E1

LM

MIC

2L

/LIN

E2

L/

MIC

DE

T

16




9.2 Functional Block Diagram


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17




9.3 Feature Description

9.3.1 Audio Data ConvertersThe TLV320AIC3104-Q1 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters also can operate atdifferent sampling rates in various combinations, which are described further as follows.

The data converters are based on the concept of an fS(ref) rate that is used internal to the part, and it is related tothe actual sampling rates of the converters through a series of ratios. For typical sampling rates, fS(ref) is either44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with additionalrestrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, andalso to enable high-quality playback of low-sampling-rate data, without high-frequency audible noise beinggenerated.

The sampling rate of the ADC and DAC can be set to fS(ref) / NCODEC or 2 × fS(ref) / NCODEC, with NCODECbeing 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6 for both the NDAC and NADC settings. In the TLV320AIC3104-Q1,NDAC and NADC must be set to the same value, as the device only supports a common sample rate for theADC and DAC channels. Therefore NCODEC = NDAC = NADC, and this is programmed by setting the value ofbits D7 to D4 equal to the value of bits D3 to D0 in register 2, on page 0.

9.3.2 Stereo Audio ADCThe TLV320AIC3104-Q1 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-timesoversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC is inoperation, the device requires that an audio master clock be provided and appropriate audio clock generation beset up within the device.

In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, tosupport the case where only mono record capability is required. In addition, both channels can be fully poweredor entirely powered down.

The integrated digital decimation filter removes high-frequency content and downsamples the audio data from aninitial sampling rate of 128 fS to the final output sampling rate of fS. The decimation filter provides a linear phaseoutput response with a group delay of 17 / fS. The –3-dB bandwidth of the decimation filter extends to 0.45 fS andscales with the sample rate (fS). The filter has minimum 75-dB attenuation over the stop band from 0.55 fS to 64fS. Independent digital high-pass filters are also included with each ADC channel, with a corner frequency thatcan be independently set.

Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,requirements for analog antialiasing filtering are very relaxed. The TLV320AIC3104-Q1 integrates a second-orderanalog antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter,provides sufficient antialiasing filtering without requiring additional external components.

The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm thatonly changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending onthe register programming (see page 0, registers 19 and 22). This soft-stepping ensures that volume controlchanges occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and onpower down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever thegain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabledby programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the partafter the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADCpower-down flag is no longer set, the audio master clock can be shut down.


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1

1

N0 N1 zH(z)

32,768 D1 z

-

-

+ ´=

- ´

18




Feature Description (continued)9.3.2.1 Stereo Audio ADC High-Pass FilterOften in audio applications it is desirable to remove the dc offset from the converted audio data stream. TheTLV320AIC3104-Q1 has a programmable first-order high-pass filter which can be used for this purpose. Thedigital filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients,N0, N1, and D1. The transfer function of the digital high-pass filter is of the form:

(1)

Programming the left channel is done by writing to page 1, registers 65 to 70, and the right channel isprogrammed by writing to page 1, registers 71 to 76. After the coefficients have been loaded, these ADC high-pass filter coefficients can be selected by writing to page 0, register 107, bits D7 to D6, and the high-pass filtercan be enabled by writing to page 0, register 12, bits D7 to D4.

9.3.3 Automatic Gain Control (AGC)An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constantoutput signal amplitude when recording speech signals (it can be fully disabled if not desired). This circuitryautomatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when aperson speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has severalprogrammable settings, including target level, attack and decay time constants, noise threshold, and maximumPGA gain applicable, that allow the algorithm to be fine-tuned for any particular application. These AGC featuresare explained in following paragraphs, and their operation is illustrated in Figure 11. The algorithm uses theabsolute average of the signal (which is the average of the absolute value of the signal) as a measure of thenominal amplitude of the output signal.

NOTECompletely independent AGC circuitry is included with each ADC channel with entirelyindependent control over the algorithm from one channel to the next. This is attractive incases where two microphones are used in a system, but may have different placement inthe end equipment and require different dynamic performance for optimal systemoperation.

The TLV320AIC3104-Q1 allows programming of eight different target levels, which can be programmed from–5.5 dB to –24 dB relative to a full-scale signal. Because the device reacts to the signal absolute average andnot to peak levels, it is recommended that the target level be set with enough margin to avoid clipping at theoccurrence of loud sounds.

Attack can be varied from 7 ms to 1,408 ms. The extended right-channel attack time can be programmed bywriting to page 0, register 103, and the left channel is programmed by writing to page 0, register 105.

Decay time can be varied in the range from 0.05 s to 22.4 s. The extended right-channel decay time can beprogrammed by writing to page 0, register 104, and the left channel is programmed by writing to page 0, register106.

The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with theclock setup that is used. Table 1 shows the relationship of the NCODEC ratio to the maximum time available forthe AGC decay. In practice, these maximum times are extremely long for audio applications and should not limitany practical AGC decay time that is needed by the system.


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W0002-01

Decay Time

TargetLevel

InputSignal

OutputSignal

AGCGain

AttackTime

19




Table 1. AGC Decay Time RestrictionNCODEC RATIO MAXIMUM DECAY TIME (SECONDS)

1 41.5 5.62 8

2.5 9.63 11.2

3.5 11.24 16

4.5 165 19.2

5.5 22.46 22.4

In this situation, the AGC considers the input signal as a silence and will set the noise threshold flag whilereducing the gain down to 0 dB in steps of 0.5 dB every sample period. The gain stays at 0 dB unless the inputspeech signal average rises above the noise threshold setting. This ensures that noise does not get gained up inthe absence of speech. Noise threshold level in the AGC algorithm is programmable from –30 dB to –90 dBrelative to full scale. A disable noise gate feature is also available. This operation includes programmabledebounce and hysteresis functionality to avoid the AGC gain from cycling between high gain and 0 dB whensignals are near the noise threshold level. When the noise threshold flag is set, the status of gain applied by theAGC and the saturation flag should be ignored.

The Maximum PGA gain applicable can be set by the user, which restricts the maximum PGA gain that can beapplied by the AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise isgreater than programmed noise threshold. It can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.

Figure 11. Typical Operation of AGC Algorithm During Speech Recording


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1

1

N0 N1 zH(z)

32,768 D1 z

-

-

+ ´=

- ´

20




NOTEThe time constants here are correct when the ADC is not in double-rate audio mode. Thetime constants are achieved using the fS(ref) value programmed in the control registers.However, if the fS(ref) is set in the registers to, for example, 48 kHz, but the actual audioclock or PLL programming actually results in a different fS(ref) in practice, then the timeconstants would not be correct.

The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with theclock setup that is used. Table 1 shows the relationship of the NCODEC ratio to the maximum time available forthe AGC decay. In practice, these maximum times are extremely long for audio applications and should not limitany practical AGC decay time that is needed by the system.

9.3.4 Stereo Audio DACThe TLV320AIC3104-Q1 includes a stereo audio DAC supporting sampling rates from 8 kHz to 96 kHz. Eachchannel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, multibitdigital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhancedperformance at low sampling rates through increased oversampling and image filtering, thereby keepingquantization noise generated within the delta-sigma modulator and signal images strongly suppressed within theaudio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 fS(ref) and changingthe oversampling ratio as the input sample rate is changed. For an fS(ref) of 48 kHz, the digital delta-sigmamodulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated within thedelta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly, for anfS(ref) rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.

The following restrictions apply in the case when the PLL is powered down and double-rate audio mode isenabled in the DAC.

Allowed Q values = 4, 8, 9, 12, 16Q values where equivalent fS(ref) can be achieved by turning on PLLQ = 5, 6, 7 (set P = 5 / 6 / 7 and K = 16 and PLL enabled)Q = 10, 14 (set P = 5, 7 and K = 8 and PLL enabled)

9.3.5 Digital Audio Processing for PlaybackThe DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment,speaker equalization, and 3D effects processing. The de-emphasis function is implemented by a programmabledigital filter block with fully programmable coefficients (see page 1, registers 21 to 26 for the left channel andpage 1, registers 47 to 52 for the right channel). If de-emphasis is not required in a particular application, thisprogrammable filter block can be used for some other purpose. The de-emphasis filter transfer function is givenby:

(2)

where the N0, N1, and D1 coefficients are fully programmable individually for each channel. The coefficients thatshould be loaded to implement standard de-emphasis filters are given in Table 2.

(1) The 48-kHz coefficients listed in Table 2 are used as defaults.

Table 2. De-Emphasis Coefficients for Common Audio Sampling RatesSAMPLING FREQUENCY N0 N1 D132 kHz 16,950 –1,220 17,03744.1 kHz 15,091 –2,877 20,55548 kHz (1) 14,677 –3,283 21,374


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LB1 LB2

RB1 RB2

B0154-01

1 2 1 2

1 2 1 2

N0 2 N1 z N2 z N3 2 N4 z N5 z

32,768 2 D1 z D2 z 32,768 2 D4 z D5 z

- - - -

- - - -

æ ö æ ö+ ´ ´ + ´ + ´ ´ + ´´ç ÷ ç ÷ç ÷ ç ÷- ´ ´ - ´ - ´ ´ - ´è ø è ø

21




In addition to the de-emphasis filter block, the DAC digital effects processing includes a fourth-order digital IIRfilter with programmable coefficients (one set per channel). This filter is implemented as cascade of two biquadsections with frequency response given by:

(3)

The N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed. The structureof the filtering when configured for independent channel processing is shown in Figure 12, with LB1corresponding to the first left-channel biquad filter using coefficients N0, N1, N2, D1, and D2. LB2 similarlycorresponds to the second left-channel biquad filter using coefficients N3, N4, N5, D4, and D5. The RB1 andRB2 filters refer to the first and second right-channel biquad filters, respectively.

Figure 12. Structure of Digital Effects Processing for Independent Channel Processing

The coefficients for this filter implement a variety of sound effects, with bass boost or treble boost being the mostcommonly used in portable audio applications. The default N and D coefficients in the part are given in Table 3and implement a shelving filter with 0-dB gain from dc to approximately 150 Hz, at which point it rolls off to a 3-dB attenuation for higher frequency signals, thus giving a 3-dB boost to signals below 150 Hz. The N and Dcoefficients are represented by 16-bit, 2s‑complement numbers with values ranging from –32,768 to 32,767.

Table 3. Default Digital Effects Processing Filter Coefficients,When in Independent Channel Processing Configuration

CoefficientsN0 = N3 D1 = D4 N1 = N4 D2 = D5 N2 = N527,619 32,131 –27,034 –31,506 26,461

The digital processing also includes capability to implement 3-D processing algorithms by providing means toprocess the mono mix of the stereo input, and then combine this with the individual channel signals for stereooutput playback. The architecture of this processing mode, and the programmable filters available for use in thesystem, are shown in Figure 13. Note that the programmable attenuation block provides a method of adjustingthe level of 3-D effect introduced into the final stereo output. This, combined with the fully programmable biquadfilters in the system, enables the user to optimize the audio effects for a particular system and provide extensivedifferentiation from other systems using the same device.


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B0155-01

LB1

RB2

Atten

LB2L

+

+

+

+

+

––

+

+R

To Left Channel

To Right Channel

22




Figure 13. Architecture of Digital Audio Processing With 3-D Effects Enabled

It is recommended that the digital effects filters should be disabled while the filter coefficients are being modified.While new coefficients are being written to the device over the control port, it is possible that a filter usingpartially updated coefficients may actually implement an unstable system and lead to oscillation or objectionableaudio output. By disabling the filters, changing the coefficients, and then re-enabling the filters, these types ofeffects can be entirely avoided.

9.3.6 Digital Interpolation FilterThe digital interpolation filter upsamples the output of the digital audio processing block by the requiredoversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filterstages. The filter provides a linear phase output with a group delay of 21/fS. In addition, programmable digitalinterpolation filtering is included to provide enhanced image filtering and reduce signal images caused by theupsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images atmultiples of 8-kHz. The images at 8 kHz and 16 kHz are below 20 kHz and still audible to the listener; therefore,they must be filtered heavily to maintain a good quality output. The interpolation filter is designed to maintain atleast 65-dB rejection of images which are below 7.455 fS. In order to use the programmable interpolationcapability, fS(ref) should be programmed to a higher rate (restricted to be in the range of 39 kHz to 53 kHz whenthe PLL is in use), and the actual fS is set using the NCODEC divider, where NCODEC = NDAC = NADC. Forexample, if fS = 8 kHz is required, then fS(ref) can be set to 48 kHz, and the DAC fS set to fS(ref) / 6. This ensuresthat all images of the 8-kHz data are sufficiently attenuated well beyond a 20-kHz audible frequency range.

9.3.7 Delta-Sigma Audio DACThe stereo audio DAC incorporates a third-order multibit delta-sigma modulator followed by an analogreconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noiseshaping techniques. The analog reconstruction filter design consists of a six-tap analog FIR filter followed by acontinuous-time RC filter. The analog FIR operates at a rate of 128 fS(ref) (6.144 MHz when fS(ref) = 48 kHz,5.6448 MHz when fS(ref) = 44.1 kHz). Note that the DAC analog performance may be degraded by excessiveclock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to a minimum.


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23




9.3.8 Audio DAC Digital Volume ControlThe audio DAC includes a digital volume control block which implements a programmable digital gain. Thevolume level can be varied from 0 dB to –63.5 dB in 0.5-dB steps, or set to mute, independently for eachchannel. The volume level of both channels can also be changed simultaneously by the master volume control.Gain changes are implemented with a soft-stepping algorithm, which only changes the actual volume by one stepper input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can be slowedto one step per two input samples through a register bit.

Because of soft-stepping, the host does not know when the DAC has been actually muted. This may beimportant if the host wishes to mute the DAC before making a significant change, such as changing samplerates. In order to help with this situation, the device provides a flag back to the host via a read-only register bitthat alerts the host when the part has completed the soft-stepping and the actual volume has reached thedesired volume level. The soft-stepping feature can be disabled through register programming. If soft-stepping isenabled, the MCLK signal should be kept applied to the device until the DAC power-down flag is set. When thisflag is set, the internal soft-stepping process and power-down sequence is complete, and the MCLK can then bestopped if desired.

The TLV320AIC3104-Q1 also includes functionality to detect when the user changes the selection of de-emphasis or digital audio processing functionality. When the new selection is detected, the TLV320AIC3104-Q1(1) soft-mutes the DAC volume control, (2) changes the operation of the digital effects processing to match thenew selection, and (3) soft-unmutes the device. This avoids any possible pop/clicks in the audio output due toinstantaneous changes in the filtering. A similar algorithm is used when first powering up or powering down theDAC. The circuit begins operation at power up with the volume control muted, then soft-steps it up to the desiredvolume level. At power down, the logic first soft-steps the volume down to a mute level, then powers down thecircuitry.

9.3.9 Analog Output Common-Mode AdjustmentThe output common-mode voltage and output range of the analog output are determined by an internal band-gapreference, in contrast to other codecs that may use a scaled version of the analog supply. This scheme is usedto reduce the coupling of noise that may be on the supply into the audio signal path.

However, due to the possible wide variation in analog supply range (2.7 V to 3.6 V), an output common-modevoltage setting of 1.35 V, which would be used for a 2.7-V supply case, would be overly conservative if thesupply is actually much larger, such as 3.3 V or 3.6 V. In order to optimize device operation, theTLV320AIC3104-Q1 includes a programmable output common-mode level, which can be set by registerprogramming to a level most appropriate to the actual supply range used by a particular customer. The outputcommon-mode level can be varied among four different values, ranging from 1.35 V (most appropriate for lowsupply ranges, near 2.7 V) to 1.8 V (most appropriate for high supply ranges, near 3.6 V). Note that therecommended DVDD voltage is dependent on the common-mode setting, as shown in Table 4.

Table 4. Appropriate SettingsCOMMON-MODE SETTING RECOMMENDED AVDD, DRVDD RECOMMENDED DVDD1.35 2.7 V to 3.6 V 1.525 V to 1.95 V1.5 3 V to 3.6 V 1.65 V to 1.95 V1.65 V 3.3 V to 3.6 V 1.8 V to 1.95 V1.8 V 3.6 V 1.95 V

9.3.10 Audio DAC Power ControlThe stereo DAC can be fully powered up or down, and in addition, the analog circuitry in each DAC channel canbe powered up or down independently. This provides power savings when only a mono playback stream isneeded.


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Gain = 0, –1.5, –3, . . ., –12 dB, Mute

To Left ADC PGA

B0156-01

MIC1L/LINE1L

MIC1R/LINE1R

Gain = 0, –1.5, –3, . . ., –12 dB, Mute

Gain = 0, –1.5, –3, . . ., –12 dB, Mute

MIC2L/LINE2L/MICDET

24




9.3.11 Audio Analog InputsThe TLV320AIC3104-Q1 includes six single-ended audio inputs. These pins connect through series resistors andswitches to the virtual ground terminals of two fully differential operational amplifiers (one per ADC/PGAchannel). By selecting to turn on only one set of switches per operational amplifier at a time, the inputs can bemultiplexed effectively to each ADC/PGA channel.

By selecting to turn on multiple sets of switches per operational amplifier at a time, mixing can also be achieved.Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal operationalamplifiers, resulting in saturation and clipping of the mixed output signal. Whenever mixing is being implemented,the user should take adequate precautions to avoid such saturation from occurring. In general, the mixed signalshould not exceed 2 VP-P (single-ended).

In most mixing applications, there is also a general need to adjust the levels of the individual signals beingmixed. For example, if a soft signal and a large signal are to be mixed and played together, the soft signalgenerally should be amplified to a level comparable to the large signal before mixing. In order to accommodatethis need, the TLV320AIC3104-Q1 includes input level control on each of the individual inputs before they aremixed or multiplexed into the ADC PGAs, with gain programmable from 0 dB to –12 dB in 1.5-dB steps. Notethat this input level control is not intended to be a volume control, but instead used occasionally for level setting.Soft-stepping of the input level control settings is implemented in this device, with the speed and functionalityfollowing the settings used by the ADC PGA for soft-stepping.

Figure 14 shows the single-ended mixing configuration for the left-channel ADC PGA, which enables mixing ofthe signals LINE1L, LINE2L, LINE1R, MIC2L, and MIC2R. The right-channel ADC PGA mix is similar, enablingmixing of the signals LINE1R, LINE2R, LINE1L, MIC2L, and MIC2R.

Figure 14. Left-Channel, Single-Ended Analog Input Mixing Configuration

9.3.12 Analog Input Bypass Path FunctionalityThe TLV320AIC3104-Q1 includes the additional ability to route some analog input signals past the integrateddata converters, for mixing with other analog signals and then direct connection to the output drivers. TheTLV320AIC3104-Q1 supports this in a low-power mode by providing a direct analog path through the device tothe output drivers, while all ADCs and DACs can be completely powered down to save power.

When programmed correctly, the device can pass the LINE1L and LINE1R signals directly to the output stage.

9.3.13 ADC PGA Signal Bypass Path FunctionalityIn addition to the input bypass path described previously, the TLV320AIC3104-Q1 also includes the ability toroute the ADC PGA output signals past the ADC, for mixing with other analog signals and then direct connectionto the output drivers. These bypass functions are described in more detail in the sections on output mixing andoutput driver configurations.


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25




9.3.14 Input Impedance and VCM ControlThe TLV320AIC3104-Q1 includes several programmable settings to control analog input pins, particularly whenthey are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into ahigh-impedance state, such that the input impedance seen looking into the device is extremely high. Note,however, that the pins on the device do include protection diode circuits connected to AVDD and AVSS. Thus, ifany voltage is driven onto a pin approximately one diode drop (~0.6 V) above AVDD or one diode drop belowAVSS, these protection diodes begin conducting current, resulting in an effective impedance that no longerappears as a high-impedance state.

In most cases, the analog input pins on the TLV320AIC3104-Q1 should be AC-coupled to analog input sources,the exception to this being if an ADC is being used for dc voltage measurement. The AC-coupling capacitorcauses a high-pass filter pole to be inserted into the analog signal path, so the size of the capacitor must bechosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed analogsignal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies with thesetting of the input level control, starting at approximately 20 kΩ with an input level control setting of 0 dB, andincreasing to approximately 80 kΩ when the input level control is set at –12 dB. For example, using a 0.1-μF AC-coupling capacitor at an analog input results in a high-pass filter pole of 80 Hz when the 0-dB input level controlsetting is selected.

9.3.15 MICBIAS GenerationThe TLV320AIC3104-Q1 includes a programmable microphone bias output voltage (MICBIAS), capable ofproviding output voltages of 2 V or 2.5 V (both derived from the on-chip band-gap voltage) with 4-mA outputcurrent drive. In addition, the MICBIAS can be programmed to be connected to AVDD directly through an on-chipswitch, or it can be powered down completely when not needed, for power savings. This function is controlled byregister programming in page 0, register 25.

9.3.16 Analog Fully Differential Line Output DriversThe TLV320AIC3104-Q1 has two fully differential line output drivers, each capable of driving a 10-kΩ differentialload. The output stage design leading to the fully differential line output drivers is shown in Figure 15 andFigure 16. This design includes extensive capability to adjust signal levels independently before any mixingoccurs, beyond that already provided by the PGA gain and the DAC digital volume control.

The PGA_L/R signals refer to the outputs of the ADC PGA stages that are similarly passed around the ADC tothe output stage. Note that because both left- and right-channel signals are routed to all output drivers, a monomix of any of the stereo signals can easily be obtained by setting the volume controls of both left- and right-channel signals to –6 dB and mixing them. Undesired signals can also be disconnected from the mix throughregister control.


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0 dB to –78 dB

0 dB to –78 dB

0 dB to –78 dB

0 dB to –78 dB

+

PGA_L

PGA_R

DAC_L1

DAC_R1

B0158-01

PGA_L

PGA_L

PGA_R

PGA_R

DAC_L1

DAC_L1

DAC_R1

DAC_R1

DAC_L3

LEFT_LOP

LEFT_LOM

B0157-01

DAC_R3

RIGHT_LOP

RIGHT_LOM

DAC_LDAC_L1

DAC_L2

DAC_L3

DAC_RDAC_R1

DAC_R2

DAC_R3

StereoAudioDAC

VolumeControls,Mixing


Gain = 0 dB to 9 dB,Mute

Gain = 0 dB to 9 dB,Mute

26




Figure 15. Architecture of Output Stage Leading to Fully-Differential Line Output Drivers

Figure 16. Detail of Volume Control and Mixing Function Shown in Figure 12 and Figure 24


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27




The DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered by register control basedon the requirements of the system. If mixing of the DAC audio with other signals is not required, and the DACoutput is only needed at the stereo line outputs, then it is recommended to use the routing through pathDAC_L3/R3 to the fully differential stereo line outputs. This results not only in higher-quality output performance,but also in lower-power operation, because the analog volume controls and mixing blocks ahead of these driverscan be powered down.

If instead the DAC analog output must be routed to multiple output drivers simultaneously (such as toLEFT_LOP/M and RIGHT_LOP/M) or must be mixed with other analog signals, then the DAC outputs should beswitched through the DAC_L1/R1 path. This option provides the maximum flexibility for routing of the DACanalog signals to the output drivers.

The TLV320AIC3104-Q1 includes an output level control on each output driver with limited gain adjustment from0 dB to 9 dB. The output driver circuitry in this device is designed to provide a low-distortion output while playingfull-scale stereo DAC signals at a 0-dB gain setting. However, a higher amplitude output can be obtained at thecost of increased signal distortion at the output. This output level control allows the user to make this tradeoffbased on the requirements of the end equipment. Note that this output level control is not intended to be used asa standard output volume control. It is expected to be used only sparingly for level setting, i.e., adjustment of thefull-scale output range of the device.

Each differential line output driver can be powered down independently of the others when it is not needed in thesystem. When placed into power down through register programming, the driver output pins are placed into ahigh-impedance state.

9.3.17 Analog High-Power Output DriversThe TLV320AIC3104-Q1 includes four high-power output drivers with extensive flexibility in their usage. Theseoutput drivers are individually capable of driving 30 mW each into a 16-Ω load in single-ended configuration, andthey can be used in pairs connected in bridge-terminated load (BTL) configuration between two driver outputs.

The high-power output drivers can be configured in a variety of ways, including:1. Driving up to two fully differential output signals2. Driving up to four single-ended output signals3. Driving two single-ended output signals, with one or two of the remaining drivers driving a fixed VCM level,

for a pseudo-differential stereo output

The output stage architecture leading to the high-power output drivers is shown in Figure 17, with the volumecontrol and mixing blocks being effectively identical to those shown in Figure 16. Note that each of these drivershas an output level control block like those included with the line output drivers, allowing gain adjustment up to 9dB on the output signal. As in the previous case, this output level adjustment is not intended to be used as astandard volume control, but instead is included for additional full-scale output signal-level control.

Two of the output drivers, HPROUT and HPLOUT, include a direct connection path for the stereo DAC outputs tobe passed directly to the output drivers and bypass the analog volume controls and mixing networks, using theDAC_L2/R2 path. As in the line output case, this functionality provides the highest quality DAC playbackperformance with reduced power dissipation, but can only be used if the DAC is not being routed to multipleoutput drivers simultaneously, and if mixing of the DAC output with other analog signals is not needed.


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VCM

VCM

HPLOUT

HPLCOM

HPRCOM

HPROUT

DAC_L2

DAC_R2

PGA_L

PGA_L

PGA_L

PGA_L

DAC_L1

DAC_L1

DAC_L1

DAC_L1

DAC_R1

DAC_R1

DAC_R1

DAC_R1

B0159-01

PGA_R

PGA_R

PGA_R

PGA_R





Volume Level0 dB to 9 dB, Mute




28




Figure 17. Architecture of Output Stage Leading to High-Power Output Drivers

The high-power output drivers include additional circuitry to avoid artifacts on the audio output during power-onand power-off transient conditions. The user should first program the type of output configuration being used inpage 0, register 14, to allow the device to select the optimal power-up scheme to avoid output artifacts. Thepower-up delay time for the high-power output drivers is also programmable over a wide range of time delays,from instantaneous up to 4 s, using page 0, register 42.

When these output drivers are powered down, they can be placed into a variety of output conditions based onregister programming. If lowest-power operation is desired, then the outputs can be placed into a high-impedance state, and all power to the output stage is removed. However, this generally results in the outputnodes drifting to rest near the upper or lower analog supply, due to small leakage currents at the pins. This thenresults in a longer delay requirement to avoid output artifacts during driver power on. In order to reduce this


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required power-on delay, the TLV320AIC3104-Q1 includes an option for the output pins of the drivers to beweakly driven to the VCM level they would normally rest at when powered with no signal applied. This outputVCM level is determined by an internal band-gap voltage reference, and thus results in extra power dissipationwhen the drivers are in power down. However, this option provides the fastest method for transitioning the driversfrom power down to full-power operation without any output artifact introduced.

The device includes a further option that falls between the other two—although it requires less power drawnwhile the output drivers are in power down, it also takes a slightly longer delay to power up without artifact than ifthe band-gap reference is kept alive. In this alternate mode, the powered-down output driver pin is weakly drivento a voltage of approximately half the DRVDD1/2 supply level using an internal voltage divider. This voltage doesnot match the actual VCM of a fully powered driver, but due to the output voltage being close to its final value, amuch shorter power-up delay time setting can be used and still avoid any audible output artifacts. These outputvoltage options are controlled in page 0, register 42.

The high-power output drivers can also be programmed to power up first with the output level (gain) control in ahighly attenuated state; then the output driver automatically reduces the output attenuation slowly to reach theprogrammed output gain. This capability is enabled by default but can be enabled in page 0, register 40.

9.3.18 Short-Circuit Output ProtectionThe TLV320AIC3104-Q1 includes programmable short-circuit protection for the high-power output drivers, formaximum flexibility in a given application. By default, if these output drivers are shorted, they automatically limitthe maximum amount of current that can be sourced to or sunk from a load, thereby protecting the device froman overcurrent condition. In this mode, the user can read page 0, register 95 to determine whether the part is inshort-circuit protection or not, and then decide whether to program the device to power down the output drivers.However, the device includes further capability to power down an output driver automatically whenever it goesinto short-circuit protection, without requiring intervention from the user. In this case, the output driver stays in apower-down condition until the user specifically programs it to power down and then power back up again, toclear the short-circuit flag.

9.3.19 Jack and Headset DetectionThe TLV320AIC3104-Q1 includes extensive capability to monitor a headphone, microphone, or headset jack,determine if a plug has been inserted into the jack, and then determine what type of headset/headphone is wiredto the plug. Figure 18 shows one configuration of the device that enables detection and determination of headsettype when a pseudo-differential (capless) stereo headphone output configuration is used. The registers used forthis function are page 0, registers 14, 96, 97, and 13. The type of headset detected can be read back from page0, register 13. Note that for best results, it is recommended to select a MICBIAS value as high as possible, andto program the output driver common-mode level at a 1.35-V or 1.5-V level.


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HPLOUT

HPROUT

To Detection Block

MIC PreAmp

s

sg m

sg m s

sgStereo

Cellular

Stereo +Cellular

m = mics = ear speakerg = ground/vcm

AVDD

B0244-02

MICBIAS

MIC2R

MIC2L/LINE2L/MICDET

PwrAmp

PwrAmp

MICBIAS

MIC2R

HPLOUT

HPROUT

ToDetection

Block

HPRCOM

HPLCOM

1.35 V

MIC2L/LINE2L/MICDETTo Detection Block

MIC PreAmp

s

sg m

sg m s

sgStereo

Cellular

Stereo +Cellular

m = mics = ear speakerg = ground/vcm

AVDD

B0243-02

PwrAmp

PwrAmp

PwrAmp

30




Figure 18. Configuration of Device for Jack Detection Using Pseudo-Differential (Capless) HeadphoneOutput Connection

A modified output configuration used when the output drivers are AC-coupled is shown in Figure 19. Note that inthis mode, the device cannot accurately determine if the inserted headphone is a mono or stereo headphone.

Figure 19. Configuration of Device for Jack Detection Using AC-Coupled Stereo Headphone OutputConnection


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To Detection Block

HPLOUT

HPLCOM

HPROUT

HPRCOM

Differential HeadphoneConnector Assembly

B0245-02

SW

1

MIC2L/LINE2L/MICDET

PwrAmp

PwrAmp

PwrAmp

PwrAmp

31




An output configuration for the case of the outputs driving fully differential stereo headphones is shown inFigure 20. In this mode, there is a requirement on the jack side that either HPLCOM or HPLOUT get shorted toground if the plug is removed, which can be implemented using a spring terminal in a jack. For this mode tofunction properly, short-circuit detection should be enabled and configured to power down the drivers if a short-circuit is detected. The registers that control this functionality are in page 0, register 38, bits D2 to D1.

Figure 20. Configuration of Device for Jack Detection Using Fully-Differential Stereo Headphone OutputConnection


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Digital Audio Data Serial Interface

ADC+

+

DIN

DO

UT

BC

LK

WC

LK

DIN

L

DIN

R

DO

UT

L

DO

UT

R

ADC

AGC

AGC

Record Path

Record Path

Effects

Effects

SW-D1

SW-D2

SW-D4

SW-D3

Left-ChannelAnalog Inputs

Right-ChannelAnalog Inputs

PGA0 dB–59.5 dB,0.5-dB Steps

PGA0 dB–59.5 dB,0.5-dB Steps

VolumeControl

VolumeControl

DACPowered

Down

DACPowered

Down

DACL

DACR

B0173-01

32




9.4 Device Functional Modes

9.4.1 Digital Audio Processing for Record PathIn applications where record-only is selected, and DAC is powered down, the playback path signal processingblocks can be used in the ADC record path. These filtering blocks can support high-pass, low-pass, band-pass ornotch filtering. In this mode, the record-only path has switches SW-D1 through SW-D4 closed, and reroutes theADC output data through the digital signal processing blocks. Because the DAC digital signal processing blocksare being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC digitalprocessing and are located on page 1, registers 1 to 52. This record-only mode is enabled by powering downboth DACs by writing to page 0, register 37, bits D7 to D6 (D7 = D6 = 0). Next, enable the digital filter pathwayfor the ADC by writing a 1 to page 0, register 107, bit D3. (Note, this pathway is only enabled if both DACs arepowered down.) This record-only path can be seen in Figure 21.

Figure 21. Record-Only Mode With Digital Processing Path Enabled

9.4.2 Increasing DAC Dynamic RangeThe TLV320AIC3104-Q1 allows trading off dynamic range with power consumption. The DAC dynamic range canbe increased by writing to page 0, register 109, bits D7 to D6. The lowest DAC current setting is the default, andthe dynamic range is displayed in Electrical Characteristics. Increasing the current can increase the DACdynamic range by up to 1.5 dB.


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LEFT_LOP

RIGHT_LOP

LEFT_LOM

RIGHT_LOM

SW-L0

SW-R0

SW-L3

SW-R3

SW-L1

SW-R1

SW-L4

SW-R4

MIC1LP/LINE1LP

MIC1RP/LINE1RP

MIC1LM/LINE1LM

MIC1RM/LINE1RM

LINE1LP

LINE1RP

LINE1LM

LINE1RM

33




Device Functional Modes (continued)9.4.3 Passive Analog Bypass During Power DownProgramming the TLV320AIC3104-Q1 to passive analog bypass occurs by configuring the output stage switchesfor passthrough. This is done by opening switches SW-L0, SW-L3, SW-R0, and SW-R3 and closing SW-L1 andSW-R1. See Figure 22. Programming this mode is done by writing to page 0, register 108.

Connecting the MIC1LP/LINE1LP input signal to the LEFT_LOP pin is done by closing SW-L1 and opening SW-L0; this action is done by writing a 1 to page 0, register 108, bit D0. Connecting the MIC1LM/LINE1LM inputsignal to the LEFT_LOM pin is done by closing SW-L4 and opening SW-L3; this action is done by writing a 1 topage 0, register 108, bit D1.

Connecting the MIC1RP/LINE1RP input signal to the RIGHT_LOP pin is done by closing SW-R1 and openingSW-R0; this action is done by writing a 1 to page 0, register 108, bit D4. Connecting MIC1RM/LINE1RM inputsignal to the RIGHT_LOM pin is done by closing SW-R4 and opening SW-R3; this action is done by writing a 1to page 0, register 108, bit D5. A diagram of the passive analog bypass mode configuration is shown inFigure 22.

In general, connecting two switches to the same output pin should be avoided, as this error shorts two inputsignals together, and would likely cause distortion of the signal as the two signals are in contention. Poorfrequency response would also likely occur.

Figure 22. Passive Analog Bypass Mode Configuration

9.4.4 Hardware ResetThe TLV320AIC3104-Q1 requires a hardware reset after power up for proper operation. After all power suppliesare at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is notperformed, the TLV320AIC3104-Q1 may not respond properly to register reads/writes.

In cases where the ESD events generate a device reset, TI recommends to add at least a 1-nF capacitorconnected between the RESET pin and DVSS. This capacitor avoids ESD events that could place the codec indefault state. A 10-kΩ pullup resistor can be added to the RESET pin in addition to the capacitor.

This device has a software reset (page 0, register 1) that can be used by the host to reset all registers on page 0and page 1 to their reset values. In cases where changes are needed only to routing or volume-control registers,the changes should be accomplished by writing directly to the appropriate registers rather than using thesoftware or hardware reset.


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SDA

SCL

tHD-STA

0.9 s³ m

tSU-STO

0.9 s³ m

P S

tSU-STA

0.9 s³ m

Sr

tHD-STA

0.9 s³ m

S

T0114-02

34




9.5 Programming

9.5.1 Digital Control Serial InterfaceThe register map of the TLV320AIC3104-Q1 actually consists of two pages of registers, with each pagecontaining 128 registers. The register at address zero on each page is used as a page-control register, andwriting to this register determines the active page for the device. All subsequent read/write operations access thepage that is active at the time, unless a register write is performed to change the active page. The active pagedefaults to page 0 on device reset.

For example, at device reset, the active page defaults to page 0, and thus all register read/write operations foraddresses 1 to 127 access registers in page 0. If registers on page 1 must be accessed, the user must write the8-bit sequence 0x01 to register 0, the page control register, to change the active page from page 0 to page 1.After this write, it is recommended that the user also read back the page control register, to ensure the change inpage control has occurred properly. Future read/write operations to addresses 1 to 127 now access registers inpage 1. When page-0 registers must be accessed again, the user writes the 8-bit sequence 0x00 to register 0,the page control register, to change the active page back to page 0. After a recommended read of the pagecontrol register, all further read/write operations to addresses 1 to 127 access page-0 registers again.

9.5.2 I2C Control InterfaceThe TLV320AIC3104-Q1 supports the I2C control protocol using 7-bit addressing and is capable of both standardand fast modes. For I2C fast mode, note that the minimum timing for each of tHD-STA, tSU-STA, and tSU-STO is 0.9 μs,as seen in Figure 23. The TLV320AIC3104-Q1 responds to the I2C address of 001 1000. I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive thebus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires arepulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, twodevices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Figure 23. I2C Interface Timing

Communication on the I2C bus always takes place between two devices, one acting as the master and the otheracting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction ofthe master. Some I2C devices can act as masters or slaves, but the TLV320AIC3104-Q1 can only act as a slavedevice.

An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmittedacross the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriatelevel while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDAline has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the receivershift register.


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DA(6) DA(0) RA(7) RA(0)SDA

SCL

DA(6) DA(0) D(7) D(0)

(M) – SDA Controlled by Master(S) – SDA Controlled by Slave

Start(M)

Write(M)

SlaveAck(S)

SlaveAck(S)

SlaveAck(S)

MasterNo Ack

(M)

Stop(M)

RepeatStart(M)

Read(M)

7-Bit Device Address(M)

8-Bit Register Address(M)

8-Bit Register Data(S)


T0148-01

DA(6) DA(0) RA(7) RA(0) D(7) D(0)

T0147-01

SDA

SCL

(M) – SDA Controlled by Master

(S) – SDA Controlled by Slave

Start(M)

Write(M)

SlaveAck(S)

SlaveAck(S)

SlaveAck(S)

Stop(M)


8-Bit Register Address(M)

8-Bit Register data(M)

35




Programming (continued)The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master readsfrom a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line.Under normal circumstances the master drives the clock line.

Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. Whencommunication is taking place, the bus is active. Only master devices can start a communication. They do this bycausing a START condition on the bus. Normally, the data line is only allowed to change state while the clockline is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or itscounterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes fromHIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.

After the master issues a START condition, it sends a byte that indicates which slave device it wants tocommunicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address towhich it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The mastersends an address in the address byte, together with a bit that indicates whether it wishes to read from or write tothe slave device.

Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit.When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for theslave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends aclock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOWto acknowledge this to the slave. It then sends a clock pulse to clock the bit.

A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is notpresent on the bus, and the master attempts to address it, it receives a not-acknowledge because no device ispresent at that address to pull the line LOW.

When a master has finished communicating with a slave, it may issue a STOP condition. When a STOPcondition is issued, the bus becomes idle again. A master may also issue another START condition. When aSTART condition is issued while the bus is active, it is called a repeated START condition.

The TLV320AIC3104-Q1 also responds to and acknowledges a general call, which consists of the master issuinga command with a slave-address byte of 00h.

Figure 24. I2C Write

Figure 25. I2C Read


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36




Programming (continued)In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.

Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressedregister, if the master issues an acknowledge, the slave takes over control of the SDA bus and transmits for thenext 8 clocks the data of the next incremental register.

9.5.3 I2C Bus Debug in Glitched SystemOccasionally, some systems may encounter noise or glitches on the I2C bus. In the unlikely event that thisaffects bus performance, then it can be useful to use the I2C Debug register. This feature terminates the I2C buserror allowing this I2C device and system to resume communications. The I2C bus error detector is enabled bydefault. The TLV320AIC3104-Q1 I2C error detector status can be read from page 0, register 107, bit D0. Ifdesired, the detector can be disabled by writing to page 0, register 107, bit D2.

9.5.4 Digital Audio Data Serial InterfaceAudio data is transferred between the host processor and the TLV320AIC3104-Q1 via the digital audio dataserial interface. The audio bus of the TLV320AIC3104-Q1 can be configured for left- or right-justified, I2S, DSP,or TDM modes of operation, where communication with standard audio interfaces is supported within the TDMmode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, theword clock (WCLK) and bit clock (BCLK) can be independently configured in either master or slave mode, forflexible connectivity to a wide variety of processors.

The word clock (WCLK) is used to define the beginning of a frame, and may be programmed as either a pulse ora square-wave signal. The frequency of this clock corresponds to the selected ADC and DAC samplingfrequency.

The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in mastermode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. Incontinuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated,so in general the number of bit clocks per frame is two times the data width. For example, if data width is chosenas 16 bits, then 32 bit clocks are generated per frame. If the bit clock signal in master mode is to be used by aPLL in another device, it is recommended that the 16-bit or 32-bit data-width selections be used. These casesresult in a low-jitter bit clock signal being generated, having frequencies of 32 fS or 64 fS. In the cases of 20-bitand 24-bt data width in master mode, the bit clocks generated in each frame are not all of equal period, due tothe device not having a clean 40-fS or 48-fS clock signal readily available. The average frequency of the bit clocksignal is still accurate in these cases (being 40 fS or 48 fS), but the resulting clock signal has higher jitter than inthe 16-bit and 32-bit cases.

In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.The TLV320AIC3104-Q1 further includes programmability to place the DOUT line in the high-impedance stateduring all bit clocks when valid data is not being sent. By combining this capability with the ability to program atwhat bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resultingin multiple codecs able to use a single audio serial data bus.

When the digital audio data serial interface is powered down while configured in master mode, the pinsassociated with the interface are put into a high-impedance state.


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BCLK

WCLK

1 10 00

T0150-01

1/fs

LSBMSB

Left Channel Right Channel

2 2SDIN/SDOUT n–1 n–1 n–1n–2 n–2 n–2n–3 n–3

BCLK

WCLK

1 00 1 0

T0149-01

1/fs

LSBMSB


2 2SDIN/SDOUT n–1 n–1n–2 n–2n–3 n–3

37




Programming (continued)9.5.5 Right-Justified ModeIn right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the fallingedge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock precedingthe rising edge of the word clock.

Figure 26. Right-Justified Serial Data Bus Mode Operation

9.5.6 Left-Justified ModeIn left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the fallingedge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock followingthe rising edge of the word clock.

Figure 27. Left-Justified Serial Data Bus Mode Operation


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BCLK

WCLK

0 0

T0152-01

1/fs

LSB LSBLSB MSB MSB


1 12 2SDIN/SDOUT n–1 n–1n–1n–2 n–3 n–3n–4 n–2

BCLK

WCLK

1 10 0

T0151-01

1/fs

LSBMSB


2 2SDIN/SDOUT n–1 n–1 n–1

1 Clock Before MSB

n–2 n–2n–3 n–3

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Programming (continued)9.5.7 I2S ModeIn I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edgeof the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock afterthe rising edge of the word clock.

Figure 28. I2S Serial Data Bus Mode Operation

9.5.8 DSP ModeIn DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first,immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.

Figure 29. DSP Serial Data Bus Mode Operation


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N–1

N–1 N–1

1

1 1

1N–1N–2

N–2 N–2

0

0 0

0N–2

Right-Channel Data

Right-Channel Data

Left-Channel Data

Left-Channel Data

• • • •

• • • • • • • •

• • • • • •

DSP Mode

Left-Justified Mode

Offset

Offset Offset

T0153-01

Word Clock

Word Clock

Bit Clock

Bit Clock

Data In/Out

Data In/Out

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Programming (continued)9.5.9 TDM Data TransferTime-division multiplexed data transfer can be realized in any of the left- transfer modes if the 256-clock bit-clockmode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By changingthe programmable offset, the bit clock in each frame where the data begins can be changed, and the serial dataoutput driver (DOUT) can also be programmed to the high-impedance state during all bit clocks except whenvalid data is being put onto the bus. This allows other codecs to be programmed with different offsets and todrive their data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignoresdata on the bus except where it is expected, based on the programmed offset.

Note that the location of the data when an offset is programmed is different, depending on what transfer mode isselected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other inthe frame. This differs from left-justified mode, where the left- and right-channel data are always a half-frameapart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left- andright-channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted inFigure 30 for the two cases.

Figure 30. DSP Mode and Left-Justified Mode, ShowingEffect of Programmed Data-Word Offset


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K*R/P2/Q

PLL_CLKIN

CODEC

CODEC_CLKIN

PLL_OUT

Q = 2, 3,….., 16, 17

MCLK BCLK

CLKDIV_IN PLL_IN

B0153-01

DAC fS ADC fS

CODEC_CLK = 256 f´ S(ref)

CLKDIV_OUT

1/8

PLLDIV_OUT

CLKDIV_CLKIN

K = J.DJ = 1, 2, 3, ...., 62, 63D = 0000, 0001, ...., 9998, 9999R = 1, 2, 3, 4, ...., 15, 16P = 1, 2, ...., 7, 8

WCLK = /NCODEC

CODEC = DAC = ADC

Set NCODEC = NADC = NDAC = 1, 1.5, 2, ...., 5.5, 6DAC DRA => NDAC = 0.5ADC DRA => NADC = 0.5

f

f f f

S(ref)

S S S

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Programming (continued)9.5.10 Audio Clock GenerationThe audio converters in the TLV320AIC3104-Q1 need an internal audio master clock at a frequency of 256 fS(ref),which can be obtained in a variety of manners from an external clock signal applied to the device.

A more detailed diagram of the audio clock section of the TLV320AIC3104-Q1 is shown in Figure 31.

Figure 31. Audio Clock Generation Processing

The device can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either aprogrammable divider or a PLL to get the proper internal audio master clock required by the device. The BCLKinput can also be used to generate the internal audio master clock.

A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequenciesavailable in the system. This device includes a highly programmable PLL to accommodate such situations easily.The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focuspaid to the standard MCLK rates already widely used.


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Programming (continued)When the PLL is disabled:

fS(ref) = CLKDIV_IN / ( 128 × Q )

where• Q = 2 to 17. Q is register programmable and can be set in page 0, register 3, bits D6 to D3• CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7 to D6 (4)

NOTEWhen NCODEC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode,MCLK can be as high as 50 MHz, and fS(ref) should fall within 39 kHz to 53 kHz, inclusive.

When the PLL is enabled:fS(ref) = ( PLLCLK_IN × K × R ) / ( 2048 × P )

where• P = 1 to 8• R = 1 to 16• K = J.D• J = 1 to 63• D = 0000 to 9999• PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5 to D4 (5)

P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimalpoint), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits ofprecision). P can be set in page 0, register 3, bits D2 to D0. R can be set in page 0, register 11, bits D3 to D0. Jcan be set in page 0, register 4, bits D7 to D2. The most-significant bits of D can be set in page 0, register 5, bitsD7 to D0, and the least-significant bits of D can be set in page 0, register 6, bits D7 to D2.

Examples:If K = 8.5, then J = 8, D = 5000If K = 7.12, then J = 7, D = 1200If K = 14.03, then J = 14, D = 0300If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specifiedperformance:

2 MHz ≤ ( PLLCLK_IN / P ) ≤ 20 MHz80 MHz ≤ ( PLLCLK _IN × K × R / P ) ≤ 110 MHz4 ≤ J ≤ 55

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specifiedperformance:

10 MHz ≤ ( PLLCLK_IN / P ) ≤ 20 MHz80 MHz ≤ ( PLLCLK _IN × K × R / P ) ≤ 110 MHz4 ≤ J ≤ 11R = 1

Example:MCLK = 12 MHz and fS(ref) = 44.1 kHzSelect P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:MCLK = 12 MHz and fS(ref) = 48 kHzSelect P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920


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Programming (continued)Table 5 lists several example cases of typical MCLK rates and how to program the PLL to achieve fS(ref) = 44.1kHz or 48 kHz.

Table 5. Programming PLLMCLK (MHz) P R J D ACHIEVED fS(ref) % ERRORfS(ref) = 44.1 kHz2.8224 1 1 32 0 44,100 05.6448 1 1 16 0 44,100 012 1 1 7 5264 44,100 013 1 1 6 9474 44,099.71 –0.000716 1 1 5 6448 44,100 019.2 1 1 4 7040 44,100 019.68 1 1 4 5893 44,100.3 0.000748 4 1 7 5264 44,100 0fS(ref) = 48 kHz2.048 1 1 48 0 48,000 03.072 1 1 32 0 48,000 04.096 1 1 24 0 48,000 06.144 1 1 16 0 48,000 08.192 1 1 12 0 48,000 012 1 1 8 1920 48,000 013 1 1 7 5618 47,999.71 –0.000616 1 1 6 1440 48,000 019.2 1 1 5 1200 48,000 019.68 1 1 4 9951 47,999.79 –0.000448 4 1 8 1920 48,000 0

9.6 Register Maps

9.6.1 Control RegistersThe control registers for the TLV320AIC3104-Q1 are described in detail as follows. All registers are 8 bits inwidth, with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant bit.

Table 6. Page 0/Register 0: Page Select RegisterBIT TYPE RESET DESCRIPTIOND7–D1 R 0000 000 Reserved. Write only zeros to these bits.

D0 R/W 0

Page Select BitWriting zero to this bit sets page 0 as the active page for following register accesses. Writing a one tothis bit sets page 1 as the active page for following register accesses. It is recommended that the userread this register bit back after each write, to ensure that the proper page is being accessed for futureregister read/writes.

Table 7. Page 0/Register 1: Software Reset RegisterBIT TYPE RESET DESCRIPTION

D7 W 0Software Reset Bit0 : Don’t care1 : Self-clearing software reset

D6–D0 W 000 0000 Reserved. Do not write to these bits.


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(1) In the TLV320AIC3104-Q1, the ADC fS must be set equal to the DAC fS. This is done by setting the value of bits D7 to D4 equal to thevalue of bits D3 to D0.

Table 8. Page 0/Register 2: Codec Sample Rate Select RegisterBIT TYPE RESET DESCRIPTION

D7–D4 R/W 0000

ADC Sample Rate Select (1)

0000: ADC fS = fS(ref) / 10001: ADC fS = fS(ref) / 1.50010: ADC fS = fS(ref) / 20011: ADC fS = fS(ref) / 2.50100: ADC fS = fS(ref) / 30101: ADC fS = fS(ref) / 3.50110: ADC fS = fS(ref) / 40111: ADC fS = fS(ref) / 4.51000: ADC fS = fS(ref) / 51001: ADC fS = fS(ref) / 5.51010: ADC fS = fS(ref) / 61011–1111: Reserved. Do not write these sequences.

D3–D0 R/W 0000

DAC Sample Rate Select (1)

0000: DAC fS = fS(ref) / 10001: DAC fS = fS(ref) / 1.50010: DAC fS = fS(ref) / 20011: DAC fS = fS(ref) / 2.50100: DAC fS = fS(ref) / 30101: DAC fS = fS(ref) / 3.50110: DAC fS = fS(ref) / 40111: DAC fS = fS(ref) / 4.51000: DAC fS = fS(ref) / 51001: DAC fS = fS(ref) / 5.51010: DAC fS = fS(ref) / 61011–1111 : Reserved, do not write these sequences.

Table 9. Page 0/Register 3: PLL Programming Register ABIT TYPE RESET DESCRIPTION

D7 R/W 0PLL Control Bit0: PLL is disabled.1: PLL is enabled.

D6–D3 R/W 0010

PLL Q Value0000: Q = 160001: Q = 170010: Q = 20011: Q = 30100: Q = 4…1110: Q = 141111: Q = 15

D2–D0 R/W 000

PLL P Value000: P = 8001: P = 1010: P = 2011: P = 3100: P = 4101: P = 5110: P = 6111: P = 7

Table 10. Page 0/Register 4: PLL Programming Register BBIT TYPE RESET DESCRIPTION

D7–D2 R/W 0000 01

PLL J Value0000 00: Reserved, do not write this sequence0000 01: J = 10000 10: J = 20000 11: J = 3…1111 10: J = 621111 11: J = 63

D1–D0 R/W 00 Reserved. Write only zeros to these bits.


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(1) Whenever the D value is changed, register 5 should be written, immediately followed by register 6. Even if only the MSB or LSB of thevalue changes, both registers should be written.

Table 11. Page 0/Register 5: PLL Programming Register CBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0000 0000PLL D Value. Eight most-significant bits of a 14-bit unsigned integer valid values for D are from zero to9999, represented by a 14-bit integer located in page 0, registers 5 to 6. Values should not be writteninto these registers that would result in a D value outside the valid range. (1)

(1) Whenever the D value is changed, register 5 should be written, immediately followed by register 6. Even if only the MSB or LSB of thevalue changes, both registers should be written.

Table 12. Page 0/Register 6: PLL Programming Register DBIT TYPE RESET DESCRIPTION

D7–D2 R/W 0000 00PLL D Value. Six least-significant bits of a 14-bit unsigned integer valid values for D are from zero to9999, represented by a 14-bit integer located in page 0, registers 5 to 6. Values should not be writteninto these registers that would result in a D value outside the valid range. (1)

D1–D0 R 00 Reserved. Write only zeros to these bits.

Table 13. Page 0/Register 7: Codec Data-Path Setup RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0

fS(ref) SettingThis register setting controls timers related to the AGC time constants.0: fS(ref) = 48 kHz1: fS(ref) = 44.1 kHz

D6 R/W 0

ADC Dual-Rate Control0: ADC dual-rate mode is disabled.1: ADC dual-rate mode is enabled.Note: ADC dual-rate mode must match DAC dual-rate mode.

D5 R/W 0DAC Dual-Rate Control0: DAC dual-rate mode is disabled.1: DAC dual-rate mode is enabled.

D4–D3 R/W 00

Left-DAC Data Path Control00: Left-DAC data path is off (muted).01: Left-DAC data path plays left-channel input data.10: Left-DAC data path plays right-channel input data.11: Left-DAC data path plays mono mix of left- and right-channel input data.

D2–D1 R/W 00

Right-DAC Data-Path Control00: Right-DAC data path is off (muted).01: Right-DAC data path plays right-channel input data.10: Right-DAC data path plays left-channel input data.11: Right-DAC data path plays mono mix of left- and right-channel input data.

D0 R/W 0 Reserved. Write only zero to this bit.

Table 14. Page 0/Register 8: Audio Serial Data Interface Control Register ABIT TYPE RESET DESCRIPTION

D7 R/W 0Bit Clock Directional Control0: BCLK is an input (slave mode).1: BCLK is an output (master mode).

D6 R/W 0Word Clock Directional Control0: WCLK is an input (slave mode).1: WCLK is an output (master mode).

D5 R/W 0Serial Output Data Driver (DOUT) 3-State Control0: Do not place DOUT in high-impedance state when valid data is not being sent.1: Place DOUT in high-impedance state when valid data is not being sent.

D4 R/W 0

Bit/Word Clock Drive Control0: BCLK/WCLK does not continue to be transmitted when running in master mode if codec is powereddown.1: BCLK/WCLK continues to be transmitted when running in master mode, even if codec is powereddown.

D3 R/W 0 Reserved. Do not write to this register bit.

D2 R/W 03-D Effect Control0: Disable 3-D digital effect processing1: Enable 3-D digital effect processing



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Table 15. Page 0/Register 9: Audio Serial Data Interface Control Register BBIT TYPE RESET DESCRIPTION

D7–D6 R/W 00

Audio Serial Data Interface Transfer Mode00: Serial data bus uses I2S mode.01: Serial data bus uses DSP mode.10: Serial data bus uses right-justified mode.11: Serial data bus uses left-justified mode.

D5–D4 R/W 00

Audio Serial Data Word Length Control00: Audio data word length = 16 bits01: Audio data word length = 20 bits10: Audio data word length = 24 bits11: Audio data word length = 32 bits

D3 R/W 0

Bit Clock Rate ControlThis register only has effect when bit clock is programmed as an output.0: Continuous-transfer mode used to determine master mode bit clock rate1: 256-clock transfer mode used, resulting in 256 bit clocks per frame

D2 R/W 0DAC Re-Sync0: Don’t care1: Re-sync stereo DAC with codec interface if the group delay changes by more than ±DAC (fS / 4).

D1 R/W 0ADC Re-Sync0: Don’t care1: Re-sync stereo ADC with codec interface if the group delay changes by more than ±ADC (fS / 4).

D0 R/WRe-Sync Mute Behavior0: Re-sync is done without soft-muting the channel (ADC/DAC).1: Re-sync is done by internally soft-muting the channel (ADC/DAC).

Table 16. Page 0/Register 10: Audio Serial Data Interface Control Register CBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0000 0000

Audio Serial Data Word Offset ControlThis register determines where valid data is placed or expected in each frame, by controlling the offsetfrom beginning of the frame where valid data begins. The offset is measured from the rising edge ofword clock when in DSP mode.0000 0000: Data offset = 0 bit clocks0000 0001: Data offset = 1 bit clock0000 0010: Data offset = 2 bit clocks…Note: In continuous transfer mode the maximum offset is 17 for I2S/LJF/RJF modes and 16 for DSPmode. In 256-clock mode, the maximum offset is 242 for I2S/LJF/RJF and 241 for DSP modes.1111 1110: Data offset = 254 bit clocks1111 1111: Data offset = 255 bit clocks

Table 17. Page 0/Register 11: Audio Codec Overflow Flag RegisterBIT TYPE RESET DESCRIPTION

D7 R 0

Left-ADC Overflow FlagThis is a sticky bit, which stays set if an overflow occurs, even if the overflow condition is removed. Theregister bit is reset to 0 after it is read.0: No overflow has occurred.1: An overflow has occurred.

D6 R 0

Right-ADC Overflow FlagThis is a sticky bit, which stays set if an overflow occurs, even if the overflow condition is removed. Theregister bit is reset to 0 after it is read.0: No overflow has occurred.1: An overflow has occurred.

D5 R 0

Left-DAC Overflow FlagThis is a sticky bit, which stays set if an overflow occurs, even if the overflow condition is removed. Theregister bit is reset to 0 after it is read.0: No overflow has occurred.1: An overflow has occurred.

D4 R 0

Right-DAC Overflow FlagThis is a sticky bit, which stays set if an overflow occurs, even if the overflow condition is removed. Theregister bit is reset to 0 after it is read.0: No overflow has occurred.1: An overflow has occurred.


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Table 17. Page 0/Register 11: Audio Codec Overflow Flag Register (continued)BIT TYPE RESET DESCRIPTION

D3–D0 R/W 0001

PLL R Value0000: R = 160001: R = 10010: R = 20011: R = 30100: R = 4…1110: R = 141111: R = 15

Table 18. Page 0/Register 12: Audio Codec Digital Filter Control RegisterBIT TYPE RESET DESCRIPTION

D7–D6 R/W 00

Left-ADC High-Pass Filter Control00: Left-ADC high-pass filter disabled01: Left-ADC high-pass filter –3-dB frequency = 0.0045 × ADC fS10: Left-ADC high-pass filter –3-dB frequency = 0.0125 × ADC fS11: Left-ADC high-pass filter –3-dB frequency = 0.025 × ADC fS

D5–D4 R/W 00

Right-ADC High-Pass Filter Control00: Right-ADC high-pass filter disabled01: Right-ADC high-pass filter –3-dB frequency = 0.0045 × ADC fS10: Right-ADC high-pass filter –3-dB frequency = 0.0125 × ADC fS11: Right-ADC high-pass filter –3-dB frequency = 0.025 × ADC fS

D3 R/W 0Left-DAC Digital Effects Filter Control0: Left-DAC digital effects filter disabled (bypassed)1: Left-DAC digital effects filter enabled

D2 R/W 0Left-DAC De-Emphasis Filter Control0: Left-DAC de-emphasis filter disabled (bypassed)1: Left-DAC de-emphasis filter enabled

D1 R/W 0Right-DAC Digital Effects Filter Control0: Right-DAC digital effects filter disabled (bypassed)1: Right-DAC digital effects filter enabled

D0 R/W 0Right-DAC De-Emphasis Filter Control0: Right-DAC de-emphasis filter disabled (bypassed)1: Right-DAC de-emphasis filter enabled

Table 19. Page 0/Register 13: ReservedBIT TYPE RESET DESCRIPTIOND7–D0 R/W 0000 0000 Reserved. Write only zeros to this register.

(1) Do not set D6 and D3 to 1 simultaneously.

Table 20. Page 0/Register 14: Headset/Button Press Detection Register BBIT TYPE RESET DESCRIPTION

D7 R/W 0Driver Capacitive Coupling0: Programs high-power outputs for capless driver configuration1: Programs high-power outputs for AC-coupled driver configuration

D6 (1) R/W 0

Stereo Output Driver Configuration ANote: Do not set bits D6 and D3 both high at the same time.0: A stereo fully differential output configuration is not being used1: A stereo fully differential output configuration is being used

D5 R 0 Reserved. Write only zero to this bit.

D4 R 0Headset Detection Flag0: A headset has not been detected.1: A headset has been detected.

D3 (1) R/W 0

Stereo Output Driver Configuration BNote: Do not set bits D6 and D3 both high at the same time.0: A stereo pseudodifferential output configuration is not being used.1: A stereo pseudodifferential output configuration is being used.



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Table 21. Page 0/Register 15: Left-ADC PGA Gain Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 1Left-ADC PGA Mute0: The left-ADC PGA is not muted1: The left-ADC PGA is muted

D6–D0 R/W 000 0000

Left-ADC PGA Gain Setting000 0000: Gain = 0 dB000 0001: Gain = 0.5 dB000 0010: Gain = 1 dB…111 0110: Gain = 59 dB111 0111: Gain = 59.5 dB111 1000: Gain = 59.5 dB…111 1111: Gain = 59.5 dB

Table 22. Page 0/Register 16: Right-ADC PGA Gain Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 1Right-ADC PGA Mute0: The right ADC PGA is not muted.1: The right ADC PGA is muted.

D6–D0 R/W 000 0000

Right-ADC PGA Gain Setting000 0000: Gain = 0 dB000 0001: Gain = 0.5 dB000 0010: Gain = 1 dB…111 0110: Gain = 59 dB111 0111: Gain = 59.5 dB111 1000: Gain = 59.5 dB…111 1111: Gain = 59.5 dB

Table 23. Page 0/Register 17: MIC2L/R to Left-ADC Control RegisterBIT TYPE RESET DESCRIPTION

D7–D4 R/W 1111

MIC2L Input Level Control for Left-ADC PGA MixSetting the input level control to one of the following gains automatically connects MIC2L to the left-ADCPGA mix.0000: Input level control gain = 0 dB0001: Input level control gain = –1.5 dB0010: Input level control gain = –3 dB0011: Input level control gain = –4.5 dB0100: Input level control gain = –6 dB0101: Input level control gain = –7.5 dB0110: Input level control gain = –9 dB0111: Input level control gain = –10.5 dB1000: Input level control gain = –12 dB1001–1110: Reserved. Do not write these sequences to these register bits.1111: MIC2L is not connected to the left-ADC PGA.

D3–D0 R/W 1111

MIC2R/LINE2R Input Level Control for Left-ADC PGA MixSetting the input level control to one of the following gains automatically connects MIC2R to the left-ADCPGA mix.0000: Input level control gain = 0 dB0001: Input level control gain = –1.5 dB0010: Input level control gain = –3 dB0011: Input level control gain = –4.5 dB0100: Input level control gain = –6 dB0101: Input level control gain = –7.5 dB0110: Input level control gain = –9 dB0111: Input level control gain = –10.5 dB1000: Input level control gain = –12 dB1001–1110: Reserved. Do not write these sequences to these register bits.1111: MIC2R/LINE2R is not connected to the left-ADC PGA.


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Table 24. Page 0/Register 18: MIC2/LINE2 to Right-ADC Control RegisterBIT TYPE RESET DESCRIPTION

D7–D4 R/W 1111

MIC2L/LINE2L Input Level Control for Right -DC PGA MixSetting the input level control to one of the following gains automatically connects MIC2L to the right-ADC PGA mix.0000: Input level control gain = 0 dB0001: Input level control gain = –1.5 dB0010: Input level control gain = –3 dB0011: Input level control gain = –4.5 dB0100: Input level control gain = –6 dB0101: Input level control gain = –7.5 dB0110: Input level control gain = –9 dB0111: Input level control gain = –10.5 dB1000: Input level control gain = –12 dB1001–1110: Reserved. Do not write these sequences to these register bits.1111: MIC2L/LINE2L is not connected to the right-ADC PGA.

D3–D0 R/W 1111

MIC2R/LINE2R Input Level Control for Right-ADC PGA MixSetting the input level control to one of the following gains automatically connects MIC2R to the right-ADC PGA mix.0000: Input level control gain = 0 dB0001: Input level control gain = –1.5 dB0010: Input level control gain = –3 dB0011: Input level control gain = –4.5 dB0100: Input level control gain = –6 dB0101: Input level control gain = –7.5 dB0110: Input level control gain = –9 dB0111: Input level control gain = –10.5 dB1000: Input level control gain = –12 dB1001–1110: Reserved. Do not write these sequences to these register bits.1111: MIC2R/LINE2R is not connected to right-ADC PGA.

Table 25. Page 0/Register 19: MIC1LP/LINE1LP to Left-ADC Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0

MIC1LP/LINE1LP Single-Ended vs Fully Differential Control. If MIC1LP/LINE1LP is selected to both left-and right-ADC channels, both connections must use the same configuration (single-ended or fullydifferential mode).0: MIC1LP/LINE1LP is configured in single-ended mode.1: MIC1LP/LINE1LP and MIC1LM/LINE1LM are configured in fully differential mode.

D6–D3 R/W 1111

MIC1LP/LINE1LP Input Level Control for Left-ADC PGA MixSetting the input level control to one of the following gains automatically connects LINE1L to the left-ADC PGA mix.0000: Input level control gain = 0 dB0001: Input level control gain = –1.5 dB0010: Input level control gain = –3 dB0011: Input level control gain = –4.5 dB0100: Input level control gain = –6 dB0101: Input level control gain = –7.5 dB0110: Input level control gain = –9 dB0111: Input level control gain = –10.5 dB1000: Input level control gain = –12 dB1001–1110: Reserved. Do not write these sequences to these register bits.1111: LINE1L is not connected to the left-ADC PGA.

D2 R/W 0Left-ADC Channel Power Control0: Left-ADC channel is powered down.1: Left-ADC channel is powered up.

D1–D0 R/W 00

Left-ADC PGA Soft-Stepping Control00: Left-ADC PGA soft-stepping at once per sample period01: Left-ADC PGA soft-stepping at once per two sample periods10–11: Left-ADC PGA soft-stepping is disabled.

Table 26. Page 0/Register 20: Reserved RegisterBIT TYPE RESET DESCRIPTIOND7–D0 R 0111 1000 Reserved. Do not write to this register.


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Table 27. Page 0/Register 21: MIC1RP/LINE1RP to Left-ADC Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0

MIC1RP/LINE1RP Single-Ended vs Fully Differential Control. If MIC1RP/LINE1RP is selected to bothleft- and right-ADC channels, both connections must use the same configuration (single-ended or fullydifferential mode).0: MIC1RP/LINE1RP is configured in single-ended mode.1: MIC1RP/LINE1RP and MIC1RM/LINE1RM are configured in fully differential mode.

D6–D3 R/W 1111

MIC1RP/LINE1RP Input Level Control for Left-ADC PGA MixSetting the input level control to one of the following gains automatically connects LINE1R to the left-ADC PGA mix.0000: Input level control gain = 0 dB0001: Input level control gain = –1.5 dB0010: Input level control gain = –3 dB0011: Input level control gain = –4.5 dB0100: Input level control gain = –6 dB0101: Input level control gain = –7.5 dB0110: Input level control gain = –9 dB0111: Input level control gain = –10.5 dB1000: Input level control gain = –12 dB1001–1110: Reserved. Do not write these sequences to these register bits.1111: LINE1R is not connected to the left-ADC PGA.


Table 28. Page 0/Register 22: MIC1RP/LINE1RP to Right-ADC Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0

MIC1RP/LINE1RP Single-Ended vs Fully Differential Control. If MIC1RP/LINE1RP is selected to bothleft- and right-ADC channels, both connections must use the same configuration (single-ended or fullydifferential mode).0: MIC1RP/LINE1RP is configured in single-ended mode.1: MIC1RP/LINE1RP and MIC1RM/LINE1RM are configured in fully differential mode.

D6–D3 R/W 1111

MIC1RP/LINE1RP Input Level Control for Right-ADC PGA MixSetting the input level control to one of the following gains automatically connects LINE1R to the right-ADC PGA mix.0000: Input level control gain = 0 dB0001: Input level control gain = –1.5 dB0010: Input level control gain = –3 dB0011: Input level control gain = –4.5 dB0100: Input level control gain = –6 dB0101: Input level control gain = –7.5 dB0110: Input level control gain = –9 dB0111: Input level control gain = –10.5 dB1000: Input level control gain = –12 dB1001–1110: Reserved. Do not write these sequences to these register bits.1111: LINE1R is not connected to the right-ADC PGA.

D2 R/W 0Right-ADC Channel Power Control0: Right-ADC channel is powered down.1: Right-ADC channel is powered up.

D1–D0 R/W 00

Right-ADC PGA Soft-Stepping Control00: Right-ADC PGA soft-stepping at once per sample period01: Right-ADC PGA soft-stepping at once per two sample periods10–11: Right-ADC PGA soft-stepping is disabled.

Table 29. Page 0/Register 23: Reserved RegisterBIT TYPE RESET DESCRIPTIOND7–D0 R/W 0111 1000 Reserved. Do not write to this register.

Table 30. Page 0/Register 24: MIC1LP/LINE1LP to Right-ADC Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0

MIC1LP/LINE1LP Single-Ended vs Fully Differential Control. If MIC1LP/LINE1LP is selected to both left-and right-ADC channels, both connections must use the same configuration (single-ended or fullydifferential mode).0: MIC1LP/LINE1LP is configured in single-ended mode.1: MIC1LP/LINE1LP and MIC1LM/LINE1LM are configured in fully differential mode.


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Table 30. Page 0/Register 24: MIC1LP/LINE1LP to Right-ADC Control Register (continued)BIT TYPE RESET DESCRIPTION

D6–D3 R/W 1111

MIC1LP/LINE1LP Input Level Control for Right-ADC PGA MixSetting the input level control to one of the following gains automatically connects LINE1L to the right-ADC PGA mix.0000: Input level control gain = 0 dB0001: Input level control gain = –1.5 dB0010: Input level control gain = –3 dB0011: Input level control gain = –4.5 dB0100: Input level control gain = –6 dB0101: Input level control gain = –7.5 dB0110: Input level control gain = –9 dB0111: Input level control gain = –10.5 dB1000: Input level control gain = –12 dB1001–1110: Reserved. Do not write these sequences to these register bits.1111: LINE1L is not connected to the right-ADC PGA.


Table 31. Page 0/Register 25: MICBIAS Control RegisterBIT TYPE RESET DESCRIPTION

D7–D6 R/W 00

MICBIAS Level Control00: MICBIAS output is powered down.01: MICBIAS output is powered to 2 V.10: MICBIAS output is powered to 2.5 V.11: MICBIAS output is connected to AVDD.

D5–D3 R 000 Reserved. Write only zeros to these bits.D2–D0 R XXX Reserved. Write only zeros to these bits.

(1) Time constants are valid when DRA is not enabled. The values change if DRA is enabled.

Table 32. Page 0/Register 26: Left-AGC Control Register ABIT TYPE RESET DESCRIPTION

D7 R/W 0Left-AGC Enable0: Left AGC is disabled.1: Left AGC is enabled.

D6–D4 R/W 000

Left-AGC Target Level000: Left-AGC target level = –5.5 dB001: Left-AGC target level = –8 dB010: Left-AGC target level = –10 dB011: Left-AGC target level = –12 dB100: Left-AGC target level = –14 dB101: Left-AGC target level = –17 dB110: Left-AGC target level = –20 dB111: Left-AGC target level = –24 dB

D3–D2 R/W 00

Left-AGC Attack TimeThese time constants (1) are not accurate when double-rate audio mode is enabled.00: Left-AGC attack time = 8 ms01: Left-AGC attack time = 11 ms10: Left-AGC attack time = 16 ms11: Left-AGC attack time = 20 ms

D1–D0 R/W 00

Left-AGC Decay TimeThese time constants (1) are not accurate when double-rate audio mode is enabled.00: Left-AGC decay time = 100 ms01: Left-AGC decay time = 200 ms10: Left-AGC decay time = 400 ms11: Left-AGC decay time = 500 ms

Table 33. Page 0/Register 27: Left-AGC Control Register BBIT TYPE RESET DESCRIPTION

D7–D1 R/W 1111 111

Left-AGC Maximum Gain Allowed0000 000: Maximum gain = 0 dB0000 001: Maximum gain = 0.5 dB0000 010: Maximum gain = 1 dB…1110 110: Maximum gain = 59 dB1110 111–1111 111: Maximum gain = 59.5 dB


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Table 33. Page 0/Register 27: Left-AGC Control Register B (continued)BIT TYPE RESET DESCRIPTIOND0 R/W 0 Reserved. Write only zero to this bit.

Table 34. Page 0/Register 28: Left-AGC Control Register CBIT TYPE RESET DESCRIPTION

D7–D6 R/W 00

Noise Gate Hysteresis Level Control00: Hysteresis = 1 dB01: Hysteresis = 2 dB10: Hysteresis = 3 dB11: Hysteresis is disabled.

D5–D1 R/W 00 000

Left-AGC Noise Threshold Control00000: Left-AGC noise/silence detection disabled00001: Left-AGC noise threshold = –30 dB00010: Left-AGC noise threshold = –32 dB00011: Left-AGC noise threshold = –34 dB…11101: Left-AGC noise threshold = –86 dB11110: Left-AGC noise threshold = –88 dB11111: Left-AGC noise threshold = –90 dB

D0 R/W 0Left-AGC Clip Stepping Control0: Left-AGC clip stepping disabled1: Left-AGC clip stepping enabled

Table 35. Page 0/Register 29: Right-AGC Control Register ABIT TYPE RESET DESCRIPTION

D7 R/W 0Right-AGC Enable0: Right AGC is disabled.1: Right AGC is enabled.

D6–D4 R/W 000

Right-AGC Target Level000: Right-AGC target level = –5.5 dB001: Right-AGC target level = –8 dB010: Right-AGC target level = –10 dB011: Right-AGC target level = –12 dB100: Right-AGC target level = –14 dB101: Right-AGC target level = –17 dB110: Right-AGC target level = –20 dB111: Right-AGC target level = –24 dB

D3–D2 R/W 00

Right-AGC Attack TimeThese time constants are not accurate when double-rate audio mode is enabled.00: Right-AGC attack time = 8 ms01: Right-AGC attack time = 11 ms10: Right-AGC attack time = 16 ms11: Right-AGC attack time = 20 ms

D1–D0 R/W 00

Right-AGC Decay TimeThese time constants are not accurate when double-rate audio mode is enabled.00: Right-AGC decay time = 100 ms01: Right-AGC decay time = 200 ms10: Right-AGC decay time = 400 ms11: Right-AGC decay time = 500 ms

Table 36. Page 0/Register 30: Right-AGC Control Register BBIT TYPE RESET DESCRIPTION

D7–D1 R/W 1111 111

Right-AGC Maximum Gain Allowed0000 000: Maximum gain = 0 dB0000 001: Maximum gain = 0.5 dB0000 010: Maximum gain = 1 dB…1110 110: Maximum gain = 59 dB1110 111–1111 111: Maximum gain = 59.5 dB



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Table 37. Page 0/Register 31: Right-AGC Control Register CBIT TYPE RESET DESCRIPTION

D7–D6 R/W 00

Noise Gate Hysteresis Level Control00: Hysteresis = 1 dB01: Hysteresis = 2 dB10: Hysteresis = 3 dB11: Hysteresis is disabled.

D5–D1 R/W 00 000

Right-AGC Noise Threshold Control00 000: Right-AGC noise/silence detection disabled00 001: Right-AGC noise threshold = –30 dB00 010: Right-AGC noise threshold = –32 dB00 011: Right-AGC noise threshold = –34 dB…11 101: Right-AGC noise threshold = –86 dB11 110: Right-AGC noise threshold = –88 dB11 111: Right-AGC noise threshold = –90 dB

D0 R/W 0Right-AGC Clip Stepping Control0: Right-AGC clip stepping disabled1: Right-AGC clip stepping enabled

Table 38. Page 0/Register 32: Left-AGC Gain RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R 0000 0000

Left-Channel Gain Applied by AGC Algorithm1110 1000: Gain = –12 dB1110 1001: Gain = –11.5 dB1110 1010: Gain = –11 dB…0000 0000: Gain = 0.0 dB0000 0001: Gain = 0.5 dB…0111 0110: Gain = 59 dB0111 0111: Gain = 59.5 dB

Table 39. Page 0/Register 33: Right-AGC Gain RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R 0000 0000

Right-Channel Gain Applied by AGC Algorithm1110 1000: Gain = –12 dB1110 1001: Gain = –11.5 dB1110 1010: Gain = –11 dB…0000 0000: Gain = 0 dB0000 0001: Gain = +0.5-dB…0111 0110: Gain = 59 dB0111 0111: Gain = 59.5 dB

(1) Time constants are valid when DRA is not enabled. The values change when DRA is enabled.

Table 40. Page 0/Register 34: Left-AGC Noise Gate Debounce RegisterBIT TYPE RESET DESCRIPTION

D7–D3 R/W 0000 0

Left-AGC Noise Detection Debounce ControlThese times (1) are not accurate when double-rate audio mode is enabled.0000 0: Debounce = 0 ms0000 1: Debounce = 0.5 ms0001 0: Debounce = 1 ms0001 1: Debounce = 2 ms0010 0: Debounce = 4 ms0010 1: Debounce = 8 ms0011 0: Debounce = 16 ms0011 1: Debounce = 32 ms0100 0: Debounce = 64 × 1 = 64 ms0100 1: Debounce = 64 × 2 = 128 ms0101 0: Debounce = 64 × 3 = 192 ms…1111 0: Debounce = 64 × 23 = 1,472 ms1111 1: Debounce = 64 × 24 = 1,536 ms


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Table 40. Page 0/Register 34: Left-AGC Noise Gate Debounce Register (continued)BIT TYPE RESET DESCRIPTION

D2–D0 R/W 000

Left-AGC Signal Detection Debounce ControlThese times (1) are not accurate when double-rate audio mode is enabled.000: Debounce = 0 ms001: Debounce = 0.5 ms010: Debounce = 1 ms011: Debounce = 2 ms100: Debounce = 4 ms101: Debounce = 8 ms110: Debounce = 16 ms111: Debounce = 32 ms

(1) Time constants are valid when DRA is not enabled. The values change when DRA is enabled.

Table 41. Page 0/Register 35: Right-AGC Noise Gate Debounce RegisterBIT TYPE RESET DESCRIPTION

D7–D3 R/W 0000 0

Right-AGC Noise Detection Debounce ControlThese times (1) are not accurate when double-rate audio mode is enabled.00000: Debounce = 0 ms00001: Debounce = 0.5 ms00010: Debounce = 1 ms00011: Debounce = 2 ms00100: Debounce = 4 ms00101: Debounce = 8 ms00110: Debounce = 16 ms00111: Debounce = 32 ms01000: Debounce = 64 × 1 = 64 ms01001: Debounce = 64 × 2 = 128 ms01010: Debounce = 64 × 3 = 192 ms…11110: Debounce = 64 × 23 = 1,472 ms11111: Debounce = 64 × 24 = 1,536 ms

D2–D0 R/W 000

Right-AGC Signal Detection Debounce ControlThese times (1) are not accurate when double-rate audio mode is enabled.000: Debounce = 0 ms001: Debounce = 0.5 ms010: Debounce = 1 ms011: Debounce = 2 ms100: Debounce = 4 ms101: Debounce = 8 ms110: Debounce = 16 ms111: Debounce = 32 ms

Table 42. Page 0/Register 36: ADC Flag RegisterBIT TYPE RESET DESCRIPTION

D7 R 0Left-ADC PGA Status0: Applied gain and programmed gain are not the same.1: Applied gain = programmed gain

D6 R 0Left-ADC Power Status0: Left ADC is in a power-down state.1: Left ADC is in a power-up state.

D5 R 0Left-AGC Signal Detection Status0: Signal power is greater than or equal to noise threshold.1: Signal power is less than noise threshold.

D4 R 0Left-AGC Saturation Flag0: Left AGC is not saturated.1: Left-AGC gain applied = maximum allowed gain for left AGC

D3 R 0Right-ADC PGA Status0: Applied gain and programmed gain are not the same.1: Applied gain = programmed gain

D2 R 0Right-ADC Power Status0: Right ADC is in a power-down state.1: Right ADC is in a power-up state.

D1 R 0Right-AGC Signal Detection Status0: Signal power is greater than or equal to noise threshold.1: Signal power is less than noise threshold.


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Table 42. Page 0/Register 36: ADC Flag Register (continued)BIT TYPE RESET DESCRIPTION

D0 R 0Right-AGC Saturation Flag0: Right AGC is not saturated.1: Right-AGC gain applied = maximum allowed gain for right AGC

Table 43. Page 0/Register 37: DAC Power and Output Driver Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0Left-DAC Power Control0: Left DAC is not powered up.1: Left DAC is powered up.

D6 R/W 0Right-DAC Power Control0: Right DAC is not powered up.1: Right DAC is powered up.

D5–D4 R/W 00

HPLCOM Output Driver Configuration Control00: HPLCOM configured as differential of HPLOUT01: HPLCOM configured as constant VCM output10: HPLCOM configured as independent single-ended output11: Reserved. Do not write this sequence to these register bits.


Table 44. Page 0/Register 38: High-Power Output Driver Control RegisterBIT TYPE RESET DESCRIPTIOND7–D6 R 00 Reserved. Write only zeros to these register bits.

D5–D3 R/W 000

HPRCOM Output Driver Configuration Control000: HPRCOM configured as differential of HPROUT001: HPRCOM configured as constant VCM output010: HPRCOM configured as independent single-ended output011: HPRCOM configured as differential of HPLCOM100: HPRCOM configured as external feedback with HPLCOM as constant VCM output101–111: Reserved. Do not write these sequences to these register bits.

D2 R/W 0Short-Circuit Protection Control0: Short-circuit protection on all high-power output drivers is disabled.1: Short-circuit protection on all high-power output drivers is enabled.

D1 R/W 0

Short-Circuit Protection Mode Control0: If short-circuit protection is enabled, it limits the maximum current to the load.1: If short-circuit protection is enabled, it powers down the output driver automatically when a short isdetected.

D0 R 0 Reserved. Write only zero to this bit.

Table 45. Page 0/Register 39: Reserved RegisterBIT TYPE RESET DESCRIPTIOND7–D0 R 0000 0000 Reserved. Do not write to this register.

Table 46. Page 0/Register 40: High-Power Output Stage Control RegisterBIT TYPE RESET DESCRIPTION

D7–D6 R/W 00

Output Common-Mode Voltage Control00: Output common-mode voltage = 1.35 V01: Output common-mode voltage = 1.5 V10: Output common-mode voltage = 1.65 V11: Output common-mode voltage = 1.8 V


D1–D0 R/W 00

Output Volume Control Soft-Stepping00: Output soft-stepping = one step per sample period01: Output soft-stepping = one step per two sample periods10: Output soft-stepping disabled11: Reserved. Do not write this sequence to these bits.


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Table 47. Page 0/Register 41: DAC Output Switching Control RegisterBIT TYPE RESET DESCRIPTION

D7–D6 R/W 00

Left-DAC Output Switching Control00: Left-DAC output selects DAC_L1 path.01: Left-DAC output selects DAC_L3 path to left line output driver.10: Left-DAC output selects DAC_L2 path to left high-power output drivers.11: Reserved. Do not write this sequence to these register bits.

D5–D4 R/W 00

Right-DAC Output Switching Control00: Right-DAC output selects DAC_R1 path.01: Right-DAC output selects DAC_R3 path to right line output driver.10: Right-DAC output selects DAC_R2 path to right high-power output drivers.11: Reserved. Do not write this sequence to these register bits.


D1–D0 R/W 00

DAC Digital Volume Control Functionality00: Left- and right-DAC channels have independent volume controls.01: Left-DAC volume follows the right-DAC digital volume control register.10: Right-DAC volume follows the left-DAC digital volume control register.11: Left- and right-DAC channels have independent volume controls (same as 00).

Table 48. Page 0/Register 42: Output Driver Pop Reduction RegisterBIT TYPE RESET DESCRIPTION

D7–D4 R/W 0000

Output Driver Power-On Delay Control0000: Driver power-on time = 0 μs0001: Driver power-on time = 10 μs0010: Driver power-on time = 100 μs0011: Driver power-on time = 1 ms0100: Driver power-on time = 10 ms0101: Driver power-on time = 50 ms0110: Driver power-on time = 100 ms0111: Driver power-on time = 200 ms1000: Driver power-on time = 400 ms1001: Driver power-on time = 800 ms1010: Driver power-on time = 2 s1011: Driver power-on time = 4 s1100–1111: Reserved. Do not write these sequences to these register bits.

D3–D2 R/W 00

Driver Ramp-Up Step Timing Control00: Driver ramp-up step time = 0 ms01: Driver ramp-up step time = 1 ms10: Driver ramp-up step time = 2 ms11: Driver ramp-up step time = 4 ms

D1 R/W 0Weak Output Common-Mode Voltage Control0: Weakly driven output common-mode voltage is generated from resistor divider off the AVDD supply.1: Weakly driven output common-mode voltage is generated from band-gap reference.


Table 49. Page 0/Register 43: Left-DAC Digital Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 1Left-DAC Digital Mute0: The left-DAC channel is not muted.1: The left-DAC channel is muted.

D6–D0 R/W 000 0000

Left-DAC Digital Volume Control Setting000 0000: Gain = 0 dB000 0001: Gain = –0.5 dB000 0010: Gain = –1 dB…111 1101: Gain = –62.5 dB111 1110: Gain = –63 dB111 1111: Gain = –63.5 dB

Table 50. Page 0/Register 44: Right-DAC Digital Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 1Right-DAC Digital Mute0: The right-DAC channel is not muted.1: The right-DAC channel is muted.


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Table 50. Page 0/Register 44: Right-DAC Digital Volume Control Register (continued)BIT TYPE RESET DESCRIPTION

D6–D0 R/W 000 0000

Right-DAC Digital Volume Control Setting000 0000: Gain = 0 dB000 0001: Gain = –0.5 dB000 0010: Gain = –1 dB…111 1101: Gain = –62.5 dB111 1110: Gain = –63 dB111 1111: Gain = –63.5 dB

9.6.2 Output Stage Volume ControlsA basic analog volume control with range from 0 dB to –78 dB and mute is replicated multiple times in the outputstage network, connected to each of the analog signals that route to the output stage. In addition, to enablecompletely independent mixing operations to be performed for each output driver, each analog signal coming intothe output stage may have up to seven separate volume controls. These volume controls all have approximately0.5-dB step programmability over most of the gain range, with steps increasing slightly at the lowest attenuations.Table 51 lists the detailed gain versus programmed setting for this basic volume control.

Table 51. Output Stage Volume Control Settings and Gains

Gain Setting Analog Gain(dB) Gain Setting Analog Gain

(dB) Gain Setting Analog Gain(dB) Gain Setting Analog Gain

(dB)0 0 30 –15 60 –30.1 90 –45.21 –0.5 31 –15.5 61 –30.6 91 –45.82 –1 32 –16 62 –31.1 92 –46.23 –1.5 33 –16.5 63 –31.6 93 –46.74 –2 34 –17 64 –32.1 94 –47.45 –2.5 35 –17.5 65 –32.6 95 –47.96 –3 36 –18 66 –33.1 96 –48.27 –3.5 37 –18.6 67 –33.6 97 –48.78 –4 38 –19.1 68 –34.1 98 –49.39 –4.5 39 –19.6 69 –34.6 99 –5010 –5 40 –20.1 70 –35.1 100 –50.311 –5.5 41 –20.6 71 –35.7 101 –5112 –6 42 –21.1 72 –36.1 102 –51.413 –6.5 43 –21.6 73 –36.7 103 –51.814 –7 44 –22.1 74 –37.1 104 –52.215 –7.5 45 –22.6 75 –37.7 105 –52.716 –8 46 –23.1 76 –38.2 106 –53.717 –8.5 47 –23.6 77 –38.7 107 –54.218 –9 48 –24.1 78 –39.2 108 –55.319 –9.5 49 –24.6 79 –39.7 109 –56.720 –10 50 –25.1 80 –40.2 110 –58.321 –10.5 51 –25.6 81 –40.7 111 –60.222 –11 52 –26.1 82 –41.2 112 –62.723 –11.5 53 –26.6 83 –41.7 113 –64.324 –12 54 –27.1 84 –42.2 114 –66.225 –12.5 55 –27.6 85 –42.7 115 –68.726 –13 56 –28.1 86 –43.2 116 –72.227 –13.5 57 –28.6 87 –43.8 117 –78.328 –14 58 –29.1 88 –44.3 118–127 Mute29 –14.5 59 –29.6 89 –44.8


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Table 53. Page 0/Register 46: PGA_L to HPLOUT Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_L Output Routing Control0: PGA_L is not routed to HPLOUT1: PGA_L is routed to HPLOUT

D6–D0 R/W 000 0000 PGA_L to HPLOUT Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 54. Page 0/Register 47: DAC_L1 to HPLOUT Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_L1 Output Routing Control0: DAC_L1 is not routed to HPLOUT.1: DAC_L1 is routed to HPLOUT.

D6–D0 R/W 000 0000 DAC_L1 to HPLOUT Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.


Table 56. Page 0/Register 49: PGA_R to HPLOUT Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_R Output Routing Control0: PGA_R is not routed to HPLOUT1: PGA_R is routed to HPLOUT

D6–D0 R/W 000 0000 PGA_R to HPLOUT Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 57. Page 0/Register 50: DAC_R1 to HPLOUT Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_R1 Output Routing Control0: DAC_R1 is not routed to HPLOUT.1: DAC_R1 is routed to HPLOUT.

D6–D0 R/W 000 0000 DAC_R1 to HPLOUT Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 58. Page 0/Register 51: HPLOUT Output Level Control RegisterBIT TYPE RESET DESCRIPTION

D7–D4 R/W 0000

HPLOUT Output Level Control0000: Output level control = 0 dB0001: Output level control = 1 dB0010: Output level control = 2 dB...1000: Output level control = 8 dB1001: Output level control = 9 dB1010–1111: Reserved. Do not write these sequences to these register bits.

D3 R/W 0HPLOUT Mute0: HPLOUT is muted.1: HPLOUT is not muted.

D2 R/W 1HPLOUT Power-Down Drive Control0: HPLOUT is weakly driven to a common-mode when powered down.1: HPLOUT is high-impedance when powered down.

D1 R 1HPLOUT Volume Control Status0: All programmed gains to HPLOUT have been applied.1: Not all programmed gains to HPLOUT have been applied yet.

D0 R/W 0HPLOUT Power Control0: HPLOUT is not fully powered up.1: HPLOUT is fully powered up.


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Table 60. Page 0/Register 53: PGA_L to HPLCOM Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_L Output Routing Control0: PGA_L is not routed to HPLCOM.1: PGA_L is routed to HPLCOM.

D6–D0 R/W 000 0000 PGA_L to HPLCOM Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 61. Page 0/Register 54: DAC_L1 to HPLCOM Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_L1 Output Routing Control0: DAC_L1 is not routed to HPLCOM.1: DAC_L1 is routed to HPLCOM.

D6–D0 R/W 000 0000 DAC_L1 to HPLCOM Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.


Table 63. Page 0/Register 56: PGA_R to HPLCOM Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_R Output Routing Control0: PGA_R is not routed to HPLCOM.1: PGA_R is routed to HPLCOM.

D6–D0 R/W 000 0000 PGA_R to HPLCOM Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 64. Page 0/Register 57: DAC_R1 to HPLCOM Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_R1 Output Routing Control0: DAC_R1 is not routed to HPLCOM.1: DAC_R1 is routed to HPLCOM.

D6–D0 R/W 000 0000 DAC_R1 to HPLCOM Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 65. Page 0/Register 58: HPLCOM Output Level Control RegisterBIT TYPE RESET DESCRIPTION

D7–D4 R/W 0000

HPLCOM Output Level Control0000: Output level control = 0 dB0001: Output level control = 1 dB0010: Output level control = 2 dB...1000: Output level control = 8 dB1001: Output level control = 9 dB1010–1111: Reserved. Do not write these sequences to these register bits.

D3 R/W 0HPLCOM Mute0: HPLCOM is muted.1: HPLCOM is not muted.

D2 R/W 1HPLCOM Power-Down Drive Control0: HPLCOM is weakly driven to a common mode when powered down.1: HPLCOM is high-impedance when powered down.

D1 R 1HPLCOM Volume Control Status0: All programmed gains to HPLCOM have been applied.1: Not all programmed gains to HPLCOM have been applied yet.

D0 R/W 0HPLCOM Power Control0: HPLCOM is not fully powered up.1: HPLCOM is fully powered up.


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Table 67. Page 0/Register 60: PGA_L to HPROUT Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_L Output Routing Control0: PGA_L is not routed to HPROUT.1: PGA_L is routed to HPROUT.

D6–D0 R/W 000 0000 PGA_L to HPROUT Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 68. Page 0/Register 61: DAC_L1 to HPROUT Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_L1 Output Routing Control0: DAC_L1 is not routed to HPROUT.1: DAC_L1 is routed to HPROUT.

D6–D0 R/W 000 0000 DAC_L1 to HPROUT Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.


Table 70. Page 0/Register 63: PGA_R to HPROUT Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_R Output Routing Control0: PGA_R is not routed to HPROUT.1: PGA_R is routed to HPROUT.

D6–D0 R/W 000 0000 PGA_R to HPROUT Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 71. Page 0/Register 64: DAC_R1 to HPROUT Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_R1 Output Routing Control0: DAC_R1 is not routed to HPROUT.1: DAC_R1 is routed to HPROUT.

D6–D0 R/W 000 0000 DAC_R1 to HPROUT Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 72. Page 0/Register 65: HPROUT Output Level Control RegisterBIT TYPE RESET DESCRIPTION

D7–D4 R/W 0000

HPROUT Output Level Control0000: Output level control = 0 dB0001: Output level control = 1 dB0010: Output level control = 2 dB...1000: Output level control = 8 dB1001: Output level control = 9 dB1010–1111: Reserved. Do not write these sequences to these register bits.

D3 R/W 0HPROUT Mute0: HPROUT is muted.1: HPROUT is not muted.

D2 R/W 1HPROUT Power-Down Drive Control0: HPROUT is weakly driven to a common mode when powered down.1: HPROUT is high-impedance when powered down.

D1 R 1HPROUT Volume Control Status0: All programmed gains to HPROUT have been applied.1: Not all programmed gains to HPROUT have been applied yet.

D0 R/W 0HPROUT Power Control0: HPROUT is not fully powered up.1: HPROUT is fully powered up.


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Table 74. Page 0/Register 67: PGA_L to HPRCOM Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_L Output Routing Control0: PGA_L is not routed to HPRCOM.1: PGA_L is routed to HPRCOM.

D6–D0 R/W 000 0000 PGA_L to HPRCOM Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 75. Page 0/Register 68: DAC_L1 to HPRCOM Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_L1 Output Routing Control0: DAC_L1 is not routed to HPRCOM.1: DAC_L1 is routed to HPRCOM.

D6–D0 R/W 000 0000 DAC_L1 to HPRCOM Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.


Table 77. Page 0/Register 70: PGA_R to HPRCOM Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_R Output Routing Control0: PGA_R is not routed to HPRCOM.1: PGA_R is routed to HPRCOM.

D6–D0 R/W 000 0000 PGA_R to HPRCOM Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 78. Page 0/Register 71: DAC_R1 to HPRCOM Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_R1 Output Routing Control0: DAC_R1 is not routed to HPRCOM.1: DAC_R1 is routed to HPRCOM.

D6–D0 R/W 000 0000 DAC_R1 to HPRCOM Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 79. Page 0/Register 72: HPRCOM Output Level Control RegisterBIT TYPE RESET DESCRIPTION

D7–D4 R/W 0000

HPRCOM Output Level Control0000: Output level control = 0 dB0001: Output level control = 1 dB0010: Output level control = 2 dB...1000: Output level control = 8 dB1001: Output level control = 9 dB1010–1111: Reserved. Do not write these sequences to these register bits.

D3 R/W 0HPRCOM Mute0: HPRCOM is muted.1: HPRCOM is not muted.

D2 R/W 1HPRCOM Power-Down Drive Control0: HPRCOM is weakly driven to a common mode when powered down.1: HPRCOM is high-impedance when powered down.

D1 R 1HPRCOM Volume Control Status0: All programmed gains to HPRCOM have been applied.1: Not all programmed gains to HPRCOM have been applied yet.

D0 R/W 0HPRCOM Power Control0: HPRCOM is not fully powered up.1: HPRCOM is fully powered up.


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Table 80. Page 0/Registers 73 to 78: ReservedBIT TYPE RESET DESCRIPTIOND7–D0 R 0000 0000 Reserved. Do not write to these registers.

Table 81. Page 0/Register 79: ReservedBIT TYPE RESET DESCRIPTIOND7–D0 R 0000 0010 Reserved. Do not write to this register.

Table 82. Page 0/Register 80: ReservedBIT TYPE RESET DESCRIPTIOND7–D0 R 0000 0000 Reserved. Do not write to this register.

Table 83. Page 0/Register 81: PGA_L to LEFT_LOP/M Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_L Output Routing Control0: PGA_L is not routed to LEFT_LOP/M.1: PGA_L is routed to LEFT_LOP/M.

D6–D0 R/W 000 0000 PGA_L to LEFT_LOP/M Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 84. Page 0/Register 82: DAC_L1 to LEFT_LOP/M Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_L1 Output Routing Control0: DAC_L1 is not routed to LEFT_LOP/M.1: DAC_L1 is routed to LEFT_LOP/M.

D6–D0 R/W 000 0000 DAC_L1 to LEFT_LOP/M Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.


Table 86. Page 0/Register 84: PGA_R to LEFT_LOP/M Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_R Output Routing Control0: PGA_R is not routed to LEFT_LOP/M.1: PGA_R is routed to LEFT_LOP/M.

D6–D0 R/W 000 0000 PGA_R to LEFT_LOP/M Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 87. Page 0/Register 85: DAC_R1 to LEFT_LOP/M Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_R1 Output Routing Control0: DAC_R1 is not routed to LEFT_LOP/M.1: DAC_R1 is routed to LEFT_LOP/M.

D6–D0 R/W 000 0000 DAC_R1 to LEFT_LOP/M Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 88. Page 0/Register 86: LEFT_LOP/M Output Level Control RegisterBIT TYPE RESET DESCRIPTION

D7–D4 R/W 0000

LEFT_LOP/M Output Level Control0000: Output level control = 0 dB0001: Output level control = 1 dB0010: Output level control = 2 dB...1000: Output level control = 8 dB1001: Output level control = 9 dB1010–1111: Reserved. Do not write these sequences to these register bits.

D3 R/W 0LEFT_LOP/M Mute0: LEFT_LOP/M is muted.1: LEFT_LOP/M is not muted.

D2 R 0 Reserved. Do not write to this register bit.


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Table 88. Page 0/Register 86: LEFT_LOP/M Output Level Control Register (continued)BIT TYPE RESET DESCRIPTION

D1 R 1LEFT_LOP/M Volume Control Status0: All programmed gains to LEFT_LOP/M have been applied.1: Not all programmed gains to LEFT_LOP/M have been applied yet.

D0 R/W 0LEFT_LOP/M Power Status0: LEFT_LOP/M is not fully powered up.1: LEFT_LOP/M is fully powered up.


Table 90. Page 0/Register 88: PGA_L to RIGHT_LOP/M Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_L Output Routing Control0: PGA_L is not routed to RIGHT_LOP/M.1: PGA_L is routed to RIGHT_LOP/M.

D6–D0 R/W 000 0000 PGA_L to RIGHT_LOP/M Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 91. Page 0/Register 89: DAC_L1 to RIGHT_LOP/M Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_L1 Output Routing Control0: DAC_L1 is not routed to RIGHT_LOP/M.1: DAC_L1 is routed to RIGHT_LOP/M.

D6–D0 R/W 000 0000 DAC_L1 to RIGHT_LOP/M Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.


Table 93. Page 0/Register 91: PGA_R to RIGHT_LOP/M Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0PGA_R Output Routing Control0: PGA_R is not routed to RIGHT_LOP/M.1: PGA_R is routed to RIGHT_LOP/M.

D6–D0 R/W 000 0000 PGA_R to RIGHT_LOP/M Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 94. Page 0/Register 92: DAC_R1 to RIGHT_LOP/M Volume Control RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0DAC_R1 Output Routing Control0: DAC_R1 is not routed to RIGHT_LOP/M.1: DAC_R1 is routed to RIGHT_LOP/M.

D6–D0 R/W 000 0000 DAC_R1 to RIGHT_LOP/M Analog Volume ControlFor 7-bit register settings versus analog gain values, see Table 51.

Table 95. Page 0/Register 93: RIGHT_LOP/M Output Level Control RegisterBIT TYPE RESET DESCRIPTION

D7–D4 R/W 0000

RIGHT_LOP/M Output Level Control0000: Output level control = 0 dB0001: Output level control = 1 dB0010: Output level control = 2 dB...1000: Output level control = 8 dB1001: Output level control = 9 dB1010–1111: Reserved. Do not write these sequences to these bits.

D3 R/W 0RIGHT_LOP/M Mute0: RIGHT_LOP/M is muted.1: RIGHT_LOP/M is not muted.

D2 R 0 Reserved. Do not write to this register bit.


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Table 95. Page 0/Register 93: RIGHT_LOP/M Output Level Control Register (continued)BIT TYPE RESET DESCRIPTION

D1 R 1RIGHT_LOP/M Volume Control Status0: All programmed gains to RIGHT_LOP/M have been applied.1: Not all programmed gains to RIGHT_LOP/M have been applied yet.

D0 R/W 0RIGHT_LOP/M Power Status0: RIGHT_LOP/M is not fully powered up.1: RIGHT_LOP/M is fully powered up.

Table 96. Page 0/Register 94: Module Power Status RegisterBIT TYPE RESET DESCRIPTION

D7 R 0Left-DAC Power Status0: Left DAC is not fully powered up.1: Left DAC is fully powered up.

D6 R 0Right-DAC Power Status0: Right DAC is not fully powered up.1: Right DAC is fully powered up.

D5 R 0 Reserved. Write only 0 to this bit.

D4 R 0LEFT_LOP/M Power Status0: LEFT_LOP/M output driver is powered down.1: LEFT_LOP/M output driver is powered up.

D3 R 0RIGHT_LOP/M Power Status0: RIGHT_LOP/M is not fully powered up.1: RIGHT_LOP/M is fully powered up.

D2 R 0HPLOUT Driver Power Status0: HPLOUT Driver is not fully powered up.1: HPLOUT Driver is fully powered up.

D1 R 0HPROUT Driver Power Status0: HPROUT Driver is not fully powered up.1: HPROUT Driver is fully powered up.

D0 R 0 Reserved. Do not write to this bit.

Table 97. Page 0/Register 95: Output Driver Short-Circuit Detection Status RegisterBIT TYPE RESET DESCRIPTION

D7 R 0HPLOUT Short-Circuit Detection Status0: No short circuit detected at HPLOUT1: Short circuit detected at HPLOUT

D6 R 0HPROUT Short-Circuit Detection Status0: No short circuit detected at HPROUT1: Short circuit detected at HPROUT

D5 R 0HPLCOM Short-Circuit Detection Status0: No short circuit detected at HPLCOM1: Short circuit detected at HPLCOM

D4 R 0HPRCOM Short-Circuit Detection Status0: No short circuit detected at HPRCOM1: Short circuit detected at HPRCOM

D3 R 0HPLCOM Power Status0: HPLCOM is not fully powered up.1: HPLCOM is fully powered up.

D2 R 0HPRCOM Power Status0: HPRCOM is not fully powered up.1: HPRCOM is fully powered up.

D1–D0 R 00 Reserved. Do not write to these bits.

Table 98. Page 0/Register 96: Sticky Interrupt Flags RegisterBIT TYPE RESET DESCRIPTION

D7 R 0HPLOUT Short-Circuit Detection Status0: No short circuit detected at HPLOUT driver1: Short circuit detected at HPLOUT driver

D6 R 0HPROUT Short-Circuit Detection Status0: No short circuit detected at HPROUT driver1: Short circuit detected at HPROUT driver


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Table 98. Page 0/Register 96: Sticky Interrupt Flags Register (continued)BIT TYPE RESET DESCRIPTION

D5 R 0HPLCOM Short-Circuit Detection Status0: No short circuit detected at HPLCOM driver1: Short circuit detected at HPLCOM driver

D4 R 0HPRCOM Short-Circuit Detection Status0: No short circuit detected at HPRCOM driver1: Short circuit detected at HPRCOM driver


D2 R 0Headset Detection Status0: No headset insertion/removal is detected.1: Headset insertion/removal is detected.

D1 R 0Left ADC AGC Noise Gate Status0: Left ADC signal power is greater than or equal to noise threshold for left AGC.1: Left ADC signal power is less than noise threshold for left AGC.

D0 R 0Right ADC AGC Noise Gate Status0: Right ADC signal power is greater than or equal to noise threshold for right AGC.1: Right ADC signal power is less than noise threshold for right AGC.

Table 99. Page 0/Register 97: Real-Time Interrupt Flags RegisterBIT TYPE RESET DESCRIPTION

D7 R 0HPLOUT Short-Circuit Detection Status0: No short circuit detected at HPLOUT driver1: Short circuit detected at HPLOUT driver

D6 R 0HPROUT Short-Circuit Detection Status0: No short circuit detected at HPROUT driver1: Short circuit detected at HPROUT driver

D5 R 0HPLCOM Short-Circuit Detection Status0: No short circuit detected at HPLCOM driver1: Short circuit detected at HPLCOM driver

D4 R 0HPRCOM Short-Circuit Detection Status0: No short circuit detected at HPRCOM driver1: Short circuit detected at HPRCOM driver


D2 R 0Headset Detection Status0: No headset insertion/removal is detected.1: Headset insertion/removal is detected.

D1 R 0Left ADC AGC Noise Gate Status0: Left ADC signal power is greater than noise threshold for left AGC.1: Left ADC signal power lower than noise threshold for left AGC.

D0 R 0Right ADC AGC Noise Gate Status0: Right ADC signal power is greater than noise threshold for right AGC.1: Right ADC signal power is lower than noise threshold for right AGC.

Table 100. Page 0/Register 98 to 100: Reserved RegistersBIT TYPE RESET DESCRIPTIOND7–D0 R 0000 0000 Reserved. Do not write to these registers.

(1) Bits D7 to D1 in register 101 are only valid in I2C control mode, when SELECT = 0.

Table 101. Page 0/Register 101: Clock RegisterBIT TYPE RESET DESCRIPTIOND7–D1 R 0000 000 Reserved. Write only zeros to these bits. (1)

D0 R/W 0CODEC_CLKIN Source Selection0: CODEC_CLKIN uses PLLDIV_OUT1: CODEC_CLKIN uses CLKDIV_OUT


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Table 102. Page 0/Register 102: Clock Generation Control RegisterBIT TYPE RESET DESCRIPTION

D7–D6 R/W 00

CLKDIV_IN Source Selection00: CLKDIV_IN uses MCLK.01: CLKDIV_IN uses GPIO2.10: CLKDIV_IN uses BCLK.11: Reserved. Do not use.

D5–D4 R/W 00

PLLCLK_IN Source Selection00: PLLCLK_IN uses MCLK.01: PLLCLK_IN uses GPIO2.10: PLLCLK _IN uses BCLK.11: Reserved. Do not use.

D3–D0 R/W 0010 Reserved. Write only 0010 to these bits.

Table 103. Page 0/Register 103: Left-AGC New Programmable Attack Time RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0Attack Time Register Selection0: Attack time for the left AGC is generated from page 0, register 26.1: Attack time for the left AGC is generated from this register.

D6–D5 R/W 00

Baseline AGC Attack time00: Left-AGC attack time = 7 ms01: Left-AGC attack time = 8 ms10: Left-AGC attack time = 10 ms11: Left-AGC attack time = 11 ms

D4–D2 R/W 000

Multiplication Factor for Baseline AGC000: Multiplication factor for the baseline AGC attack time = 1001: Multiplication factor for the baseline AGC attack time = 2010: Multiplication factor for the baseline AGC attack time = 4011: Multiplication factor for the baseline AGC attack time = 8100: Multiplication factor for the baseline AGC attack time = 16101: Multiplication factor for the baseline AGC attack time = 32110: Multiplication factor for the baseline AGC attack time = 64111: Multiplication factor for the baseline AGC attack time = 128


(1) Decay time is limited based on NCODEC ratio that is selected. ForNCODEC = 1, Maximum decay time = 4 sNCODEC = 1.5, Maximum decay time = 5.6 sNCODEC = 2, Maximum decay time = 8 sNCODEC = 2.5, Maximum decay time = 9.6 sNCODEC = 3 or 3.5, Maximum decay time = 11.2 sNCODEC = 4 or 4.5, Maximum decay time = 16 sNCODEC = 5, Maximum decay time = 19.2 sNCODEC = 5.5 or 6, Maximum decay time = 22.4 s

Table 104. Page 0/Register 104: Left-AGC New Programmable Decay Time RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0Decay Time Register Selection (1)

0: Decay time for the left AGC is generated from page 0, register 26.1: Decay time for the left AGC is generated from this register.

D6–D5 R/W 00

Baseline AGC Decay Time00: Left-AGC decay time = 50 ms01: Left-AGC decay time = 150 ms10: Left-AGC decay time = 250 ms11: Left-AGC decay time = 350 ms

D4–D2 R/W 000

Multiplication Factor for Baseline AGC000: Multiplication factor for the baseline AGC decay time = 1001: Multiplication factor for the baseline AGC decay time = 2010: Multiplication factor for the baseline AGC decay time = 4011: Multiplication factor for the baseline AGC decay time = 8100: Multiplication factor for the baseline AGC decay time = 16101: Multiplication factor for the baseline AGC decay time = 32110: Multiplication factor for the baseline AGC decay time = 64111: Multiplication factor for the baseline AGC decay time = 128



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Table 105. Page 0/Register 105: Right-AGC New Programmable Attack Time RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0Attack Time Register Selection0: Attack time for the right AGC is generated from page 0, register 29.1: Attack time for the right AGC is generated from this register.

D6–D5 R/W 00

Baseline AGC attack time00: Right-AGC attack time = 7 ms01: Right-AGC attack time = 8 ms10: Right-AGC attack time = 10 ms11: Right-AGC attack time = 11 ms

D4–D2 R/W 000

Multiplication Factor for Baseline AGC000: Multiplication factor for the baseline AGC attack time = 1001: Multiplication factor for the baseline AGC attack time = 2010: Multiplication factor for the baseline AGC attack time = 4011: Multiplication factor for the baseline AGC attack time = 8100: Multiplication factor for the baseline AGC attack time = 16101: Multiplication factor for the baseline AGC attack time = 32110: Multiplication factor for the baseline AGC attack time = 64111: Multiplication factor for the baseline AGC attack time = 128


(1) Decay time is limited based on NCODEC ratio that is selected. ForNCODEC = 1, Maximum decay time = 4 secondsNCODEC = 1.5, Maximum decay time = 5.6 secondsNCODEC = 2, Maximum decay time = 8 secondsNCODEC = 2.5, Maximum decay time = 9.6 secondsNCODEC = 3 or 3.5, Maximum decay time = 11.2 secondsNCODEC = 4 or 4.5, Maximum decay time = 16 secondsNCODEC = 5, Maximum decay time = 19.2 secondsNCODEC = 5.5 or 6, Maximum decay time = 22.4 seconds

Table 106. Page 0/Register 106: Right-AGC New Programmable Decay Time RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0Decay Time Register Selection (1)

0: Decay time for the right AGC is generated from page 0, register 29.1: Decay time for the right AGC is generated from this register.

D6–D5 R/W 00

Baseline AGC Decay Time00: Right-AGC decay time = 50 ms01: Right-AGC decay time = 150 ms10: Right-AGC decay time = 250 ms11: Right-AGC decay time = 350 ms

D4–D2 R/W 000

Multiplication Factor for Baseline AGC000: Multiplication factor for the baseline AGC decay time = 1001: Multiplication factor for the baseline AGC decay time = 2010: Multiplication factor for the baseline AGC decay time = 4011: Multiplication factor for the baseline AGC decay time = 8100: Multiplication factor for the baseline AGC decay time = 16101: Multiplication factor for the baseline AGC decay time = 32110: Multiplication factor for the baseline AGC decay time = 64111: Multiplication factor for the baseline AGC decay time = 128


Table 107. Page 0/Register 107: New Programmable ADC Digital Path and I2C Bus Condition RegisterBIT TYPE RESET DESCRIPTION

D7 R/W 0Left-Channel High-Pass Filter Coefficient Selection0: Default coefficients are used when ADC high pass is enabled.1: Programmable coefficients are used when ADC high pass is enabled.

D6 R/W 0Right-Channel High-Pass Filter Coefficient Selection0: Default coefficients are used when ADC high pass is enabled.1: Programmable coefficients are used when ADC high pass is enabled.

D5–D4 R/W 00

ADC Decimation Filter Configuration00: Left and right digital microphones are used.01: Left digital microphone and right analog microphone are used.10: Left analog microphone and right digital microphone are used.11: Left and right analog microphones are used.


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Table 107. Page 0/Register 107: New Programmable ADC Digital Path and I2C Bus ConditionRegister (continued)

BIT TYPE RESET DESCRIPTION

D3 R/W 0ADC Digital Output to Programmable Filter Path Selection0: No additional programmable filters other than the HPF are used for the ADC.1: The programmable filter is connected to ADC output, if both DACs are powered down.

D2 R/W 0I2C Bus Condition Detector0: Internal logic is enabled to detect an I2C bus error, and clears the bus error condition.1: Internal logic is disabled to detect an I2C bus error.

D1 R 0 Reserved. Write only zero to these register bits.

D0 R 0I2C Bus Error Detection Status0: I2C bus error is not detected.1: I2C bus error is detected. This bit is cleared by reading this register.

Table 108. Page 0/Register 108: Passive Analog Signal Bypass Selection During Power Down RegisterBIT TYPE RESET DESCRIPTIOND7 R/W 0 Reserved. Write only zero to this bit.D6 R 0 Reserved. Write only zero to these register bits.

D5 R/W 0LINE1RM Path Selection0: Normal signal path1: Signal is routed by a switch to RIGHT_LOM.

D4 R/W 0LINE1RP Path Selection0: Normal signal path1: Signal is routed by a switch to RIGHT_LOP.

D3 R/W 0 Reserved. Write only zero to this bit.D2 R 0 Reserved. Write only zero to these register bits.

D1 R/W 0LINE1LM Path Selection0: Normal signal path1: Signal is routed by a switch to LEFT_LOM.

D0 R/W 0LINE1LP Path Selection0: Normal signal path1: Signal is routed by a switch to LEFT_LOP.

Based on the register 108 settings, if BOTH LINE1 and LINE2 inputs are routed to the output at the same time,then the two switches used for the connection short the two input signals together on the output pins. Theshorting resistance between the two input pins is two times the bypass switch resistance (RDS(ON)). In general,this condition of shorting should be avoided, as higher drive currents are likely to occur on the circuitry that feedsthese two input pins of this device.

Table 109. Page 0/Register 109: DAC Quiescent Current Adjustment RegisterBIT TYPE RESET DESCRIPTION

D7–D6 R/W 00

DAC Current Adjustment00: Default01: 50% increase in DAC reference current10: Reserved11: 100% increase in DAC reference current

D5–D0 R/W 00 0000 Reserved. Write only zeros to these bits.


Table 111. Page 1/Register 0: Page Select RegisterBIT TYPE RESET DESCRIPTIOND7–D1 X 0000 000 Reserved, write only zeros to these bits.

D0 R/W 0

Page Select BitWriting zero to this bit sets page 0 as the active page for following register accesses. Writing a one tothis bit sets page 1 as the active page for following register accesses. It is recommended that the userread this register bit back after each write, to ensure that the proper page is being accessed for futureregister read/writes. This register has the same functionality on page 0 and page 1.


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SPACE

NOTEWhen programming any coefficient value in Page 1, the MSB register should always bewritten first, immediately followed by the LSB register. Even if only the MSB or LSB of thecoefficient changes, both registers should be written in this sequence.

Table 112. Page 1/Register 1: Left-Channel Audio Effects Filter N0 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0110 1011Left-Channel Audio Effects Filter N0 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 113. Page 1/Register 2: Left-Channel Audio Effects Filter N0 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 1110 0011Left-Channel Audio Effects Filter N0 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.
















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Table 124. Page 1/Register 13: Left-Channel Audio Effects Filter D1 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0111 1101Left-Channel Audio Effects Filter D1 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 125. Page 1/Register 14: Left-Channel Audio Effects Filter D1 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 1000 0011Left-Channel Audio Effects Filter D1 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.












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Table 132. Page 1/Register 21: Left-Channel De-Emphasis Filter N0 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0011 1001Left-Channel De-Emphasis Filter N0 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 133. Page 1/Register 22: Left-Channel De-Emphasis Filter N0 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0101 0101Left-Channel De-Emphasis Filter N0 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 134. Page 1/Register 23: Left-Channel De-Emphasis Filter N1 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 1111 0011Left-Channel De-Emphasis Filter N1 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 135. Page 1/Register 24: Left-Channel De-Emphasis Filter N1 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0010 1101Left-Channel De-Emphasis Filter N1 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 136. Page 1/Register 25: Left-Channel De-Emphasis Filter D1 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0101 0011Left-Channel De-Emphasis Filter D1 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 137. Page 1/Register 26: Left-Channel De-Emphasis Filter D1 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0111 1110Left-Channel De-Emphasis Filter D1 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 138. Page 1/Register 27: Right-Channel Audio Effects Filter N0 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0110 1011Right-Channel Audio Effects Filter N0 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 139. Page 1/Register 28: Right-Channel Audio Effects Filter N0 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 1110 0011Right-Channel Audio Effects Filter N0 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.




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Table 150. Page 1/Register 39: Right-Channel Audio Effects Filter D1 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0111 1101Right-Channel Audio Effects Filter D1 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.


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Table 151. Page 1/Register 40: Right-Channel Audio Effects Filter D1 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 1000 0011Right-Channel Audio Effects Filter D1 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.













Table 158. Page 1/Register 47: Right-Channel De-Emphasis Filter N0 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0011 1001Right-Channel De-Emphasis Filter N0 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 159. Page 1/Register 48: Right-Channel De-Emphasis Filter N0 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0101 0101Right-Channel De-Emphasis Filter N0 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 160. Page 1/Register 49: Right-Channel De-Emphasis Filter N1 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 1111 0011Right-Channel De-Emphasis Filter N1 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.


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Table 161. Page 1/Register 50: Right-Channel De-Emphasis Filter N1 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0010 1101Right-Channel De-Emphasis Filter N1 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 162. Page 1/Register 51: Right-Channel De-Emphasis Filter D1 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0101 0011Right-Channel De-Emphasis Filter D1 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 163. Page 1/Register 52: Right-Channel De-Emphasis Filter D1 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0111 1110Right-Channel De-Emphasis Filter D1 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 164. Page 1/Register 53: 3-D Attenuation Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0111 11113-D Attenuation Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 165. Page 1/Register 54: 3-D Attenuation Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 1111 11113-D Attenuation Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.


Table 167. Page 1/Register 65: Left-Channel ADC High-Pass Filter N0 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0011 1001Left-Channel ADC High-Pass Filter N0 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 168. Page 1/Register 66: Left-Channel ADC High-Pass Filter N0 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0101 0101Left-Channel ADC High-Pass Filter N0 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 169. Page 1/Register 67: Left-Channel ADC High-Pass Filter N1 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 1111 0011Left-Channel ADC High-Pass Filter N1 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 170. Page 1/Register 68: Left-Channel ADC High-Pass Filter N1 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0010 1101Left-Channel ADC High-Pass Filter N1 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 171. Page 1/Register 69: Left-Channel ADC High-Pass Filter D1 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0101 0011Left-Channel ADC High-Pass Filter D1 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.


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74




Table 172. Page 1/Register 70: Left-Channel ADC High-Pass Filter D1 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0111 1110Left-Channel ADC High-Pass Filter D1 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 173. Page 1/Register 71: Right-Channel ADC High-Pass Filter N0 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0011 1001Right-Channel ADC High-Pass Filter N0 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 174. Page 1/Register 72: Right-Channel ADC High-Pass Filter N0 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0101 0101Right-Channel ADC High-Pass Filter N0 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 175. Page 1/Register 73: Right-Channel ADC High-Pass Filter N1 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 1111 0011Right-Channel ADC High-Pass Filter N1 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 176. Page 1/Register 74: Right-Channel ADC High-Pass Filter N1 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0010 1101Right-Channel ADC High-Pass Filter N1 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 177. Page 1/Register 75: Right-Channel ADC High-Pass Filter D1 Coefficient MSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0101 0011Right-Channel ADC High-Pass Filter D1 Coefficient MSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 178. Page 1/Register 76: Right-Channel ADC High-Pass Filter D1 Coefficient LSB RegisterBIT TYPE RESET DESCRIPTION

D7–D0 R/W 0111 1110Right-Channel ADC High-Pass Filter D1 Coefficient LSBThe 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a2s‑complement integer, with possible values ranging from –32,768 to 32,767.

Table 179. Page 1/Registers 77 to 127: Reserved RegistersBIT TYPE RESET DESCRIPTIOND7–D0 R 0000 0000 Reserved. Do not write to these registers.


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TLV320AIC3104-Q1

MIC2L/LINE2L

MIC1LP/LINE1LP

MIC1RP/LINE1RP

MIC2R/LINE2R

MIC1LM/LINE1LM

0.1 Fµ

0.1 Fµ

0.47 Fµ

0.47 Fµ

0.1 Fµ

0.1 Fµ

0.1 Fµ

0.1 Fµ

0.1 Fµ

1 Fµ

1 Fµ

1 Fµ

1 Fµ 1F

µ10 Fµ

MICBIAS

A

AVDD_DAC

AVSS_DAC

AVSS_ADC

DRVDD

DVDD

DVSS

IOVDD

DRVDD

DRVSS

A

D

1.525 V–1.95 V

LE

FT

_L

OP

LE

FT

_L

OM

RIG

HT

_R

OP

RIG

HT

_R

OM

HP

LC

OM

HP

LO

UT

HP

RO

UT

A

HP

RC

OM

MIC1RM/LINE1RM

SD

A

SC

L

IOVDD

RE

SE

T

MC

LK

BC

LK

WC

LK

DO

UT

DIN

DSPor

Apps ProcessorRP

RP

1 kΩ

1 kΩ

RadioTuner

IOVDD(1.1 V–3.3 V)

AVDD(2.7 V–3.6 V)

8 Ω

8 Ω

External Audio Power AmplifiersTPA6211A1-Q1 (Mono Class-AB in MSOP)TPA3111D1-Q1 (Mono Class-D in PWP)TPA3110D2-Q1 (Stereo Class-D in PWP)

0.1 Fµ

0.1 Fµ1 kΩA

TPA2005D1-Q1 (Mono Class-D in SON, MSOP)

1 kΩ

75




10 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

10.1 Application InformationThe TLV320AIC3104-Q1 is a highly integrated low-power stereo audio codec with integrated stereoheadphone/line amplifier, as well as multiple inputs and outputs that are programmable in single-ended or fullydifferential configurations. All the features of the TLV320AIC3104-Q1 are accessed by programmable registers.External processor with I2C protocol is required to control the device. It is good practice to perform a hardwarereset after initial power up to ensure that all registers are in their default states. Extensive register-based powercontrol is included, enabling stereo 48-kHz DAC playback as low as 14 mW from a 3.3-V analog supply, makingit ideal for various car audio applications such as cluster, telematics, emergency call (eCall), navigation systems,and head units.

10.2 Typical Applications

10.2.1 External Speaker Driver in Infotainment and Cluster Applications

Figure 32. Typical Connections With Differential Inputs for External Speaker Driver


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Input = −65 dBFS

Sig

nal-to

-Nois

e R

atio (

dB

)

24

26

28

30

32

34

36

38

40

42

PGA Gain Setting (dB)

0 10 20 30 40 50 60

Am

plit

ude (

dB

)

−160

−140

−120

−100

−80

−60

−40

−20

0

Frequency (kHz)

0 2 4 6 8 10 12 14 16 18 20

Am

plit

ude (

dB

)

−160

−140

−120

−100

−80

−60

−40

−20

0

Frequency (kHz)

0 2 4 6 8 10 12 14 16 18 20

76




Typical Applications (continued)10.2.1.1 Design RequirementsFor this design example, use the parameters shown in Table 180.

Table 180. Design ParametersPARAMETER VALUE

Supply Voltage (AVDD, DRVDD) 3.3 VSupply Voltage (DVDD, IOVDD) 1.8 VAnalog Fully Differential Line Output Driver Load 10 kΩ

10.2.1.2 Detailed Design Procedure• Use Figure 32 as a guide to integrate the hardware into the system.• Following the recommended component placement, schematic layout and routing given in Figure 38,

integrate the device and its supporting components into the system PCB file.• Determining sample rate and master clock frequency is required when powering up the device because all

internal timing is derived from the master clock. Refer to the Audio Clock Generation section to obtain moreinformation on how to configure correctly the required clocks for the device.

• As the TLV320AIC3104-Q1 is designed for low-power applications, when powered up, the device has severalfeatures powered down. A correct routing of the TLV320AIC3104-Q1 signals is achieved by a correct settingof the device registers, powering up the required stages of the device and configuring the internal switches tofollow a desired route.

10.2.1.3 Application Curves

Figure 33. DAC to Line Output FFT at 1-kHz Signal Plot Figure 34. Line Input to ADC FFT at 1-kHz Signal Plot

Figure 35. ADC SNR vs PGA Gain Setting, –65-dBfs Input


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TLV320AIC3104-Q1

MIC2L/LINE2L

MIC1LP/LINE1LP

MIC1RP/LINE1RP

MIC2R/LINE2R

MIC1LM/LINE1LM

0.1 Fµ

0.1 Fµ

0.1 Fµ

0.1 Fµ

0.47 Fµ

0.47 Fµ

0.1 Fµ

0.1 Fµ

0.1 Fµ

0.1 Fµ

0.1 Fµ

1 Fµ

1 Fµ

1 Fµ

1 Fµ 1F

µ

10 Fµ

MICBIAS

A

A

AVDD_DAC

AVSS_DAC

AVSS_ADC

DRVDD

DVDD

DVSS

IOVDD

DRVDD

DRVSS

A

D

1.525 V–1.95 V

LE

FT

_L

OP

LE

FT

_L

OM

RIG

HT

_R

OP

RIG

HT

_R

OM

HP

LC

OM

HP

LO

UT

HP

RO

UT

A

HP

RC

OM

MIC1RM/LINE1RMS

DA

SC

L

IOVDD

RE

SE

T

MC

LK

BC

LK

WC

LK

DO

UT

DIN

DSPor

Apps ProcessorRP

RP

1 kΩ1 kΩ

1 kΩ

1 kΩ

RadioTuner

IOVDD(1.1 V–3.3 V)

AVDD(2.7 V–3.6 V)

8 Ω

8 Ω

External Audio Power AmplifiersTPA6211A1-Q1 (Mono Class-AB in MSOP)TPA3111D1-Q1 (Mono Class-D in PWP)TPA3110D2-Q1 (Stereo Class-D in PWP)

LINE_OUT_R–

LINE_OUT_R+

LINE_OUT_L–

LINE_OUT_L+

TPA2005D1-Q1 (Mono Class-D in SON, MSOP)

77




10.2.2 External Speaker Amplifier With Separate Line Outputs

Figure 36. Typical Connections With Single-Ended Outputs for External AmplifierWith Separate Line Outputs


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IOVDD

AVDD, DRVDD

DVDD

t1

t 2

t3

78




10.2.2.1 Design RequirementsRefer to the previous Design Requirements section.

10.2.2.2 Detailed Design ProcedureRefer to the previous Detailed Design Procedure section.

11 Power Supply RecommendationsThe TLV320AIC3104-Q1 has been designed to be extremely tolerant of power supply sequencing. However, insome rare instances, unexpected conditions can be attributed to power supply sequencing. The followingsequence will provide the most robust operation.

Power up IOVDD first. The analog supplies, which include AVDD and DRVDD, should be powered up second.The digital supply DVDD should be powered up last. Keep RESET low until all supplies are stable. The analogsupplies should be greater than or equal to DVDD at all times.

Figure 37. Power Supply Sequencing

Table 181. Power Supply SequencingPARAMETER MIN MAX UNIT

t1 IOVDD to AVDD, DRVDD 0mst2 AVDD to DVDD 0 5

t3 IOVDD, to DVDD 0

12 Layout

12.1 Layout GuidelinesPCB design is made considering the application, and the review is specific for each system requirements.However, general considerations can optimize the system performance.• The TLV320AIC3104-Q1 thermal pad should be connected to analog output driver ground.• Analog and digital grounds should be separated to prevent possible digital noise from affecting the analog

performance of the board.• The TLV320AIC3104-Q1 requires the decoupling capacitors to be placed as close as possible to the device

power supply terminals.• If possible, route the differential audio signals differentially on the PCB. This is recommended to get better

noise immunity.


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-Q1

79




12.2 Layout Example

Figure 38. Layout Example


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80




13 Device and Documentation Support

13.1 Device Support

13.1.1 Device NomenclatureTarget level Represents the nominal output level at which the AGC attempts to hold the ADC output signal level.

Attack time Determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud.It can be varied from 7 ms to 1,408 ms.

Decay time Determines how quickly the PGA gain is increased when the input signal is too low.It can be varied in the range from 0.05 s to 22.4 s.

Noise gate threshold Determines the level at which the input speech average falls below.

Maximum PGA gain applicable Allows the user to restrict the maximum PGA gain that can be applied by theAGC algorithm.

13.2 Documentation Support

13.2.1 Related DocumentationFor related documentation see the following:• TIDA-00724 Automotive Emergency Call (eCall) Audio Subsystem Reference Design• TPA3111D1-Q1 10-W Filter-Free Mono Class-D Audio Power Amplifier With SpeakerGuard™• TPA3110D2-Q1 15-W Filter-Free Stereo Class D Audio Power Amplifier with SpeakerGuard™• TPA6211A1-Q1 3.1-W Mono Fully Differential Audio Power Amplifier• TPA2005D1-Q1 1.4-W Mono Filter-Free Class-D Audio Power Amplifier

13.3 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

13.4 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

13.5 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

13.6 Electrostatic Discharge CautionThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.


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13.7 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.


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PACKAGE OPTION ADDENDUM

www.ti.com 18-Jan-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

6PAIC3104IRHBRQ1 ACTIVE VQFN RHB 32 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 3104I

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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PACKAGE OPTION ADDENDUM


Addendum-Page 2

OTHER QUALIFIED VERSIONS OF TLV320AIC3104-Q1 :

• Catalog: TLV320AIC3104

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

6PAIC3104IRHBRQ1 VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

6PAIC3104IRHBRQ1 VQFN RHB 32 3000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 2

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IMPORTANT NOTICE

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