timing pulse shift register a shift register bsystembus.com/lecture/architecture/chapter5.pdf ·...

1997 by Prentice-Hall, Inc.LOGIC AND COMPUTER DESIGN FUNDAMENTALS Simon & Schuster / A Viacom CompanyMano & Kime Upper Saddle River, New Jersey 07458

T-103

Timingpulse Shift Register A Shift Register B

Initial valueAfter T1After T2After T3After T4

10000

01000

10100

11010

01101

00110

10011

01001

Serial Transfer Example


T-104

Upward Counting Sequence Downward Counting Sequence

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

0000000011111111

0000111100001111

0011001100110011

0101010101010101

1111111100000000

1111000011110000

1100110011001100

1010101010101010

Counting Sequence of Binary Counter


T-105

Present state

Nextstate Flip-flop inputs

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 JQ3 KQ3 JQ2 KQ2 JQ1 KQ1 JQ0 KQ0

0000000011111111

0000111100001111

0011001100110011

0101010101010101

0000000111111110

0001111000011110

0110011001100110

1010101010101010

00000001

00000001

0001

0001

0001

0001

01

01

01

01

01

01

01

01

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

State Table and Flip-Flop Inputs for Binary Counter


T-106

Present State Next State Output Flip-Flop Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Y TQ8 TQ4 TQ2 TQ1

0000000011

0000111100

0011001100

0101010101

0000000110

0001111000

0110011000

1010101010

0000000001

0000000101

0001000100

0101010100

1111111111

State Table and Flip-Flop Inputs for BCD Counter


T-107

PresentState Next State Flip-Flop Inputs

A B C A B C JA KA JB KB JC KC

000111

001001

010010

001110

010010

100100

001333

333001

013013

331331

130130

313313

State Table and Flip-Flop Inputs for Binary Counter

1997 by Prentice-Hall, Inc.LOGIC AND COMPUTER DESIGN FUNDAMENTALS Simon & Schuster / A Viacom CompanyMANO & KIME Upper Saddle River, New Jersey 07458

T-108

•

•

•

D

C

R

•D

C

R

•D

C

R

•D

C

R

•

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Clock

Clear

•

•

•

(a) Logic diagram

Clock

(d) Timing diagram

Load

C inputs

• C inputs (clock inputsof flip-flops)

(c) Load control input

LoadClock

(b) Symbol

REG

Clear

D0

•Q0

D2 Q2

D3 Q3

D1 Q1

4-Bit Register


T-109

•

Load

D0

D1

D2

D3

Clock

Q0

Q1

Q2

Q3

•

•

•

•

•

•

•

•

•

D

C

D

C

D

C

D

C

•

•

•

•

•

4-Bit Register with Parallel Load


T-110

(b) Symbol

Sl

SRG 4Clock

SO

(a) Logic diagram

D

C

Serialinput SI

Clock

D

C

D

C

D

C

Serialinput S0

• • •

4-Bit Shift Register


T-111

(a) Block diagram

(b) Timing diagram

T1 T2 T3 T4

Clock

Shift

C Input

Sl

C

Register A

SO0

SRG 4

Sl

C

Register B

SO

SRG 4

ShiftClock ••

Serial Transfer


T-112

Reset

Reset

Reset

•

Sl

Register A

SO

SRG 4

•

•

FA

X

Y

Z

S

C

Full Adder(Figure 3-26)

Carry

C

D

R

•

Sl

Clear

Register B

SO

SRG 4

Shift

Clock

Serialinput

•

•

Clear

C

C

Serial Addition


T-113

•

•D

C

D

C

D

C

D

C

(b) Symbol

SHR 4

Shift

Load

Sl

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Shift

Load

Serialinput

D0

•

••

•

•

•

•

•

••

•

•

•

•

•

•

••

•

•

•

•

•

•

D1

D2

D3

Clock

Q0

Q1

Q2

Q3

•

•

•

•

Shift Register with Parallel Load


T-114

D

C

D

C

D

C

(b) Symbol

SHR 4

S1

S0

LSI

D0

D1

D2

D3

Q0

Q1

Q2

Q3

RSI

Mode S1

Mode S0

Left serial input

Right serial input

Clock

•

•

•

•

•

S1

S0

Di

MUX

S1

S0

0

1

2

3

Clock

Qi – 1

Qi

Qi + 1

(a) Logic diagram of one typical stage

Bidirectional Shift Register with Parallel Load


T-115

J

C

KR

J

C

KR

J

C

KR

J

C

KR

Clock pulses

Logic 1

Q0

Q1

Q2

Q3

•

•

••

•

•

•

•

•

•

•

•

•Clear

•

•

•

•

•

•

•

•

4-Bit Ripple Counter


T-116

KQ3 = Q0Q1Q2

1

X XX X

X XX X00

01

00 01Q1Q0

Q3Q2

Q1

Q0

Q3

11 10

11

10

Q2

1

X XX X

JQ3 = Q0Q1Q2

X XX X

KQ2 = Q0Q1JQ2 = Q0Q1

KQ1 = Q0JQ1 = Q0

1

X XX X

X XX X

1

1

XX

XX

X X

X X

1

1

1

1

X X

X X

1

X XX X

X XX X

1

XX

XX

1

1

1

Maps for Input Equations of a Binary Counter


T-117

J

C

K

J

C

K

J

C

K

J

C

KCount enable EN

Clock

Carryoutput CO

Q0

Q1

Q2

Q3

• •

••

•

•

•

•

••

•

•

••

(b) Symbol

CTR 4

EN•Q1

Q2

Q3

CO

Q0

(a) Logic diagram

•

4-Bit Synchronous Binary Counter


T-118

EN •

••

••

•

• • • •

Q0

Q1

C1

Q2

C2

C3

CO

Q3

(b) Parallel gating

D

C

D

C

D

C

D

C

•

•

•

•

•

•

•

•

•

•

•

•

•

•

Count enable EN

Clock

Carryoutput CO

Q0

Q1

Q2

Q3

(a) Serial gating

•

4-Bit Binary Counter with D Flip-Flops


T-119

•

•

•

•

•

J

C

K

J

C

K

J

C

K

J

C

K

Count

Load

D0

D1

D2

D3

Q0

Q1

Q2

Q3

CarryOutput CO

•

••

•

•

•

•

••

•

•

•

•

•

•

•

••

•

•

•

•

•

(b) Symbol

CTR 4

Load

Count

D0

D1

D2

D3

Q0

Q1

Q2

Q3

CO

Clock

(a) Logic diagram

•

•

•

•

4-Bit Binary Counter with Parallel Load


T-120

CTR 4

Load

Count

D0

D1

D2

D3

Q0

Q1

Q2

Q3

CO

Clock

1

(Logic 0)

Q0

Q1

Q2

Q3

•

••

BCD Counter


T-121

(b) State diagram

111

001 110

010 101

100 011

000

(a) Logic diagram

•Clock

JC

K JC

KJC

K

•

•

• •

•

A B C

Logic-1

•

Counter with Arbitrary Count


T-122

(a) 4-bit register

1D

R

C1

(b) 4-bit register with parallel load

1, 2D

M1 [Load]

C2

Standard Graphics Symbols for Registers


T-123

SRG4

M1M2

C3/1

ShiftLoadClock

Serial input

D0

D1

D2

D3

1, 3DQ0

Q1

Q2

Q3

1, 2, 3D

1, 2, 3D

Graphic Symbol for Shift Register with Parallel Load


T-124

Outputcarry

Count

Load

Clock

D0

D1

D2

D3

CTR DIV 16

M1

M2

C4/2, 3 +

Q0

Q1

Q2

Q3

1, 4D [1]

[2]

[4]

[8]

M3

3CT = 15

Graphic Symbol for a 4-Bit Binary Counter with Parallel Load

timing pulse shift register a shift register bsystembus.com/lecture/architecture/chapter5.pdf ·...

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