time and statistical information utilization in sar adcs jon guerber december 4, 2012 1 advisor: dr....
TRANSCRIPT
Time and Statistical Information Utilization in SAR ADCs
Jon Guerber December 4, 2012
1
Advisor: Dr. Un-Ku MoonSchool of Electrical Engineering and
Computer ScienceOregon State University, Corvallis, OR
Oregon State UniveristyMixed Signal Design
10110
SAR ADC Outline
• ADC Motivation• MCS and EMCS Structures• The Ternary SAR (TSAR)• Residue Shaping• The Feedback Initialized TSAR• Conclusions
2
SAR ADC Outline
• ADC Motivation– Power Aware ADCs– SAR ADC Benefits
• MCS and EMCS Structures• The Ternary SAR (TSAR)• Residue Shaping• The Feedback Initialized TSAR• Conclusions
3
The Need for ADCs
4
• Analog to Digital Conversion– Used when digital processing units require data from analog real-
world sources– Important parameters: accuracy, bandwidth, power, cost, size …
10110
ADC Motivation
• Power Aware ADCs– Power is becoming vital
in portable and medical electronics applications
– Digital computational computations / Joule doubles every 1.5 years [1| Intel 2009]
– ADC samples / Joule doubles every 3.3 years [2| Murmann 2010]
5
• Successive Approximation ADCs – Provide an efficient operation in the 6-14b resolution range with
bandwidths below 100MHz
Signal Bandwidth
4
6
8
10
12
14
16
18
20
22
1kHz 10kHz 100kHz 1MHz 10MHz100MHz 1GHz
Res
olu
tio
n(b
it)
1 W
1mW1 W
1 kWsuper
audio
audio
Telephony
short rangewireless
homeinternet
Inter-connectivity
UWB
MobileBasestation
WirelessLAN
cellphones
video
Signal Bandwidth
4
6
8
10
12
14
16
18
20
22
1kHz 10kHz 100kHz 1MHz 10MHz100MHz 1GHz
Res
olu
tio
n(b
it)
1 W
1mW1 W
1 kWsuper
audio
audio
Telephony
short rangewireless
homeinternet
Inter-connectivity
UWB
MobileBasestation
WirelessLAN
cellphones
video
SAR Motivation
• SAR ADC Design– Based on feedback
subtraction– Single comparator as
quantizer unit– Feedback subtraction
accomplished with passive elements (Caps or Resistors)
• SAR Design Benefits– Low Power: Dynamic, High efficiency– Scalable: Good Small Process node FOM, Small Area– Moderate Speed/Accuracy ( < 100MHz, 6-14 Bits)
Jon Guerber/6
Assume box = 13kg
Is box > 8 kg?
Initial Weight = 8kg
Yes – Add 4 kg
Is box > 12 kg? Yes – Add 2 kg
Is box > 14 kg? No – Sub 1 kg
Box = 13 kg
SAR Motivation
• SAR ADC Design– Based on feedback
subtraction– Single comparator as
quantizer unit– Feedback subtraction
accomplished with passive elements (Caps or Resistors)
• SAR Design Benefits– Low Power: Dynamic, High efficiency– Scalable: Good Small Process node FOM, Small Area– Moderate Speed/Accuracy ( < 100MHz, 6-14 Bits)
SAR
DAC Driver
DAC Driver
Cap DAC
Cap DAC
VIN
DOUT
Jon Guerber/7
SAR ADC Outline
• ADC Motivation• MCS and EMCS Structures
– SAR ADC Operation – Switching Efficiency Optimization
• The Ternary SAR (TSAR)• Residue Shaping• The Feedback Initialized TSAR• Conclusions
8
Merged Capacitor Switching SAR
• Merged Capacitor Switching (MCS) – Sampling reference
is Vcm [1,2]– Differentially
switches DAC – Minimizes switching
power– Maintains virtual
node common mode
C2^(N-3)C2^(N-2)C
VINP
SAR
DACP
VT
DACN
VINN
C2^(N-3)C2^(N-2)C
VCM
VCMVDD
VDD
Jon Guerber/9
MCS Switching Power
• MCS Switching Power– Saves switching
energy over previous structures
– Switching efficiency come from the direct switching behavior of the DAC in each phase
– Beats the efficient of the competing “monotonic” method
10
VIN+-
VCM VCM VCM
VCM VCM VCM
VDD VCM VCM
GND VCM VCM
GND VCM VCM
VDD VCM VCM
VDD VDD VCM
GND GND VCM
VDD GND VCM
GND VDD VCM
GND VDD VCM
VDD GND VCM
GND GND VCM
VDD VDD VCM
EVDD = (½)CVDD²
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C CEVDD = (1/8)CVDD²
EVDD = (5/8)CVDD²
EVDD = (½)CVDD²
EVDD = (5/8)CVDD²
EVDD = (1/8)CVDD²
Φ1 Φ2
Early Reset MCS (EMCS) SAR
• EMCS Switching – Uses different
switching pattern then MCS
– On “10” and “01” transitions, previous DAC cap is reset and current cap is charged oppositely
– In each stage, current cap is charged to original MSB
– Comp output dictates resetting
11
VIN+-
VCM VCM VCM
VCM VCM VCM
VDD VCM VCM
GND VCM VCM
GND VCM VCM
VDD VCM VCM
VDD VDD VCM
GND GND VCM
VCM VDD VCM
VCM GND VCM
VCM GND VCM
VCM VDD VCM
GND GND VCM
VDD VDD VCM
EVDD = (½)CVDD²
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C CEVDD = (1/8)CVDD²
EVDD = (3/8)CVDD²
EVDD = (½)CVDD²
EVDD = (3/8)CVDD²
EVDD = (1/8)CVDD²
Φ1 Φ2
Energy and Linearity Comparison
• MCS vs. EMCS– EMCS has 12.5% lower average switching energy (uniform input)– 18.4% lower with a Gaussian input– Mathematically proven to be lower or equal energy for each code– Static linearity improvements
12
0 1000 2000 3000 4000300
400
500
600
700
800
900
MCSEMCS
Code
En
erg
y P
er
Co
de
Co
nv
. (C
Vd
d²)
0 250 500 750 10000
0.05
0.1
0.15
0.2
0.25
MCS INLEMCS INL
CodeR
MS
INL
(L
SB
s)
SAR Performance Enhancements
• Meaningful SAR Performance Improvements– How can we better
use 3-level DAC?– Are we discarding
any valuable information to find the input magnitude?
13
C2^(N-3)C2^(N-2)C
VINP
SAR
DACP
VT
DACN
VINN
C2^(N-3)C2^(N-2)C
VCM
VCMVDD
VDD
Comparator Delay Variation per Stage
Comparator Transfer Function
1 3 5 7 9 11 13250
300
350
400
450
500
550
SAR Stage (For Fullscale Stage Voltage)
Bu
ffe
red
Co
mp
ara
tor
De
lay
(p
s)
tOUT GV = V exp A - 1 t / τ
Comparator Delay vs. Stage Voltage
• Comparator decision time increases linearly with stage• Comparator delay is an indicator of input magnitude
Jon Guerber/14
SAR ADC Outline• ADC Motivation• MCS and EMCS Structures• The Ternary SAR (TSAR)
– Redundancy, Speed and Power Improvements– Stage Grouping, Skipping, Shaping– Implementation Optimization
• Residue Shaping• The Feedback Initialized TSAR• Conclusions 15
Ternary SAR (TSAR) Architecture
• Ternary SAR (TSAR) uses comparator delay information to create a coarse third level– Middle level is based on input magnitude– DAC operation is skipped for a middle code
16
Vfs/4
-Vfs/4
Vfs
-Vfs
10
01
00
Subtract Vfs/2 From
Input
Add Vfs/2 to Input
Defer Decision to Next Stage
Digital Output
DAC Action
Time Comp = 1
Voltage Comp = 1
Voltage Comp = 0
Time Comp = 0
SAR
DAC Driver
DAC Driver
Cap DAC
Cap DAC
VIN
DOUTTime Comp
Delay
TSAR Redundancy
• TSAR Provides 1.5b/stage redundancy– Tolerates small settling errors, fixes over-range errors– No extra cycles or sub-radix arrays needed– Adds just like conventional 1.5b/stage pipelined ADCs17
Vfs/4
-Vfs/4
Vfs
-Vfs
10
01
00
Subtract Vfs/2 From
Input
Add Vfs/2 to Input
Defer Decision to Next Stage
Digital Output
DAC Action
Time Comp = 1
Voltage Comp = 1
Voltage Comp = 0
Time Comp = 0
X XX X
X XX X
d1
d2
d3
d4
b1 b2 b3 b4 b5
TSAR Speed Enhancements
• Comparison Time Reduced in Coarse Steps– Codes that take longer then Vfs/4 = middle code– Comparator delay per stage is now reduced– Worst case conversion delay shortened
18
Binary SAR
TSAR
Fixed Conversion Time
TSAR DAC Activity Reduction
• TSAR Switching Activity Reduction– When the input is in the center code, no DAC cap is
switched– Like “Multi-Comparator” Circuit but with no extra
voltage comparators [Liu, VLSI 2010] 19
Switch
Switch
Switch
Stage 1 Stage 2 Stage 3
No Switching
VREF
-VREF
0
Switch
TSAR Residue Shaping
• TSAR Residue Shaping due to 1.5b redundancy– Improves SQNR by 6dB (Reduces DAC spread by ½)– Further reduces latter stage DAC activity 20
1 -11/2 -1/2
1/2
0
Stage 1
1/4 -1/4
1 -11/2 -1/2
1/2
0
Stage 2
1/4 -1/4
3/2
1 -11/2 -1/2
1/2
0
Stage 3
1/4 -1/4
7/2
-1/512 1/512-1/1024 1/10240
.05%.05%
99.9% of CodesStage 9 PDF
TSAR Stage Grouping and Skipping
• TSAR Stage Grouping– Allows for cycle skipping (10b in 8.02 ave. cycles)– Reduces number of distinct reference levels 21
VFS
-VFS
VFS
-VFS
VFS VFS VFS
-VFS -VFS -VFS
VIN
STAGE: 1 2 3 4 5
Skip
Stage
Don’t
Charge
Caps
ACTION: Normal
Operation
Normal
Operation
Normal
Operation
TSAR Stage Grouping and Skipping
• TSAR Stage Grouping– Grouping based on
power simulations– Comparator power
also reduces (20% less on average)
22
1 2 3 4 5 6 7 8 9Stages:
Delay Reference(As a fraction of Vfs) 1/8 1/10241/32
0 250 500 750 10003
4
5
6
7
8
9
10
MCSTSAR
Code
Nu
mb
er
of
Co
mp
ari
so
ns
Comparisons Per Code
TSAR Switching and Driver Energy
• TSAR Energy Reductions over the MCS SAR– Average DAC switching energy is reduced by 63.9%– Average driver energy is reduced by 61.3% 23
0 250 500 750 10000
50
100
150
200MCS
TSAR
Code
En
erg
y p
er
Co
de
(C
Vd
d²)
0 250 500 750 10000
100
200
300
400
500
MCSTSAR
CodeD
riv
er
Ca
pa
cit
ors
Sw
itc
he
d
DAC Switching Energy per Code Driver Energy per Code
TSAR Implementation
• TSAR Implemented in 0.13µm CMOS – Delay elements consist of current starved inverters– Input switches are bootstrapped [Dessouky JSSC 2001]– Inverter based DAC Drivers 24
SAR
DAC Driver
DAC Driver
Cap DAC
Cap DAC
VIN
DOUTTime Comp
Delay
TSAR Voltage Comparator
• Voltage Comparator– NMOS input devices, PMOS latch only– Uses high VTH devices to read output– Outputs directly feed time comparator 25
CPVINP VINN
CLK CLK
CLK
CLK
CN
Time Comp
Time Comp
TCN TCP
TSAR Time Comparator
• Time Comparator– Gated Inverter
Based– Device strength
based on speed and accuracy
– Outputs fed to SAR Registers
26
CLK
CP
TNP
Internal Clock
Voltage Comparator Regerating
Time Comparator Transparent
Voltage Comparator
Resetting
Time Data Latched
Comparator Operations
TSAR State Machine Enhancements
• TSPC DFF optimized for SAR ring counter– Reduces energy on “00” state with simple asy. reset– Saves 70% of state machine power – Increases setup time by 50% 27
bN-1 bN ETSPC EPROP
7.93fJ 0.10fJ
3.67fJ
6.69fJ0.02fJ
3.73fJ
9.10fJ0.02fJ
0
0
11
0
1
01
CK
CK
CK
CK
RSTD
Q
TSAR Reference 3 Calibration
• Reference Calibration Sets Third Reference– No static power, reference stored as capacitor voltage– First 2 references are coarse and only used for
redundancy in groups 1 and 2– Works on the principle that latter stage distribution
become more white [Levy TCASI 2011]28
Mod-N ACC
Dynamic CP
01 (+1)
10,00 (-1)
Roll Up
Roll DN
VTREF3
For ¼ Time Level, 50% of codes should equal “01”
TSAR Die Photo
• Layout Specs– JAZZ 0.13µm
CMOS– Active Area =
0.056mm² 29
311µm
180µm
Analog CoreSAR and
Logic
Cap Drivers
Capacitor
Array
Capacitor
Array
Calibration
Circuit
200µm x
80µm
Cap Drivers
[Guerber 2010]
TSAR Measured Results
30
4 407
7.5
8
8.5
9
9.5
10
ENOB @ 0.8V VDD
ENOB @ 1.2V VDD
Sampling Clock Frequency (MHz)
Eff
ec
tiv
e N
um
be
r o
f B
its
(E
NO
B)
0 1 2 3 4-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Frequency (MHz)
Ma
gn
itu
de
(d
B)
TSAR Frequency Response Nyquist ENOB vs. CLK Frequency
8 MHz CLKVDD = 0.8VFOM = 16.9fJ/C-S
TSAR Measured Results
31
4 407
7.5
8
8.5
9
9.5
10
ENOB @ 0.8V VDD
ENOB @ 1.2V VDD
Sampling Clock Frequency (MHz)
Eff
ec
tiv
e N
um
be
r o
f B
its
(E
NO
B)
0 1 2 3 4-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Frequency (MHz)
Ma
gn
itu
de
(d
B)
TSAR Frequency Response Nyquist ENOB vs. CLK Frequency
8 MHz CLKVDD = 0.8VFOM = 16.9fJ/C-S
TSAR Power Consumption
32
-50 -40 -30 -20 -10 0210
230
250
270
290
310
Input Signal (dBFS)
To
tal
TS
AR
Po
we
r (u
W)
Measured TSAR Power vs. Input TSAR Power Breakdown
40%
38%
6%
4%8%
4%
Comparator Cap Array/DriversTime Comparison Bootstrap SwitchSAR Logic Ref/CLK Gen
TSAR Performance Summary
33
CLK Freq. (MHz) 8 (12b) 8 (10b) 20 (10b) 20 (10b)
Supply (V) 0.8 1.2 0.8 1.2
Input Freq. (MHz) 4 4 10 10
Total Power (µW) 75.2 231 202 526
SNDR (dB) 61.1 59.6 53.3 55.7
SFDR (dB) 79 76.8 74.1 78.6
FOM (fJ/CS) 10.0 36.8 26.8 52.8
TSAR Summary
• Accuracy Improvements– Redundancy, Residue Shaping, and Calibration
• Speed Improvements– Reduced comp. delay and capacitor settling time
• Power Reduction– Stage Skipping, DAC activity reduction, residue
shaping, and logic modifications
• Implementation– Working chip demonstrated in 0.13um CMOS
34
SAR ADC Outline• ADC Motivation• MCS and EMCS Structures• The Ternary SAR (TSAR)• Residue Shaping
– SQNR Impacts– Bounded Offset Tolerance
• The Feedback Initialized TSAR• Conclusions
35
TSAR Residue Shaping
• TSAR Residue Shaping due to 1.5b redundancy– Improves SQNR by 6dB (Reduces DAC spread by ½)– Further reduces latter stage DAC activity 36
1 -11/2 -1/2
1/2
0
Stage 1
1/4 -1/4
1 -11/2 -1/2
1/2
0
Stage 2
1/4 -1/4
3/2
1 -11/2 -1/2
1/2
0
Stage 3
1/4 -1/4
7/2
-1/512 1/512-1/1024 1/10240
.05%.05%
99.9% of CodesStage 9 PDF
Pipeline ADC Residue Shaping
• Residue Shaping Present in any Multi-Stage ADC– Pipeline is similar to SAR with constant full scale range – SQNR Improvement related to overall resolution 37
1 1/2 -1/20
Stage 1
1/4 -1/4
1 1/2 -1/2
1/4
0
Stage 2
1/4 -1/4
3/4
1/8Stage 3
7/8
R-Shaped
R-Shaped Traditional
-M*ST10
SQNR
SQNR -SQNR
20log 2 1- 2
Pipeline ADC PDF Residue Shaping Effect
Residue Shaping ADC Design
• Last Stage Full-Scale Range Shrinks by ½– Quantization noise is shaped into smaller range– Final stage references should change 38
VFS
01/2
-1/2
-VFS
VFS
1/43/4
-1/4
-VFS
VFS
1/4
-1/4
-VFS
0
Traditonal Proposed0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
9
9.5
10
10.5
11
11.5
12
1x Digital Gain
1/2x Digital Gain
Symmetric Last Stage Flash Outer Level Magnitude as a Fraction of Vfs
EN
OB
(N
o O
ffs
et)
Last Stage Reference Levels for SQNR Improvement
Residue Shaping with Other Red.
• Residue Shaping is not Present in Other Red.– Extra cycle redundancy just swaps PDF halves– Sub-Radix redundancy does change the PDF, but does
not minimize quantization noise full-scale range 39
1 -11/2 -1/2
1/2
0
Stage 1
1/4 -1/4
1 -11/2 -1/20
Stage 2a
1/4 -1/4 1 -11/2 -1/20
Stage 3
1/4 -1/4
21
1 -11/2 -1/20
Stage 2b
1/4 -1/4
1
Swap PDF Halves
Extra Cycle Redundancy Residue Shaping
Residue Shaping Offset Tolerance
• Sub-ADC Offset Tolerance only Slightly Reduced– 1.5b/stage redundancy gives +/- Vfs/4 comparator offsets– With residue shaping, early stage sub-ADC offsets tolerated
similarly, later comps. should be more accurate 40
VFS
1/4
-1/4
-VFS
VFS
-VFS
VFS
-VFS
VFS
-VFS
3/8
-3/8
VFS
1/4
-1/4
-VFS
01/8
-1/8
7/16
-7/16
1/16-1/16
15/32
-15/32
1/32-1/32
SAR Residue Shaping Comparator Offset Bounds Example
VFS
-VFS
VFS
-VFS
VFS
-VFS
VFS
3/32
-3/32
VFS
1/64
-1/640
7/32
-7/32
15/32
-15/32
1/32-1/32
1/32-1/32
1/32-1/32
1/32-1/32
Pipeline Residue Shaping Comparator Offset Bounds Example
Residue Shaping Offset Tolerance
• SQNR Improves even with Offsets– Half-bit SQNR increase with no architectural changes– Resolution improves with bounding requirements
followed 41
0 0.05 0.1 0.15 0.2 0.2510.2
10.4
10.6
10.8
11
11.2
11.4
11.6
11.8
12
ADC w/ 2b Tradtional Back-end FlashADC w/ 2b Scaled Back-end FlashADC w/ 2b Scaled Back-end Flash and Ideal St. 9ADC w/ Bounded Comparison Levels
3-Sigma Offset Level
EN
OB
SAR ADC Outline
• ADC Motivation• MCS and EMCS Structures• The Ternary SAR (TSAR)• Residue Shaping• The Feedback Initialized TSAR
– TSAR Comparison and DAC Inefficiencies– Coarse/Fine Nestings and Recoding
• Conclusions42
TSAR Inefficiencies
Driver Activity DAC Switching Comparator Energy
Switch
Switch
Switch
Stage 1 Stage 2
No Switching
VFS
-VFS
0
Switch
Switch
Switch
Switch
No Switching
VFS
-VFS
0
Switch
-VFS/2
-VFS/4
VFS/4
-VFS/2
-VFS/2
-VFS/4
VFS/4
-VFS/2
TSAR
Optimal
Φ1 Φ2 Φ3
Φ1 Φ1 Φ1
2C
2C
C
C
C
C
TSAR Switching
Phases
Optimal Switching
Phases
VG
VG
1
StageSized
Comparator Accuracy
13b
2 13b
3 13b
TSAR Comparator Sizes
1
StageSized
Comparator Accuracy
3b
2 4b
3 5b
Optimal Comparator Sizes
43
FITSAR Block Diagram
• FITSAR Architectural Benefits:– Nested coarse ADC structure (Comparator Energy)– Fine DAC bit recoding (DAC Activity and Switching)– Fine DAC feedback initialization (DAC Activity and Switching)
Coarse DAC
Data Timed 6b Binary SAR
7b TSARFine DAC LSBs
(R2R Based)
Fine DAC MSBs (Cap Based)
Rec
od
ed
VIN
Jon Guerber/44
FITSAR Nesting
• Multi-Stage SAR ADCs– Pipelined: Requires Inter-stage Amplification, Decouples
Fine/Corse Bits– Split Comparator: No Inter-stage Amplification, Coupled
Fine/Corse Bits– Nested: No Amplification, Decouples Fine/Corse Bits
SAR
DAC Driver
DAC Driver
Cap DAC
Cap DAC
VIN
DOUTTime Comp
Delay
Coarse SAR
45
Feedback TSAR Recoding
• FITSAR Recoding optimizes DAC “Windowing”– Converts binary coarse output to optimal ternary codes– Maintains redundancy and residue shaping– Implemented with simple logic blocks
000001010011100101110111
COUT F1 F2
VDD
VCM
GND
VDD
VDD
VDDVCM
VCM VCM
VCM VCM
VCM
VCMGND
GND GND
F1(VDD)C1C2
F1(GND)C1bC2b
F2(VDD)C1C3
F2(GND)C1bC3b
VCM
1/4 1/8 1/32
FITSAR DAC Movement
EC = 7.71*(CVDD²)
Φ1 Φ1 Φ1 Φ1 Φ1 Φ1
0 0 0
VFS
-VFS
DAC Recoding DAC Logic
Jon Guerber/46
Feedback Initialization
• Fine DAC switching is grouped– All codes from the coarse SAR are switched to the fine
in a single phase– Large energy savings due to large fine DAC and small
coarse DAC
Φ1 Φ2 Φ3
GND to VDD Switching Phase
Φ1 Φ1 Φ2
Φ1 Φ1 Φ1
2DD DDVDD DD DD
V V 5E = V 2C +C = CV
2 4 4
2VDD DD DD DD DD
3 3E = V 3C V - V = CV
4 4
VDDE = 0 Floating
Switching Energy
2C
2C
2C
C
C
C
C
C
C
Jon Guerber/47
DAC Switching Comparison
• Time-Based DAC Movement Comparison– MCS requires the DAC to switch in each phase, high activity– TSAR eliminates DAC switching for small virtual ground inputs– FITSAR optimizes switching operation to only be in one direction– FITSAR also switching in one phase, reducing crossover losses
VCM 1/4 1/8 1/32
FITSAR DAC Movement
EC = 7.71*(CVDD²)
Φ1 Φ1 Φ1 Φ1 Φ1 Φ1
0 0 0
VFS
-VFS
VCM 1/20
1/8
1/32
TSAR DAC Movement
EC = 14.09*(CVDD²)
Φ1 Φ2 Φ3 Φ4 Φ5 Φ6
0 0
VFS
-VFS
VFS
-VFS
VCM1/2
1/4
1/8 1/16
1/32
1/64
MCS DAC Movement
EC = 23.32*(CVDD²)
Φ1 Φ2 Φ3 Φ4 Φ5 Φ6
Jon Guerber/48
FITSAR Switching and Driver Energy
• FITSAR Optimally Reduces Fine DAC Switching for 3 Levels– DAC Power Reduced 86% over MCS (61% over TSAR)– Driver activity Reduced 74% over MCS (34% over TSAR)
0 500 1000 1500 2000 2500 3000 3500 40000
100
200
300
400
500
600
700
800
900MCS
FIT
TSAR
Code
En
erg
y P
er
Co
de
Co
nv
ers
ion
(C
Vd
d²)
0 1000 2000 3000 40000
200
400
600
800
1000
FIT
TSAR
CodeC
ap
ac
ito
rs S
wit
ch
ed
pe
r C
od
e C
on
ve
rsio
n
49
FITSAR Comparator Activity Red.
• Fine Comparator Activity Reduced over TSAR– MCS: 12 Comps/Code– TSAR: 10.2 Comps/Code (15% energy reduction over MCS)– FITSAR: 5.6 Comps/Code (53% energy reduction over MCS)
0 500 1000 1500 2000 2500 3000 3500 40002
3
4
5
6
7
8
9
10
11
12
MCS
TSAR
Code
No
. Eq
v. F
ine
Co
mp
ari
so
ns
Pe
r C
od
e
0 500 1000 1500 2000 2500 3000 3500 40002
3
4
5
6
7
8
9
10
11
12
MCS
FIT
CodeN
o. E
qv
. Fin
e C
om
pa
ris
on
s P
er
Co
de
50
CP
VINP VINN
CLK CLK
CLK
CLK
CN
P-LatchStrongarm
CP
VINP
CLK CLK
CLK
CN
CLK
• Coarse ADC Comp– Lower Accuracy (8-bit
noise)– High Speed– No Static Power
• Fine ADC Comp– Higher Accuracy (14-bit
noise)– Med Speed– Static Power when not
Reset
Comparator Implementation
Jon Guerber/51
VIN+-
VCM VCM VCM
VCM VCM VCM
VDD VCM VCM
GND VCM VCM
GND VCM VCM
VDD VCM VCM
VDD VDD VCM
GND GND VCM
VCM VDD VCM
VCM GND VCM
VCM GND VCM
VCM VDD VCM
GND GND VCM
VDD VDD VCM
EVDD = (½)CVDD²
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C C
2C
2C C C
C CEVDD = (1/8)CVDD²
EVDD = (3/8)CVDD²
EVDD = (½)CVDD²
EVDD = (3/8)CVDD²
EVDD = (1/8)CVDD²
ER Merged CapacitorSwitching
• EMCS Coarse ADC– Output is
automatically recoded– Higher coarse
linearity– Lower switching
power, fewer latches
DFFD Q
R
DFFD Q
R
DFFD Q
R
DFFD Q
R
DFFD Q
DFFD Q
CK
ST
UP1
DN1
DFFD Q
DN2
UP2
VGP
VGN
Φ1 Φ2
R
Φ3
A
B
MU
X
DFFD Q
R
EMCS Implementation
Coarse ADC: EMCS
52
FITSAR Comparator Gating
• Comparator Clock Gated by Stage Outputs– Replaces Skipping for faster critical delay logic path– Gates clock to comparator based on state outputs
53
UP(n+1) DN(n+1)
PH(n+1)
UP(n+2) DN(n+2)
PH(n+2)
PH(n)
CLK COMPCLK
Comparator Clock Gating Circuit
FITSAR R2R DAC Nesting
• SAR DAC arrays are often Mismatch Limited– Can reduce overall DAC by calibration or Nesting– Now Thermal noise limited, 4x-ish reduction– No “Coupling capacitor” problems 54
FN F(N-1) F4
2(N-5)C 2(N-6)C 2C C
2R
R
2R
R
2R
2R
F3F2F1
VCM
VINP
FITSAR Nested DAC
Ternary R2R DAC
Jon Guerber/55
• 3-level R2R DAC– 3-level DAC has a 79% power improvement over the traditional 2-level– Provides linearity improvements by eliminating major transition
RR2R
B2B3B4
GND
2R 2R 2R
VOUT
R
B1
2R
RR2R
T1T2T3
2R 2R 2R
2R 2R 2R
B1/2
T1bT2bT3b
VOUT
+
-B1b/2
0 10 20 30 40 50 600
0.2
0.4
0.6
0.8
1
1.2
1.4
1.62-Level 3-Level
Code
Nor
mal
ized
Pow
er (W
/R)
Traditional R2R DAC
3-level R2R DAC
FITSAR Prototype Layout
Jon Guerber/56
• FITSAR Prototype Layout– Area is 0.06mm²– Fabricated in National 0.13u CMOS– Psudo-differential layout
FITSAR Die Photo
FITSAR Floorplan
FN CMP
Inp
ut
Sw
itch
es Bootstrapping Circuit
Bootstrapping Circuit
Internal CLK GEN
Ref Buf
Coarse Logic and Comparator
Coarse DAC
Coarse DAC
Fine Cap DAC
R2R DAC and
Buffers
Fine Cap DAC
Fine DAC
Buffers
R2R DAC and
Buffers
Clock Gen and Buffer
Digital Buffers
Digital Buffers
Fine DAC
Buffers
Fine Logic
and State Machine
Scan and Trim Logic
Scan and Trim Logic
VINN
VINP
57
Spec/Date FITSAR 1.2V FITSAR 0.8V TSAR 0.8V
ENOB 11.76 11.18 9.85
Frequency 50 MHz 10 MHz 8 MHz
Power 362 uW 32.8 uW 75.2 uW
Process (VDD)
Optimos2 (1.2)
Optimos2 (0.8)
Jazz 0.13u (0.8)
FOM 2.08 fJ/CS 1.41 fJ/CS 10.0 fJ/CS
FITSAR Transistor Level Simulations
SAR ADC Outline
• SAR Motivation• MCS and EMCS Structures• The Ternary SAR (TSAR)• Residue Shaping• The Feedback Initialized TSAR• Conclusions
58
Published Work• J. Guerber, H. Venkatram, M. Gande, and U. Moon, “A Ternary R2R DAC Design
for Improved Energy Efficiency,” Elec. Letters, Submitted Dec. 2012.
• J. Guerber, M. Gande, H. Venkatram, A. Waters, U. Moon, “A 10b Ternary SAR ADC with Quantization Time Information Utilization,” IEEE J. Solid State Circuits. Nov. 2012.
• J. Guerber, M. Gande, U. Moon, “The Analysis and Application of Redundant Multi-Stage ADC Resolution Improvements Through PDF Residue Shaping,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., Aug. 2012.
• J. Guerber, H. Venkatram, T. Oh, U. Moon, “Enhanced SAR ADC Energy Efficiency from the Early Reset Merged Capacitor Switching Algorithm,” IEEE Int. Symp. Circuits Syst., May 2012.
• J. Guerber, M. Gande, H. Venkatram, A. Waters, U. Moon, “A 10b Ternary SAR ADC with Decision Time Quantization Based Redundancy,” IEEE Asian Solid-State Circuits Conf. Nov. 2011, pp. 63-65.
59
Conclusions
• Energy Efficient SAR Architectural Changes – Switching efficiency though EMCS, TSAR, and FITSAR– Comparison Reduction through TSAR and FITSAR– Stage Skipping and grouping though TSAR– Recoding and Nesting with FITSAR
• ADC Sample Rate Enhancements– Comparator speed enhancements though TSAR – Coarse SAR speed increase in FITSAR
• Accuracy Improvements– Residue shaping SQNR increases in TSAR, FITSAR, and pipelined
structures– 1.5b/stage redundancy shown in TSAR and FITSAR
60
Questions
61
Backup Slides
62
Residue Shaping with Sub-Radix
TSAR Core Timing Diagram
TSAR Capacitor Layout
TSAR Quantizer Schematic
TSAR State Machine Logic
FITSAR Core Blocks
FITSAR Coarse Logic (EMCS)
Residue Shaping with Sub-Radix
• Residue Shaping is not Present in Sub-Radix– PDF does shape, but does not minimize full-scale range
due to effective 1 bit quantization per stage 63
Sub-Radix Redundancy Residue Shaping
1.4 -14.70 -.70
½
0
.70 -.70.41 -.41
1
0
.41 -.41.29 -.29
1
0.24 -.24
2
.24 -.24.17 -.17
2
0.14 -.14
3
.06 .06
4
.14 -.14.08 -.08
5
0.06 -.06
3
.01 -.01
45
43
Stage 1
Stage 2
Stage 3
Stage 4
Stage 5
4
TSAR Core Timing Diagram
64
Internal Clock
Regenerating Transparent
Resetting
Data Latched
Voltage Comp. Op:Time Latch Op:
Virtual Ground Nodes
Internal SAR Phase
Time Reference
Phase N Phase N+1
Ref. N Ref. N+1
Falling Edge Set By Time Reference
TSAR Capacitor Layout
• Layout in Unit Elements– Common
centroid to fix first order gradients
– Maintain average distance to center
– Digital inputs all enter from right
– Virtual ground exits on left
65
9 8 9 9 9 7 9 8 8 9 7 9 9 9 8 9
8 9 7 9 8 9 8 9 9 8 9 8 9 7 9 8
9 7 9 8 9 8 9 7 7 9 8 9 8 9 7 9
9 9 8 9 6 9 8 9 9 8 9 6 9 8 9 9
9 8 9 6 9 5 9 8 8 9 5 9 6 9 8 9
7 9 8 9 5 9 7 9 9 7 9 5 9 8 9 7
9 8 9 8 9 7 4 6 6 4 7 9 8 9 8 9
8 9 7 9 8 9 6 3 1 6 9 8 9 7 9 8
8 9 7 9 8 9 6 2 3 6 9 8 9 7 9 8
9 8 9 8 9 7 4 6 6 4 7 9 8 9 8 9
7 9 8 9 5 9 7 9 9 7 9 5 9 8 9 7
9 8 9 6 9 5 9 8 8 9 5 9 6 9 8 9
9 9 8 9 6 9 8 9 9 8 9 6 9 8 9 9
9 7 9 8 9 8 9 7 7 9 8 9 8 9 7 9
8 9 7 9 8 9 8 9 9 8 9 8 9 7 9 8
9 8 9 9 9 7 9 8 8 9 7 9 9 9 8 9
TSAR Quantizer Schematic
66
SAR Registers,
Phase selector
and Reference selector
RSTVGP
VGN
CKSET
CKRST
CKSET
CKRST
CKRST
CKSET
Current Starved
2x
2x
12x
6x
3x
3x
TSAR State Machine Logic
67
DFFD Q
QDFFD Q
QDFFD Q
QDFFD Q
Q
DFFD Q
QDFFD Q
QDFFD Q
QDFFD Q
QDFFD Q
Q
DFFD Q
Q
CK CK
CK CK CK CKCKCK
CK CK
CK
R
1x
1x
S0 S1S2
UP2
DN2
UP3
DN3S3
S4
UP5
DN5 S5
UP6
DN6S6
UP7
DN7S7
UP8
DN8S8
S9
EOC
SN2
SN3
FITSAR Core Blocks
68
P9CKB
PIN
10x/10x 10x/10x9x 6x
REF2REF1
9x 6x
PIN
RB
P10CKB
P9
10x/10x9x 6x
REF3
CKB
EOCCKB
P10
10x/10x9x 6x
REF4
CKB
REFOUT (To Internal CLK Gen)
RST CLKGATE CMP
EOC REF TD
Reference Mux
Internal Clock Generator
FITSAR Coarse Logic (EMCS)
69
VGP
VGN
CLK
A
B
MU
X
DLTD Q
R
DLTD Q
R
AOI
DLT
D1 Q
R
AOI
R
D2
DLT
D1 Q
R
D2
DLT
D1 Q
R
AOI
R
D2
DLT
D1 Q
R
D2
DLT
D1 Q
R
AOI
R
D2
DLT
D1 Q
R
D2
DLT
D1 Q
R
AOI
R
D2
DLT
D1 Q
R
D2
DLTQ D
RS
DFFD Q
R
DFFD Q
R
DFFD Q
R
DFFD Q
R
DFFD Q
R
U1
UF1
U2
UF2 UF3 UF4 UF5
U3 U4 U5
DF1 DF2 DF3 DF4 DF5
D1 D2 D3 D4 D5
P7
P5
P5
P7B
R
RB
POUT
FITSAR Fine Logic (Gating)
70
DLTD Q
R
DLT
D Q
R
Qb
Qb
U6
D6
DFFD Q
R
DLTD Q
R
DLT
D Q
R
Qb
Qb
U7
D7
DFFD Q
R
DLTD Q
R
DLT
D Q
R
Qb
Qb
U8
D8
DFFD Q
R
DLTD Q
R
DLT
D Q
R
Qb
Qb
U9
D9
DFFD Q
R
DLTD Q
R
DLT
D Q
R
Qb
Qb
U10
D10
EOC
DFFD Q
R
CKM
R
FCP
FCN
PIN
P7
Gate
3x5x 3x 3x 5x 3x
TSAR Layout Floorplan
71
CMP/ TC
Inp
ut
Sw
itch
es Bootstrapping Logic
Bootstrapping Logic
Internal CLK GEN
Ref Buf
Fine Cap DAC
Fine Cap DAC DAC Buffers
Clock Gen and Buffer
Digital Buffers
Calibration
Digital Buffers
DAC Buffers
Fine Logic and
State Machine
Calibration
VINN
VINP
Boot Cap
Boot Cap
TSAR Prototype Test Setup
72
BP FilterRF Signal GeneratorHP 8665A 50
SMA
VCM 10n
BP FilterRF Signal GeneratorAG 8643A 50
100n
RPOT
BandgapMAX6126
Power Supply
AGe3631
RP50k
RP1k
100n10u 100n/10u
ADA4004
Output Buffers
SN74AVC
Logic Analyzer TLA720
7 REF2-8
REF1
8
MATLAB Analysis
Power Supply
AGe3631
LDOADP1708 I-Meter
Fluke45100n/10u 100n 10u
RP50kADJ
SUP1
SUP2-65 6
AVR uCTiny84
AVR ProgISPMKII
TSARVIN
VIP
CLK REFS
SCANSUP
DO
10 10
AVR Studio
63
ADT1-1WT
References I
1. V. Hariprasath, J. Guerber, S.-H. Lee, and U. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electron. Lett., vol. 46, pp. 620-621, Apr. 29, 2010.
2. Y. Zhu, C.-H. Chan, et al., “A 10b 100MS/s reference-free SAR ADC in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1111-1121, Jun. 2010.
3. J. Yang, T. Naing, and R. Brodersen, “A 1 GS/s 6b 6.7mW successive approximation ADC using asynchronous processing,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1469-1478, Aug. 2010.
4. C.-C. Liu, S.-J. Chang, et al., “A 1V 11fJ/conversion-step 10b 10MS/s asynchronous SAR ADC in 0.18um CMOS,” IEEE Symp. On VLSI Circuits, June 2010, pp. 241-242.
73
References II
5. B. Levy, “A propagation analysis of residual distribution in pipeline ADCs,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 58, no. 10, pp. 2366-2376, Oct. 2011.
6. M. Dessouky, A. Kaiser, “Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping,” IEEE J. Solid-State Circuits, vol. 36, no. 3, Mar. 2001.
74