power efficient adcs

7/23/2019 Power Efficient ADCs

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10

Power Efficient ADCs forBiomedical Signal Acquisition

Alberto Rodrguez-Prez, Manuel Delgado-Restituto

and Fernando MedeiroInstitute of Microelectronics of Seville (IMSE-CNM) and University of Seville

Spain

1. IntroductionIn the last years, there has been a growing interest in the design of biomedical wireless

sensors (Harrison et al., 2007; Zou et al., 2009). These sensors can be used for online

monitoring, detection and prevention of many diseases with a minimum disturbance to the

patient and reducing the hospital expenses, so they are having a big acceptance in the

medical community.

Most biomedical signals are characterized by their low voltage amplitude (in the range of

mili-volts) and their low frequency ranges (few tens of kHz) (Northrop, 2001; Northrop,

2004). Also, due to the electrode used to sense them, they usually present a high DC offset

that needs to be suppressed. A typical biomedical sensor interface consists on a band-pass

filter, a low-noise programmable amplifier and an Analog-to-Digital Converter (ADC). Thedigitalization of the sensed biosignals is usually done with 8 or 12-bits of resolution

(depending on the kind of signal) and with sampling frequencies between 1kS/ s and

100kS/ s (Scott et al., 2003; Verma and Chandrakasan, 2007; Zou et al., 2009).

Due to their isolation from any kind of external supply source, one of the most important

design constraints of these wireless sensors is the minimization of their power consumption.

Because of that, most of the works about biomedical sensor designs have been focused on

low-power and low-voltage techniques and architectures.

For the design of the ADCs, many authors choose the SAR architecture with capacitive-

based DACs due to their suitability for low-power and low-voltage needed requirements

(Agnes et al., 2008; Hong and Lee, 2007; Saurbrey et al., 2003; Scott et al., 2003; Verma and

Chandrakasan, 2007; Zou et al., 2009).

However, this architecture present some problems when the needed resolution growths.

They become more area consumer, present high sensitivity to parasitic capacitances and

demand more power from the supply source.

In this chapter we will present two different architectures, the most-known SAR and a new

one based on a Switched Capacitor (SC) implementation of a Binary Search Algorithm,

which solves many of the limitations of the SARs and present higher reconfigurability, a

very important fact in these kinds of applications. The chapter will focus on the most

relevant design constraints and the study of the effect of the different non-idealities, in order

to get an area and power optimized design.

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Biomedical Engineering Trends in Electronics, Communications and Software172

Two real implementations will be presented at the end of the chapter to illustrate the given

theory through experimental and simulation results.

2. Low-power ADC architectures

2.1 Successive approximation architectureThe successive approximation algorithm performs the A/ D conversion over multiple clock

periods by exploiting the knowledge of previously determined bits to determine the next

significant bit. The method aims to reduce the circuit complexity and power consumption

using a low conversion rate by allowing one clock period per bit (plus one for the input

sampling).

Fig. 1a shows the typical block diagram of an n-bit SA ADC. It consists of a Sample-and-

Hold (S&H) circuit followed by a feedback loop composed by a comparator, a Successive

Approximation Register (SAR) logic block, and an n-bit DAC. Circuit operation is controlled

by a clock signal with frequencyfclk. The SAR block captures the data from the comparator at

each clock cycle and assembles the words driving the DAC bit by bit, from the most- to theleast-significant bit, using a binary search algorithm, as Fig. 1b illustrates (Maloberti, 2007).

After ncycles, the digital counterpart, dout, of the analog sampled voltage, vsh, is obtained.

Besides, the S&H clock uses m clock periods for the sampling of the input signal, vin.

Therefore, a total of n+mclock intervals are required for completing an n-bitconversion.

At the start of the next conversion, while the S&H is sampling the next input, the SAR

provides the n-bit output and resets the registers.

VshVDAC

1 2 11

# iterations

0000000000 1000000000 0100000000 011000100 0D(9:0)

Sampling

period

: sampling: conversion

S&H

-

+SAR

Logic

DAC

Dout

Vin Vsh

N

VDAC

a) b)

Fig. 1. a) SAR ADC architecture, b) Timing diagram

Among the very different existing architectures to perform the Analog-to-Digital

Conversion, the Successive Approximation one have been chosen by many authors as the

most efficient in terms of power consumption to digitalize biomedical signals. As it has been

explained above, a minimum number of analog blocks and a very simple digital logic areneeded to perform the complete conversion. Therefore, the overall power consumption

presented by these solutions is very low.

2.2 Capacitive-based DACOne of the most critical blocks of these solutions in terms of power consumption reduction is

the Digital-to-Analog Converter. To implement it, many authors choose a capacitive-based

solution (Agnes et al., 2008; Hong and Lee, 2007; Saurbrey et al., 2003; Scott et al., 2003; Verma

and Chandrakasan, 2007; Zou et al., 2009) due to their low power consumption characteristics

and because they can also be used as a passive S&H. As they are based on the charge

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Power Efficient ADCs for Biomedical Signal Acquisition 173

redistribution principle, they only consume power at the beginning of the conversion, when

the matrix is loaded. Therefore, they are really suitable for the biomedical devices.

One of the main problems of these capacitive DACs is that their performance is in many

cases strongly affected by the parasitic capacitances (Cong, 2001; Rodriguez-Perez et al.,

2010). We will present an exhaustive study about the effect of the parasitic capacitances onthe performance of the capacitive-based DACs.

Depending on their structure, the capacitive-based DACs can be divided in different sub-

types.

VOut

Cu Cu 2Cu 4Cu 2N-2Cu 2N-1Cu

R

LSB MSB

Vref

VOut

Cu Cu 2Cu 4Cu 2N/2-2Cu 2N/2-1Cu

R

LSB

Vref

2Cu 4Cu 2N/2-2Cu 2N/2-1Cu

MSB

Cu

Csplit

VOut

Cu Cu Cu Cu Cu

R

LSB

Vref

Cu

2Cu 2Cu 2Cu

MSB

a) b)

c)

Fig. 2. Capacitive DACs architectures: a) Binary Weighted Array (BWA), b) C-2C,

c) Binary Weighted Array with an attenuation Capacitor (BWAC)

Binary Weighted Arrays (BWA)

This structure is used by many authors in their works. It consists on a binary scaled array of

capacitors, as Fig. 2a shows. The top of the capacitors are shorted and constitute the analog

output of the DAC, while the bottoms are connected to different switches controlled by thedigital input bits. The MSB is connected to the biggest capacitor while the LSB is connected

to the smallest one. Then, the voltage output of the DAC will be given by:

1

0

2

2

Ni

i

i

out N

D

V

=

=

(1)

whereNis the resolution of the DAC andDiis the i-th input bit.

The power of these capacitive DACs is essentially due to the switching activity of the

capacitive matrix, which will be given by:

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21 2 2

NDC S u DACP f C V= , (2)

wherefsis the sampling frequency,Nthe resolution and Cuthe unitary capacitance.

The area occupied by the DAC will be proportional to 2N

cuA , where Acu is the areaoccupied by an unitary capacitance.

Considering that the equivalent parasitic capacitance at the top of the capacitive matrix is

given by Cp(which groups parasitic capacitances at the top of the capacitors and parasitic

capacitances due to the routing), the output voltage will be given by:

1

0

22

2 2

Ni

iNu i

out N Nu p

DC

VC C

== +

(3)

As can be extracted from the given equation, parasitic capacitances in the BWA structure

produce a gain error in the final result.

The main drawback of this solution is that its power consumption and area occupation

increase binarily with the resolution. Therefore, for more than 8-bits of resolution DACs, this

architecture is not recommended due to the difficulty of doing a proper matched array and

the huge increase in terms of area and power consumption.

Binary Weighted Arrays with an attenuation capacitor (BWAC)

As the former architectures are not suitable for medium-high resolutions because their

increase in terms of power consumption, area occupation and complexity, many authors

prefer to divide the BWA into two using a capacitive divider for the less significant part of

the matrix (Agnes et al., 2008). The schematic of the architecture is shown in Fig. 2c), where

the value of the attenuation capacitor, attC , is given by:

2

21

2

2

N

NattC = , (4)

whereNis the resolution of the converter. Then, the output voltage of the capacitive DAC is

given by:

( )22

2

N

out N

m nV

+= , (5)

where m is the number of capacitors placed on the most significant part of the matrix, while

n is the number in the Least Significant one. The optimum configuration in terms of area

and power consumption is when mand n are the same, that is, there is the same number of

capacitors in the most significant part of the matrix as in the least one.

The switching power of these architectures is given by:

21 21 2

2

N

DAC S u DACP f C V+= , (6)

being the area occupation of these structures proportional to 21

2 N

cuA+

.

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It is obvious at first glance that this architecture can reduce the number of unitary elements

of the BWA solutions. This reduction helps in the optimization of the power consumption

and area occupation, which is one of the main objectives in the design of devices for

biomedical purposes.

However, these attenuation capacitor-based architectures present higher sensitivity towardsparasitic capacitances than the BWA ones. While in the second ones parasitic capacitances

only induce an offset error, in this case they cause a non linearity error, which degrades the

performance and the effective resolution of the DAC.

To evaluate the effect of the parasitic capacitances in these architectures, we have to

distinguish between the parasitic capacitances at the top of the most significant part of the

matrix, which will be named as AC and those at the least significant one, BC . Considering

that the two parts of the matrix are equal and that the attenuation capacitor is almost an

unitary one, the output voltage of the DAC will be given by:

( ) ( )

22

2

1 1

0 2 2

/ / / /

NN

N

Ni

iref i u ref i ui i att

outatt eqMSBeqMSB eqLSB att eqLSB eqMSB att

V D C V D C CV

C CC C C C C C

= =

= + ++ +

, (7)

where eqMSBC is the equivalent capacitance of the MSB part the array, and eqLSBC is the

equivalent capacitance of the LSB part of the matrix.

( ) ( )

( )( )

( )

2

2

2

2

2

2

22

2

2

1

1

0

2

2

2 1 2

2

2 12 1

22 1

N

N

N

N

N

N

NN

N

N

Ni

ref i ui

out

u pB att

u pAu pB att

iref i u

i att

att u pAu pA att

u pB

u pA att

V D C

VC C C

C CC C C

V D CC

C C CC C C

C CC C C

=

=

= ++

+ ++ +

+ + + + + +

+ +

(8)

Fig. 3 shows the best straight line INL for different parasitic capacitances per unit

capacitances ratio for a 10-bit DAC. When the parasitic per unitary capacitance ratio rises

above 3%, the non-linearity introduced by the parasitic capacitances is so high that theequivalent resolution is affected.

Then, although the architecture is better in terms of area and power consumption than theBWA one, it is more affected by the parasitic capacitances and its design must be carefullystudied, as will be described later.

C-2C Structures

The schematic of the C-2C structures are shown in Fig. 2b. This kind of structures is an

extension of the BWAC ones, in which the matrix is divided as many times as bits to be

converted, using attenuation capacitors to divide the different unitary capacitances. The

value of these attenuation capacitors is given by the expression (4), whereN is two. Then,

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Fig. 3. INL of parasitic capacitances effect on 10-bit BWAC DAC

the value of these attenuation capacitors must be twice higher than the unitary capacitance,

building the C-2C structures.

The switching power dissipated will be given by:

21 ( 1) 2

DAC S u DACP f N C V= + , (9)

and the area occupation is proportional to ( 1) cuN A+ .

The area and power consumption of these architectures are drastically reduced if comparedwith the other solutions. However, they are rarely employed due to their extremely high

sensitivity towards the parasitic capacitances, which completely degrades its performance

unless they were very low, which is not feasible in standard technologies.

To study the effect of the parasitic capacitances in the C-2C structures, we have to consider

the parasitic capacitances shown in Fig. 4, where ( )' 2pA put pubC C C= + , while3 2A put pubC C C= + . As the bottom parasitic capacitances are usually bigger than those of

the top, we can consider that ' A pAC C for simplicity.

VOut

Cu CuCu Cu Cu

Vrefp

Cu

2Cu 2Cu 2Cu

Vrefn

CpA 2Ctu

D0 D1 D2 DN-1DN-2

Ceqr(0)

CpA CpA CpA

Ceqr(1)Ceql(1) Ceql(2) Ceqr(N-2) Ceql(N-1)

Fig. 4. Parasitic capacitances on C-2C structure

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The output of the DAC can be calculated as:

1

0

( )N

out i DAC

i

V D V i

=

= , (10)

whereDiwill be the i-th digital input bit (with a digital value of 1 or 0), and VDAC(i)is the

equivalent voltage at the output of the DAC if only the bit i-th is activated. These voltages

will be given by:

2

1

2

1

2 2 0 1

( ) ( ) 2 2 ( )

2 2( ) 0

(0) 2 2 ( )

( 1)

Nref u u u

eql eqr u u eqrn i

Nref u u u

DACu eqr u u eqrn

ref u

eql

V C C Ci N

C i C i C C C n

V C C CV i i

C C C C C n

V C

C N

= +

=

< < + + + + +

= =+ + + + +

+

1i N

=

(11)

where 3 2u put pubC C C= + + and 2u putC C= + . Ceqr(i) and Ceql(i) are the equivalentcapacitance at the right and left of the i-th bit, respectively. To calculate these equivalent

capacitances, the following expression can be employed:

2 ( 1) 0 2

( 1) 2( )

2 2

2

u eqr

eqr ueqr

u

u

C C ii N

C i CC i

Ci N

C

+ + < + + +=

=

+

(12)

( )

2 ( 1) 0 1

( 1) 2( )

2 2

3

u eqr

eqr ueql

u u

u

C C ii N

C i CC i

C Ci N

C

+ + < + + +

= +

= +

(13)

These expressions allow us to build the INL figure shown in Fig. 5, where it is clear that theparasitic capacitances induce a complete degradation in the linearity and, consequently, the

performance of the DAC, even if they are small.

Although there are some solutions which try to solve the parasitic capacitance sensitivity ofthese ladders (Cong, 2001), they are not really implementable as they are based on non-

integer scaling of the reference voltages. Also, there are some solutions which implement

these structures in Silicon-Over-Insulator (SOI) technologies, where substrate parasitic

capacitances are dramatically reduced due to the bulk isolation.

As a consequence, these solutions are rarely employed in real implementations.

2.3 Binary search algorithmAlthough the SAR ADC architectures based on capacitive DAC matrix are widely used onbiomedical sensor interfaces, they present some drawbacks which usually difficult theirdesign:

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Fig. 5. INL of parasitic capacitances effect on 10-bit C-2C DAC

Large area occupation. Capacitive-based DACs, and especially in the case of the BWAstructures, usually require a huge area to be implemented (even more if the resolution

is high), because they need many unitary capacitors. This high number of elements also

complicates the routing and their proper matching.

Large switching power consumption.Although one of the benefits of the capacitiveDACs is that they are based on the charge redistribution principle and they dont have

static power consumption is zero, the peaks of current from the supply voltage can be

large, which can complicate the correct working of the circuit as they are usually

supplied by unstable sources.

High equivalent input capacitance.Due to the fact that the capacitive matrix is usually

employed as a passive Sample & Hold in order to save power consumption, the inputsignal has to be load in the capacitive matrix at the beginning of the conversion. As this

input signal has to be amplified and filtered by a previous active block, this latter has to

load a very high capacitance, which means an increase in the power consumption.

High sensitivity towards parasitic capacitances. As it has been previously studied,parasitic capacitances can affect the performance of the capacitive-based DACs, so their

proper design can be complicated.

Due to the listed problems related to the design of the capacitive DACs for the SAR ADC

architectures, we introduce another architecture implemented using Swithed-Capacitor

Circuits (SC) and based on the Binary Search Algorithm.

The Binary Search Algorithm, which Flow Diagram is shown in Fig. 6a, is really the basis of

the Successive Approximation conversion principle. It begins with the sampled of the input

signal, which is compared with a certain threshold value. The result of this first comparison

will set the Most Significant Bit (MSB), and we will add or subtract (depending on the result

of the comparison) to the input value a certain reference voltage Vref. Then we will perform

again a new comparison, which will set the next bit, and after that we will add or subtract

the reference voltage divided by two. This iteration is successively repeated as many times

as bits to be converted, dividing by two the residual reference voltage each time. Then, after

n iterations, the residual value of the reference voltage that we add or subtract will be

/ 2nrefV .

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S&H

S&H 2

s

s

s

S+1

in

1

2

in+2

SAR

LOGIC

1

Vin

Vref

dout

VA

Vth

Vint

Vint(1)=Vshn=1

I f(Vint (n)0)

dout[N-n]=0Vint(n+1)=Vint(n)+Vref/

2n

dout[N-n]=1Vint(n+1)=Vint(n)-Vref/2

n

If(N=n)

End of Conversion

a)

b)

Fig. 6. Binary Search Algorith: a) Flow Diagram, b) Block Diagram schematic

s1

1

2

Vint

Vth

Vin1

: Sampling Period

Vin2

1 2 3 N4 # Clock

Period

s2

VA

Vref

Ibias Ibias/ 2 Ibias/ 4 IbiasIbias/ NOTA

bias

N+1

Fig. 7. Waveform of the Binary Search Algorithm implementation

Based on this algorithm, the block diagram of the proposed solution is presented in Fig. 6b.

It consists on a Sample&Hold, an integrator, a divider-by-two and some logic to implement

the Binary Search Algorithm. The evolution of the signals during a conversion for a certain

input Vinis shown in Fig. 7.

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2.4 Reconfigurable ADC based on SC techniquesBased on the block diagram of Fig. 6b, a Switched-Capacitor solution to implement the

desired ADC in presented in Fig. 8a. The proposed solution only uses one operational

amplifier in order to minimize as much as possible the power consumption (Rodriguez-

Perez el al., 2009).Fully-Differential operation reduces charge injection errors, makes easier the sum and

subtraction operations and allows rail-to-rail input swing. The scheme is reconfigurable in

terms of input gain (through programmable input capacitances Cvar), resolution (controlling

the number of performed iterations) and sampling frequency (through the frequency of the

input clock).

The current bias of the operational amplifier is also programmed depending on the chosen

configuration for the ADC in order to optimize the overall power consumed. Once a

configuration has been selected, this current is also dynamically controlled during the

conversion operation in order to adapt it to the residual reference voltage, which is smaller

each time. Fig. 7 illustrates how the bias current is successively adapted along the conversion.

The schematic of the S&H operation is shown in Fig. 8c. This operation is performed duringthe first three cycles of the conversion. During the first one, the fully-differential input signal

is stored on the programmable capacitor Cvar. The next two cycles are used to transfer the

stored charge on the integrator. This configuration is insensitive to parasitic capacitances

(Johns and Martin, 1997).

vcm

vcm

s1

s1

s2

s2

Vinn

vcm

vcm

Vrefp

Cint

Cint

vcm

s

2n

2

1

2p

1

Cin

C2C

1

s1

vcm

vcm

s1

s1

s2

s2

Vinp

vcm

vcm

Vrefn

vcm

s

2n

2

1

2p

1

Cin

C2C1

s1

2 Vcomp

Integrator

vcm

vcm

S

S

1

1

1

2Vcom

p

2Vcomp

2VcompVref

C1

C1

C2

C2

2

2

1

Divisor

Capacitors

ReferenceCapacitors

S

S in

in

Vin

vcm

vcm

vcm

vcm

Cvar

Cvar

in

in S

S

S1

S2

BoostingSwi tches Vari able

Capacitors Integrator

a)

b) c)

Fig. 8. Reconfigurable SC-based ADC: a) Schematic, b) Division-by-two, c) Programmable

Gain Amplifier S&H

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As the value of the capacitor Cvar is reconfigurable, this architecture can be used as a

Programmable Gain Amplifier, which is very useful for the biomedical interfaces as the

amplitude of the input signal can vary along time.

The reference voltage division is made capacitively as Fig. 8b shows. During the first

periods, the reference voltage is stored on the capacitor C1. After that, during phase 2, halfof the charge is transferred to capacitor C2 and it is either summed or subtracted to the

integrated value depending on the value of the signal Vcomp. During the phase1, capacitorC2is reset.

The schematic of the fully differential operational amplifier is shown in Fig. 9a. It follows a

folded-cascode architecture where the transistors M2 and M3 of the input differential pair

are biased in weak inversion in order to get the best /m Dg I ratio (Enz et al., 1995).

Transistors M1, M4, M5, M10 and M11, which are current mirrors, are biased in the

saturation region of strong inversion in order to improve their mismatch. The width of these

transistors can be programmed in order to get the dynamic bias control.

Vin+ Vin-

Vbn

Vcp

Vcmc

Vcn

Vbn

Vout- Vout+

M1

M2 M3

M4 M5

M6 M7

M8 M9

M10 M11

VbnMb

Adaptative

Ibias

a)

1

1

12

2

2

Vbp

Vcm

Vcm

Vcmc

Vout+

Vout-

b)

Fig. 9. a) Schematic of the folded-cascode opamp, b) SC common-mode feedback

The schematic of the capacitive common-mode control circuit in presented in Fig. 9b. This

circuit controls the common-mode voltage through the control of the gate voltage of

transistors M10 and M11 (Gray et al., 2001). The use of a capacitive-based configuration

allows the minimization of the power consumption.

3. Basic building blocks design

3.1 ComparatorThe comparator is a key block in any of the presented ADCs and one of the biggest power

consumers, so its design must be carefully done in order to optimize the power

consumption without a degradation in the performance of the ADC.

Many published SAR ADCs use a simple current-controlled dynamic latch as a comparator

(Scott et al., 2003, Zou et al., 2009). Although these solutions are very attractive because of

their low power consumption, they can present a DC offset of around 10mV due to the

mismatch of their input differential pair, which imply an offset error in the performance of

the ADC too. Considering that the circuit operates from rail-to-rail, this error means a loss in

the input range of the converter.

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in-

in+dynamic latch

OUT

Vref

Vref

in

in

inVin-

Vout

S1

S3

S6

S5

in

in

S2

Vin+in

S4

Fig. 10. Schematic of the comparator with an autozeroed pre-amplifierFig. 10 shows the schematic of the proposed comparator, which solves the offset problem.

The comparator consists on a fully differential pre-amplifier stage with a cancellation offset

scheme followed by a current-controlled dynamic-latch that boosts the pre-amplified

difference to the rails. The auto-zeroing is achieved by closing a unity gain loop around it

and storing the offset voltage on the input capacitors (Rodriguez-Perez et al., 2009). The gain

of the pre-amplifier should be high enough in order to save the input voltage offset of the

dynamic-latch.

VinVip

Vbpc

q

Von Vop

M1

M2 M3

Mq

M4 M5

Vbnc

a)

b)

in-in+

Vbn

out-out+

ss

M1

M2 M3

M4 M5

s

Vbn Vbn

Fig. 11. a) Schematic of the pre-amplifier, b) Schematic of the dynamic-latch

The schematic of the pre-amplifier is shown in Fig. 11a. It is a single differential pair with a

SC-based common-mode control circuit. In order to maximize the transconductance of the

input differential pair and their matching, transistors M2 and M3 work in weak inversion.

The rest of the transistors, which work as current mirrors, are in the saturation region to

improve their matching.

The schematic of the dynamic-latch is presented in Fig. 11b. It is formed by an input

differential pair which imbalances a pair of cross-coupled inverters, creating a positive

feedback that boost the outputs to the rails. Current-controlled digital buffers are connected

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at the outputs before an RS latch that gives the digital single-ended output of the

comparator.

In order to optimize the power consumption of the comparator, the minimum required bias

current for the pre-amplifier has to be evaluated. The design of the pre-amplifier will

depend on the minimum input voltage needed at the input of the dynamic latch tocounteract the offset voltage. It means that the dynamic gain of the pre-amplifier must be:

1

2

2latchlatch

off Npre offLSB

VA V+> = , (14)

wherelatchoff

V is the offset voltage of the dynamic latch and N is the required resolution.

Considering that the dynamic gain of the pre-amplifier for a period TSis approximated by:

Spre m

TA g

C= (15)

where Cprepresents the parasitic capacitance at the output of the pre-amplifier, andgmthe

transconductance of the input transistors.

Following theEKVmodel (Enz et al., 1995), the /m Dg I expression for MOS transistors valid

for all regions is given by:

1 2

1 1 4

m

D T

g

I n U IC=

+ + , (16)

where n is the slope factor, UT is the thermal voltage and IC is the inversion coefficient,

given by:

( )2 'D

Wox TL

IIC

n C U= . (17)

Depending on the value of this coefficient, the transistor will work in weak inversion

( 0.1IC< ), moderate inversion ( 0.1 10IC< < ), or strong inversion ( 10IC> ). To obtain theoptimum /m Dg I ratio, we will dimension the transistors to work in weak inversion.

Then, considering equations (14)-(16) we have that:

( )12 1 1 42

Noffset T

DS

V nU IC

I T

+ + +

> (18)

For a standard technology, normal values are n=7, UT=27mV, Cp=250fFand IC=0.1. Using

this values and the needed sampling frequency in equation (18) gives us the minimum

required bias current for the pre-amplifier.

3.2 Boosted switchIn order to get rail-to-rail input voltage swing, the input switch must be boosted in order to

avoid a degradation of the signal due to the dependence of the switch resistance with the

input voltage, especially when the input frequency is near to Nyquist.

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s

Ms

s

s

Vdd

V1 V2

b

b

M1

M2 M3

Cb

M4M5

M6

M7

M8

M9

Fig. 12. Schematic of the boosting switch

The schematic of the boosted switch is shown in Fig. 12 (Dessouky and Kaiser, 1999). The

circuit works as follows. When sw=0, the supply capacitor Cbis charged to VDD-Vthp. In the

next phase, when swswitches on, this stored value is added to the input voltage to set the

gate voltage swof the input switch,MS, which ensures a constant conductance of the input

transistor during the sampling phase.

3.3 SAR logicThe Successive Approximation algorithm starts with the activation of the MSB while the

others remain to zero. While the conversion is running, the rest of the bits are successivelyactivated, while the value of the one who was activated just before will depend on the result

of the comparator.

The schematic of the logic that implements the Successive Approximation operation is

shown in Fig. 13a.

This architecture is based on the dependency of the state of each bit with the others bits state

(Rossi and Fucili, 1996). Each bit evaluates the state of the others and in function of the

result, it decides either it has to be activated, keeps its value, or take the value of the

comparator.

The logic is implemented using a cascade of N+1 multiple input shift registers (Fig. 13b).

Through a multiplexer and a decoder, each register (kth) can choose three data inputs coming

from: the output of the (k+1)thflip-flop, the output of the comparator or itself output. Thisselection will depend on itself state and the state of the following registers states.

With only 11 flips-flops to complete a 10-bits conversion, this architecture consumes nearly a

forty percent less than others more popular (Anderson, 1972), which need 22 flip-flops to

perform the same operation.

3.4 Current reference generator circuitIn order to generate on-chip the bias current needed for the active blocks, some current

reference generator cell is needed. The non-resistance Oguey based cell shown in Fig. 14 is a

good solution.

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Ak

cmpshift

k

Ak

cmpshift

k

Ak

cmpshift

k

Ak

cmpshift

k

set rst rst rst

D1

D0

Dn-1

Dn

rstcomp

D Q

clk

AB

cmp

shift

Ak

clk

k

MUX LOGIC

A B OUT

0 0 shift

0 1 cmp

1 - k

a)

b)

Fig. 13. Schematic of the Succesive Approximation Logic

The cell is based on the circuit presented in (Oguey and Aebischer, 1997), where the resistor

has been replaced by an nMOS transistor working below saturation. The added transistors

M2 and M1 provide the gate voltage for M3.

The generated current reference Iref is given by:

( ) ( )( )22 2

3 2 2 2 1

1, 1 ln

2ref n T eff eff I n V K K K K K K

= = +

(19)

where 4 716 5

M M

M M

S SK

S S= and 3 22

1 5

M M

M M

S SK

S S= , being MxS the W/Lratio of the transistorMx.

It is also important to include a start-up circuit to the current reference circuit in order to

bring out the reference circuit from a zero current operation point to its normal operation

point, like the presented in Fig. 14. It also provides the possibility of leaving the circuit on a

standby mode (Mandal et al., 2006).

4. Simulation and experimental results

In order to validate the theoretical study done along the chapter, two different designs have

been implemented and validated.

4.1 A 1-V, 10-bit, 2kS/s SAR ADC with a BWAC architecture capacitive DACThe SAR ADC was implemented in a 0.35um CMOS standard technology with a resolution

of 10-bit, 2kS/ s of sampling frequency and 1-V of voltage supply. It uses a BWAC

architecture for the implementation of the capacitive-based DAC.

The layout of the ADC can be seen in Fig. 15.

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M1

M2

M3

M4

M5

M6

M7

pwd_down

start-up circuit

Fig. 14. Schematic of the current reference and start-up circuit

SAR LOGIC

&

PHASE GENERATOR

CAPACITIVE

DACCOMPARA

TOR

&

CURRENTREF

ERENCE

BOOSTING

SWITCH

Fig. 15. Layout of the SAR ADC with capacitive DAC

Table 1 summarises the measured results of the integrated SAR ADC for the nominal

conditions. The Equivalent Number of Bits (ENOB) is defined as:

1.76

6.02

SNDRENOB

= (20)

Fig. 16 shows the 8192-samples FFT of the ADC output response for a 140-Hz sinusoidal

input signal of 1-V amplitude sampled at 2kHz at 1-V supply. The Signal to Noise

Distorsion Ratio (SNDR) of 58.39dB, which gives a ENOB of 9.41-bits.

Fig. 16a compares the performance of the circuit for different input frequencies, supply

voltages and sampling frequencies configurations. As can be extracted from the given

graph, the ADC can work under a high range of supply voltages. This is extremely

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Technology CMOS 0.35m

Nominal Voltage Supply 1-V

Input Voltage Range Rail-to-Rail

Nominal Resolution 10-bits

Sampling Frequency 2kS/ s 8kS/ s

SNDR(300Hz Input tone) 58.40dB

ENOB(300Hz Input tone) 9.4-bits

INL < 0.8LSB

DNL -0.7


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Fig. 17. Evolution of the resolution of the ADC with the input frequency for different voltage

supplies under different sampling frequencies: a) 2kS/ s, b) 4kS/ s, c) 6kS/ s, d) 8kS/ s

should affect the behaviour of the ADC, degrading its resolution and linearity. This was

validated in the experimental measurements, as Fig. 18 illustrate. The solution that included

dummies presented higher harmonics than the other. Also, the parasitic capacitances

introduced by the dummies capacitors induce higher errors in the INL and DNL than those

due to the mismatch of the unitary capacitors of the capacitive array.

These linearity errors induce losses of more than 0.2-bits ENOB, as was predicted by the

post-layout simulation results.

Fig. 18. Comparison of performance of the SAR ADC with and without dummies: a) FFT-

response, b) INL and DNL

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4.2 A 1.2-V, 10-bit reconfigurable SC-based ADCThe Reconfigurable ADC based on a Binary Search Algorithm with SC techniques was

designed in a standard CMOS 130nm technology. The ADC is reconfigurable in terms of

input gain (from 0.5 to 4 by means of 2-bits) and sampling frequency (from 10kS/ s to

100kS/ s). The power consumption is adapted to the chosen configuration in order tooptimize it, and varies between 200nW to 2uW.

SAR LOGIC &

CLOCK PHASE GENERATOR

CAPACITOR ARRAY

ADAPTATIVE

OPAMP

BIASING

OPAMP

DYNAMIC

LATCH

Fig. 19. Layout of the SC-based ADC

The layout of the complete ADC is presented in Fig. 19. It occupies an area of 190um x 225um.

Technology CMOS 0.13m

Nominal Voltage Supply 1.2-V

Input Voltage Range Rail-to-Rail

Nominal Resolution 10-bits

Sampling Frequency 10kS/ s 100kS/ s

SNDR 60.76dB

ENOB 9.8-bits

Power consumption

10kS/ s

100kS/ s

200nW

2uW

Area occupation 0.043mm2

Table 2. Performance summary of the SC-based ADC

Post-layout simulations with Process, Voltage and Temperature (PVT) variations were

performed to validate the design. Table 2 summarises the main characteristics of the ADC,

while Fig. 20a and Fig. 20b present the FFT-spectrum response for small and Nyquist

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sinusoidal inputs frequencies sampled at 20kS/ s and 90kS/ s, respectively. Simulation

results show a SNDR of 60.76dB, which gives an ENOB of 9.8-bits.

0 5 10 15 20 25 30 35 40 45

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Frequency(kHz)

Magnitude(dB)

InputFrequency=42kHz

InputFrequency=1.2kHz

0 2000 4000 6000 8000 10000-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Frequency(Hz)

Magnitude(dB)

InputFrequency=10.5kHz

InputFrequency=305Hz

b)a)

Fig. 20. FFT-response of the SC-based ADC for small and Nyquist frequency sinusoidal

inputs sampled at: a) 20kS/ s, b) 90kS/ s.

5. Conclusions

This chapter have introduced the main concepts concerning to the design of ADC for

biomedical interfaces, where two main architectures have been studied, concluding with the

presentation and results of some real implementations.

The chapter has studied the most important design concerns of the Successive

Approximation Architecture with capacitive DACs, one of the most popular ones. This

architecture is very useful in a biomedical contest due to its low area and low power

consumption. However, the implementation of this structures can derivate some problems

related to their high sensitivity to parasitic capacitances and their high area and switchingenergy demand, especially when the resolution became higher than 8-bits.

The presented example includes a 10-bit SAR ADC with a capacitive-based DAC using a

Binary Weighted Array with an attenuation capacitor to reduce the size of the matrix. The

importance of the parasitic capacitances effect over other non-idealities was shown by

means of two different implementations, one using a capacitive array with dummies an

another one without them. As the first one presented more parasitic capacitances,

experimental results showed that its performance was more degraded than in the case of the

second one implementation without dummies, unless the mismatch of this latter was worse.

Due to some of the drawbacks of the of the SAR architecture, we have introduced in this

chapter another proposal based on the Binary Search Algorithm too, but using an

implementation based on SC-techniques. This architecture results highly flexible as it can be

easily reconfigured in terms of resolution, sampling frequency and input gain. Also, the area

occupation and switching power demand is dramatically reduced due to the elimination of

the big capacitive arrays needed in the SAR capacitive DACs based architectures.

6. References

Anderson, T. O. (1972). Optimum control logic for successive approximation A-D

converters. Computer Design, vol. 11, no. 7, July 1972, pp. 81-86.

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Agnes, A.; Bonizzoni, P. ; Malcovati, P. and Maloberti, F. (2008). A 9.4-ENOB 1V 3.8uW

100kS/ s SAR ADC with Time-Domain Comparator,Proceedings of International

Solid-State Circuits Conference, pp. 246-247, San Francisco, February 2008.

Cong, L. (2001). Pseudo C-2C Ladder-Based Data Converter Technique.IEEE Transactions on

Circuits and Systems II, vol. 48, no. 10, October 2001, pp. 927-929.Dessouky, M. and Kaiser, A. (1999). Input switch configuration suitable for rail-to-rail

operation of switched opamp circuits.Electronic Letters, vol. 35, January 1999, pp. 8-

10.

Enz, C. C. ; Krummernacher, F. and Vittoz, E. A. (1995). An Analytical MOS Transistor

Model Valid for All Regions of Operation and Dedicated to Low-Voltage Low-

Current Applications.Analog Integrated Circuits and Signal Processing Journal, vol. 8,

July 1995, pp. 83-114.

Gray, P. R. ; Hurst, P. J. ; Lewis, S. L. and Meyer, R. G. (2001). Analog Design of Analog

Integrated Circuits, 4th Edition. John Wiley & Sons, ISBN 0-471-32168-0, New York,

USA.

Harrison, R. R. ; Watkins, P. T. ; Kier, R. J. ; Lovejoy, R. O. ; Black, D. J. ; Greger, B. and

Solzbacher (2007). A Low-Power Integrated Circuit for Wireless 100-Electrode

Neural Recording System.IEEE Journal of Solid-State Circuits, vol. 42, no. 1, January

2007, pp. 123-132.

Hong, H. C. and Lee, G. M. (2007). A 65fJ/ Conversion-Step 0.9-V 200kS/ s Rail-to-Rail 8-bit

Successive Approximation ADC.IEEE Journal of Solid-State Circuits, vol. 42, October

2007, pp. 2161-2168.

Johns, D. and Martin, K. (1997).Analog Integrated Circuit Design. John Wiley & Sons, ISBN

0471144487, New York, USA.

Maloberti, F. (2007). Data Converters. Springer Publishers, ISBN 0-387-32485-2, Dordrecht,

The Netherlands.

Mandal, S. ; Arfin, S. and Sarpeshkar, R. (2006). Fast Startup CMOS Current References,

Proceedings of International Symposium on Circuits and Systems, pp. 2845-2848, Greece,

May 2006.

Northrop, R. B. (2001), Non-Invasive Instrumentation and Measurements in Medical Diagnosis.

CRC Press LLC, ISBN 0-8493-0961-1, Boca Raton, Florida.

Northrop, R. B. (2004), Analysis and Application of Analog Electronic Circuits to Biomedical

Instrumentation. CRC Press LLC, ISBN 0-8493-2143-3, Boca Raton, Florida.

Oguey, H. J. and Aebischer, D. (1997). CMOS Current Reference Without Resistance.IEEE

Journal of Solid-State Circuits, vol. 32, no. 7, July 1997, pp. 1132-1135.

Rodriguez-Perez, A. ; Delgado-Restituto, M. ; Medeiro, F. and Rodriguez-Vazquez, A.

(2009). A low-power Reconfigurable ADC for Biomedical Sensor Interfaces,Proceedigns of Biomedical Circuits and Systems Conference, pp. 253-256, Beijing,

November 2009.

Rodriguez-Perez, A. ; Delgado-Restituto, M. and Medeiro, F. (2010). Impact of parasitic

capacitances on the performance of SAR ADCs based on capacitive arrays,

Proceedings of Latin-American Symposium on Circuits and Systems, Iguaz, February

2010.

Rossi, A. and Fucili, G. (1996). Nonredundant successive approximation register for A/ D

converters.Electronic Letters, vol. 32, no. 12, June 1996, pp. 1055-1057.

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Sauerbrey, J. ; Schmitt-Landsiedel, D. and Thewes, R. (2003). A 0.5-V 1-uW Successive

Approximation ADC.IEEE Journal of Solid-State Circuits, vol. 38, July 2003, pp. 1261-

1265.

Scott, M. D. ; Boser, B. E. and Pister, K. S. J. (2003). An ultralow-energy ADC for smart dust.

IEEE Journal of Solid-State Circuits, vol. 38, July 2003, pp. 1123-1129.Verma, N. and Chandrakasan, A. P. (2007). An Ultra Low Energy 12-bit Rate-Resolution

Scalable SAR ADC for Wireless Sensor Nodes. IEEE Journal of Solid-State Circuits,

vol. 42, June 2007, pp. 1196-1205.

Zou, X. ; Xu, X. ; Yao, L. and Lian, Y. (2009). A 1-V 450-nW Fully Integrated Programmable

Biomedical Sensor Interface Chip.IEEE Journal of Solid-State Circuits, vol. 44, no. 4,

April 2009, pp. 1067-1077.

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Biomedical Engineering, Trends in Electronics, Communications

and Software

Edited by Mr Anthony Laskovski

ISBN 978-953-307-475-7

Hard cover, 736 pages

Publisher InTech

Published online 08, January, 2011

Published in print edition January, 2011

InTech Europe

University Campus STeP RiSlavka Krautzeka 83/A

51000 Rijeka, Croatia

Phone: +385 (51) 770 447

Fax: +385 (51) 686 166

www.intechopen.com

InTech China

Unit 405, Office Block, Hotel Equatorial ShanghaiNo.65, Yan An Road (West), Shanghai, 200040, China

Phone: +86-21-62489820

Fax: +86-21-62489821

Rapid technological developments in the last century have brought the field of biomedical engineering into a

totally new realm. Breakthroughs in materials science, imaging, electronics and, more recently, the information

age have improved our understanding of the human body. As a result, the field of biomedical engineering is

thriving, with innovations that aim to improve the quality and reduce the cost of medical care. This book is the

first in a series of three that will present recent trends in biomedical engineering, with a particular focus on

applications in electronics and communications. More specifically: wireless monitoring, sensors, medical

imaging and the management of medical information are covered, among other subjects.

How to reference

In order to correctly reference this scholarly work, feel free to copy and paste the following:

Alberto Rodrguez-Prez, Manuel Delgado-Restituto and Fernando Medeiro (2011). Power Efficient ADCs for

Biomedical Signal Acquisition, Biomedical Engineering, Trends in Electronics, Communications and Software,

Mr Anthony Laskovski (Ed.), ISBN: 978-953-307-475-7, InTech, Available from:

http://www.intechopen.com/books/biomedical-engineering-trends-in-electronics-communications-and-

software/power-efficient-adcs-for-biomedical-signal-acquisition

power efficient adcs

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