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Thermoreectance mapping observation of Power MOSFET under UIS avalanche breakdown condition Koichi Endo a,e , Kenji Norimatsu b , Tomonori Nakamura d , Takashi Setoya c , Koji Nakamae e a Semiconductor & Storage Products Company, Toshiba Corporation, 300, Ikaruga, Taishi-cho, Ibo-gun, Hyogo 671-1595, Japan b Semiconductor & Storage Products Company, Toshiba Corporation, 800, Yamanoisshiki-cho, Yokkaichi City, Mie 512-8550, Japan c Semiconductor & Storage Products Company, Toshiba Corporation, 1-1-1, Shibaura, Minato-ku, Tokyo 105-8001, Japan d System Division, Hamamatsu Photonics K.K., 812, Joko-cho, Higashi-ku, Hamamatsu City, Shizuoka 431-3196, Japan e Dept. Information Systems Engineering, Grad. Sch. Information Science and Technology, Osaka University, 2-1, Yamada-oka, Suita City, Osaka 565-0871, Japan abstract article info Article history: Received 25 May 2015 Received in revised form 20 June 2015 Accepted 21 June 2015 Available online xxxx Keywords: MOSFET Thermoreectance Avalanche breakdown Electro optical frequency mapping Electro optical probing In this study, we investigated the temperature variation of the top surface image of power MOSFET under UIS condition, measured by the optical probed thermo-reectance image mapping (OPTIM) (using electro optical frequency mapping: EOFM). The measured data obtained by the thermoreectance mapping was found to be sensitive to changes in temperature rather than the temperature distribution. These results suggest that the thermoreectance mapping method has higher measuring ability of heat generation distribution, since it has higher time-resolution than that of thermography. © 2015 Published by Elsevier Ltd. 1. Introduction In recent years, there has been an increase in the applications of power devices, such as metal-oxide semiconductor eld-effect transis- tors (MOSFETs) and insulated-gate bipolar transistors (IGBTs), in the automotive industry. As the destruction of devices may lead to serious accidents, semiconductor devices are required to have high reliability. For these applications, power devices drive large inductive loads, and the current and voltage uctuate signicantly. Power devices can be damaged with melting beyond their thermal limitation because of the power consumption during avalanche breakdown or overcurrent appli- cations. However, it is difcult to identify the root cause of the damage by performing only physical analyses because the structure and compo- sition of the destruction point would have been signicantly changed by the thermal melting. In order to identify these root causes of destruction and to investi- gate their associated mechanisms, we require an observation method for which abnormal operation and the causes of failures are investigated prior to destruction. To estimate the cause of destruction, the tempera- ture distribution measurement on the surface of the device and the cur- rent distribution measurement in the device are effective. By detecting abnormal points or differences during a comparison of these measured data and device design values obtained by simulations, we can under- stand the mechanisms that lead to the destruction. In this study, we pro- pose a technique which can evaluate the temperature behaviour of power devices with high time-resolving power. When high energy consumption is required to drive an inductive load, the temperature of the device rises and there is an increased emis- sion of infrared rays. Several techniques which measure the infrared (IR) light and determine the temperature distribution and changes on the device surface have been reported [1]. Previously, we reported an equivalent-time sampling technique using an IR thermography camera which has a 35 μm sensitivity range as a method to measure the temperature behaviour of power devices before destruction [2]. In addition, observations of the temperature changes obtained using the reectance temperature dependency (thermoreectance) have been reported [4,5]. However, passive thermographic techniques have limitations in terms of their time-resolving power, and the ability to understand the distribution of changes in the temperature caused by external bias. In addition, the time and spatial resolving power are insufcient to obtain data that enables us to adequately compare the temperature distribu- tion and behaviour based on numerical simulations [3]. With active measuring methods, it is possible to measure temperature changes using the thermoreectance, and this enables us to observe the behav- iour of the heat source neighbourhood. In this study, we investigated the temperature variation of an image of the surface of a power MOSFET under unclamped inductive switching Microelectronics Reliability xxx (2015) xxxxxx E-mail address: [email protected] (K. Endo). MR-11580; No of Pages 6 http://dx.doi.org/10.1016/j.microrel.2015.06.031 0026-2714/© 2015 Published by Elsevier Ltd. Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr Please cite this article as: Endo K, et al, Thermoreectance mapping observation of Power MOSFET under UIS avalanche breakdown condition, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.031

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Page 1: Thermoreflectance mapping observation of Power MOSFET ...homepages.laas.fr/nolhier/ESREF2015/SESSION_C/PC_6.pdf · Power-device circuits are not designed to be under UIS condition

Microelectronics Reliability xxx (2015) xxx–xxx

MR-11580; No of Pages 6

Contents lists available at ScienceDirect

Microelectronics Reliability

j ourna l homepage: www.e lsev ie r .com/ locate /mr

Thermoreflectance mapping observation of Power MOSFET under UIS avalanchebreakdown condition

Koichi Endo a,e, Kenji Norimatsu b, Tomonori Nakamura d, Takashi Setoya c, Koji Nakamae e

a Semiconductor & Storage Products Company, Toshiba Corporation, 300, Ikaruga, Taishi-cho, Ibo-gun, Hyogo 671-1595, Japanb Semiconductor & Storage Products Company, Toshiba Corporation, 800, Yamanoisshiki-cho, Yokkaichi City, Mie 512-8550, Japanc Semiconductor & Storage Products Company, Toshiba Corporation, 1-1-1, Shibaura, Minato-ku, Tokyo 105-8001, Japand System Division, Hamamatsu Photonics K.K., 812, Joko-cho, Higashi-ku, Hamamatsu City, Shizuoka 431-3196, Japane Dept. Information Systems Engineering, Grad. Sch. Information Science and Technology, Osaka University, 2-1, Yamada-oka, Suita City, Osaka 565-0871, Japan

E-mail address: [email protected] (K. Endo).

http://dx.doi.org/10.1016/j.microrel.2015.06.0310026-2714/© 2015 Published by Elsevier Ltd.

Please cite this article as: Endo K, et al, TherMicroelectronics Reliability (2015), http://dx

a b s t r a c t

a r t i c l e i n f o

Article history:Received 25 May 2015Received in revised form 20 June 2015Accepted 21 June 2015Available online xxxx

Keywords:MOSFETThermoreflectanceAvalanche breakdownElectro optical frequency mappingElectro optical probing

In this study, we investigated the temperature variation of the top surface image of power MOSFET under UIScondition, measured by the optical probed thermo-reflectance image mapping (OPTIM) (using electro opticalfrequency mapping: EOFM). The measured data obtained by the thermoreflectance mapping was found to besensitive to changes in temperature rather than the temperature distribution. These results suggest that thethermoreflectance mapping method has higher measuring ability of heat generation distribution, since it hashigher time-resolution than that of thermography.

© 2015 Published by Elsevier Ltd.

1. Introduction

In recent years, there has been an increase in the applications ofpower devices, such as metal-oxide semiconductor field-effect transis-tors (MOSFETs) and insulated-gate bipolar transistors (IGBTs), in theautomotive industry. As the destruction of devices may lead to seriousaccidents, semiconductor devices are required to have high reliability.For these applications, power devices drive large inductive loads, andthe current and voltage fluctuate significantly. Power devices can bedamaged with melting beyond their thermal limitation because of thepower consumption during avalanche breakdown or overcurrent appli-cations. However, it is difficult to identify the root cause of the damageby performing only physical analyses because the structure and compo-sition of the destruction pointwould have been significantly changed bythe thermal melting.

In order to identify these root causes of destruction and to investi-gate their associated mechanisms, we require an observation methodforwhich abnormal operation and the causes of failures are investigatedprior to destruction. To estimate the cause of destruction, the tempera-ture distributionmeasurement on the surface of the device and the cur-rent distribution measurement in the device are effective. By detectingabnormal points or differences during a comparison of these measured

moreflectance mapping obse.doi.org/10.1016/j.microrel.2

data and device design values obtained by simulations, we can under-stand themechanisms that lead to thedestruction. In this study,we pro-pose a technique which can evaluate the temperature behaviour ofpower devices with high time-resolving power.

When high energy consumption is required to drive an inductiveload, the temperature of the device rises and there is an increased emis-sion of infrared rays. Several techniques which measure the infrared(IR) light and determine the temperature distribution and changes onthe device surface have been reported [1]. Previously, we reported anequivalent-time sampling technique using an IR thermography camerawhich has a 3–5 μm sensitivity range as a method to measure thetemperature behaviour of power devices before destruction [2]. Inaddition, observations of the temperature changes obtained using thereflectance temperature dependency (thermoreflectance) have beenreported [4,5].

However, passive thermographic techniques have limitations interms of their time-resolving power, and the ability to understand thedistribution of changes in the temperature caused by external bias. Inaddition, the time and spatial resolving power are insufficient to obtaindata that enables us to adequately compare the temperature distribu-tion and behaviour based on numerical simulations [3]. With activemeasuring methods, it is possible to measure temperature changesusing the thermoreflectance, and this enables us to observe the behav-iour of the heat source neighbourhood.

In this study, we investigated the temperature variation of an imageof the surface of a powerMOSFET under unclamped inductive switching

rvation of Power MOSFET under UIS avalanche breakdown condition,015.06.031

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Fig. 1. (a) Cross-section schematic of planer-type power MOSFET, (b) Top-view image ofchip.

Fig. 2. Block diagram of OPTIM.

2 K. Endo et al. / Microelectronics Reliability xxx (2015) xxx–xxx

(UIS) conditions, as measured by the thermoreflectance mapping. Weperformed measurements using the system of electro optical probing(EOP), and they were obtained using a two-dimensional (2D) detectorwith a conventional approach.

Fig. 3. Drain-source voltage Vdss characteristic

Please cite this article as: Endo K, et al, Thermoreflectance mapping obseMicroelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2

2. Method

The proposed method involves observation of the temperaturechange based on changes in the reflectance, and it is widely known asthe thermoreflectance method [4,5]. The variation of temperature andreflectance is expressed by the following formula [6]:

ΔRR

¼ 1R∂R∂T

ΔT ¼ κΔT:

In the thermoreflectance method, the temperature change is deter-mined by measuring the normalized variation of the optical reflectioncoefficient on the device surface.

Fig. 1 shows the cross-section and top-view images of the power de-vice considered in this study. The power device chip hasmetal electrodelayers on both surfaces, and this serves the purpose of driving a highcurrent. Because of the low emissivity and high reflectance of themetal, the thermoreflectance method has the possibility to realize ahigher sensitivity than the thermography method.

In this study, we used an emission microscope iPHEMOS and EOPunit [7] that were made by Hamamatsu Photonics Corporation. TheEOP unit has high-speed sampling capabilities over a range of severalGHz,which enables tomeasure the LSI switching time. EOP is conductedwith laser irradiation from the backside of the chip, and observes varia-tion of reflectance due to the status of transistor. We use this functionfor observing the reflectance change of the surface metal. We obtainedthe distribution of the reflectance change using a function of the electrooptical frequency mapping (EOFM) of the instrument. We call this ob-servationmethod the optical probed thermoreflectance imagemapping(OPTIM). Fig. 2 shows a block diagram.

Generally, the reflection intensity of light depends on the roughnessof metal layer surface the absorption factor of the protective films suchas polyimide. However, the surface state of the chip does not almost in-fluence an observation result if the light strength is enough, becauseOPTIM measures the reflectance change. In the case of low sensitivity,laser power should be controlled in the range that does not affect thetemperature of the sample.

Power-device circuits are not designed to be under UIS conditionduring normal use to drive inductive loads such as motors. However,UIS is a simple condition that is used to produce large temperaturechanges on power device. For this reason, in this study, we used theUIS condition for the observation of temperature changes in powerdevices.

s of samples. (a) Normal, (b) Leak failure.

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Fig. 4. Circuit diagram for themeasurement of the distribution of the leakage current withlock-in thermography.

Fig. 6. Switching waveform of MOSFET under UIS condition. Vds = 100 V/div, Id =200 mA/div, Vgs = 10 V/div, time = 400 ns/div.

3K. Endo et al. / Microelectronics Reliability xxx (2015) xxx–xxx

The surface temperature of power devices vary mainly as a result ofthe propagation of heat generated in Si under avalanche breakdowncaused by heat conduction. This temperature change due to heat con-duction is of the order of several micro seconds, and the instrumentshave sufficient time-resolving power. We observed the distribution ofthermoreflectance by performing scanning laser beam and mapping.In this report, we present an evaluation of the use of thermographyfor comparison with the thermoreflectance results.

3. Experiment

The samples used in this study were simple planar-type N-channelMOSFETs. The measured chips were assembled on a ceramic substrateand connected using Al wire bonding. The electrical characteristics ofthe sample are as follows: withstand voltage between the drain andsource Vdss N 600 V, maximum drain current Id(max) = 10 A, and ava-lanche current IAR = 10 A. The physical data of the chip are as follows:chip size = 4.7 × 4.7 mm, surface metal = ~4 μm thick aluminium,and top polyimide layer = 3–5 μm.

OPTIM uses a 1.3 μm wavelength continuous wave laser. The poly-imide patterning was not effective to the strength of reflected light, be-cause the 1.3 μmwavelength absorption factor of polyimide on this chipwas not so high. In this experiment no revision of data was applied. Onthe other hand, the 3–5 μm wavelength absorption was not negligible,so the thermography image shows the polyimide pattern. However, al-most areas of the chip were observed under a condition, so we didn'tapply the data correction.

In this paper, we present the data for two samples. Fig. 3 shows thedrain-source voltage Vdss characteristics of these samples. In Fig. 3(a),the leakage current at the withstand voltage is less than 10 nA. InFig. 3(b), there are ‘soft leak’ characteristics and the leakage current at650 V is over 5 μA. However, the latter sample can be operated underUIS conditions.

Fig. 5. Circuit diagram with power MOSFET under UIS condition.

Please cite this article as: Endo K, et al, Thermoreflectance mapping obseMicroelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2

First, we applied high-voltage lock-in thermography (LIT) to deter-mine the area within which the leakage current flows. The leakage cur-rent distribution, which depends on the applied voltage, is equal to thedistribution of the withstand voltage. Fig. 4 shows the circuit diagramfor the measurement of the distribution of the leakage current usingLIT. The 10Hz lock-in voltagewas applied between the drain and sourceunder the condition where the voltage between the gate and sourceVgs = 0 V. In this experiment, we used 10% on-duty pulse to suppressthe temperature rise.

Next, we measured the IR light intensity distribution on the surfaceof the MOSFET under UIS conditions using a 2D LIT camera and equiva-lent time sampling technique [2]. The integration timewas 50 μs and cu-mulative cycle was 1000 times.

Fig. 5 shows the UIS bias circuit for the condition where the powerdevice experiences a temperature change. It is a simple circuit for induc-tive switching. When a sufficient current flows through the inductorunder the on state of the MOSFET, there is an avalanche breakdown in-side the device when the MOSFET is turned off.

Finally, we measured the change in the thermoreflectance using theOPTIM. In order to detect the signal indicating the change of reflectance,a high-frequency trigger signal is required. In addition, high-speed ob-servation can detect changes in the heat distribution that are due toheat conduction. In this experiment, we used a 10-kHz outer trigger sig-nal to enable the gate pulse to make repetitive avalanche breakdown,and to obtain synchronization signals from the measurement instru-ment. Because a repetitive avalanche condition of 10 kHz representedthe high load condition, the drain electric current in this experimentwas applied at less than 10% of the maximum rating specification toavoid thermal destruction. The value of the inductive load was 2 mH.Therefore, as shown in Fig. 6, the avalanche breakdown was finishedin a short time. However, the temperature changes were sufficient toenable us to examine the technique in order to understand the behav-iour of the temperature distribution on the surface of the power device.

In this experiment, we used a 1.3 μmwavelength 180 mW continu-ous laser. Themagnification of the lenswas 2.5 times. The laser spotwas

Fig. 7. Distribution image of withstand voltage on the normal sample in Fig. 3(a).

rvation of Power MOSFET under UIS avalanche breakdown condition,015.06.031

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Fig. 8. Distribution image of withstand voltage on leakage failure sample in Fig. 3(b).

4 K. Endo et al. / Microelectronics Reliability xxx (2015) xxx–xxx

circular and about 70 μm diameter on the sample surface. And laserpower in the terminal part of the lens was about 4.5 mW.

Fig. 9. Mid IR emission image of the leakage failure sample measured using equivalent-time sampling method.

4. Results

Figs. 7 and 8 show the withstand voltage distributions as measuredby high-voltage LIT. In these figures, the colour charts are normalizedusing the highest amplitude value of IR light for each applied voltagecondition.

The normal sample in Fig. 3(a) shows the IR signal only in its outerperipheral part.

The leakage failure sample in Fig. 3(b) shows a significant distribu-tion pattern in the withstand voltage. Below 300 V, there is a spike inthe LIT signal. Over 600V, as the leakage current increases, the LIT signalappears to be linear, and its amplitude also increases. The leakage line isroughly in the b410 N line direction. There are high IR amplitude areason the edge of the device along the leakage line.

Next, we measured the IR light intensity distribution using a ther-mography camera under repetitive UIS conditions. The UIS bias circuitis shown in Fig. 5, for conditions of L = 2 mH, I (peak) = 400 mA, and100 Hz. The equivalent-time sampling method [2] was applied for thismeasurement.

Please cite this article as: Endo K, et al, Thermoreflectance mapping obseMicroelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2

The IR light intensity distribution pattern of the leakage failure sam-ple was detected, as shown in Fig. 9 under repetitive UIS conditions(L= 2mH,Il (peak)= 400mA, 100 Hz). The area coloured from yellow

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Fig. 10. Phase and I/Q image data obtained using the thermoreflectance method.(a) Normal sample. (b) Leakage failure sample.

5K. Endo et al. / Microelectronics Reliability xxx (2015) xxx–xxx

to red shows the high intensity of the emitted light. There is a high IRemission area along the leakage line.

Then,wemeasured the IR light intensity deviation distribution usingOPTIM. The data obtained at a specific time are shown in Figs. 10. Thefigures on the left side show the phase images, which are equivalentto the delay from a trigger signal, and the figures on the right sideshow I/Q images expressed by the following equation.

IQ ¼ A � cos 2π f t þ φð Þ

where A is the amplitude, f is the frequency, andφ is the phase. The bluecoloured dots in phase image and white dots in I/Q image indicate thatthere is a large deviation in the reflectance. In the leakage failure sam-ple, there is a large deviation area of the reflectance along a leak lineas in the thermography result. There is no expansion area around theedge of the chip, when compared with the IR light emission data ofFig. 9.

Fig. 11. Time-dependency shift of thermoreflectance deviation peak. Blue solid line (L): peak ofPAD, orange dotted line (N): Base line for comparison.

Please cite this article as: Endo K, et al, Thermoreflectance mapping obseMicroelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2

Fig. 11 shows the I/Q data for the leakage failure sample at 26.2 μsand 52.3 μs after the trigger signal. The blue solid line is a line for thepeaks of the thermoreflectance I/Q deviation value. The peak line inthe b410N line direction is the same as the LIT data and the obtainedthermography data. In this case, the difference is that the position ofthe peak has shifted. From the data, the speed of motion of this line is4.49 μm/μs as an ingredient to the vertical directions of this line.

5. Discussion

By comparing the LIT data and thermography data, as shown inFigs. 7 and 8, respectively, with the OPTIM data in Figs. 10 and 11,there are areas where the IR light spreads out at the edge of the chipin the data obtained using thermography. The LIT sensor is an InSb 2Dcamerawhich passively detects the IR light generated by black-body ra-diation depending on the temperature and its emissivity. The differencein the radiation rate is the difference in the detection strength for thispassive detector. In addition, the InSb sensor detects light with wave-lengths of 3–5 μm. It is therefore difficult to maintain a resolution lessthan 3 μm. It is still unclear whether the temperature increase is dueto heat conduction or a difference in the emissivity. However, on theedge of the power device, there are areas with high emissivity. There-fore, it is not clear whether the areas where strong IR light spreads outat the edge of chip are due to the high temperature or whether theyare due to the effect of the chip-edge structure.

On the other hand, the OPTIM method is an active measurement ofthe rate of change of the intensity ΔR/R, and it is not easily affected bythe difference in the emissivity of the neighbouring area.

The OPTIM is considered to be high speed if the measurement fre-quency is greater than 10 kHz, and if there is a high time resolvingpower. We assume that the data obtained by the OPTIM reflects thetemperature-deviated point depending on the high time resolution,and heat generating point almost itself. In addition, Fig. 11 shows themovement of the peak line of the reflectance deviation. It shows thatthe temperature-deviation peak shifts toward the baseline, focusingon the positional relationship between the solid blue line, which repre-sents the temperature deviation, and the dotted orange line, which rep-resents the baseline. These results suggest that the OPTIM method isbetter able tomeasure the heat-generation distribution, which dependson a high time resolution, as opposed to thermography,whichmeasuresthe temperature passively.

In Fig. 11, the line peak of the leakage current moves only towardone direction. Therefore, the movement is unlikely to be propagationdue to heat conduction. In addition, there is a possibility that the leakmay be related to defects in the crystals because they were linearlypositioned.

thermoreflectance deviation, yellow dashed line (M): MOSFET chip image; chip edge and

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6. Conclusions

In this study, we investigated the temperature variation of animage of the surface of a power device that is under UIS condition,as measured by thermoreflectance mapping (OPTIM). The resultsobtained show that this method successfully measured the heat-generation distribution of the power device. In future, we aim tosolve the problem regarding the phenomenon whereby there is ashift in the distribution of the phase and I/Q data in the leakage-failure sample.

Acknowledgements

Wewould like to express our thanks to the entire Hamamatsu Pho-tonics team and the Toshiba Information System team for their assis-tance with all of the experiments.

Please cite this article as: Endo K, et al, Thermoreflectance mapping obseMicroelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2

References

[1] Riccio M, Rossi L, Irace A, Napoli E, Breglio G, Spirito P, et al. Analysis of large areaTrench-IGBT current distribution under UIS test with the aid of lock-in thermography.Microelectron Reliab 2010:1725–30.

[2] Endo K, Sugano K, Yoshii I, Fujiwara T, Nagatomo T, Fujimaki S. Transient thermalresponse measurement of Power MOSFET avalanche breakdown by equivalent timesampling technique (in Japanese). 32th LSI Testing Symposium (LSITS); 2012. p. 45–9.

[3] Riccio M, De Falco G, Maresca L, Breglio G, Napoli E, Irace A, et al. 3D electro-thermalsimulations of wide area power devices operating in avalanche condition.Microelectron Reliab 2012:2385–90.

[4] Christofferson J, Vashaee D, Shakouri A, Melese P. Real time sub-micron thermal im-aging using thermoreflectance. International Mechanical Engineering Congress andExposition; 2001.

[5] Christofferson J, Shakouri A. Thermoreflectance based thermal microscope. Rev SciInstrum 2005;76:024903.

[6] Celi G, Dudit S, Parrassin T, Perdu P, Reverdy A, Lewis D, et al. Thermal frequency im-aging: a new application of laser voltage imaging applied on 40 nm technology. Pro-ceedings from the 37th International Symposium for Testing and Failure Analysis(ISTFA); 2011. p. 18–23.

[7] Hamamatsu Photonics KK. Electro optical probing unit. http://www.hamamatsu.com/resources/pdf/sys/SSMS0052E_EOP.pdf.

rvation of Power MOSFET under UIS avalanche breakdown condition,015.06.031