IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY-PART C, VOL. 19, NO. 2, APRIL 1996 85

Thermal Preprocessing to Shorten Flows, Simplify Lithography, and

Radically Reduce Processing Cycle T h e Timothy D. Stanley, Member, ZEEE

Abstract-In integrated circuit (IC) manufacturing, mismatch in processing times (about one minute per wafer for some steps to over ten hours per wafer for others) forces grouping of wafers into lots and batches for economic processing. If separation through implanted oxygen (SIMOX) silicon-on-insulator (SOI) wafer production was followed by blanket gate oxide growth and poly silicon deposition before the wafers entered the semiconduc- tor fabrication process, processing could start with the critical lithographic step, poly-silicon patterning, thereby avoiding over- lay issues. This step could be followed by sourcddrain formation, and rapid-thermal-annealing (RTA) to activate the implants and a shallow trench to the buried oxide for isolation. This would complete the front-end processing with no need for long thermal steps. The result would be simplified lithography, reduced process flow length, and better matched processing times facilitating more complete clusterization of the factory and, thereby, a radically reduced cycle time. The cycle time using this approach is expected to be on the order of one day, accelerating yield learning, reducing inventory risks, and reducing processing overhead in cleans and inspections.

Index Terms- Cycle time reduction, process simplification, thermal preprocessing, silicon-on-insulator.

I. INTRODUCTION

HILE integrated circuit (IC) manufacturing has demon- strated continuous productivity improvement over the

last 20 years (as given by Moore’s Law), there are obvious areas for substantial improvement. The time from the start of silicon processing until the IC’s are ready for testing is often several months. The process is operator intensive, with wafers moving over a path of about ten miles to be processed. All of this is done in a very unfriendly stringent clean room environment.

In integrated microelectronics circuit fabrication, most of the approximately 300 production process steps require, at most, a few minutes to process each wafer. But some steps, called “thermal batch processes” typically require many hours to accomplish. To balance the capacities of these slow thermal tools with the rest of the factory, as many as 150 wafers are loaded together in the thermal reactor for concurrent processing. This group of up to 150 wafers loaded together for processing, is called a batch. In addition to the processing time required for the thermal steps, additional delay results from the need to accumulate wafers to form batches and then

Manuscript received January 15, 1996; revised March 15, 1996. The author is with Factory Modeling & Simulation, Motorola, Manufactur-

Publisher Item Identifier S 1083-4400(96)043 18-5. ing Technology Development, Austin, TX 78704-1294 USA.

to disassemble the batches for subsequent processing. This additional delay is roughly equal to the thermal processing time for a fully loaded, balanced fab.

In a SEMATECH four-metal level, 0.25 pm logic flow examined by the author, the processing time required for thermal batch steps totaled over seven days while all of the remaining process steps, if done one wafer at a time, would require about 11 hours. Clearly, if the thermal steps could be eliminated and single wafer processing used, the cycle time could be on the order of one day.

A very short cycle-time was demonstrated by the Micro- electronics Manufacturing Science and Technology (MMST) program funded by the Department of Defense and accom- plished by Texas Instruments, Inc. The approach used in the MMST program was to replace furnace steps with rapid thermal processes (RTP’s) reactors and use all single wafer processes. For a 0.35 pm double level metal CMOS, the MMST team processed wafers in less than three days. They also showed that if their tool set had included multiple implanters, so that species change over time could have been avoided, and if the transport time between tools was minimized, that a cycle time of one day could have been achieved [ 11.

Very short cycle-time manufacturing would provide substan- tial economic advantage through accelerated yield learning, reduced need for cleans, inspections, and control wafers, much less inventory, and the ability to respond quickly to customer needs. Currently, factories ramp up to volume production over several years as the learning in the factory improves. Cutting the cycle time, a factor of ten would potentially increase the learning rate by a factor of ten, allowing the factory to ramp to full production much sooner, thus, minimizing the time between investment and payback. But lto be a viable improvement, short cycle time must be achieved without compromising yields or the flexibility of the factory. Other options to reduce the time required for thermal steps include small batch, fast ramp furnaces, and continuou!; flow reactors. Small batch, fast ramp furnaces reduce the overhead time associated with ramping temperature while their small batch size reduces the time to assemble and disassemble large batches. A continuous flow furnace (where wafers enter on one end of the furnace and exit on the opposite end) eliminates the need to assemble and disassemble batches

Another help in reducing cycle-times is process simplifica- tion. Examples include high energy MEV implanters to allow

10834400/96$05.00 0 1996 IEEE

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY-PART C , VOL. 19, NO. 2, APRIL 1996

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Fig

High Dose, High Energy Oxygen Implant

4 Nigh Temperature Anneal

Silicon Wafer

Fig. 2. In the batchless factory concept, wafers would be preprocessed before entering the semiconductor fabricator by growing a gate oxide followed by poly-silicon deposition.

1. SIMOX process consists of a high energy (-200 MEV), high dose (GlO'') oxygen implant followed by a high temperature ( ~ 1 3 0 0 ~ C ) a n n e a l for about six hours

multiplc implant steps to bc combined in one masking level and silicon-on-insulator (SOI) technology that eliminates the need for wells in CMOS production and simplifies isolation. By reducing the total number of processing steps, process simplification shortens the cycle time.

The focus of this paper is a preprocessing concept that moves the thermal processing steps out of the semiconductor fabrication facility, eliminating the processing time mismatch and allowing more processing steps to be clustered to facilitate dramatic cycle time reduction. A secondary effect is substantial simplification of the front end of line processing further reducing cycle time.

While not essential to the concept, the most easily described embodiment is in conjunction with Separation through IM- planted Oxygen (SIMOX) SOL The SIMOX process consists of a high dose oxygen implant followed by a high temperature anneal to form an insulating buried oxide under the active surface silicon of a wafer. This process is illustrated in Fig. 1.

A bulk silicon embodiment would require formation of wells through the polysilicon and gate oxide that would complicate the process. Also deep trenches andor guard rings would be required for isolation further complicating the process.

11. BATCHLESS FACTORY CONCEPT

In this concept, wafers would be preprocessed before en- tering the semiconductor fab by growing gate oxide over the surface of the wafer followed by a blanket poly-silicon gate deposition. Then, through the use of trench or field shield isolation, complementary MOS transistors could be built, isolated, and integrated without the need to grow isolation or gate oxides. A conceptualization of this preprocessed starting material is given in Fig. 2.

If this technique were used in conjunction with SIMOX, the wafer supplier already needs to grow capping oxides and accomplish high temperature anneal steps as part of the SIMOX SOT process. So growing a gate oxide and depositing

Fig. 3 . The first process step is the critical lithographic step of gate definition by patterning the poly silicon. Since it is the first lithographic step, no alignment to previous levels is required, simplifying processing and increasing lithography options. Side walls would then be produced.

poly silicon should be readily done at their location with only a relatively small impact on the cost of the SO1 material.

The fabrication sequence for this concept, illustrated in Figs. 3-5, starts with poly-line definition that determines the MOSFET channel length. Since this most critical lithograph step is first, no alignment to previous levels is required. This increases the lithographic options available for accomplishing this step. Next, the sources and drains would be masked and then implanted. All implants would be activated in one rapid thermal step. Next, shallow trenches would be cut to the buried oxide to isolate the gates where required. Note that in using SO1 technology that wells are not required, so that drains that are at the same potential, like the complementary pair in an inverter, can be physically joined. In Fig. 6, a conceptual layout for a cross coupled inverter latch is given.

111. ADVANTAGES OF BATCHLESS FACTORY CONCEPT

In this concept, the critical lithography step that defines the channel width is first, so that alignment of the critical level to previous levels (overlay) is not an issue. This expands lithographic options and reduces lithographic concerns.

STANLEY: THERMAL PREPROCESSING TO SHORTEN FLOWS, SIMPLIFY LITHOGRAPHY, AND RADICALLY REDUCE PROCESSING CYCLE TIME 87

Trench to BOX 1 I i---

Fig. 4. implants would be activated in one rapid thermal step.

The next step is to mask and implant the sources and drains. All

I

Fig. 5. the devices.

Next, shallow trenches would be cut to the buried oxide to isolate

The steps removed from the process flow would, to a limited extent, shorten the processing time and improve yields. But the major improvement in cycle time would result from eliminating the batch thermal steps from the factory flow, thereby, providing a much better processing time and process load match between tools. The result would be a factory where processes could be more completely clustered, reducing the effective lot size and radically shortening the factory cycle time. The reduced effective lot size would also reduce the in-process wafer inventory in the factory for lower inventory costs and risks.

A one day cycle time would also reduce process overhead by eliminating many of the current inspection requirements and reducing the number of cleans required. Also, the time required to go from product entry yields to mature production yields would be reduced from many months to a few weeks. This would have a major impact on the profitability of the factory. Also the factory could be more responsive to customer needs without the current inefficient practices of hot lots and contingency lots.

Currently, wafers are preprocessed to deposit epitaxial sili- con layers and to produce novel substrates like SO1 materials. So, preprocessing wafers to grow gate oxide and deposit poly- silicon is not an unreasonable paradigm shift.

v N+Drains Fig. 6. Conceptual layout for a cross-coupled inverter 1at:h.

Iv. POTENTIAL PROBLEMS WITH CONCEPT

Some process limitations result from movinig the thermal steps from about a third of the way through processing to a preprocessing step. These include an inability to adjust threshold voltages without implanting through the gate oxide, and the need for a very few standard gate orride and poly silicon thicknesses. These standards in oxide and poly thick- nesses would make it harder for semiconductor manufacturers to compete in processing, since a substantial portion of the processing would be complete when the wafers come into the factory. On the plus side, standardizing on proce,ss flows would make standardization of tools easier with lower tool costs the result.

The problem of adjusting the threshold voltage can be handled through the use of dual poly-doping for work function threshold voltage adjustment, and the use of depletion mode devices.

V. ENABLING TECHNOLOGIES Now AVAILABLE

Implants for sources, drains, and poly-dopin g would need to be accomplished without batch thermal steps to activate the implants. Fortunately, RTP has evolved to take: care of these needs.

Care would need to be exercised in transporf of the wafers with gate oxide and poly to the fabrication facility to avoid gate oxide rupture or ionic contamination. This coiild be accom- plished through the use of static dissipating mini-environments to transport the wafers and prevent charge buildup. This technology is now available through several suppliers.

Oxygen implantation and anneal (SIMOX) processes to produce SO1 material have evolved to the quality of commer- cial applicability. The potential of SO1 to simplify processes, reduce die sizes, and increase speeds at low power is well rec- ognized in the semiconductor industry. This technology with

88 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY-PART C, VOL. 19, NO. 2, APRIL 1996

the capability to obtain full isolation with shallow trenches, greatly simplifies the issues of moving the thermal steps out of the IC fabrication facility.

To obtain maximum cycle time reduction benefit from removing the thermal steps from the semiconductor fah, the effective lot size needs to be reduced. The technology to combine single wafer steps into one tool is called clusterization

thermal processing steps and processing by lots. In addition to alternatives in high yielding RTP technologies, the possibility of moving the thermal steps to a preproduction process coupled with more complete clusterization of the factory should be explored as a way to radically reduce the cycle time of IC manufacturing.

and has the potential to enable a one day cycle time. For this REFERENCES

product of the components reliability. While integration of the complete factory into a single cluster tool system is not a feasible goal from reliability and flexibility considerations, a reasonable goal may be to have each mask level accomplished in a single clustered tool system.

Timothy D. Stanley (M’88) received the B.S. degree in physics from Brigham Young University, Provo, UT, in 1971, the M.S. degree in economics from South Dakota State University, Brookings, in 1975, the M.S. degree in nuclear

VI. CONCLUSION

engineering from the Air Force Institute of Technology, Wright-Patterson Air Force Base, OH, in 1976, and the Ph.D. degree in electrical engineering from the University of New Mexico, Albuquerque, in 1985.

He served for 20 years in the United States Air Force, completing his duty as Lieutenant Colonel assigned to SEMATECH. He left the Air Force and joined SEMATECH as a direct hire in 1991. There, he evaluated modeling

The goal for the semiconductor be to lower the cycle time from the current practice of a few months to a few days. h,fany technologies are becoming to

biggest limiters to software packages, analyzed factory architecture options, and studied large wafer factory benefits. He was promoted to Senior Member of the Technical Staff at SEMA’CH in 1994. In Februaw 1995. he ioined Motorola to helD shorter cyc1e times.

, _ .

very short cycle time semiconductor fabrication are the batch develop manufacturing capability on 300 mm wafers.