the processor: datapath & control. implementing instructions simplified instruction set...
TRANSCRIPT
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The Processor:Datapath & Control
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Implementing Instructions Simplified instruction set
memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and,
or, slt control flow instructions: beq (bne), j (jal)
Generic implementation: 1. PC to supply instruction address2. get the instruction from memory3. use the instruction to decide what to do4. read registers
Majority of instructions use the ALU the actions differ.
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Clocking Methodology 1/2Edge-triggered methodology
values stored in a sequential logic elements are updated only on clock edge
Typical execution:read contents of state elements, send values through some combinational logicwrite results to one or more state elements
state element 1
state element 2Combinational Logic
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Clocking Methodology 2/2
An edge-triggered methodology allows a state element to be read and written in the same clock cycle
state element Combinational Logic
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Abstract View of DatapathTwo types of functional units:
combinational, e.g. ALUsequential, e.g. registers
Add
ALU Address
Data Memory
Data
Data
Registers
Reg. No
Reg. No
Reg. NoInstruction
Memory
Address
Instruction
PC
Add4
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Datapath Including Control
ALU Address
Data Memory
Data
Data
Registers
Reg. No
Reg. No
Reg. NoInstruction
Memory
Address
Instruction
PC
AddAdd
4
MemWrite
MemRead
RegWrite
Control
zero
branch
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Register File
Read registernumber 1
Read registernumber 2
Writeregister
Write data
Register file
read
data 1
read
data 2Write
5
5
5
32
32
32
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ALU Symbol & ControlALU control
linesFunction
0000 AND
0001 OR
0010 add
0110 subtract
0111 slt
1100 NOR
ALU
32
a
b
32
Result32
Zero
Overflow
CarryOut
ALU Control
4
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Instruction Fetch
Add
InstructionMemory
Address
Instruction
PC
4
Instruction
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R-Type Instructions
ALU Control
Instruction
read register 1
Read register 2
Writeregister
Write data
Register file
read
data 1
read
data 2Write
5
5
5
32
32
32
ALU
Zero
Overflow
CarryOut
4rs
rt
rd
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
add rd, rs, rt
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Implementing Load & Stores
rt
rs
rt ALU Address
Data Memory
WriteData
Write Data
Registers
Read Reg. 1
MemWrite
MemRead
RegWrite
zero
Read Reg. 2
Write Reg.
Read Data 1
Read Data 2 Read
Data
SignExtend 3
2
Instruction
16
Immediate
ALU Control
op rs rt Imm
6 bits 5 bits 5 bits 16 bits
lw rt, index(rs)
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Implementing Branches
ALU
Write Data
Registers
Read Reg. 1
RegWrite
zero
Read Reg. 2
Write Reg.
Read Data 1
Read Data 2
SignExtend 3
2
Instruction
rs
rt
16
Immediate
ALU Control
AddShiftleft 2
PC+4
BranchTarget
Address
To BranchControlLogic
op rs rt Imm
6 bits 5 bits 5 bits 16 bits
beq rs, rt, Label
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Building the Datapath Idea: Use multiplexors to stitch them together
rs
rt
Imm
rd
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Implementing Jumpop Address
6 bits 26 bits
j Label
ALU
Write Data
Registers
Read Reg. 1
RegWrite
Read Reg. 2
Write Reg.
Read Data 1
Read Data 2
Instruction
rs
rtALU Control
Shiftleft 2
PC+4 [31 : 28]
JumpTarget
Address
[27 : 0]
26
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Complete Datapath with Control
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ControlControl Signals
Selecting the operations to performControlling the flow of data (via MUX)Read/write enable inputs of memory and register file
Information comes from the instruction
Example: add $t0, $s0, $s1
op
000000 10000 10001 01000 00000 100000
rs rt rd shamt funct
• ALU operation is based on instruction type and function code
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ALU ControlExample: lw $t0, 100($s2) What should the ALU do with this instruction?
ALU Control lines Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 set on less than
1100 NOR
op
100101 10010 01000 0000000001100100
rs rt address
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ALU Control UnitALU performs
addition for loads and storessubtraction for branches (beq)no operation for jumpsor the operation is determined by the
function field for R-type instructions.ALU Control unit will have the following
inputs:2-bit control field called ALUOp6-bit function field
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ALU Control Unit
Instruction opcode
Instruction operation
ALUop Funct field
Desired ALU
action
ALU Control
lw Load word 00 xxxxxx add 0010
sw Store word 00 xxxxxx add 0010
beq Branch equal
01 xxxxxx subtract 0110
R-type Add 10 100000
add 0010
R-type Subtract 10 100010
subtract 0110
R-type AND 10 100100
and 0000
R-type OR 10 100101
or 0001
R-type slt 10 101010
slt 0111
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Main Control Unit
0 rs rt rd shamt funct
31-26 25-21 20-16 15-11 10-6 5-0
rs rt Imm
31-26 25-21 20-16 15-0
2 address
35 or 43
31-26 25-0
rs rt Imm
31-26 25-21 20-16 15-0
4
R-type
Load or store
jump
branch
Fields of Different Instruction Classes:
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Datapath with Control Signals
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Seven Control SignalsSignal name
Effect when de-asserted
Effect when asserted
RegDst The destination register number comes from rt.
The destination register number comes from rd.
RegWrite None Destination register is written with value on Writedata
ALUSrc 2nd ALU operand comes from Read_Data_2
2nd ALU operand is the sign extended, lower 16 bit of the instruction
PCSrc The PC is replaced by PC + 4
The PC is replaced by the branch target address
MemRead None Memory is read
MemWrite None Memory is written
MemtoReg The value to the register Writedata input comes from the ALU.
The value to the register Writedata input comes from the data memory
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RegDst & RegWrite
read register #1
read register #2
writeregisterwrite data
Register file
read #1
Writeread #1
RegWrite
RegDst
0
1
rt: Ins[20-16]
rd: Ins[15-11]
load
R-type
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ALUSrc
read register #1
read register #2
writeregisterwrite data
Register file
read #1
read #1
RegWrite
ALUSrc
0
1
signextend
Imm: Ins[15-0]
3216
result
Zero
ALU
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MemtoReg
Address
write data
DataMemory
read data
MemtoReg
1
0
Zero
To the write data input of Register File
From the read data 2output of Register File
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PCSrc
AddPCSrc
0
1
PC
Shiftleftby 2
Imm: Ins[15-0]
32
signextend
Add4
zerobranch
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Datapath & Control
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Operation of the Datapath
101000X0Xbeq
000100X1Xsw
000011110lw
010001001R-format
ALUOp0
ALUOp1
BranchMem
Write
Mem
Read
RegWrite
Memto-Reg
ALUSrcRegDestInstruction
Example Flow: beq $s0, $s1, address• The instruction is fetched from memory and PC is
incremented• Read two register values• Subtract one from the other, calculate the branch address• Use the zero signal to determine which of the addresses is
to be used for fetching the next instruction
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Control FunctionInput or output
Signal name
R-format lw sw beq
Inputs
Op5 0 1 1 0
Op4 0 0 0 0
Op3 0 0 1 0
Op2 0 0 0 1
Op1 0 1 1 0
Op0 0 1 1 0
Outputs
RegDst 1 0 x x
ALUSrc 0 1 1 0
MemtoReg 0 1 x x
RegWrite 1 1 0 0
MemRead 0 1 0 0
MemWrite 0 0 1 0
Branch 0 0 0 1
ALUOp1 1 0 0 0
ALIOp0 0 0 0 1
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Cycle TimeThe control logic is combinational
every instruction is executed in one clock cycle
Cycle time determined by length of the longest path
state element 1
state element 2Combinational Logic
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Single Cycle ApproachDifferent instructions have different execution
timesAdd: 3 nsSubtract: 3.5 nsMemory access: 10 nsMultiplication: 20 ns
In single cycle approach, the slowest instruction determines the clock cycle time.
Another approach, divide instruction into smaller parts and execute each in a shorter clock cycle
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Instruction in Datapath
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Instruction TimingsInstruction
classFunctional Units used by the instruction class
R-type Instruction fetch
Register access
ALU Register access
Load word Instruction fetch
Register access
ALU Memory access
Register access
Store word Instruction fetch
Register access
ALU Memory access
Branch Instruction fetch
Register access
ALU
Jump Instruction fetch
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ExampleMemory access: 200 psALU and addition operations: 100 psRegister file access (read or write): 50 ps
And assume other parts (multiplexors, control units, etc) have no delay.
Instruction mix: 25% loads, 10% stores, 45% ALU ops, 15% branches, 5% jumps
Compare two approaches: single fixed clock cycle and multiple clock cycle per instruction, i.e.
what is the clock period per instruction and CPI for a fixed cycle
what is the nominal clock period and CPI for the multiple cycle approach
Execution times?