datapath i
TRANSCRIPT
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Outline Processor Design
–
• A simple
implementation:
Single
Cycle
–
• Performance
considerations• u cyc e es gn
– Data path and control
• croprogramme
con ro
• Exception handling
2
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•
• Design overview
• Division into ata pat an contro
• Building blocks
combinational
and
sequential
• Clock and timings
•
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• Arithmetic lo ic instructions
–add,
sub,
and,
or,
slt•
–lw,
sw• on ro ow ns ruc ons
–beq, jIncremental
changes
in
the
design
to
include
other instructions will be discussed later
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• Use the ro ram counter PC to su l
instruction
address
• Get the instruction from memor
• Read registers
do
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InstructionData
PC Address
Instruction
Register
Address
Reg#
Data
Memory
ALU
Reg#
Data
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DATA PATH
control status
CONTROLLER
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• Elements that
operate
on
data
values
combinational
– Output is function of current input
– No memor
• Elements that contain state (sequential)
– Out ut is function of current and revious in uts
– State = memory
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, , , , ,
• Multiplexer
• Decoder• Adder, subtractor, comparator
• Array multipliers
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•
• Registers• Register files
• Memories
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•
– State changes
only
with
clock
edge
– State
changes
can
occur
with
changes
in
other
falling edge
cycle time
rising edge
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Q R Q
C
_
Q S
_
Q
C
Q
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_Q
_Q
D
latchC
D
latchC
C
D
C
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Clock
and
timin sD
Set-up time Hold time
C
Element
2
Element
1
Combinational
Logic
oc yc e
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•
• Adder
• Multiplexer
• eg s er e
• Program memory
• Data memory
• Bit manipulation components
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PC
32 32
clock
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PC+4PC
32
+
32
+
32offset
32
4
3232
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operation
a=b
a overflow
result
b
32
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+
mux
1 32
select
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5Register
Read
Data 1
Read Reg 1
5
Number
Data
Read Reg 2
Registers
Read
Data 2
r e eg
32
Write dataData
32
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MIPS Com onents:
Pro ram
memor
Instruction
Instruction
Instruction
Memory
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Mem
Write
Data
A ress
Read
data
Memory
Write
data
Mem
ea
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MIPS Components
Bit manipu ation
circuits
MSB
sign
xtend
MSB
shift0 LSB