the no n a apd readout chip
DESCRIPTION
The NO n A APD Readout Chip. Tom Zimmerman Fermilab May 19, 2006. Continuous reset adjust. Continuous reset adjust. 32. Analog pipeline (64 deep). 10-bit ADC (Wilkinson). Digital Readout. APDs. Integrator. Shaper. Hard reset. Hard reset. Write clock 500 ns. - PowerPoint PPT PresentationTRANSCRIPT
The NOA APD Readout Chip
Tom Zimmerman
Fermilab
May 19, 2006
2
NOA Detector Readout Requirements
• Record neutrino signal from detector APDs (APD gain ~ 100, C ~ 10pF)• MIP ~ 25 pe gives 2500e input signal• Need low noise front end (< 200 e)• 10 us long beam spill every 2 seconds• Beam spill arrival known to +/- 10 us • Integrate APD signals in 500 ns buckets during a 30 us window• After acquisition, perform Dual Correlated Sampling (DCS) and digitize
to extract pulse height and timing• LSB ~ 100e, max. input = 100Ke: 10-bit dynamic range• Measurement resolution required = a few percent
Original proposed ASIC(“Pipeline” version)
Integrator Shaper Analog pipeline (64 deep)
10-bit ADC(Wilkinson)
DigitalReadout
Write clock 500 ns
Read clock ~ 5 us
Continuousreset adjust
Hard reset
Continuousreset adjust
Hard reset
APDs32
Output clock
3
“Pipeline” version design
10
CK
D
10
S
hif
t R
egis
ter
10
GAIN
BW
FE RST FE RST
Compare Count Latch
10-BIT GRAY COUNTER
IN
RAMP GEN.
CONTROL LOGIC
Vref
(One channel of 32 shown)
Wri
te
Rea
d
Control Section (common to all channels)
Ram
p
Co
un
t
Digital readout mode DATA OUT format example: Cell only digitize mode (10-bit DATA words)
Previous Channel
Next Channel
Integrator: 10 mV/fC
Shaper: programmablegain, shaping
Analog pipeline, 64 deep (32 us)
10-bit ADC
Digital output
4
Alternate ASIC configuration (“Mux” version)• Would also like to detect supernova neutrino signal (capture 10s of seconds)
• Requires near 100% live time (continuous acquisition and digitization)
• Use four 8:1 analog multiplexers with external ADCs. Multiplex and digitize at 8 X [sample freq.] = 8 X [1/500ns] = 16 MHz. Perform DCS and additional processing digitally in FPGA
• Risk: coupling to low noise front end from continuous digitize/readout
Integrator Shaper
Continuousreset adjust
Hard reset
Continuousreset adjust
Hard reset
APDs32 32
8
8
8
8
8:1 Mux
8:1 Mux
8:1 Mux
8:1 Mux
S.E. to diff.output amps
Mux clock
10-bit ADC
10
FP
GA
ASIC
10-bit ADC
10
10-bit ADC
10
10-bit ADC
10
Quad ADC
5
Which approach for NOA ?
• Baseline approach: “Mux” ASIC with external ADCs, allowing 100% live time. Required: ASIC + Quad ADC + FPGA.
• Backup approach: “Pipeline” ASIC, allowing separate acquire/digitize cycles if necessary. Required: ASIC + FPGA.
• Prototype ASIC: integrate both approaches on one chip, giving maximum flexibility for optimizing the APD readout strategy. Use TSMC 0.25 micron process.
6
10
CK
D
10
S
hif
t R
egis
ter
10
10
GAIN
BW
FE RST FE RST
INTEGRATOR SHAPER
SAMPLING PIPELINE (64 deep)
READ AMP
ADC COMPARATOR
ADC COUNT LATCH
10-BIT GRAY COUNTER
APD READOUT CHIP
IN
RAMP GEN.
CONTROL LOGIC
Vref
RingCk RampCntl
(One channel of 32 shown)
GrayCk
Wri
te
Re
ad
Control Section
Next Ch.
Digital Readout DATA OUT
10
Prev. Ch.
Ra
mp
Co
un
t
OutCk
En
able
Pip
elin
e
1
of 4
An
alo
g
Rea
do
uts
(8
ch
. eac
h)
Serial Program Register
ChipReset
SRCk
Shift Data Clock
ShiftIn Prog. bits
ReadWrite
S.E. to Diff.
ANALOG MUX CNTL.
MUX1
MUX1
Prog. bits
Gain, BW, ...
8 1
NOA prototype ASICMux versionanalog output
Pipeline versiondigital output
7
Integrator• 1 LSB ~ 100e: use 10 mV/fC (CFB = 0.1pF), followed by shaper gain (x2-x10)
• 500 ns sample time: M1 is PMOS to avoid significant 1/f noise contribution.
• M1 (PMOS) source is referred to VDD, not ground.
• Where to refer APD capacitance for best PSRR?
• If IBIAS is fixed, then Vgs1 is constant, so Vin = VDD. If CAPD grounded: Vout/VDD = Vout/Vin = CAPD/ CFB = 100 (disaster!!)
• If CAPD is referred to VDD:
– Tight input loop (minimizes pickup)
Vout/VDD = 1 (better!!)
VDD
Vout
CFB
Iin
?
CAPD
0.1p
10p
IBIAS
Vgs1Vin
<<IBIAS
M1
10 mV/fC
8
• But what about CSTRAY to ground (bond pad, bondwire, etc.)? Ruins PSRR.
• Use M2 with Vgs = VDD to generate IBIAS.
Two advantages:– 1. For a given IBIAS, max. Vgs2 yields min. gm2, lowest M2 noise.
– 2. IBIAS changes with VDD. Now Vin = (VDD)[1 - (gm2/gm1)].
If (CSTRAY/CAPD) = (gm2/gm1), then Vout = 0!! (to 1st order).
• Typically (gm2/gm1) ~ 0.05:
M2 noise contribution ~ 2%
Optimum CSTRAY ~ 0.5pF
• Unavoidable CSTRAY is of order 0.5pF!
• Add small programmable input C to gnd.
• Make IBIAS (M2 width) programmable.
• Tweak for best PSRR!
• Assumes same C’s on all channels.
VDD
Vout
CFB
CAPD
0.1p
10p
VDD
CSTRAY
?
Bias current source, Vgs2 = VDD
IBIAS
Iin
Vgs1+Vin
M1
M2
<<IBIAS
9
VDD = 20 mV (externally forced transient)
Integrator outputs for 3 different values of Cstray
Cin = 15 pF (to VDD) + Cstray (to gnd, programmable)
Tweak Cstray for best VDD immunity!
Integrator output response to VDD transient
10
Shaper
10p 2 – 48K
Vref(0.3V)Cin
Cfb
Vref
1 – 4.5 pF
8R
R
Vout
VinRin
Vref
falltime adjust
5 x M1
1V range(0.3-1.3V)
110 mV range (0.3-0.41V)(divider keeps M1 linear)
“hard” reset
“continuous” reset
M1
risetime adjust
gain adjust(x2.2 – x10)
• Risetime set by (RinCin), programmable. Not affected by gain setting.• Voltage gain set by (Cin/Cfb), programmable. Not affected by risetime setting.• External adjustment for falltime. Falltime affected by gain setting (Cfb).• Falltime independent of signal magnitude.
11
Shaper output programmable risetime
16 settings give risetime from 57 ns to 446 ns
12
Shaper output programmable gain
8 settings give shaper gain from x2.2 to x10.No significant effect on risetime.
13
Shaper output with finite fall time
4 values of Vout: 120, 300, 600, 1200 mV(normalized)
(feedback divider gives relatively stable falltime for different output amplitudes)
Vout = 1200 mV
Vout = 120 mV
14
Mux Version: single-ended shaper output converted to differential output to drive ADC
Vout+(0.75-1.75V)
common modefeedback
Vout-(1.75-0.75V)
RCM
RCM
VDD/2(1.25V)
R
R
2R
2R
Shapers
Ch. 1
Ch. 2
Ch. 8
Mux 1
Mux 8
0.3 - 1.3V(Vref = 0.3V)
0.8V(Vref + 0.5V)
Differential gain = 2.Output common mode stays at VDD/2.
Single-ended to diff. conversion
15
S.E. to diff. amplifier response for different amplitudes (scaled)
30 mV
Vout+ (positive amplifier output)
60 mV
120 mV
240 mV
400 mV 1000 mV
nominal amp bias
2X nominal amp bias
10 ns/divCompletely settled in < 40 ns
Vout =
16
Differential output [(Vout+) – (Vout-)] for max. amplitude (2V)
0 pFCout =
10 pF20 pF30 pF
400 mV/div
10 ns/div
17
VDD = 0.3 mV (from operating the mux).(1 mV/div)
Tweak Cstray for best integrator immunity!Optimum Cstray depends on Cin to VDD.
unbondedchannels
bonded channel,Cin = 15 pF to VDD
Mux readout for 3 different programmed values of Cstray.(10 mV/div)
unbondedchannels
Multiplexer readout with VDD transientVariations at integrator outputs (amplified by shaper) appear at mux output.
Ch. 0 1 2 3 4
18
Pipeline Version: 64 deep pipeline + on-chip multichannel Wilkinson ADC
10
CK
D
10
S
hif
t R
egis
ter
10
10
SAMPLING PIPELINE (64 deep)
READ AMP
ADC
Vref W
rite
Re
ad
Next Ch.
Prev. Ch.
Ram
p
Gra
y
Co
un
t
Shaper output
READOUT (1 channel shown)
COMPARATOR
Sh
ift
Dat
a
LATCH
Read amp out V1
V2
Compare Reset
Ramp
Gray Counter Clock
V
V
Comparator flips andlatches Gray count
Digitize V = (V2 – V1):
19
Two digitize options
• Option 1: cell only
V1 = Read amp reset voltage (Vref) always
V2 = Pipeline cell voltage (Vref + excursion due to shaper output)
The ADC directly digitizes the shaper signal level sampled by each cell of the pipeline. The signal is always positive with respect to Vref.
• Option 2: DCS
V1 = Pipeline cell (n-1) voltage
V2 = Pipeline cell (n) voltage
The ADC digitizes the difference between two neighboring pipeline cell voltages (dual correlated sampling). Continuous shaper reset should not be used , since only positive differences can be digitized.
cell 0
cell 1cell 2
Vref
Digitize cell 0
Digitize cell 1
Digitize cell 2
cell 0
cell 1cell 2
Digitize (1 – 0)
Digitize (2 – 1)
20
Two acquire/digitize modes
• Mode 1: Separate acquisition and digitization:
First acquire signals by filling the pipeline, then stop acquisition.
Digitize and readout all pipeline cells.
• Mode 2: Concurrent acquisition and digitization:
Acquisition and digitization occur simultaneously (with latency). Range or resolution must be sacrificed in order to digitize every 500 ns.
21
Progress to date
• The chip is completely functional.
• MUX version: performance is adequate and meets all specs.
• PIPELINE version: only the “Separate acquisition and digitization” mode has been tested. The on-chip ADC digitizes dual correlated samples as desired.
• The DCS digitize option was used to measure noise.
• “Concurrent acquisition and digitization” mode not yet studied. Coupling from digital back end to analog front end???
22
Noise Measurements
Conditions:
• Integrator input transistor bias current = 1mA
• Shaper rise time constant = 206 ns (hard reset, infinite fall time)
• Shaper gain = X10 (integrator + shaper = 100 mV/fC)
• Dual correlated sample (t = 1000 ns)
• Noise downstream from integrator (shaper + ADC) = 41 electrons (for shaper gain = 10). Subtract this noise from the measurement to get only the integrator noise contribution.
• Many different variations of input transistor W/L.
23
W/L DCS noise (e)
880/.32 6e + 8.5e/pF
1200/.32 9e + 7.7e/pF
1540/.32 14e + 7.3e/pF
620/.4 7e + 9.4e/pF
880/.4 5e + 8.4e/pF
1540/.4 19e + 7.5e/pF
620/.6 8e + 9.5e/pF
1540/.6 21e + 7.9e/pF
620/1 23e + 10.2e/pF
1540/1 49e + 8.4e/pF
• Noise slope measurement is accurate
• Noise intercept not as accurate (stray wiring C ~ 7pF subtracted out)
• The measured noise is lower than the simulated noise! High confidence in measurements.
• SVX3 chip noise measurements with NMOS input transistor (TSMC 0.25 u) showed “excess” noise at shorter channel lengths (used L = 0.8u). PMOS shows no such behavior – shorter is better (should have tried L = 0.25u!).
Best: 10 pF noise = 87e20 pF noise = 160e
Integrator Noise Measurements